74ALVCH16374 (ON Semiconductor)
Low-Voltage 16-Bit D-Type Flip-Flop

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74ALVCH16374
Low−Voltage 16−Bit D−Type
Flip−Flop with Bus Hold
1.8/2.5/3.3 V
(3State, NonInverting)
The 74ALVCH16374 is an advanced performance, noninverting
16bit Dtype flipflop. It is designed for very highspeed, very
lowpower operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCXH16374 is byte controlled, with each byte functioning
identically, but independently. Each byte has separate Output Enable
and Clock Pulse inputs. These control pins can be tied together for full
16bit operation.
The 74ALVCH16374 consists of 16 edgetriggered flipflops with
individual Dtype inputs and 3.6 Vtolerant 3state outputs. The
clocks (CPn) and Output Enables (OEn) are common to all flipflops
within the respective byte. The flipflops will store the state of
individual D inputs that meet the setup and hold time requirements on
the LOWtoHIGH Clock (CP) transition. With the OE LOW, the
contents of the flipflops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. The OE input level
does not affect the operation of the flipflops. The data inputs include
active bushold circuitry, eliminating the need for external pullup
resistors to hold unused or floating inputs at a valid logic state.
Designed for Low Voltage Operation: VCC = 1.65 3.6 V
3.6 V Tolerant Inputs and Outputs
High Speed Operation: 3.6 ns max for 3.0 to 3.6 V
4.5 ns max for 2.3 to 2.7 V
7.8 ns max for 1.65 to 1.95 V
Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
IOFF Specification Guarantees High Impedance When VCC = 0 V
Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds ±250 mA @ 125°C
ESD Performance: Human Body Model >2000V; Machine Model >200V
Second Source to Industry Standard 74ALVCH16374
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MARKING DIAGRAM
48
48
1
TSSOP48
DT SUFFIX
CASE 1201
74ALVCH16374DT
AWLYYWW
1
A = Assembly
Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN NAMES
Pins
Function
OEn
CPn
D0D15
O0O15
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
ORDERING INFORMATION
Device
Package
74ALVCH16374DTR
TSSOP
Shipping
2500 / Reel
†To ensure the outputs activate in the 3state condition, the output enable pins
should be connected to VCC through a pullup resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
© Semiconductor Components Industries, LLC, 2006
June, 2006 Rev. 3
1
Publication Order Number:
74ALVCH16374/D


74ALVCH16374 (ON Semiconductor)
Low-Voltage 16-Bit D-Type Flip-Flop

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74ALVCH16374
OE1 1
O0 2
O1 3
GND 4
O2 5
O3 6
VCC 7
O4 8
O5 9
GND 10
O6 11
O7 12
O8 13
O9 14
GND 15
O10 16
O11 17
VCC 18
O12 19
O13 20
GND 21
O14 22
O15 23
OE2 24
48 CP1
47 D0
46 D1
45 GND
44 D2
43 D3
42 VCC
41 D4
40 D5
39 GND
38 D6
37 D7
36 D8
35 D9
34 GND
33 D10
32 D11
31 VCC
30 D12
29 D13
28 GND
27 D14
26 D15
25 CP2
Figure 1. 48Lead Pinout
(Top View)
1
OE1
48
CP1
47
D0
nCP
Q
D
2
O0
24
OE2
25
CP2
36
D8
nCP
Q
D
46
D1
nCP
Q
D
3
O1
35
D9
nCP
Q
D
44
D2
nCP
Q
D
5
O2
33
D10
nCP
Q
D
43
D3
nCP
Q
D
6
O3
32
D11
nCP
Q
D
41
D4
nCP
Q
D
8
O4
30
D12
nCP
Q
D
40
D5
nCP
Q
D
9
O5
29
D13
nCP
Q
D
38
D6
nCP
Q
D
11
O6
27
D14
nCP
Q
D
37
D7
nCP
Q
D
12
O7
26
D15
nCP
Q
D
Figure 2. Logic Diagram
1
OE1
CP1
48
25
CP2 24
OE2
EN1
EN2
EN3
EN4
D0 47
D1 46
D2 44
D3
D4
43
41
D5 40
D6 38
D7
D8
37
36
D9 35
D10 33
D11
D12
32
30
D13 29
D14 27
D15 26
1 1
1 2
1 3
1 4
2 O0
3 O1
5 O2
6
8
O3
O4
9 O5
11 O6
12
13
O7
O8
14 O9
16 O10
17
19
O11
O12
20 O13
22 O14
23 O15
Figure 3. IEC Logic Diagram
13
O8
14
O9
16
O10
17
O11
19
O12
20
O13
22
O14
23
O15
Inputs
Outputs
Inputs
Outputs
CP1 OE1 D0:7
O0:7
CP2
OE2
D8:15
O8:15
LH H LH H
L L L L L L
X L X O0 X L X O0
X H X Z XH X Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; = LowtoHigh Transition; X = High or Low Voltage Level and
Transitions Are Acceptable, for ICC reasons, DO NOT FLOAT Inputs. O0 = No Change.
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74ALVCH16374 (ON Semiconductor)
Low-Voltage 16-Bit D-Type Flip-Flop

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74ALVCH16374
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
VCC
VI
VO
IIK
IOK
IO
ICC
IGND
TSTG
TL
TJ
qJA
MSL
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
Moisture Sensitivity
VI < GND
VO < GND
*0.5 to )4.6
*0.5 to )4.6
*0.5 to )4.6
*50
*50
$50
$100
$100
*65 to )150
260
)150
90
Level 1
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
FR
VESD
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30 to 35
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
UL 94 VO @ 0.125 in
u2000
u200
N/A
V
ILATCHUP LatchUp Performance
Above VCC and Below GND at 125°C (Note 6)
$250
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mmby1 inch, 2ounce copper trace with no air flow.
3. Tested to EIA/JESD22A114A.
4. Tested to EIA/JESD22A115A.
5. Tested to JESD22C101A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Max
VCC Supply Voltage
Operating
Data Retention Only
2.3
1.5
3.6
3.6
VI Input Voltage
VO Output Voltage
(Note 7)
(Active State)
(3State)
0.5
0
0
3.6
3.6
3.6
TA Operating FreeAir Temperature
*40
)85
Dt/DV
Input Transition Rise or Fall Rate
VCC = 2.5 V $ 0.2 V
VCC = 3.0 V $ 0.3 V
0
0
20
10
7. Unused inputs may not be left open. All inputs must be tied to a highlogic voltage level or a lowlogic input voltage level.
Unit
V
V
V
°C
ns/V
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74ALVCH16374 (ON Semiconductor)
Low-Voltage 16-Bit D-Type Flip-Flop

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74ALVCH16374
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Condition
VIH
HIGH Level Input Voltage
1.65 V v VCC t 2.3 V
(Note 8)
2.3 V v VCC v 2.7 V
2.7 V t VCC v 3.6 V
VIL
LOW Level Input Voltage
1.65 V v VCC t 2.3 V
(Note 8)
2.3 V v VCC v 2.7 V
2.7 V t VCC v 3.6 V
VOH HIGH Level Output Voltage 1.65 V v VCC v 3.6 V; IOH = *100 mA
VCC = 1.65 V; IOH = *4 mA
VCC = 2.3 V; IOH = *6 mA
VCC = 2.3 V; IOH = *12 mA
VCC = 2.7 V; IOH = *12 mA
VCC = 3.0 V; IOH = *12 mA
VCC = 3.0 V; IOH = *24 mA
VOL
LOW Level Output Voltage
1.65 V v VCC v 3.6 V; IOL = 100 mA
VCC = 1.65 V; IOL = 4 mA
VCC = 2.3 V; IOL = 6 mA
VCC = 2.3 V; IOL = 12 mA
VCC = 2.7 V; IOL = 12 mA
VCC = 3.0 V; IOL = 24 mA
II Input Leakage Current 1.65 V v VCC v 3.6 V; 0 V v VI v 3.6 V
II(HOLD) Minimum Bushold Input
Current
VCC = 3.6 V; VIN = 0 to 3.6 V
VCC = 3.0 V, VIN = 0.8 V
VCC = 3.0 V, VIN = 2.0 V
VCC = 2.3 V, VIN = 0.7 V
VCC = 2.3 V, VIN = 1.7 V
VCC = 1.65 V, VIN = 0.58 V
VCC = 1.65 V, VIN = 1.07 V
IOZ 3State Output Current
1.65 V v VCC v 3.6 V; 0 V v VO v 3.6 V; VI = VIH or VIL
IOFF
PowerOff Leakage Current VCC = 0 V; VI or VO = 3.6 V
ICC
Quiescent Supply Current
1.65 V v VCC v 3.6 V; VI = GND or VCC
(Note 9)
1.65 V v VCC v 3.6 V; 3.6 V v VI, VO v 3.6 V
DICC
Increase in ICC per Input
2.7 V t VCC 3.6 V; VIH = VCC * 0.6 V
8. These values of VI are used to test DC electrical characteristics only.
9. Outputs disabled or 3state only.
TA = *405C to )855C
Min Max
0.65 VCC
1.7
2.0
0.35 VCC
0.7
0.8
VCC * 0.2
1.2
2.0
1.7
2.2
2.4
2.0
0.2
0.45
0.4
0.7
0.4
0.55
$5.0
$500
75
*75
45
*45
25
*25
$10
10
40
$40
750
Unit
V
V
V
V
mA
mA
mA
mA
mA
mA
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74ALVCH16374 (ON Semiconductor)
Low-Voltage 16-Bit D-Type Flip-Flop

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74ALVCH16374
AC CHARACTERISTICS (Note 10; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
Limits
TA = 40°C to +85°C
Symbol
Parameter
WaveVCC = 3.0 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V
form
Min
Max
Min
Max
Min
Max
Unit
fmax Clock Pulse Frequency
1 250
200
100
MHz
tPLH Propagation Delay
tPHL
CP to On
1 1.0 3.6 1.0 4.5 1.0
1.0 3.6 1.0 4.5 1.0
7.8 ns
7.8
tPZH
tPZL
Output Enable Time to
High and Low Level
2 1.0 4.7 1.0 6.0 1.0
1.0 4.7 1.0 6.0 1.0
9.2 ns
9.2
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2 1.0 4.1 1.0 5.1 1.5
1.0 4.1 1.0 5.1 1.5
6.8 ns
6.8
ts
Setup Time, High or Low Dn to CP
3
1.5
0.5
2.5
ns
th
Hold Time, High or Low Dn to CP
3
1.0
0.5
1.0
ns
tw CP Pulse Width, High
3 1.5
0.5
4.0
ns
tOSHL OutputtoOutput Skew
0.5 0.5
0.75 ns
tOSLH
(Note 11)
0.5 0.5
0.75
10. For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGHtoLOW (tOSHL) or LOWtoHIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
CPD Power Dissipation Capacitance
12. VCC = 1.8, 2.5 or 3.3 V; VI = 0 V or VCC.
Condition
Note 12
Note 12
Note 12, 10 MHz
Typical
6
7
20
Unit
pF
pF
pF
Dn
ts
CPn
On
Vm
th
Vm
fmax
tPLH, tPHL
Vm
VIH
Vm
0V
VIH
Vm
0V
VOH
OEn
tPZH
On
tPZL
On
VOL
Vm
tPHZ
Vm
tPLZ
Vm
Vm
VIH
0V
VOH
Vy
0V
VCC
Vx
VOL
WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 4. AC Waveforms
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74ALVCH16374 (ON Semiconductor)
Low-Voltage 16-Bit D-Type Flip-Flop

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74ALVCH16374
CPn Vm
tw
VIH
Vm
0V
tw
CPn Vm
VIH
Vm
WAVEFORM 3 − PULSE WIDTH
tR = tF = 2.0 ns (or fast as required) from 10% to 90%
Figure 5. AC Waveforms
0V
Symbol
VIH
Vm
Vx
Vy
3.3 V ±0.3 V
2.7 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
VCC
2.5 V ±0.2 V
VCC
VCC/2
VOL + 0.15 V
VOH 0.15 V
1.8 V ±0.15 V
VCC
VCC/2
VOL + 0.15 V
VOH 0.15 V
PULSE
GENERATOR
VCC
DUT
RT
RL
CL RL
6 V or VCC × 2
OPEN
GND
TEST
SWITCH
tPLH, tPHL
tPZL, tPLZ
Open
6 V at VCC = 3.3 ±0.3 V;
VCC× 2 at VCC = 2.5 ±0.2V; 1.8 V ±0.15 V
tPZH, tPHZ
CL = 50 pF for VCC = 3.0 ± 0.3 V
RL = 500 W or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 6. Test Circuit
GND
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74ALVCH16374 (ON Semiconductor)
Low-Voltage 16-Bit D-Type Flip-Flop

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K
t
TOP
COVER
TAPE
B1 K0
SEE
NOTE 2
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B0
74ALVCH16374
10 PITCHES
CUMULATIVE
TOLERANCE ON
P0
TAPE
±0.2 mm
D P2 (±0.008")
E
A0 SEE NOTE 2
+ B0
+
P
EMBOSSMENT
USER DIRECTION OF FEED
FW
+
CENTER LINES
OF CAVITY
D1
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
BENDING RADIUS
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS R"
WITHOUT DAMAGE
EMBOSSED
CARRIER
*TOP COVER
TAPE THICKNESS (t1)
0.10 mm
(0.004") MAX.
EMBOSSMENT
10° MAXIMUM COMPONENT ROTATION
TYPICAL
COMPONENT CAVITY
CENTER LINE
100 mm
(3.937")
1 mm MAX
TAPE
TYPICAL
COMPONENT
CENTER LINE
1 mm
250 mm
(0.039") MAX (9.843")
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 7. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)
Tape
Size
B1
Max
D
D1 E
F
K
P P0 P2 R T W
24mm 20.1mm 1.5 + 0.1mm 1.5mm
1.75
11.5 11.9 mm 16.0
4.0
2.0 30 mm 0.6 mm 24.3 mm
(0.791")
−0.0
Min ±0.1 mm ±0.10 mm Max ±0.1 mm ±0.1 mm ±0.1 mm (1.18") (0.024") (0.957")
(0.059
(0.060") (0.069 (0.453 (0.468") (0.63
(0.157 (0.079
+0.004" −0.0)
±0.004") ±0.004")
±0.004") ±0.004") ±0.004")
13. Metric Dimensions GovernEnglish are in parentheses for reference only.
14. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity.
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74ALVCH16374 (ON Semiconductor)
Low-Voltage 16-Bit D-Type Flip-Flop

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74ALVCH16374
A 20.2 mm MIN
(0.795")
1.5 mm MIN
(0.06")
13.0 mm ±0.2 mm
(0.512" ±0.008")
t MAX
50 mm MIN
(1.969")
FULL RADIUS
Figure 8. Reel Dimensions
G
REEL DIMENSIONS
Tape Size A Max
24 mm
360 mm
(14.173")
G
24.4 mm + 2.0 mm, −0.0
(0.961" + 0.078", −0.00)
t Max
30.4 mm
(1.197")
DIRECTION OF FEED
BARCODE LABEL
POCKET
Figure 9. Reel Winding Direction
HOLE
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74ALVCH16374 (ON Semiconductor)
Low-Voltage 16-Bit D-Type Flip-Flop

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74ALVCH16374
CAVITY TOP TAPE
TAPE
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
COMPONENTS
DIRECTION OF FEED
Figure 10. Tape Ends for Finished Goods
TAPE LEADER
NO COMPONENTS
400 mm MIN
User Direction of Feed
Figure 11. Reel Configuration
ÉÉÉÉÉÉK ÉÉÉÉÉÉÉÉÉÉÉÉ
L 48 Leads
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
F
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
G
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
Figure 12. Package Footprint
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74ALVCH16374 (ON Semiconductor)
Low-Voltage 16-Bit D-Type Flip-Flop

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74ALVCH16374
PACKAGE DIMENSIONS
48
L
1
PIN 1
IDENT.
D
0.076 (0.003)
TSEATING
PLANE
C
TSSOP
DT SUFFIX
CASE 120101
ISSUE A
48X K REF
0.12 (0.005) M T U S
A
V
G
VS
25
24
J JÇÇÇÉÉÉ1 ÇÇÇÉÉÉKK1ÇÇÇÉÉÉ
SECTION NN
B
U
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
FM
DETAIL E 0.25 (0.010)
DETAIL E
H
W
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 12.40 12.60 0.488 0.496
B 6.00 6.20 0.236 0.244
C −−− 1.10 −−− 0.043
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.50 BSC
0.0197 BSC
H 0.37 −−− 0.015 −−−
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.17 0.27 0.007 0.011
K1 0.17 0.23 0.007 0.009
L 7.95 8.25 0.313 0.325
M 0_ 8_ 0_ 8_
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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