ICS8714008I (Integrated Device Technology)
Zero Delay Buffer/ Clock Generator

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FemtoClock® Zero Delay Buffer/ Clock
Generator for PCI Express™ and Ethernet
ICS8714008I
DATASHEET
General Description
The ICS8714008I is Zero-Delay Buffer/Frequency Multiplier with
eight differential HCSL output pairs, and uses external feedback
(differential feedback input and output pairs) for “zero delay” clock
regeneration. In PCI Express and Ethernet applications, 100MHz
and 125MHz are the most commonly used reference clock
frequencies and each of the eight output pairs can be independently
set for either 100MHz or 125MHz. With an output frequency range of
98MHz to 165MHz, the device is also suitable for use in a variety of
other applications such as Fibre Channel (106.25MHz) and XAUI
(156.25MHz). The M-LVDS Input/Output pair is useful in backplane
applications when the reference clock can either be local (on the
same board as the ICS8714008I) or remote via a backplane
connector. In output mode, an input from a local reference clock
applied to the CLK, nCLK input pins is translated to M-LVDS and
driven out to the MLVDS, nMLVDS pins. In input mode, the internal
M-LVDS driver is placed in High-impedance state using the
OE_MLVDS pin and MLVDS, nMLVDS pin then becomes an input
(e.g. from a backplane).
The ICS8714008I uses very low phase noise FemtoClock
technology, thus making it ideal for such applications as PCI Express
Generation 1, 2 and 3 as well as for Gigabit Ethernet, Fibre Channel,
and 10 Gigabit Ethernet. It is packaged in a 56-VFQFN package
(8mm x 8mm).
Features
Eight 0.7V differential HCSL output pairs, individually selectable
for 100MHz or 125MHz for PCIe and Ethernet applications
One differential clock input pair CLK, nCLK can accept the
following differential input levels: LVPECL, LVDS, M-LVDS,
LVHSTL, HCSL
One M-LVDS I/O pair (MLVDS, nMLVDS)
Output frequency range: 98MHz - 165MHz
Input frequency range: 19.6MHz - 165MHz
VCO range: 490MHz - 660MHz
PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s)
jitter compliant
External feedback for “zero delay” clock regeneration
RMS phase jitter @ 125MHz (1.875MHz – 20MHz):
0.59ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Lead-free (RoHs 6) packaging
Pin Assignment
VDD
OE_MLVDS
MLVDS
nMLVDS
GND
PLL_SEL
VDD
nc
FBO_DIV
MR
OE0
OE1
OE2
GND
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1 42
2 41
3 40
4 39
5 38
6 37
7 36
8 35
9 34
10 33
11 32
12 31
13 30
14 29
15 17 18 21 24 25 27 28
VDD
Q2
nQ2
Q3
nQ3
VDD
Q4
nQ4
Q5
nQ5
FBOUT
nFBOUT
VDD
IREF
ICS8714008DKI REVISION A NOVEMBER 25, 2013
ICS8714008I
56-Lead VFQFN
8mm x 8mm x 0.925mm package body
4.5mm x 5.2mm ePad size
K Package
Top View
1 ©2013 Integrated Device Technology, Inc.


ICS8714008I (Integrated Device Technology)
Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Block Diagram
MR1
PDIV1
PDIV0
CLK
nCLK
MR1
OE_MLVDS
MLVDS
nMLVDS
Pulldown
Pulldown
Pulldown
Pulldown
PU/PD
Pulldown
Pullup
PDIV1:0
00 ÷4 (default)
01 ÷5
10 ÷8
11 ÷1
FBI_DIV1
FBI_DIV0
FBIN
nFBIN
Pullup
Pullup
Pulldown
PU/PD
MR1 Pulldown
PLL_SEL
MR1
Pullup
Pulldown
FBI_DIV1:0
00 ÷1
01 ÷2
10 ÷4
11 ÷5 (default)
QDIV0
0 ÷4 (default)
1 ÷5
3
OE2:0 (PU:PU)
QDIV0 (PD)
Q0
nQ0
0
PD
VCO
490-660MHz
1
QDIV7
0 ÷4 (default)
1 ÷5
FBO_DIV
0 ÷4 (default)
1 ÷5
8 total HCSL Output pairs
QDIV7 (PD)
Q7
nQ7
FBO_DIV (PD)
FBOUT
nFBOUT
IREF
1One Master Reset pin (MR) is used to reset all the internal dividers, but the MR lines are not drawn as all tied together to reduce control line clutter, making the block diagram
easier to read.
PU means internal pull-up resistor on pin (power-up default is HIGH if not externally driven)
PD means internal pull-down resistor on pin (power-up default is LOW if not externally driven)
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 7, 30, 37,
42, 45
VDD
Power
Core supply pins.
2
OE_MLVDS
Input
Pullup
Active High Output Enable. When HIGH, the M-LVDS output driver is active
and provides a buffered copy of reference clock applied the CLK, nCLK
input to the MLVDS, nMLVDS output pins. The MLVDS, nMLVDS
frequency equals the CLK, nCLK frequency divided by the PDIV Divider
value (selectable ÷1, ÷4, ÷5, ÷8). When LOW, the M-LVDS output driver is
placed into a High-impedance state and the MLVDS, nMLVDS pins can
accept a differential input. LVCMOS/LVTTL interface levels.
3
MLVDS
I/O
Non-Inverting M-LVDS input/output. The input/output state is determined by
the OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and
drives the non-inverting M-LVDS output. When OE_MLVDS = LOW, this pin
is an input and can accept the following differential input levels: M-LVDS,
LVDS, LVPECL, HSTL, HCSL.
4 nMLVDS
5, 14, 19
GND
I/O
Power
Inverting M-LVDS input/output. The input/output state is determined by the
OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives
the inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input
and can accept the following differential input levels: M-LVDS, LVDS,
LVPECL, HSTL, HCSL.
Power supply ground.
PLL select. Determines if the PLL is in bypass or enabled mode (default). In
6
PLL_SEL
Input
Pullup
enabled mode, the output frequency = VCO frequency/QDIV divider. In
bypass mode, the output frequency = reference clock frequency/(PDIV
*QDIV). LVCMOS/LVTTL interface levels.
8, 26
nc Unused
No internal connection.
Output Divider Control for the feedback output pair, FBOUT, nFBOUT.
9
FBO_DIV
Input
Pulldown Determines if the output divider = ÷4 (default), or ÷5. Refer to Table 3D.
LVCMOS/LVTTL interface levels.
Active High master reset. When logic HIGH, the internal dividers are reset
causing all the true outputs Qx to drive High-impedance. Note that assertion
10
MR
Input
Pulldown
of MR overrides the OE[2:0] control pins and all outputs are disabled. When
logic LOW, the internal dividers are enabled and the state of the outputs are
determined by OE[2:0]. MR must be asserted on power-up to ensure
outputs phase aligned. LVCMOS/LVTTL interface levels.
Output Enable. Together with OE1 and OE2, determines the output state of
the outputs with the default state: all output pairs switching. It should also be
11
OE0
Input
Pullup noted that the feedback output pins (FBOUT, nFBOUT) are always
switching and are not affected by the state of OE[2:0]. Refer to Table 3B for
truth table. LVCMOS/LVTTL Interface levels.
Output Enable. Together with OE0 and OE2, determines the output state of
the outputs with the default state: all output pairs switching. It should also be
12
OE1
Input
Pullup noted that the feedback output pins (FBOUT, nFBOUT) are always
switching and are not affected by the state of OE[2:0]. Refer to Table 3B for
truth table. LVCMOS/LVTTL Interface levels.
Output Enable. Together with OE0 and OE1, determines the output state of
the outputs with the default state: all output pairs switching. It should also be
13
OE2
Input
Pullup noted that the feedback output pins (FBOUT, nFBOUT) are always
switching and are not affected by the state of OE[2:0]. Refer to table 3B for
truth table. LVCMOS/LVTTL Interface levels.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Table 1. Pin Descriptions
Number
Name
15 FBI_DIV0
16
17
18
20
21
22
23
24, 25
27, 28
29
31,
32
33, 34
35, 36
38, 39
40, 41
43, 44
46, 47
48
49
50
51
52
53
FBI_DIV1
nFBIN
FBIN
QDIV0
QDIV1
QDIV2
QDIV3
Q7, nQ7
Q6, nQ6
IREF
nFBOUT,
FBOUT
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
QDIV7
QDIV6
QDIV5
QDIV4
VDDA
CLK
Type
Input
Pullup
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input
Pullup
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Power
Input
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Description
Feedback Input Divide Select 0. Together with FBI_DIV1, determines the
feedback input divider value. Refer to Table 3C.
LVCMOS/LVTTL interface levels.
Feedback Input Divide Select 1. Together with FBI_DIV0, determines the
feedback input divider value. Refer to Table 3C.
LVCMOS/LVTTL interface levels.
Inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.”
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.”
Output Divider Control for Q0, nQ0. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q1, nQ1. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q2, nQ2. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q3, nQ3. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
An external fixed resistor from this pin to ground is needed to provide a
reference current for the differential HCSL outputs. A resistor value of 475
provides an HCSL voltage swing of approximately 700mV.
Differential feedback output pair. The feedback output pair always switches
independent of the output enable settings on the OE[2:0] pins.
HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Output Divider Control for Q7, nQ7. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q6, nQ6. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q5, nQ5. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Output Divider Control for Q4, nQ4. Refer to Table 3E.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Non-inverting differential clock input.
Accepts LVPECL, HCSL, LVDS, M-LVDS and HSTL input levels.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Table 1. Pin Descriptions
Number
Name
Type
Description
54
nCLK
Input
Pullup/ Inverting differential clock input.
Pulldown Accepts LVPECL, HCSL, LVDS, M-LVDS and HSTL input levels.
55
PDIV0
Input
Pulldown
Input Divide Select 0. Together with PDIV1 determines the input divider
value. Refer to Table 3F. LVCMOS/LVTTL Interface levels.
56
PDIV1
Input
Pulldown
Input Divide Select 1. Together with PDIV0 determines the input divider
value. Refer to Table 3F. LVCMOS/LVTTL Interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLUP
RPULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Function Tables
Table 3A. Common Configuration Table (not exhaustive)NOTE 1
Input
Output
Frequency Frequency Application
Frequency
Mult. Factor
100MHz
100MHz PCIe Buffer
1
125MHz
125MHz PCIe, Ethernet Buffer
1
100MHz
125MHz PCIe Multiplier
5/4
125MHz
100MHz PCIe Divider
4/5
25MHz
100MHz PCIe Multiplier
4
25MHz
125MHz PCIe, Ethernet Multiplier
5
25MHz
156.25MHz XAUI Multiplier
25/4
62.5MHz
125MHz Ethernet Multiplier
2
53.125MHz 106.25MHz Fibre Channel Multiplier
2
PDIV
÷1
÷1
÷1
÷1
÷1
÷1
÷1
÷1
÷1
FBI_DIV
÷1
÷1
÷1
÷1
÷4
÷4
÷5
÷2
÷2
FBO_DIV
÷5
÷4
÷5
÷4
÷5
÷5
÷5
÷4
÷5
QDIVx
÷5
÷4
÷4
÷5
÷5
÷4
÷4
÷4
÷5
NOTE 1: This table shows more common configurations and is not exhaustive. When using alternate configurations, the designer must ensure
the VCO frequency is always within its range of 490MHz – 660MHz.
Table 3B. Output Enable Truth Table
Inputs
OE2
OE1
OE0
000
001
010
011
100
101
110
111
State
Q[0:7], nQ[0:7]
Q0, nQ0 switching; Q[1:7], nQ[1:7] = High-impedance
Q[0:1], nQ[0:1] switching; Q[2:7], nQ[2:7] = High-impedance
Q[0:2], nQ[0:2] switching; Q[3:7], nQ[3:7] = High-impedance
Q[0:3], nQ[0:3] switching; Q[4:7], nQ[4:7] = High-impedance
Q[0:4], nQ[0:4] switching; Q[5:7], nQ[5:7] = High-impedance
Q[0:5], nQ[0:5] switching; Q[6:7], nQ[6:7] = High-impedance
Q[0:6], nQ[0:6] switching; Q7, nQ7 = High-impedance
All output pairs switching (default)
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Table 3C. Feedback Input Divider Control Table
Inputs
FBI_DIV1
FBI_DIV0 Feedback Input Divider Values
00
÷1
01
÷2
10
÷4
11
÷5 (default)
Table 3D. Feedback Output Divider Control Table
Inputs
FBO_DIV
Feedback Output Divider Value
0 ÷4 (default)
1 ÷5
Table 3E. Output Divider Control Control Table
Inputs
QDIV[7:0]
Output Divider Value
0 ÷4 (default)
1 ÷5
Table 3F. Input Divide Select Control Table
Inputs
PDIV1
PDIV0
Input Divider Values
00
÷4 (default)
01
÷5
10
÷8
11
÷1
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VDD
Inputs, VI
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
Rating
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
26.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VDD
VDDA
IDD
IDDA
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Outputs Unloaded
Outputs Unloaded
3.135
3.135
Typical
3.3
3.3
170
11
Maximum
3.465
3.465
210
15
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VIH Input High Voltage
VIL Input Low Voltage
IIH
Input
High Current
MR, PDIV[1:0],
QDIV[7:0], FBO_DIV
PLL_SEL, OE_MLVDS,
FBI_DIV[1:0], OE[2:0]
VDD = VIN = 3.465V
VDD = VIN = 3.465V
2.2
-0.3
IIL
Input
Low Current
MR, PDIV[1:0],
QDIV[7:0], FBO_DIV
PLL_SEL, OE_MLVDS,
FBI_DIV[1:0], OE[2:0]
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
-150
Typical
Maximum
VDD + 0.3
0.8
Units
V
V
150 µA
5 µA
µA
µA
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
IIH
Input High
Current
CLK, nCLK,
FBIN, nFBIN
VDD = VIN = 3.465V
IIL
Input Low
Current
CLK, FBIN
nCLK, nFBIN
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
-150
VPP
Peak-to-Peak Voltage;
NOTE 1
0.15
VCMR
Common Mode Input
Voltage; NOTE 1, 2
GND + 0.5
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. M-LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
370
0.3
Typical
Typical
410
2.1
Maximum
150
1.3
Units
µA
µA
µA
V
VDD – 0.85
V
Maximum
470
50
2.3
50
Units
mV
mV
V
mV
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
AC Electrical Characteristics
Table 5A. PCI Express Jitter Specifications, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
tj
(PCIe Gen 1)
tREFCLK_HF_RMS
(PCIe Gen 2)
tREFCLK_LF_RMS
(PCIe Gen 2)
tREFCLK_RMS
(PCIe Gen 3)
Parameter
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
Phase Jitter
RMS; NOTE 2, 4
Phase Jitter
RMS; NOTE 2, 4
Phase Jitter
RMS;
NOTE 3, 4
Test Conditions
ƒ= 100MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ= 125MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ= 100MHz,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ= 125MHz,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ= 100MHz,
Low Band: 10kHz - 1.5MHz
ƒ= 125MHz,
Low Band: 10kHz - 1.5MHz
ƒ= 100MHz
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ= 125MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum
Typical
20
12
2
0.8
0.10
0.10
0.5
0.2
PCIe Industry
Maximum Specification Units
30 86 ps
25 86 ps
3 3.1 ps
1.4 3.1 ps
0.30 3.0 ps
0.25 3.0 ps
0.7 0.8 ps
0.3 0.8 ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Table 5B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
fOUT
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
tsk(o)
Output Skew; NOTE 1, 2
Outputs measured Q[0:7], nQ[0:7]
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3, 4
125MHz, Integration Range:
1.875MHz – 20MHz
100MHz, Integration Range:
1.875MHz – 20MHz
tL
VMAX
PLL Lock Time
Absolute Max Output Voltage;
NOTE 5, 6
VMIN
Absolute Min Output Voltage;
NOTE 5, 7
VRB
tSTABLE
Ringback Voltage; NOTE 8, 9
Time before VRB is allowed;
NOTE 8, 9
VCROSS
Absolute Crossing Voltage;
NOTE 5, 10, 11
VCROSS
Total Variation of VCROSS over
all edges; NOTE 5, 10, 12
Rise/Fall Rising/Falling Edge Rate;
Edge Rate NOTE 8, 13
Measured between
-150mV to +150mV
odc Output Duty Cycle; NOTE 14
Minimum
98
-300
-100
500
150
0.6
45
Typical
35
100
0.587
0.592
Maximum
165
80
210
Units
MHz
ps
ps
ps
100
1150
ps
ms
mV
mV
100 mV
ps
550 mV
140 mV
4 V/ns
55 %
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. Characterized with configurations in Table 3A.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Refer to the Phase Noise plots.
NOTE 4: Measurements depend on input source used.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8: Measurement taken from a differential waveform.
NOTE 9: tSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range. See Parameter Measurement Information Section.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
VCROSS for any particular system. See Parameter Measurement Information Section.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
See Parameter Measurement Information Section.
NOTE 14: Input duty cycle must be 50%.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Typical Phase Noise at 125MHz
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.587ps (typical)
Offset Frequency (Hz)
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Typical Phase Noise at 100MHz
100MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.592ps (typical)
Offset Frequency (Hz)
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Parameter Measurement Information
3.3V±5%
VDD,
VDDA
HCSL
IREF
GND
475Ω
33Ω
33Ω
49.9Ω
49.9Ω
50Ω
50Ω
Qx 450Ω
SCOPE
2pF
nQx 450Ω
2pF
0V
This load condition is used for VMAX, VMIN, VRB, tSTABLE, VCROSS,
VCROSS and Rise/Fall Edge Rate measurements.
3.3V HCSL Output Load Test Circuit
3.3V±5%
VDD,
VDDA
HCSL
IREF
GND
SCOPE
0V 0V
This load condition is used for tjit(cc), tjit(Ø) and tsk(o)
measurements.
3.3V HCSL Output Load Test Circuit
3.3V±5%
POWER SUPPLY
+ Float GND –
VDD,
VDDA
SCOPE
Qx
nQx
VDD
nCLK, nFBIN
CLK, FBIN
V
PP
GND
Cross Points
3.3V M-LVDS Output Load Test Circuit
Differential Input Level
V
CMR
nQx
Qx
nQy
Qy
Output Skew
ICS8714008DKI REVISION A NOVEMBER 25, 2013
nQ0:Q7,
nFBOUT
Q0:Q7
FBOUT
tcycle n
tcycle n+1
| |tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Parameter Measurement Information, continued
VDD
DC Input M-LVDS
out
out VOS/Δ VOS
RMS Phase Jitter
M-LVDS Offset Voltage Setup
VDD
DC Input M-LVDS
100
out
100 VOD/Δ VOD
out
M-LVDS Differential Output Voltage Setup
Differential Measurement Points for Ringback
Single-ended Measurement Points for Delta Cross Point
Single-ended Measurement Points for Absolute Cross
Point/Swing
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Parameter Measurement Information, continued
Differential Measurement Points for Duty Cycle/Period
Differential Measurement Points for Rise/Fall Time
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Applications Information
Overview
The is a high performance FemtoClock Zero Delay Buffer/
Multiplier/Divider which uses external feedback for accurate clock
regeneration and low static and dynamic phase offset. It can be used
in a number different ways:
• Backplane clock multiplier. Many backplane clocks are relatively
low frequency because of heavy electrical loading. The
ICS8714008I can multiply a low frequency backplane clock (e.g.
25MHz) to an appropriate reference clock frequency for PCIe,
Ethernet, 10G Ethernet: 100MHz, 125MHz, 156.25MHz. The
device can also accept a high frequency local reference
(100MHz or 125MHz, for example) and divide the frequency
down to 25MHz M-LVDS to drive a backplane.
• PCIe frequency translator for PCIe add-in cards. In personal
computers, the PCIe reference clock is 100MHz, but some 2.5G
serdes used in PCI Express require a 125MHz reference. The
ICS8714008I can perform the 100MHz 125MHz and
125MHz 100MHz frequency translation for a PCI Express
add-in card while delivering low dynamic and static phase
offset.
• General purpose, low phase noise Zero Delay Buffer
Configuration Notes and Examples
When configuring the output frequency, the main consideration is
keeping the VCO within its range of 490MHz - 660MHz. The designer
must ensure that the VCO will always be within its allowed range for
the expected input frequency range by using the appropriate choice
of feedback output and input dividers. There are two input modes for
the device. In the first mode, a reference clock is provided to the CLK,
nCLK frequency input and this reference clock is divided by the value
of the PDIV divider (selectable ÷1, ÷4, ÷5, ÷8). In the second mode,
a reference clock is provided to the MLVDS, nMLVDS input pair.
OE_MLVDS determines the input mode. When OE_MLVDS = HIGH
(default), the M-LVDS driver is active and provides an M-LVDS output
to the MLVDS, nMLVDS pins and also the reference to the phase
detector via the PDIV divider. When OE_MLVDS is LOW, the internal
M-LVDS driver is in a High-impedance state and the MLVDS,
nMLVDS pin pair becomes an input and the reference clock applied
to this input is applied to the phase detector.
MLVDS, nMLVDS Output Mode
OE_MLVDS = HIGH (default)
VCO frequency =
CLK, nCLK frequency * FBI_DIV * FBO_DIV/ (PDIV value)
Allowed VCO frequency = 490MHz - 660MHz
Output frequency = VCO frequency/QDIVx value =
CLK, nCLK freq. * FBI_DIV * FBO_DIV/(PDIV*QDIVx)
Example: a frequency synthesizer provides a 125MHz reference
clock to CLK, nCLK frequency input. The ICS8714008I must provide
a 25MHz M-LVDS clock to the backplane and also provide two local
clocks: one 100MHz HCSL output to an ASIC and one 125MHz
output to the PCI Express serdes.
Solution: Since only two outputs are needed, the two unused outputs
can be disabled. Set OE[2:0] = 001b so that only Q0, nQ0 and Q1,
nQ1 are switching. Since a 25MHz backplane clock is needed from a
125MHz reference clock, set PDIV = ÷5 and OE_MLVDS = HIGH to
enable the M-LVDS driver. 25MHz is applied to the MLVDS, nMLVDS
pins and to the phase detector input. Set FBO_DIV = 4 and FBI_DIV
= 5 which makes the VCO run at 500MHz (25MHz * 4 * 5 = 500MHz).
Set QDIV0 = 0 (÷4) for 125MHz output and QDIV1 = 1 (÷5) for
100MHz output. To figure out what pins must pulled up or down
externally with resistors, check the internal pullup or pulldown
resistors on each pin in the pin description table or on the block
diagram. PDIV[1:0] defaults to 00/÷4 and we need 01/÷5. So PDIV1
can be left floating (it has an internal pulldown resistor) and PDIV0
must be driven or pulled up via external pullup resistor to HIGH state.
OE_MLVDS defaults to Logic 1 (active) and this is what we need, so
that pin can be left floating. The FBO_DIV and FBIN dividers default
to the desired values, so their respective control pins can be left
floating (FBO_DIV and FBI_DIV[1:0]). QDIV0 needs to be ÷4, which
is a default value so this pin can be left floating. QDIV1 must be HIGH
for ÷5, so this pin must be pulled high or driven high externally.
OE[2:0] = 001, so OE0 can Float and OE[2:1] must be pulled Low.
MLVDS, nMLVDS Input Mode
OE_MLVDS = LOW
VCO frequency = MLVDS, nMLVDS freq. * FBI_DIV * FBO_DIV
Output frequency = VCO frequency/QDIVx value = MLVDS,
nMLVDS freq. * FBI_DIV * FBO_DIV/(QDIVx)
Example - backplane: The 8714008I sits on a backplane card and
must multiply a 25MHz reference that comes from the backplane into
one 125MHz reference clock for a Gigabit Ethernet serdes and one
100MHz reference clock for a PCI Express serdes.
Solution. Since only two outputs are needed, the two unused outputs
can be disabled. Set OE[2:0] = 001b so that only Q0, nQ0 and Q1,
nQ1 are switching. Set OE_MLVDS = 0 so the internal M-LVDS driver
is in a High-impedance state, allowing the MLVDS, nMLVDS pins to
function as an input for the 25MHz clock reference. Set FBO_DIV =
4 and FBI_DIV = 5 which makes the VCO run at 500MHz (25MHz *
4 * 5 = 500MHz). Set QDIV0 = 0 (÷4) for 125MHz output and QDIV1
= 1 (÷5) for 100MHz output. To figure out what pins must pulled up or
down externally with resistors, check the internal pullup or pulldown
resistors on each pin in the pin description table or on the block
diagram. PDIV[1:0] defaults to 00/÷4 and we need 01/÷5. So PDIV1
can be left floating (it has an internal pulldown resistor) and PDIV0
must be driven or pulled up via external pullup resistor to HIGH state.
OE_MLVDS defaults to Logic 1(active) and this is what we need, so
that pin can be left floating. The FBO_DIV and FBIN dividers default
to the desired values, so their respective control pins can be left
floating (FBO_DIV and FBI_DIV[1:0]). QDIV0 needs to be ÷4, which
is a default value so this pin can be left floating. QDIV1 must be HIGH
for ÷5, so this pin must be pulled high or driven high externally.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
OE[2:0] = 001, so OE0 can Float and OE[2:1] must be pulled Low.
25 MHz
MLVDS
MLVDS
Master Clock Card
ICS8714008I
÷4
CLK
CLK
100 MHz HCSL
SSC Synthesizer
ICS841402I
FemtoClock
VCO
100 MHz HCSL
FPGA
125 MHz HCSL
PCIe Serdes
Backplane
25 MHz
MLVDS
Slave Clock Card
ICS8714008I
÷4
CLK
CLK
Slave synthesizer
Off or output disabled
SSC Synthesizer
ICS841402I
FemtoClock
VCO
100 MHz HCSL
FPGA
125 MHz HCSL
PCIe Serdes
Figure 1. Example Backplane Application
Bold lines
indicate active clock path
This example shows a case where each card may be dynamically
configured as a master or slave card, hence the need for an
ICS8714008I and ICS841402I on each card. On the master timing
card, the ICS841402I provides a 100MHz reference to the
ICS8714008I CLK, nCLK input. The M-LVDS pair on the
ICS8714008I is configured as an output (OE_MLVDS = Logic 1) and
the internal divider is set to ÷4 to generate 25MHz M-LVDS to the
backplane. The 25MHz clock is also used as a reference to the
FemtoClock PLL which multiplies to a VCO frequency of 500MHz.
Each of the four output pairs may be individually set for ÷4 or ÷5 for
125MHz or 100MHz operation respectively and in this example, one
output pair is set to 100MHz for the FPGA and another output pair is
set to 125MHz for the PCI Express serdes. For the slave card, the
M-LVDS pair is configured as an input (OE_MLVDS = LOW) and the
FemtoClock PLL multiplies this reference frequency to 500MHz VCO
frequency and the output dividers are set to provide 100MHz to the
FPGA and 125MHz to the PCI Express Serdes as shown.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1 = VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1 in the center of the input voltage swing.
For example, if the input clock swing is 3.3V and VDD = 3.3V, R1 and
R2 value should be adjusted to set V1 at 1.25V. The values below are
for when both the single ended swing and VDD are at the same
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 3A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 3B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
VCC
R1
100
Ro Rs Zo = 50 ohms
Zo = Ro + Rs
LVCMOS Driver
R2
100
XTAL_OUT
C1
XTAL_IN
.1uf
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
Zo = 50 ohms
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
C2
XTAL_IN
.1uf
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 4A to 4F show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 4A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1 R2
50Ω 50Ω
nCLK
Differential
Input
Figure 4A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1 R2
50Ω 50Ω
nCLK
Differential
Input
R2
50Ω
Figure 4B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
LVPECL
3.3V
3.3V
CLK
nCLK
Differential
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 4C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
*R3
HCSL
*R4
3.3V
CLK
nCLK
Differential
Input
Figure 4D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
3.3V
MLVDS
Zo = 50Ω
R2
100Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 4E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
ICS8714008DKI REVISION A NOVEMBER 25, 2013
Figure 4F. CLK/nCLK Input Driven by a
3.3V MLVDS Driver
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
PIN SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE
THERMAL VIA
LAND PATTERN
(GROUND PAD)
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kresistor can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kresistor can be tied from CLK to ground.
MLVDS/nMLVDS Inputs
For applications not requiring the use of the differential input, both
MLVDS and nMLVDS can be left floating. Though not required, but for
additional protection, a 1kresistor can be tied from MLVDS to
ground.
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
M-LVDS Outputs
All unused M-LVDS output pairs can be either left floating or
terminated with 100across. If they are left floating, there should be
no trace attached.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Recommended Termination
Figure 7A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™and HCSL output types.
All traces should be 50impedance single-ended or 100
differential.
0.5" Max
L1
Rs
22 to 33 +/-5%
0-0.2"
L2
PCI Expres s
Driver
L1
L2
0-0.2" L3 L3
1-14"
L4
L4
PCI Expres s
C o n n e cto r
0.5 - 3.5"
L5
L5
PCI Expres s
Add-in Card
Rt 49.9 +/- 5%
Figure 7A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 7B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0to 33. All traces should be 50
impedance single-ended or 100differential.
0.5" Max
L1
L1
PCI Expres s
Driver
Rs
0 to 33
0 to 33
0-18"
L2
L2
Rt
0-0.2"
L3
L3
49.9 +/- 5%
Figure 7B. Recommended Termination (where a point-to-point connection can be used)
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I (Integrated Device Technology)
Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows the
most frequently used Common Clock Architecture in which a copy of
the reference clock is provided to both ends of the PCI Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
Hts= H3s  H1sH2s
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Ys= Xs  H3s  H1sH2s
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
PCIe Gen 2A Magnitude of Transfer Function
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen 2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and the
evaluation is performed over the entire spectrum. The transfer
function parameters are different from Gen 1 and the jitter result is
reported in RMS.
PCIe Gen 1 Magnitude of Transfer Function
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
PCIe Gen 3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note PCI Express
Reference Clock Requirements.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I (Integrated Device Technology)
Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Schematic Example
Figure 9 (next page) shows an example ICS8714008DI application
schematic. The schematic example focuses on functional
connections and is not configuration specific. Refer to the pin
description and functional tables in the datasheet to ensure the logic
control inputs are properly set. Input and output terminations shown
are also intended as examples only and may not represent the exact
user configuration.
In this particular schematic the MLVDS port is in output mode,
configured by setting OE_MLVDS = 1. Since the zero delay function
is local to the chip, the FBOUT to FBIN connection is a special case
of a point to point PCIe link. The close proximity of these two ports
means that the 33series resistors are not necessary and the 49.9
termination resistors are to be placed at the FBIN port.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS8714008DI provides
separate VDD, VDDO and VDDA power supplies to isolate any high
switching noise from coupling into the internal PLL.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1µF capacitors be placed on the device side
of the PCB as close to the power pins as possible. This is
represented by the placement of these capacitors in the schematic.
If space is limited, the ferrite bead, 10µF and 0.1µF capacitors
connected to 3.3V can be placed on the opposite side of the PCB. If
space permits, place all filter components on the device side of the
board.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I (Integrated Device Technology)
Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
 
Logic Control Input Examples
Set Logic
Set Logic
VD D Input to '1' V DD Input to '0'
RU1
1K
To Logic
Input
pins
RD1
N ot I ns t all
RU2
N ot I ns t al l
To Logic
Input
pins
RD2
1K
VD D
C2
10 u F
VD D A 2
FB2
1
C3
1 0uF
B LM18BB22 1S N 1
3 .3 V
FB 1
21
BLM18BB 22 1SN 1
C1
0 .1uF
U1
OE_MLV DS
O E0
2
11
OE_ML VD S
O E1
O E2
12 OE0
13 OE1
O E2
MR
PL L_S EL
10
6 MR
PLL _SEL
FBI _D IV 0
FBI _D IV 1
FBO_D IV
15
16 FB I_D I V0
9 FB I_D I V1
FB O_D I V
PD I V0
PD I V1
QD IV0
QD IV1
QD IV2
QD IV3
QD IV4
QD IV5
QD IV6
QD IV7
55
56 PD I V0
PD I V1
20
21 QD IV 0
22 QD IV 1
23 QD IV 2
51 QD IV 3
50 QD IV 4
49 QD IV 5
48 QD IV 6
QD IV 7
T o M LV DS bus
ML VD S
nMLVD S
3
ML VD S
4
nMLV D S
OE_MLVDS = 1
to select
MLVDS output
Zo = 50 Ohm
CLK 53
R1 CLK
Zo = 50 Ohm
1 00
nCLK 54
nC LK
LVD S D riv e r
R13
49. 9
R 12
49 . 9
18
FB IN
17
nFBI N
52
V D DA
47
Q0 46
nQ0
44
Q1 43
nQ1
41
Q2 40
nQ2
39
Q3 38
nQ3
36
Q4 35
nQ4
34
Q5 33
nQ5
27
Q6 28
nQ6
24
Q7 25
nQ7
IR EF
nc
29
8
FBOU T
nFBOU T
32
31
VD D
C4
0. 1 uF
C6 C7
0.1 uF 0 .1uF
C8
0 .1 u F
C9
0. 1uF
C 10
0. 1 uF
C11
0.1 uF
V DD A
C5
0. 1u F
R6 33
R9 33
R7
50
Place each 0.1uF bypass cap directly
adjacent to its corresponding VDD or
VDDA pin.
1" to 14"
Zo = 50
0.5" to 3.5"
Z o = 50
+
Zo = 50
R4
50
Z o = 50
-
H C SL_Rec e iv er
PCI Express Add-In Card
HCSL Termination
R3 33
R2 33
Optional
R11
475
0" to 18"
Zo = 50
Zo = 50
R8
50
+
-
HC S L_R e ceiv er
R5
50 PCI Express
P oi n t-to -P o i n t
Connec tion
Figure 9. ICS8714008I Schematic Example
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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ICS8714008I (Integrated Device Technology)
Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8714008I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8714008I is the sum of the core power plus the analog power plus the output power dissipated due to
the load. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating output power dissipated due to the load.
• Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(210mA + 15mA) = 779.6mW
• Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 44.5mW = 400.5mW
Total Power_MAX = 779.6mW + 400.5mW = 1180.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 26.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.180W * 26.7°C/W = 116.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 56-Lead VFQFN, Forced Convection
JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
26.7°C/W
1
21.71°C/W
2
20.23°C/W
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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 10.
VDD
IOUT = 17mA
RREF =
475± 1%
VOUT
RL
50
IC
Figure 10. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50load to ground.
The highest power dissipation occurs when VDD_MAX.
Power = (VDD_MAX – VOUT) * IOUT,
since VOUT = IOUT * RL
= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44.5mW
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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Zero Delay Buffer/ Clock Generator

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Reliability Information
Table 7. JA vs. Air Flow Table for a 56-Lead VFQFN
JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
26.7°C/W
Transistor Count
The transistor count for ICS8714008I is: 4962
1
21.71°C/W
2
20.23°C/W
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