MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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MOTOROLA
Order this document
by MCI431 50/D
_ SEMICONDUCTOR - - - - - - - - - - - - - -
TECHNICAL DATA
MC143150
MC143120
Advance Information
NEURON®CHIP Distributed Communications
and Control Processors
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(M_Cl_431_20_)
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COMMUNICATIONS
PORT
··CP4
CPO
1/0
SECTION
I TIMER I COUNTER 1
I ITIMER I COUNTER 2
1010
100
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r- - -r--------,
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INTERFACE
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(MCl43150)
1L--_- -__-
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CLOCK
CLOCK
CONTROL
© Motorola, Inc. 1993
MOTOROLA _
REV 2


MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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This document contains Information on a n_ product. Specifications and information herein are subject to change without notice.
This IC containsfirmware which has license restrictions. Sample NEURONS can be obtained from Motorola after signing a developers license agree-
ment with Echelon Corporation. Production procurement of the NEURON CHIPS can be acquired from Motorola only after signing an OEM license
agreement with Echelon Corporation.
Echelon, LON, and NEURON are registered trademarks of Echelon Corporation. LoNBulLDER, LONMANAGER, LONMARK, LoNTALK, LoNWORKS, and
NEUROWIRE are trademarks of Echelon Corporation.
Motorola reserves the right to make changes wRhcutfurther noticeto any products herein. Motorola makes no warranty. representation orguarantee regarding
the suRability of Rs products for any particular purpose, nor doea Motorola assume any liability arising out of the application or use of any product or circuit,
and specificallydisctaims anyand aliliabilRy, including wRhout limitation consequential orincidental damages. "Typical" parameters can and dovary in different
applications. All operating parameters, inctuding "Typicals" must be validated for each customer application by customer's technical experts. Motorola doea
not convey any license under Rs patent rights nor the rights of others. Motorola products are not deSigned, intended, or authorized for use as components
in systems intanded for surgical implant into the body, or other applications intanded to support or sustain life, or for any other application In which the failure
of the Motorola product could create a sRuetion where personal injury or death may occur. Shculd Buysr purchase or use Motorola products for any such
unintanded or unauthorized application, Buyer shall Indemnify and hold Motorola and Its ofIIcers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal Injury or death
®associated wRh such unintanded or unauthorized use, even Hsuch claim alleges that Motorola was negligent regarding the deSign or manufacture of the part.
Motorola and are registered trademar1<s of Motorola, Inc. Motorola, Inc. is an Equal OpportunRy/Affirmative Action Employer.
ii
MC143150'MC143120
MOTOROLA


MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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CONTENTS
Paragraph
Number
Title
Page
Number
SECTION 1
INTRODUCTION
1-1
SECTION 2
LONWORKS TECHNOLOGY OVERVIEW AND ARCHITECTURE
2-1
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.3
3.3.1
3.3.2
SECTION 3
NEURON CHIP PROCESSOR FAMILY-HARDWARE RESOURCES
PROCESSING UNITS ................................................. .
MEMORy ............................................................ .
Memory Allocation Overview .......................................... .
EEPROM .......................................................... .
Static RAM .......................................................... .
Preprogrammed ROM ............................................... .
External Memory Interface (MC143150 Only) ........................... .
INPUT/OUTPUT ...................................................... .
Eleven Bidirectional I/O Pins .......................................... .
Two 16-Bit Timer/Counters ........................................... .
3-1
3-7
3-7
3-7
3-8
3-8
3-8
3-10
3-10
3-12
4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.7
SECTION 4
NETWORK COMMUNICATIONS
INTRODUCTION ...................................................... .
SINGLE-ENDED MODE ................................................ .
DIFFERENTIAL MODE ................................................ .
SPECIAL-PURPOSE MODE ............................................ .
CLOCKING SYSTEM .................................................. .
Clock Generation ................................................... .
Assembly Instruction Set ............................................. .
ADDITIONAL FUNCTIONS ............................................. .
SleeplWake-Up Circuitry ............................................. .
Watchdog Timer .................................................... .
Power On Reset .................................................... .
Reset Processes and Timing ......................................... .
SERVICE PIN ......................................................... .
MOTOROLA
MC143150'MC143120
4-1
4-4
4-7
4-12
4-15
4-15
4-17
4-18
4-18
4-19
4-19
4-22
4-26
iii


MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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CONTENTS (Continued)
Paragraph
Number
Title
Page
Number
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.6
5.6.1
5.6.2
5.7
5.8
SECTION 5
INPUT/OUTPUT INTERFACES
HARDWARE CONSIDERATIONS ....................................... .
SOFTWARE CONSIDERATIONS ....................................... .
DIRECT OBJECTS (BIT I/O, BYTE I/O, LEVEL DETECT, AND NIBBLE) ......... .
Bitl/O ............................................................. .
Byte I/O ............................................................ .
Level Detect (Logic Low Level for Input >200 ns) ........................ .
Nibble I/O .......................................................... .
PARALLEL I/O INTERFACE OBJECT ...................................... .
Introduction ........................................................ .
Master/Slave A Mode ................................................ .
Slave B Mode ...................................................... .
Token Passing ...................................................... .
Handshaking ....................................................... .
Data Transferring ................................................... .
SERIALOBJECTS ..................................................... .
Bitshift I/O .......................................................... .
Magcard Input ...................................................... .
NEUROWIRE (SPI Interface) I/O Object ................................. .
Serial I/O ........................................................... .
TIMER/COUNTER OBJECTS ........................................... .
Timer/Counter Input Objects (Dualslope, Edgelog, Infrared, On-Time,
Period, Pulsecount Input, Quadrature, Totalcount) ....................... .
Timer/Counter Output Objects (Frequency, One-Shot, Pulsecount Output,
Pulsewidth, Triac, Triggered Count) .................................... .
MUXBUS I/O ......................................................... .
NOTES .............................................................. .
5-1
5-4
5-5
5-5
5-6
5-7
5-8
5-9
5-9
5-10
5-14
5-15
5-15
5-16
5-18
5-18
5-20
5-22
5-24
5-25
5-26
5-35
5-42
5-43
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.3
6.3.1
6.3.2
6.3.3
6.3.4
iv
SECTION 6
NEURON CHIP ELECTRICAL AND MECHANICAL SPECIFICATIONS
INTRODUCTION ...................................................... .
ELECTRICAL SPECIFICATIONS ........................................ .
Absolute Maximum Ratings ........................................... .
Recommended Operating Conditions .................................. .
Electrical Characteristics ............................................. .
External Memory Bus Timing - MC143150FU, VDD ± 10% .............. .
External Memory Bus Timing - MC143150FU, VDD ± 5% ............... .
External Memory Bus Timing - MC143150FU1, VDD ± 10% ............. .
MECHANICAL SPECIFICATIONS ....................................... .
MC143150 Pin Assignments .......................................... .
MC143150 Package Dimensions ...................................... .
MC143150 Pad Layout .............................................. .
MC143120 Pin Assignment ........................................... .
6-1
6-1
6-1
6-2
6-2
6-3
6-3
6-4
6-6
6-6
6-7
6-8
6-9
MC143150·MC143120
MOTOROLA


MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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CONTENTS (Continued)
Paragraph
Number
Title
Page
Number
6.3.5
6.3.6
6.3.7
MC143120 Package Dimensions ...................................... .
MC143120 Pad Layout .............................................. .
Sockets for NEURON CHIPS ........................................... .
6-9
6-10
6-10
SECTION 7
LONWORKS PROGRAMMING MODEL
7.1 TIMERS .............................................................. . 7-1
7.2 NETWORK VARIABLES ............................................... . 7-1
7.3 EXPLICIT MESSAGES ................................................ . 7-4
7.4 SCHEDULER ......................................................... . 7-7
7.5 ADDITIONAL LIBRARY FUNCTIONS .................................... . 7-8
7.6 BUILT-IN VARIABLES .................................................. . 7-9
7.7 MC1'43120 SYSTEM LIBRARy ......................................... . 7-9
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
SECTION 8
LONTALK PROTOCOL
MULTIPLE MEDIA SUPPORT .......................................... .
SUPPORT FOR MULTIPLE COMMUNICATION CHANNELS ............... .
COMMUNICATIONS RATES ............................................ .
LONTALK ADDRESSING LIMITS ......................................... .
MESSAGE SERVICES ................................................. .
AUTHENTICATION .................................................... .
PRIORITY ............................................................ .
COLLISION AVOIDANCE ....................... , ...................... .
COLLISION DETECTION .............................................. .
DATA INTERPRETATION .............................................. .
NETWORK MANAGEMENT AND DIAGNOSTIC SERVICES ................ .
8-1
8-1
8-1
8-2
8-2
8-3
8-3
8-3
8-4
8-4
8-4
A.1
A.U
A.2
A.2.1
A.3
A.3.1
A.3.2
A.3.3
A.3.4
A.3.5
A.3.6
A.3.7
A.3.8
APPENDIX A
NEURON CHIP CONFIGURATION DATA STRUCTURES
FIXED READ-ONLY DATA STRUCTURE ................................. .
Read-Only Structure Field Descriptions ................................ .
THE DOMAIN TABLE .................................................. .
Domain Table Field Descriptions ...................................... .
THE ADDRESS TABLE ................................................ .
Declaration of Group Address Format .................................. .
Group Address Field Descriptions ..................................... .
Declaration of Subnet/Node Address Format ............................ .
Subnet/Node Address Field Descriptions ............................... .
Declaration of Broadcast Address Format .............................. .
Broadcast Address Field Descriptions .................................. .
Declaration of Turnaround Address Format ............................. .
Turnaround Address Field Descriptions ................................ .
MOTOROLA
MC143150·MC143120
A-3
A-4
A-7
A-8
A-8
A-9
A-9
A-10
A-10
A-10
A-11
A-11
A-11
v


MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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CONTENTS (Concluded)
Paragraph
Number
Title
Page
Number
A.3.9
A3.10
A3.11
A.4
A.4.1
A.4.2
A5
A5.1
A.5.2
A.5.3
A.6
A.6.1
A.6.2
Declaration of NEURON ID Address Format ............................. .
NEURON ID Address Field Descriptions ................................. .
Timer Field Descriptions ............................................. .
NETWORK VARIABLE TABLES ......................................... .
Network Variable Configuration Table Field Descriptions .................. .
Network Variable Fixed Table Field Descriptions ......................... .
THE STANDARD NETWORK VARIABLE TYPE (SNVT) STRUCTURES ...... .
SNVT Structure Field Descriptions .................................... .
SNVT Descriptor Table Field Descriptions .............................. .
SNVT Table Extension Records ....................................... .
THE CONFIGURATION STRUCTURE ................................... .
Configuration Structure Field Descriptions .............................. .
Direct-Mode Transceiver Parameters Field Descriptions .................. .
A-11
A-12
A-12
A-13
A-14
A-15
A-15
A-16
A-17
A-17
A-18
A-19
A-22
B.1
B.1.1
B.1.2
B.1.3
B.1.4
B.1.5
B.1.6
B.2
B.3
APPENDIX B
NETWORK MANAGEMENT AND DIAGNOSTIC SERVICES
NETWORK MANAGEMENT MESSAGES ................................ .
Node Identification Messages ......................................... .
Domain Table Messages ............................................. .
Address Table Messages ............................................. .
Network Variable-Related Messages ................................... .
Memory-Related Messages .......................................... .
Special-Purpose Messages ........................................... .
NETWORK DIAGNOSTIC MESSAGES .................................. .
NETWORK VARIABLE MESSAGES ..................................... .
B-5
B-6
B-7
B-9
B-10
B-12
B-14
B-16
B-19
APPENDIXC
EXTERNAL MEMORY INTERFACING
C-1
D.1
D.1.1
D.1.2
D.1.3
D.2
D.3
APPENDIX D
DESIGN AND HANDLING GUIDELINES
APPLICATION CONSIDERATIONS ...................................... .
Termination of Unused Pins .......................................... .
Avoidance of Damaging Conditions .................................... .
Power Supply, Ground, and Noise Considerations ....................... .
BOARD SOLDERING CONSIDERATIONS ............................... .
HANDLING PRECAUTIONS ............................................ .
D-1
D-1
D-2
D-3
D-4
D-4
vi
MC143150·MC143120
MOTOROLA


MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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LIST OF FIGURES
Figure
Number
Title
Page
Number
1-1
1-2
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10a
4-10b
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
5-1
5-2
5-3
MC143150 NEURON CHIP Simplified Block Diagram ........................ .
MC143120 NEURON CHIP Simplified Block Diagram ........................ .
Typical Node Block Diagram ............................................ .
The MC143150 or MC143120 in a LONWORKS Network .................... .
MC143150 ........................................................... .
MC143120 ........................................................... .
Processor Organization Memory Allocation ............................... .
Processor/Memory Activity During One of the Three Phases of a Minor Cycle ..
Base Page Memory Layout ............................................. .
MC143150 Processor Memory Map ...................................... .
MC143120 Processor Memory Map ...................................... .
Minimum MC143150 Memory Interface .................................. .
External Memory Interface Timing Diagram ............................... .
Timer/Counter Circuits ................................................. .
Internal Transceiver Block Diagram ...................................... .
Differential Manchester Data Encoding ................................... .
Single-Ended Mode Configuration ...........................,............ .
Single-Ended Mode Data Format ........................................ .
Packet Timing ........................................................ .
EIA-485 Twisted Pair Interface (Used with single-ended mode) .............. .
Differential Mode ...................................................... .
Differential Mode Data Format .......................................... .
Simple Direct Connect Network Interface (Used with direct mode differential) ..
Transformer Isolated Twisted Pair Interface (78 kbps) ...................... .
Transformer Isolated Twisted Pair Interface (1.25 Mbps) .................... .
Special-Purpose Mode Data Format ..................................... .
NEURON CHIP Clock Generator Circuit .................................... .
Power on Reset Circuit ................................................. .
Typical Analog Waveform on Reset Pin at Power On ....................... .
Example Low Voltage Detect/Reset Circuit ................................ .
Output Pin State Transitions for 5 MHz Node .............................. .
Reset Timeline ........................................................ .
Service Pin Circuit ..................................................... .
Summary of I/O Objects ................................................ .
Synchronization of External Signals ...................................... .
when-Clause to when-Clause Latency, tww and Scheduler Overhead
Latency, tsol ......................................................... .
MOTOROLA
MC143150·MC143120
1-1
1-2
2-1
2-2
3-2
3-3
3-4
3-5
3-6
3-8
3-8
3-9
3-11
3-12
4-3
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-15
4-20
4-20
4-21
4-21
4-22
4-27
5-3
5-4
5-5
vii


MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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LIST OF FIGURES (Continued)
Figure
Number
Title
Page
Number
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
5-41
5-42
5-43
6-1
6-2
6-3
viii
Bit VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Input Latency Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Output Latency Values ...............................................
Byte I/O .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Input Latency Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Output Latency Values .............................................
Level Detect Input Latency Values. ...... .......... ... ..... ....... . .......
Nibble I/O .............................................................
Nibble Input Latency Values .............................................
Nibble Output Latency Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O - Master and Slave A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Mode Timing....................................................
Siave-A Mode Timing ...................................................
Parallel I/O Master/Slave B (NEURON CHIP as Memory-Mapped I/O Device) ....
Siave-B Mode Timing ...................................................
Bitshift I/O ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bitshift Input Latency Values .............................................
Bitshift Output Latency Values ...........................................
Magcard Input Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NEUROWIRE I/O ........................................................
NEUROWIRE (SPI) Master Timing .........................................
NEUROWIRE (SPI) Slave Timing ..........................................
Serial Input .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Output ..........................................................
when Statement Processing Using the On-Time Input Function. . . . . . . . . . . . . . .
Dualslope Input Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Edgelog Input Object ...................................................
Infrared Input Object. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Time Latency Values ................................................
Period Input Latency Values .............................................
Pulse Count Input Latency Values ........................................
Quadrature Input Latency Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total Count Input Latency Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Output Latency Values ........................................
One-Shot Output Latency Values ........................... . . . . . . . . . . . . . .
Pulse Count Output Latency Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsewidth Output Latency Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triac Output Latency Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triggered Count Output Latency Values ...................................
Muxbus I/O Object. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Loading for Memory Interface Timing SpeCifications ..................
Drive Levels and Test Points for Memory Interface Timing Specifications ......
External Memory Interface Timing Diagram ................................
5-5
5-6
5-6
5-7
5-7
5-7
5-8
5-8
5-9
5-9
5-10
5-11
5-12
5-15
5-16
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-41
5-42
6-4
6-4
6-5
MC143150-MC143120
MOTOROLA


MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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LIST OF FIGURES (Concluded)
Figure
Number
Title
Page
Number
8-1 Network Variable Message Structure ..................................... . 8-20
C-1 General EPROM Memory Interface ...................................... . C-1
C-2 Low Supply Current EPROM Memory Interface ........................... . C-2
C-3 General NEURON 3150 CHIP External Memory Interface with 32K-Byte
EPROM and 32K-8yte RAM ............................................ . C-3
C-4 Low Supply Current NEURON 3150 CHIP External Memory Interface with 32K-8yte
EPROM and 32K-8yte RAM ............................................ . C-4
0-1 CMOS Inverter ........................................................ . 0-1
0-2 Oigital Input ........................................................... . 0-3
0-3 Oigital I/O ............................................................ . 0-3
0-4 Networks for Minimizing ESO and Reducing CMOS Latch Up Susceptibility ... . 0-6
0-5 Typical Manufacturing Work Station ...................................... . 0-6
0-6 CMOS Wafer Cross Section ............................................ . 0-8
0-7 Latch Up Circuit Schematic ............................................. . 0-8
MOTOROLA
MC143150·MC143120
ix


MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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LIST OF TABLES
Table
Number
Title
Page
Number
3-1
3-2
3-3
3-4
4-1
4-2
4-3
4-4
4-5
4-6
4-7a
4-7b
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
5-1
5-2
5-3
5-4
5-5
5-6
8-1
A-1
A-2
Comparison of MC143150 and MC143120 Processors ..................... .
Register Set .......................................................... .
External Memory Interface Pins ......................................... .
External Memory Bus Timing ........................................... .
Communications Port Pin Characteristics ................................. .
Single-Ended and Differential Network Data Rates ......................... .
Communications Port Programmable Hysteresis Values
(Expressed as differential peak to peak voltages in terms of VDD) ........... .
Communications Port Programmable Glitch Filter Values ................... .
Differential Transceiver Electrical Characteristics .......................... .
Receiver Jitter Tolerance Windows ...................................... .
Suggested Twisted Pair Transformer Manufacturers for 78 kbps and
1.25 Mbps ............................................................ .
Echelon Twisted Pair Transceiver Modules ............................... .
Special-Purpose Mode Transmit and Receive Status Bits ................... .
Clock Generator Component Values ..................................... .
Typical Start-Up Times ................................................. .
Program Control Instruction Timings ..................................... .
Memory/Stack Instruction Timings ....................................... .
ALU Instruction Timings ................................................ .
Time Required for MC143120 to Perform Reset Sequence .................. .
Time Required for MC143150 to Perform Reset Sequence .................. .
Summary of Input Device Driver Objects ................................. .
Summary of Output Device Driver Objects ................................ .
Summary of Bidirectional Device Driver Objects ........................... .
Timer/Counter Resolution and Maximum Range ........................... .
Timer/Counter Square Wave Output ..................................... .
Timer/Counter Pulse Train Output ....................................... .
LONTALK Protocol Layering ............................................. .
Encoding of Timer Field Values ......................... ; ................ .
Transceiver Bit Rate (kbit/s) as a Function of comm_clock and input_clock .... .
3-1
3-5
3-9
3-10
4-2
4-4
4-8
4-8
4-9
4-9
4-10
4-11
4-14
4-16
4-16
4-17
4-17
4-18
4-25
4-26
5-2
5-2
5-2
5-43
5-43
5-44
8-1
A-13
A-20
x
MC143150·MC143120
MOTOROLA


MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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SECTION 1
INTRODUCTION
The Motorola MC143150FU, MC143150FU1, and MC143120DW NEURON CHIPS are sophisticated VLSI
devices that make it possible to implement low-cost local operating network applications. Through a unique
combination of hardware and firmware, they provide all the key functions necessary to process inputs from
sensors and control devices intelligently, and propagate control information across a variety of network
media. The MC143150 and MC143120 with the LONBulLDER Developer's Workbench offer the system
designer:
• Easy implementation of distributed sense and control networks
• Flexible reconfiguration capability after network installation
• Management of LONTALK protocol messages on the network
• An object-oriented high level environment for system development
ADDRESS
DATA
RNi
E
MAC
PROCESSOR
NETWORK
PROCESSOR
APPLICATION
PROCESSOR
RAM
2KBYTES
I
EEPROM
512 BYTES
r- "'
(J)
::J (J)
(]) ::J
(J) (])
(J)
aw:
0
~
<C
0
0..:: Ia-;;
<X)
Ia-;
<j!.
"- "-
NETWORK
COMM.
PORT
APPLICATIONS
I/O:
GENERAL
I/O
PARALLEL
PORT
SERIAL
PORT
2TIMER/
COUNTERS
CLOCKING
AND
CONTROL
CP4
CP3
CP2
CPl
CPO
1010
100
CLKl
CLK2
SERVICE
RESET
MOTOROLA
Figure 1-1. MC143150 NEURON CHIP Simplified Block Diagram
MC143150'MC143120
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MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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MAC
PROCESSOR
NETWORK
PROCESSOR
APPLICATION
PROCESSOR
RAM
1KBYTES
I
EEPROM
512 BYTES
ROM
10K BYTES
I
r- "-
:e:n>
<Xl
enaewnn:
~
<Xl
~
~
l!al
t--
~
~
~
h.. ""-
NETWORK
COMM.
PORT
APPLICATIONS
I/O:
GENERAL
I/O
PARALLEL
PORT
SERIAL
PORT
2 TIMER/
COUNTERS
CLOCKING
AND
CONTROL
CP4
CP3
CP2
CP1
CPO
1010
100
CLK1
CLK2
SERViCE
RESET
Figure 1-2. MC143120 NEURON CHIP Simplified Block Diagram
The MC143150 is designed for sense and control systems that require large application programs. An
external memory interface allows the system designer to use 42K of the available 64K of address space for
application program storage. The MC143150 has no ROM on the device. The communications protocol,
developer's operating system, and 291/0 device driver object code are provided with Echelon'S LONBUlLD-
ER Workbench. The protocol and application object code can be stored in external ROM, EEPROM,
NVRAM, or battery-backup static RAM.
The MC143150 NEURON IC is available in two versions (suffix FU and FU1). The FU device can be oper-
ated at different voltage ranges to achieve specific performance goals. This will optimize the overall system
cost with the associated external memories. The devices are:
Device
Clock Speed
Rate
MC143150FU
MC143150FU
MC143150FU1
10 MHz
10 MHz
5 MHz
Memory Access
Time
90 ns
105 n5
200n5
Supply Voltage
Range
4.5-5.5 V
4.75-5.25 V
4.5-5.5 V
EEPROM Programming
Temperature Range Typical 100
- 20 to + 85°C
- 20 to + 85°C
- 40 to + 85°C
32mA
32mA
20mA
As shown, the MC143150FU is designed for input clock operation up to and at 10 MHz clock rate over-40
to + 85°C with writes to internal EEPROM guaranteed down to - 20°C. The MC143150FU1 is a lower cost
device deSigned for 5 MHz operation and below, and operates over the full industrial temperature range of
- 40 to + 85°C.
The MC143120 has no external memory interface and is designed for applications that require smaller
application programs. It contains 10K of masked ROM that implements the communications protocol,
operating system and the 24 I/O functions that can be accessed by the application program. The applica-
tion program resides in the internal 512 bytes of EEPROM and accesses the firmware in the masked ROM
for performing most of the communications and control functions.
1-2
MC143150-MC143120
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Neuron Chip Distributed Communications and Control Processor

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Both parts have an eleven pin I/O interface with integrated hardware and firmware for connecting to motors,
valves, display drivers, NO converters, pressure sensors, thermistors, switches, relays, triacs, tachom-
eters, other microprocessors, modems, etc. They each have three processors, of which two interact with a
communication subsystem to make the transfer of information from node to node in a distributed control
system an automatic process. These devices make it possible to rapidly implement many applications.
These include distributed sense and control systems, instrumentation, machine automation, process con-
trol, diagnostic equipment, environmental monitoring and control, power distribution and control, produc-
tion control,lighting control, building automation and control, security systems, data collection/acquisition,
robotics, home automation, consumer electronics, and automotive electronics.
The NEURON CHIPS can send and receive information on either the 5-pin communications port or the 11-pin
applications I/O port.
Features
• Three 8-bit pipelined processors
Selectable input clock rates: 625 kHz to 10 MHz
• On-chip memory
2 Kbyte static RAM (MC143150)
1 Kbyte static RAM (MC143120)
512 byte EEPROM
10 Kbyte ROM (MC143120)
• 11 programmable I/O pins
29 selectable modes of operation
Programmable pull-ups
20 mA current sink
• Two 16-bit timer/counters for frequency and timer I/O
• Sleep mode for reduced current consumption while retaining operating state
• Network communications port
Single-ended mode
Differential mode
Selectable transmission rates: 0.6 kbit/s to 1.25 Mbit/s
280 packets/s throughput sustained; 700 packets/s peak
40 mA current output for differentially driving twisted-pair networks
Optional collision detect input
• Firmware
LONTALK protocol conforming to 7-layer OSI reference model
I/O drivers
Event-driven task scheduler
• Service pin for remote identification and diagnostics
• Unique 48-bit internal NEURON 10
MOTOROLA
MC143150·MC143120
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Neuron Chip Distributed Communications and Control Processor

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Neuron Chip Distributed Communications and Control Processor

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SECTION 2
LONWORKS TECHNOLOGY OVERVIEW AND ARCHITECTURE
LONWORKS technology is a complete platform for implementing control network systems. These networks
consist of intelligent devices or nodes that interact with their environment, and communicate with one
another over a variety of communications media using a common, message-based control protocol.
LONWORKS technology includes all of the elements required to design, deploy and support control net-
works, specifically the following components:
• MC143150 and MC143120 NEURON CHIPS
• LONTALK Protocol
• LONWORKS Transceivers
• LONBUILDER Developer's Workbench
The Motorola NEURON CHIP is a VLSI component that performs the network and application-specific pro-
cessing within a node. A node typically consists of a NEURON CHIP, a power source, a transceiver for
communicating over the network medium, and circuitry for interfacing to the device being controlled or
monitored. The specific circuitry will depend on the networking medium and application. See Figures 2-1
and 2-2.
Sense or Control Devices:
e.g. Motors, Valves,
Encoders, SWRches
MOTOROLA
Networking Medium (Twisted Pair, AF, Power Line, etc.)
Figure 2-1. Typical Node Block Diagram
MC143150·MC143120
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MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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lONWORKS Node 1
Sense/Control
Device
t
I II/O CircuRry
. . . .1
I ITransceiver
1
lONWORKS Node 2
lONWORKS Node 3
Sense/Control
Device
1
I II/O CircuRry
Illlllllt,".1
I ITransceiver
Sense/Control
Device
I II/O CircuRrv
.N~D\c.%tl
I ITransceiver
11
Network Transmission Medium
lONWORKS Node 4
Sense/Control
Device
!I I/O Circuitry
~liNE.eH.
I ITransceiver
lONWORKS Node 5
Sense/Control
Device
t
I II/O CircuRrv
MI_.1I1
I ITransceiver
1
lONWORKS Node 6
Sense/Control
Device
t
I II/O Circuitry
_1• •lG%!
I ITransceiver
lONWORKS
Router
1
Network Transmission Medium
I ITransceiver
fli.lIJiimftljl
[%lJ)N~pdi• •
I ITransceiver
Figure 2-2. The MC143150 or MC143120 in a LONWORKS Network
The NeURON IC and LONTALK protocol are licensed products of Echelon Corporation. The following discus-
sions are meant to give customers an awareness of the various restrictions and license fees that are
associated with using LONWORKS technology. Contact either Motorola or Echelon for a copy of the com-
plete license agreement. The key topics covered are:
A) Development License Agreement - no cost.
B) OEM License Agreement (Rev. F) - Contact Echelon for price.
C) Special Purpose Mode protocol (restrictions) - Generally no cost.
D) Router License Agreement - Various cost options.
E) Various Software License Agreements.
A) Development License Agreement
To get started, a customer needs a Development License Agreement. This enables them to receive
NeURON CHIP samples from Motorola to be used in their product development.
There is no time limit or price associated with this license. It simply informs the customer of the various
restrictions associated with LONWORKS technology. The following is a sample of one of the paragraphs in
the Development License Agreement.
Development License Agreement (Rev. F)
Entitles the user to a nonexclusive license, under Echelon intellectual property. solely to use NeURON CHIPS
to develop and design LONWORKS Applications.
2-2
MC143150·MC143120
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MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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Licensee's rights to use the LONTALK Protocol and NEURON CHIPS shall not extend to use of the LONTALK
Protocol in devices that duplicate functions of all or part of the NEURON CHIPS, or to use of the NEURON
CHIPS with any communications protocol other than the LONTALK Protocol. The foregoing limitation shall
apply to all NEURON CHIPS used by Licensee, including NEURON CHIPS contained in products or equipment
purchased by Licensee.
Contact either Motorola or Echelon for a copy of the complete license agreement if you are interested in
receiving samples from Motorola.
B) OEM License Agreement
When the design is complete and ready for production, an OEM License Agreement will need to be signed
to enable the customer to purchase volume quantities of NEURON ICs from Motorola. The cost is payable to
Echelon Corporation (consult Echelon for pricing). The following is a sample of one of the paragraphs in the
Development License Agreement.
OEM License Agreement (Rev. F)
Echelon grants Licensee a nonexclusive license, under Echelon Intellectual Property, to make, use, and
sell LONWORKS Applications. Licensee agrees that whenever a NEURON CHIP is executing instructions, the
NEURON CHIP Firmware shall be loaded into it starting at address location 0 (zero). Licensee's rights to use
the LONTALK Protocol and NEURON CHIP shall not extend to use of the LONTALK Protocol in devices that
duplicate the functions of all or part of the NEURON CHIPS, or to use the NEURON CHIP with any communica-
tions protocol other than the LONTALK Protocol. The foregoing limitations shall apply to all NEURON CHIPS
used by Licensee, including NEURON CHIPS contained in products or equipment purchased by Licensee.
Contact either Motorola or Echelon for a copy of the complete license agreement.
C) Special Purpose Mode Protocol Restriction
The NEURON IC has three different communication modes for building transceivers. One specific mode,
called Special Purpose Mode, uses a unique handshake protocol for communications to an external trans-
ceiver, such as a powerline or RF. There are restrictions associated with this mode of operation that limit the
types of transceivers that can be interfaced to the NEURON IC without written approval from Echelon. The
following is a sample of one of the paragraphs in the Development License Agreement.
Special Purpose Protocol Restriction
Unless otherwise approved in writing by Echelon, such transceivers must be of licensee's own proprietary
design, and LONWORKS applications containing such transceivers must include licensee's proprietary soft-
ware that will perform the end use functions in addition to network connections, for which the particular
LONWORKS Application was designed. Contact either Motorola or Echelon for a copy of the complete
license agreement.
D) Router License Agreement
For LONWORKS systems needing routers, bridges or gateways, customers can purchase complete or
board based products from Echelon with shrink wrapped license but no license cost. For customers need-
ing to develop their own routers, they can purchase the Source Code from Echelon and pay per run time
license fees. Contact either Motorola or Echelon for a copy of the complete license agreement.
E) Various Software License Agreements
Echelon sells various software packages to help reduce customer's development times. There are various
restrictions, along with upfront and run time cost. Contact Echelon for more information on product offering
and cost.
MOTOROLA
MC143150·MC143120
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Neuron Chip Distributed Communications and Control Processor

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Neuron Chip Distributed Communications and Control Processor

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SECTION 3
NEURON CHIP PROCESSOR FAMILY-HARDWARE RESOURCES
The first members of the NEURON CHIP processor family are the MC143150 and the MC143120. The
MC143150 (Figure 3-1) supports external memory for more complex applications, while the MC143120
(Figure 3-2) is a complete system on a chip that supports many applications. The major hardware blocks of
both processors are the same, except where noted; see Table 3-1.
Table 3-1. Comparison of MC143150 and MC143120 Processors
Charactarlstlc
Processors
RAM Bytes
ROM Bytes
EEPROM Bytes
16·Bit Timer/Counters
External Memory Interface
Package
Pins
MC143150
3
2,048
-
512
2
Yes
PQFP
64
MC143120
3
1,024
10,240
512
2
No
SOG
32
3.1 PROCESSING UNITS
The three processors are dedicated to the following functions by the system firmware (Figure 3-3).
Processor 1 is the Media Access Control (MAC) layer processor that handles layers one and two of the
seven-layer network protocol stack. This includes driving the communications subsystem hardware as well
as executing the collision avoidance algorithm. Processor 1 communicates with Processor 2 using network
buffers located in shared memory.
Processor 2 is the Network Processor that implements layers three through six of the network protocol
stack. It handles network variable processing, addressing, transaction processing, authentication, back-
ground diagnostics, software timers, network management, and routing functions. Processor 2 uses net-
work buffers in shared memory to communicate with Processor 1, and Application Buffers to communicate
with Processor 3. The buffers are also Icoated in shared memory. Access to them is mediated with hard-
ware semaphores to resolve contention when updating shared data.
MOTOROLA
MC143150·MC143120
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MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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AfJ 64
Al
63
~
Processor
1
A2 62
A3 61
A4 60
AS 59
A6 58
A7 57
AS 58
/IS 55
Al0
54
I--
Processor
2
-
Processor
3
~
~
~
~
~
I-
Communi-
cations
Port
~
~
!!
eIII
~
..E
J~
All 53
A12
Memory
52 Expansion
A13 51 Bus
AO-A15
A14 50
00-07
A15 47
DO 43
,2 I Control
Input!
Output
Section
Two
TImer!
Counters
01 42
02 36
D3 37
I--
RAM
2KX8
I-
D4 36
D5
35
D6 34
07 33
Rfii
45
16 V 8 V
II
-
EEPROM
512X8
Clock and
I - Control
Section
E 46
NOTE: Pin numbers apply to 64-lead package.
28
29
30
31
32
2
3
4
5
10
11
12
13
14
15
16
24
23
17
6
Figure 3-1. MC143150
CPO
CPl
CP2
CP3
CP4
100
101
102
103
104
105
106
107
108
109
1010
Clock 1
Clock 2
3-2
MC143150·MC143120
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MC143150 (Motorola)
Neuron Chip Distributed Communications and Control Processor

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-Processor
1
--
Processor
2
I-
Communi-
cations
Port
CPO
19
CP1
20
CP2
17
CP3
21
CP4
22
- -Processor
3
ROM
10KX8
--
~
."
~!!l
<aID
lij
:s
..I!D!l
1ii
0
<a
E
~
!!l
eID
'E!
8
<a
E
:'s"
Input!
Output
Section
Two
TImer/
Counters
--RAM
1KX8
EEPROM
512X8
.-16 /
--
8V
/
I-
I-
Clock and
Control
Section
100
7
101
6
102
5
103
4
104
3
105
30
106
29
107
28
108
27
109
26
1010
24
Clock 1
15
14 Clock 2
Service
8
1
Figure 3-2. MC143120
MOTOROLA.
MC143150·MC143120
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Neuron Chip Distributed Communications and Control Processor

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Communications Port
Input/Output Port
"I
I
I
I Network Buffers
Application Buffers
II
L ______________ ~
Shared RAM
Figure 3·3. Processor Organization Memory Allocation
Processor 3 is the Application Processor. It executes the code written by the user, together with the operat-
ing system services called by user code. The primary programming language used by most applications is
NEURON C, a derivative of the C language optimized and enhanced for LON distributed control applica-
tions. The major enhancements are:
o A built-in multitasking scheduler that allows the programmer to express logically parallel event-driven
tasks in a natural way, and to control the priority execution of these tasks.
o A declarative syntax for input/output objects directly mapping into the input/output capabilities of the
processor-see Section 7 for details.
o A declarative syntax for network variables, which are NEURON C language objects whose values are
automatically propagated over the network whenever values are assigned to them.
o A declarative syntax for millisecond and second timer objects which activate user tasks on expiration.
o A run-time library offunction calls to perform event checking, manage input/output activities, send and
receive messages across the network, and to control miscellaneous functions of the NEURON.
The support for all these capabilities is part of the LONWORKS firmware, and does not need to be written by
the programmer. This allows even complex applications to be written in the application program memory
space of the MC143120 processor.
Each of the three identical processors has its own register set (Table 3-2), but all three processors share
data and address ALUs and memory access circuitry (Figure 3-4). Each CPU minorcycle consists of three
system clock cycles, or phases; each system clock cycle is two input clock cycles. The minor cycles of the
three processors are offset from one another by one system clock cycle, so that each processor can access
memory and ALUs once during each instrument cycle. Figure 3-4 shows the active elements for each pro-
cessor during one of the three phases of a minor cycle. The system thus pipelines the three processors,
reducing hardware requirements without affecting performance. This allows the execution of three pro-
cesses in parallel without time-consuming interrupts and context switching.
3-4
MC143150o MC143120
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Neuron Chip Distributed Communications and Control Processor

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Mnemonic
FLAGS
IP
BP
DSP
RSP
TOS
Table 3-2. Register Set
Bits Contents
8 CPU number, fast I/O select, and carry bit
16 Next Instruction Pointer
16 Address of 2S6-byte Base Page
8 Data Stack Pointer within base page
8 Return Stack Pointer within base page
8 Top Of Data Stack, ALU input
Processor 2
Registers
Processor 3
Registers
l1li Active elements - Processor 1
~ Active elements - Processor 2
IlII Active elements - Processor 3
Figure 3-4. Processor/Memory Activity During One of the Three Phases
of a Minor Cycle
MOTOROLA
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Neuron Chip Distributed Communications and Control Processor

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The architecture is stack-oriented; one 8-bit wide stack is used for data references, and the ALU operates
on the TOS (Top Of Stack) register and the next entry in the data stack which is in RAM. A second stack
stores the return addresses for CALL instructions, and may also be used for temporary data storage. This
zero-address architecture leads to very compact code. Tables 3-15, 3-16, and 3-17 outline the instruction
set.
Figure 3-5 shows the layout of a base page, which may be up to 256 bytes iong. Each of the three pro-
cessors uses a different base page, whose address is given by the contents of the BP register of that pro-
cessor. The top ofthe data stack is in the 8-bit TOS register, and the next element in the data stack is atthe
location within the base page at the offset given by the contents of the DSP register. The data stack grows
from low memory towards high memory, and the return stack grows from high memory towards low
memory.
BP+RSP
BP+DSP 1 - - - - - - - 1 - - OQ[J
Data Stack
BP+Ox18
BP+Ox17 1 - - - - - - - - 1
16 Directly·
Addressable Bytes
BP+Ox8 1-_ _ _ _ _--1
BP+Ox7
Four Two·Byte
Pointer Registers
BP
Figure 3-5. Base Page Memory Layout
3-6
MC143150·MC143120
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Neuron Chip Distributed Communications and Control Processor

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3.2 MEMORY
3.2.1 Memory Allocation Overview
3.2.1.1 MC143150 MEMORY ALLOCATION (SEE FIGURE 3-6).
• 512 bytes of in-circuit programmable EEPROM that store:
- Network configuration and addressing information
- Unique 48-bit LON identification code - written at the factory
- User-written application code and read-mostly data
• 2,048 bytes of static RAM that store:
- Stack segment, application, and system data
- LON protocol network buffers and application buffer
• Up to 65,536 bytes of memory address space - any mix of ROM, EPROM, EEPROM or RAM. The
processor can access 59,392 bytes of this memory via the external memory interface; 6,144 bytes
of the address space are mapped internally.
• 16,384 bytes of external memory are required to store:
- The LONWORKS operating system, including the system firmware executed by the MAC and Net-
work processors, and the executive supporting the application program.
• The rest of external memory is available for:
- User-written application code
- Additional application read/write data
- Additional network buffers and application buffer
3.2.1.2 MC143120 MEMORY ALLOCATION (SEE FIGURE 3-7).
• 512 bytes of in-circuit programmable EEPROM that store:
- Network configuration and addressing information
- Unique 48-bit LON identification code - written at the factory
- User-written application code and read-mostly data
• 1,024 bytes of static RAM that store:
- Stack segment, application, and system data
- LON protocol network buffers and application buffer
• 10,240 bytes of masked ROM that store:
- LONWORKS firmware executed by the MAC and Network processors
- Operating system supporting the application program
3.2.2 EEPROM
Both the MC143150 and the MC143120 have 512 bytes in-circuit programmable EEPROM. All but eight
bytes of the EEPROM can be written under program control using an on-chip charge pump to generate the
required programming voltage. The remaining eight bytes are written during manufacture, and contain a
unique 48-bit identifier for each part, plus 16 bits for the manufacturer's device code. Erase time and write
time are each 10 ms per byte. The EEPROM may be written up to 10,000 times with no data loss. For both
the MC143120 and the MC143150 the EEPROM stores the installation-specific information such as
network addresses and communications parameters. For the MC143120, EEPROM memory also stores
the application program generated by the LONBulLDER Developer's Workbench. The application code for
the MC143150 may either be stored on-chip, or off-chip in external memory. Note that when the NEURON
CHIP is not within the specified power supply voltage range, a pending or on-going EEPROM write is not
guaranteed, and while there is built-in protection to prevent EEPROM corruption during power-down, it is
important to hold the RESET pin low whenever VDD is below its minimum operating level to avoid this possi-
bility (see Section 4.6.3). The EEPROM of the MC143150 can usually be corrected in the event of a fault by
executing the program EE-Blank, which is supplied with the LONBUILDER Developer's Workbench.
MOTOROLA
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Neuron Chip Distributed Communications and Control Processor

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0000
3FFF
4000
E7FF
E800
EFFF
FOoo
F1FF
FCoo
FFFF
16K NEURON CHIP
Firmware and
Reserved Space
42K of Memory
Space Available
10 the User
2KRAM
0.5KEEPROM
2.5K Reserved
1K Memol)'-rTlapped
110 and Reserved Space
I
EXTERNAL
I
INTERNAL
Figure 3-6. MC143150 Processor
Memory Map
0000
10K NEURON CHIP
Firmware (ROM)
27FF
1
Unavailable
INTERNAL
ECOO
EFFF
FOOO
F1FF
FCDD
FFFF
lKRAM
0.5KEEPROM
2.SK Reserved
1KMemory-mapped
110 and Reserved Space
Figure 3-7. MC143120 Processor
Memory Map
3.2.3 Static RAM
The MC143150 has 2048 bytes of static RAM and the MC143120 has 1024 bytes of static RAM. The RAM
state is retained as long as power is applied to the device, even in "sleep" mode. Reset will clear the RAM.
3.2.4 Preprogrammed ROM
The MC143120 contains 10,240 bytes of pre-programmed ROM. This memory contains the LONWORKS
firmware, including the LONTALK protocol code, real time task scheduler and application function libraries.
The MC143150 accesses external memory for all of these. The object code is supplied with the
LONBUILDER Developer's Workbench.
3.2.5 External Memory (MC143150 Only)
This interface supports up to 42K bytes of external memory space for additional user program and data.
The total address space is 64K bytes. However, 6K of address space is reserved for on-chip, leaving 58K of
external address space. Of this space, 16K is used by the NEURON CHIP firmware, LONBulLDER develop-
ment debugger, and reserved space. The external memory space can be populated with RAM, ROM,
PROM, EPROM, or EEPROM in 256 byte increments. The memory maps are shown in Figure 3-6 and
Figure 3-7. The bus has eight bidirectional data lines, and sixteen address lines driven by the processor.
Two interface lines (R/W and E) are used for external memory access (see Figure 3-1). At the maximum
3-8
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clock rate (10 MHz input clock), 90 ns or better access time to external memory is required for the
MC143150FU. If the input clock is scaled down, slower memory can be used. The suggested input clock
rates are 10 MHz, 5 MHz, 2.5 MHz, 1.25 MHz, and 625 kHz. The Enable Clock (1:) runs at the system clock
rate, which is one half the input clock rate. The Enable Clock is low whenever data is being transferred
between the NEURON CHIP and external memory. All memory, both internal and external, may be accessed
by any ofthe three processors at the appropriate phase of the instruction cycle. Since the instruction cycles
of the three processors are offset by one third of a cycle with respect to each other, the memory bus is in use
by only one processor at a time.
Appendix C shows diagrams of interfacing the MC143150 to different types of memory. A minimum hard-
ware configuration would use one external EPROM containing both the protocol code and user application
code (see Figure 3-8). This configuration would not allow the system engineer to change the application
code after installation. Binding and address information however could be altered because this information
resides in the internal 512 bytes of EEPROM. When developing nodes that must be rewritten over the net-
work with application code, external EEPROM, NVRAM or battery backed up SRAM are required ifthe user
code will not fit in the 512 bytes of internal EEPROM. Also when designing a node, using a slower crystal
clock rate, where possible, will significantly reduce memory speed and cost in addition to reducing power
consumption. The pins used for external memory interfacing are listed in Table 3-3. liming information is
listed in Table 3-4 and is measured relative to the rising edge of E clock. The E clock signal is not typically
used for reading external memory but can be gated with decoded address lines and the RfiN signal to gen-
erate WRITE signals to external memory. A15 (address line 15) or a PAL decoded signal gated with RfiN
can be used to generate read signals to external memory. The MC143150FU needs to see data (setup
time) 55 ns ahead of the rising edge of E clock. The data hold time required when reading data is 0 ns.
MC143150
A15
A14-AO
07-DO
32Kx8EPROM
CE
15
Al4-AO
8
07-00
.r- IOE
16K: LONTALK Protocol
I
16K: User Application Program
Figure 3-8. Minimum MC143150 Memory Interface
Table 3-3. External Memory Interface Pins
Pin Designation
Ao-A15
0D-07
E'
RNV
Direction
Output
Input/Output
Output
Output
Function
Address pins
Data pins
Enable clock
Read/not Write select
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Because one of the internal processors is always using the address bus, sharing the address and data bus
(and memory) with another MPU's address and data bus can only be accompljshed with the use of external
three-state bus drivers on the 16 address lines. This method is not recommended or emulated with the
LONBUILDER Developer's Workbench. The preferred method of interfacing the NEURON CHIP to another
MPU is through the 11 I/O pins. There are parallel modes and serial modes for this purpose which are easily
implemented using the NEURON C programming language. Memory mapped I/O is supported in the
LONBuILDER environment.
Table 3-4. External Memory Bus TIming* (VDD =4.5 to 5.5 V, TA =- 40° to 85°C)
Symbol
Parameter
Min Max Unit
Icyc
PWEH
PWEL
tAO
tAH
tRD
tRH
Memory Cycle Time (System Clock Period) (Note 1)
Pulse Width. E High
Pulse Width. E Low
Delay. E High to Address Valid
Address Hold Time
Delay. E High to RfIi/ Valid Read
RfIi/ Hold lime Read
200
tcyd2 - 5
tcyd2 - 5
-
7
-
5
3200
tcyd2 + 5
tcyd2+ 5
55
-
25
-
ns
ns
ns
ns
ns
ns
ns
tDSR
Read Data Setup lime
55 - ns
tDZR
Delay Data Bus High-Z to RfIi/ High
5 - ns
tDHR
Data Hold Time Read
0 - ns
twR Delay. E High to RfIi/ Valid WrHe
- 25 ns
-twDD
Delay. RfIi/ Low to Data Drivers On (Note 2)
10
ns
toDW
Delay. E Low to Data Valid
- 60 ns
twH RiW Hold lime Write
5 - ns
NOTES:
* Table 3-4 is for the MC143150FU. See Section 6 for FUI timing.
1. !eye = 20 111. where f is the input clock frequency.
_
2. see FIgure 3-9. The NEURON CHIP drives the previously read data until after the falling edge of E. Therefore. an
external memory and the NEURON CHIP may both be driving the data lines to the same levels during this time without
contention.
3.3 INPUT/OUTPUT
3.3.1 Eleven Bidirectional I/O Pins
These pins are usable in several different configurations to provide flexible interfacing to external hardware
and access to the internal timer/counters. The level of output pins may be read back by the application
processor. See Section 6 for detailed electrical characteristics.
Pins 104-107 have programmable pull-up current sources. They are enabled or disabled with a compiler
directive (see NEURON C Programmers Guide). Pins 10G-103 have high current sink capability (20 mA @
0.8 V). The others have the standard sink capability (1.4 mA@ 0.4 V). All pins (100 to 1010) have TTL-level
inputs with hysteresis. Pins 100 to 107 also have low level detect latches.
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s::
@
o::0
~
I.
1'--E
l20 pF load }
Iteye .1
P'lVt:H--I--P'lVt:L-'
\
\'--__..
."
c.eO.."
CD
Co)
I
!D
-...m
)(
CD
s:: :::J
~
~
~
e!.
s::
CD
01 3
.0 0
...s:: '<
~ 5"
~
-(.)
CD
-'- ::I.
I\)
0
III
0
CD
-f
§"
:i"
(Q
c
...iii"
(Q
III
3
AG--A15
50pFIoad ~~'
I ~'
I ~~'
'~
Riii
50 pF load
Data (In)
'I
I
I
Nl--tDZR
Data (Out)
50 pF load
r---j tDHR
I
I
I
Memory READ
Memory READ
r-
Memory WRITE
l -tWH"j
I
I
I
Memory WRITE
NOTES:
E,1. The NEURON CHIP drives the previously read data until after the falling edge of Therefore, an external memory and the NEURON CHIP may both be driving the data lines
to the same levels during this time without contention.
2. Since the data bus goes high-Z at the beginning of a read cycle, the effective data hold time is dependent on the current load on the bus. Typically this will be »50 ns.
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3.3.2 Two 16-81t Timer/Counters
The timer/counters are implemented as a load register writeable by the processor, a 16-bit counter, and a
latch readable by the processor. The 16-bit registers are accessed a byte at a time. Both the MC143150
and MC143120 have one timer/counter whose input is selectable among pins 104 through 107, and whose
output is pin 100, and a second timer/counter with input from pin 104 and output to pin 101 (Figure 3-10).
Note that no I/O pins are dedicated to timer/counter functions. If for example, Timer/Counter 1 is used for
input signals only, then 100 is available for other input or output functions. Timer/counter clock and enable
inputs may be from external pins, or from scaled clocks derived from the system clock; the clock rates of the
two timer/counters are independent of each other. External clock actions occur optionally on the rising
edge, the falling edge, or both rising and falling edges of the input.
System Clock Divide Chain
+ 1.2.4.8.16.32.64.128
System Clock Divide Chain
+1.2.4.8.16.32.64.128
107
106 TImer/Counter 1
105
104
103 •
TImer/Counter 2
102 •
101 R-----o-"C>----------------I
100 ~~------------~--------~
Figure 3-10. Timer/Counter Circuits
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