NB3H5150 (ON Semiconductor)
2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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NB3H5150
2.5V / 3.3V Low Noise
Multi-Rate Clock Generator
Description
The NB3H5150 is a high performance Multi−Rate Clock generator
which simultaneously synthesizes up to four different frequencies
from a single PLL using a 25 MHz input reference. The reference
frequency can be provided by a crystal, LVCMOS/LVTTL, LVPECL,
HCSL or LVDS differential signals. The REFMODE pin will select
the reference source.
Three output banks (CLK1A/CLK1B to CLK3A/CLK3B) produce
user selectable frequencies of: 25 MHz, 33.33 MHz, 50 MHz,
100 MHz, 125 MHz, or 156.25 MHz and have ultra−low noise/jitter
performance of less than 0.3 ps.
The fourth output bank (CLK4A/CLK4B) can produce the
following integer and FRAC−N frequencies in pin−strap mode:
33.33 MHz, 66.66 MHz, 100 MHz, 106.25 MHz, 125 MHz,
133.33 MHz, 155.52 MHz, 156.25 MHz or 161.1328 MHz.
Each output block can create two single−ended in−phase LVCMOS
outputs or one differential pair of LVPECL outputs.
Each of the four output blocks is independently powered by a
separate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V for
LVCMOS.
The serial (I2C and SMBUS) interface can be used to load register
files into the NB3H5150 to program a variety of functions including
the frequencies and output levels of each output which can be
individually enabled and disabled.
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1 32
MARKING
DIAGRAM*
1
QFN32
MN SUFFIX
CASE 485CE
NB3H
5150
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information on page 18 of
this data sheet.
Features
Flexible Input Reference − 25 MHz Crystal, Oscillator,
1 ps maximum RMS Phase Jitter FRAC−N (CLK4)
Single−Ended or Differential Clock
Four Independent User−Programmable Clock
Frequencies from 25 MHz to 250 MHz
Independently Configurable Outputs:
Up to Eight LVCMOS Single Ended outputs or,
Up to Four Differential LVPECL Outputs or any
combination of LVCMOS and LVPECL
Flexible Input/Core and Output Power Supply
Combinations:
VDD (Core) = 3.3 V ±5% or 2.5 V ±5%
VDDOn (Outputs) = 3.3 V ±5% or 2.5 V ±5% or
1.8 V ±5% (LVCMOS Only)
Independent Power Supply for each Output Bank
300 ps max Output Rise and Fall Times, LVPECL
1000 ps max Output Rise and Fall Times, LVCMOS
300 fs maximum RMS Phase Jitter Interger−N
(CLK1:4) 156.25 MHz
155.52 MHz
I2C / SMBus Compatible Interface
−40°C to +85°C Ambient Operating Temperature
Zero ppm Multiplication Error
Fractional Divide Ratios for Implementing Arbitrary
FEC/Inverse−FEC Ratios
For Additional Pin−strap Frequency and Output Type
Combinations, Contact ON Semiconductor Sales Office
32−Pin QFN, 5 mm x 5 mm
This is a Pb−Free Device
Applications
Telecom
Networking
Ethernet
SONET
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 3
1
Publication Order Number:
NB3H5150/D


NB3H5150 (ON Semiconductor)
2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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CLK_XTAL1
CLK_XTAL2
SDA
SCL/PD
MMC
REFMODE
FTM
NB3H5150
VDD AVDD1 AVDD2 AVDD3
XTAL
OSC
PLL
REF (I2C Mode)
Integer N
DIV1
Integer N
DIV2
Configuration Table
&
I2C Interface
LDOs
LDO1 LDO2 LDO3 LDO4
Integer N
DIV3
Integer N or
Fractional N
DIV4
VDDO1
CLK1A
CLK1B
VDDO2
CLK2A
CLK2B
VDDO3
CLK3A
CLK3B
VDDO4
CLK4A
CLK4B
Figure 1. Simplified Block Diagram of NB3H5150
Exposed Pad (EP)
32 31 30 29 28 27 26 25
CLK_XTAL2 1
24 FTM
REFMODE 2
23 CLK2B
SDA 3
22 CLK2A
SCL/PD 4
VDD 5
NB3H5150
21 VDDO2
20 VDDO3
FS1 6
19 CLK3A
FS2 7
18 CLK3B
FS3 8
17 MMC
9 10 11 12 13 14 15 16
Figure 2. 32−Lead QFN Pinout (Top View)
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NB3H5150 (ON Semiconductor)
2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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NB3H5150
Table 1. PIN DESCRIPTION
Pin Name
I/O
1 CLK_XTAL2
Crystal or
LVPECL/LVDS
Input
2 REFMODE LVTTL/LVCMOS
Input
3 SDA LVTTL/LVCMOS
Input
4 SCL/PD LVTTL/LVCMOS
Input
5 VDD
6 FS1
7 FS2
8 FS3
9 FS4A
10 FS4B
11 LDO4
12 AVDD3
13 LDO3
14 CLK4A
Power
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
Power
Power
Power
Output
15 CLK4B
16 VDDO4
17 MMC
Output
Power
LVTTL/LVCMOS
Input
18 CLK3B
19 CLK3A
Output
Output
20 VDDO3
21 VDDO2
22 CLK2A
Power
Power
Output
23 CLK2B
24 FTM
25 VDDO1
26 CLK1B
27 CLK1A
Output
Power
Output
Output
28 AVDD2
29 LDO2
30 AVDD1
31 LDO1
Power
Power
Power
Power
Description
Crystal Output or Differential Clock Input (complementary); If CLK_XTAL1 is used as
single−ended input, CLK_XTAL2 must be connected to ground. See Table 2.
Reference Input Select to either use a crystal, or overdrive with a single−ended or
differential input; see Table 2. Internal pull−down.
Serial Data Input for I2C/SMBus compatible; Defaults High when left open; internal pull−up.
5V tolerant.
Serial Clock Input for I2C/SMBus compatible; Defaults High when left open; internal
pull−up.
SCL/PD is also a device power−down pin (when High) in pin−strap mode only. 5V tolerant.
3.3 V / 2.5 V Positive Supply Voltage for the Inputs and Core
Frequency Select 1 for DIV1, CLK1A & CLK1B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 2 for DIV2, CLK2A & CLK2B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 3 for DIV3, CLK3A, & CLK3B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 4A for DIV4, CLK4A & CLK4B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 4.
Frequency Select 4B for DIV4, CLK4A & CLK4B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 4.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD3 = VDD.
1.8V LDO − Install Power Conditioning Bypass Capacitor to Ground
LVCMOS (single−ended) or Non− Inverted Differential LVPECL Clock A for Channel 4
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 4 Output
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK4A/4B Outputs
Mix Mode Control Pin for use as a combination of FSn settings and I2C setting for the
CLK(n) outputs in the I2C mode; see Table 6. No logic level default; use a RPull−up resistor
for High or a RPull−down resistor for Low.
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 3 Output
LVCMOS (single−ended) or Non−Inverted Differential LVPECL Clock A for Channel 3
Output
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK3A/3B Outputs
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK2A/2B Outputs
LVCMOS (single−ended) or Non− Inverted Differential LVPECL Clock A for Channel 2
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 2 Output
Factory Test Mode. Must connect this pin to Ground.
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK1A/1B Outputs
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 1 Output
LVCMOS (single−ended) or Non−Inverted Differential LVPECL Clock A for Channel 1
Output
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD2 = VDD.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD1 = VDD.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
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NB3H5150 (ON Semiconductor)
2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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NB3H5150
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
32 CLK_XTAL1
Crystal or
Crystal Input or Single−Ended or Differential Clock Input; If CLK_XTAL1 is used as
LVTTL/LVCMOS single−ended input, CLK_XTAL2 must be connected to ground. See Table 2.
or LVPECL/LVDS
Input
EP Exposed Pad
Ground
Ground – Negative Power Supply is connected via the Exposed Pad .
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat
sinking conduit. The pad is electrically connected to the die,carries all power supply return
currents and must be electrically connected to GND.
1. All VDD, AVDDn, VDDOn, EP (GND) pins must be externally connected to a power supply for proper operation. VDD and AVDDn must all
be at the same voltage.
NB3H5150 BASIC OPERATION
Introduction
The NB3H5150 is a Multi−Rate Clock Generator. The
clock reference for the PLL can be either a 25 MHz crystal,
single−ended LVCMOS or LVTTL signal or a differential
LVPECL, LVDS or HCSL signal.
There are two modes of operation for the NB3H5150,
Pin−Strap and I2C.
In the Pin−Strap Mode, the user can select any of the
defined output frequencies for each of the four output banks
as specified in Tables 3 and 4 via the three−level Frequency
Select pins: FS1, FS2, FS3, FS4A and FS4B.
In the I2C mode, the user can select one of the approved
register files in Table 5. Each register file is an expanded
selection of output frequencies and level combinations,
output enable/disable and bypass mode functions.
CLKnA & CLKnB − Output Frequency and Output
Level Selection
There are four output banks: CLK1A&B, CLK2A&B and
CLK3A&B are integer only divider outputs, whereas
CLK4A&B can be set or programmed as an integer or
fractional divider.
The output levels for each output bank can be LVPECL
(differential) or LVCMOS (two single−ended). Output
Enable / Disable functions are available in I2C only.
CLK1, 2, 3 and 4 outputs are not phase−aligned, in PLL
or PLL bypass modes.
Power−On Output Default
Upon power−up, all four outputs will be forced to and held
at static LVPECL levels (CLKnA = Low, CLKnB = High)
until the PLL is stable. The PLL will be stable before any of
the output Clocks, CLKnx, are enabled.
The I2C interface pins, SCL and SDA, are used to load
register files into the NB3H5150.
These register files will configure the internal registers to
achieve an expanded selection of output frequencies and
levels combinations for each of the four output blocks.
Subsequent changes in the registers can then be performed
with another register file to modify any of the output
frequencies or output modes.
OE, Output Enable
An OE, Output Enable/Disable function is available only
in the I2C mode by loading a register file, such that any
individual output bank can be enabled or disabled. In
LVCMOS modes outputs will disable LOW for CLKnA and
CLKnB, while the LVPECL mode outputs will disable
CLKnA = Low and CLKnB = High.
Mixed Mode Control (MMC)
In the I2C mode, the Mixed Mode Control (MMC) pin is
used for a combination of FSn settings and I2C settings to
control the CLK(n) outputs’ function as defined in Table 7.
REFMODE – Select a Crystal or External Clock Input
Interface (See Table 2)
The REFMODE pin will select the reference input for the
CLK_XTAL1 and CLK_XTAL2 pins to use either a crystal,
an overdriven single−ended or differential input.
When using a crystal, set the REFMODE pin to a LOW.
The CLK_XTAL1 and CLK_XTAL2 input pins will accept
a 25 MHz crystal.
When using a direct−coupled differential input, set the
REFMODE pin to a HIGH.
SDA & SCL/PD - Serial Data Interface – I2C
The NB3H5150 incorporates a two−wire Serial Data
Interface to expand the flexibility and function of the
NB3H5150 clock generator.
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NB3H5150 (ON Semiconductor)
2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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NB3H5150
When REFMODE is HIGH, the CLK_XTAL1 and
CLK_XTAL2 differential input pins have internal AC
coupling capacitors selected with self−bias circuity for the
differential input buffer. This differential buffer will directly
accept any differential signal including LVPECL, LVDS,
HCSL or CML. Drive the CLK_XTAL1 pin with the true
signal and the CLK_XTAL2 pin with the complementary
signal.
When overdriving the CLK_XTAL1 input pin with a
single−ended signal set REFMODE to a HIGH, and connect
CLK_XTAL2 to Ground. The input has internal AC
coupling capacitor with self−bias circuitry.
Table 2. CRYSTAL INPUT INTERFACE AND REFMODE TRUTH TABLE
Input Mode Crystal/External Clock
REFMODE
CLK_XTAL1
Crystal
LOW
Use a Crystal
Any Differential Input
HIGH
Overdrive with True Input
Single−Ended Input
HIGH
Overdrive
CLKb_XTAL2
Use a Crystal
Overdrive with Complementary Input
Connect to Ground
LVCMOS Outputs
LVCMOS outputs are powered with VDDOn = 3.3 V,
2.5 V or 1.8 V
A 33 W series terminating resistor may be used on each
clock output if the metal trace is longer than one inch.
Any unused LVCMOS output can be left floating, but
there should be no metal trace attached to the package pin.
LVPECL Differential Outputs
The differential LVPECL outputs are powered with
VDDO = 3.3 V or 2.5 V and must be properly loaded. See
Figure 10.
Any unused differential output pair should either be left
floating or terminated.
REF Out
In the PLL bypass mode available via I2C, the input
reference frequency can be routed to CLK1A and CLK1B as
phase aligned LVCMOS or differential LVPECL outputs
with the same frequency. The output frequency and duty
cycle equals the input frequency and duty cycle.
Power Supplies
The NB3H5150 has several power supply pins:
VDD is the supply voltage for the input and digital core
circuitry.
AVDD1, AVDD2 and AVDD3 powers the core analog
circuits. VDD = AVDD1 = AVDD2 = AVDD3.
VDDO1, VDDO2, VDDO3 and VDDO4 are individual
power supplies for each of the four CLKnA/B output
banks.
Upon power−up, all four VDDOn pins must be connected
to a power supply, even if only one output is being used.
Any combination of VDD and VDDOn power supply
voltages is allowed.
A power supply filtering scheme in Figure 8 is
recommended for best device performance.
When all VDD, AVDDn and VDDOn pins reach their
minimum voltage per Table 10, the NB3H5150 will operate
at the proper output frequencies.
EP Exposed Pad
The exposed pad on the bottom side of the package must
be connected to Ground.
LDO Pins
The NB3H5150 has integrated low noise 1.8 V
Low−Drop−Out (LDO) voltage regulators which provide
power internal to the NB3H5150.
The LDOs require decoupling capacitors in the range of
1 mF to 10 mF for compensation and high frequency PSR.
When powered−down, the device turns off the LDOs and
enters a low power shutdown mode consuming less than
1 mA.
FTM
This is a Factory Test Mode pin and must be connected to
the Ground of the application for proper operation.
PIN−STRAP / FSn Frequency Select MODE: (see
Tables 3 and 4)
The NB3H5150 can be configured to operate in pin−strap
mode where the control pins FSnA/B can be set to generate
the necessary clock outputs of the device.
Prerequisites:
SDA and SCL/PD must be Low at all times while in
pin−strap mode to enable FS control. If SDA ever
goes High, pin−strap is exited and the only way to
go back is to power cycle the device.
Mixed Mode Control pin (MMC) level will be
IGNORED.
Sequencing:
1. Upon device power−up (assuming SCL is LOW)
a. All four CLK(n) frequency and output type
selections will be pre−loaded according to the
FS pin settings, but all four outputs will be held
at static LVPECL levels (CLKnA = Low,
CLKnB = High) until the PLL has become
stable.
b. After the PLL is stable, all CLK(n) output type
selections (i.e. LVPECL or LVCMOS) will
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NB3H5150 (ON Semiconductor)
2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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NB3H5150
become effective and will begin to output the
selected frequencies.
2. Subsequent changes to any FS pin(s) will cause
the associated CLK(n) output(s) to momentarily
go to static levels, and then to resume at the new
frequency; CLK(n) will follow the FS(n) pin
programmable Tables 3 and 4 for output
frequencies and interface levels.
Note that in changing from LVPECL to LVCMOS
(or vice−versa), output logic levels cannot be
guaranteed. This is because the receiver inputs are
not likely to change in a given application, and the
LVPECL output loading in the application will
also not change. It is logical to presume that the
output type will be predetermined and fixed.
Therefore, in a system/application, the user should
be aware that subsequent change to the FS pin
should only change frequency, and not output type.
3. Power off/on cycle will repeat the entire sequence
4. Power Down
To initiate the Power−Down mode, the SDA pin
must be LOW and remain LOW. If the SCL/PD
pin is taken HIGH at any time, the device enters a
complete power−down mode with a current
consumption of less than 1 mA for the entire
device. When SCL/PD is subsequently taken
LOW, the device will function as though power
were removed and re−applied. That is, sequencing
will begin at #1.
Power−down is also available via I2C with a
register file.
FS(n) Pin Programmable Selection of Output Frequencies and Levels
Table 3. NB3H5150 − CLK1A:3A & CLK1B:3B OUTPUT FREQUENCY SELECT
TABLE WITH 25 MHz CRYSTAL
Logic Level
Low
FS1 (CLK1)
(MHz)
50.00 (LVCMOS)
FS2 (CLK2)
(MHz)
156.25 (LVPECL)
FS3 (CLK3)
(MHz)
156.25 (LVPECL)
Mid / Float*
33.33 (LVCMOS)
25.00 (LVPECL)
125.00 (LVCMOS)
High
25.00 (LVCMOS)
125.00 (LVPECL)
100.00 (LVPECL)
*(Default)
Table 4. NB3H5150 − CLK4A & CLK4B OUTPUT FREQUENCY SELECT TRUTH
TABLE (MHz) WITH 25 MHz CRYSTAL*
FS4A
FS4B
CLK4 (MHz)
Divider Type
Low Low 33.33 (LVCMOS)
Integer
Low
Mid / Float
66.66 (LVCMOS)
Fractional
Low
High
133.33 (LVCMOS)
Fractional
Mid / Float
Low
155.52 (LVPECL)
Fractional
Mid / Float*
Mid / Float*
156.25 (LVPECL)
Integer
Mid / Float
High
125.00 (LVPECL)
Integer
High
Low 106.25 (LVPECL)
Fractional
High
Mid / Float
100.00 (LVCMOS)
Integer
High
High
161.1328 (LVPECL)
Fractional
*(Default)
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NB3H5150 (ON Semiconductor)
2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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NB3H5150
I2C MODE: (see Table 6)
Some features that are not available in pin−strap mode can
be obtained in I2C mode, such as Output Enable/Disable,
By−Pass mode and Power−Down. In addition, output
frequency and output levels can also be I2C controlled.
The NB3H5150 I2C Programming Guide can be found on
the NB3H5150 web site. This application note provides
details on configuring the NB3H5150 by writing to registers
in the NB3H5150 with approved register files through the
I2C/SMBus interface.
http://www.onsemi.com/pub/Collateral/NB3H5150%20I2
C%20PROGRAMMING%20GUIDE%20%20..PDF
The user can select a Register File from the ON
Semiconductor website from the NB3H5150 I2C Register
Files folder. Additional Register Files can be generated by
the factory upon request.
http://www.onsemi.com/pub/Collateral/NB3H5150%20I2
C%20REGISTER%20FILES.ZIP
Prerequisites:
SDA and SCL must be connected to I2C SMBus
SDA must be logic High.
1. Upon device power−up.
a. All four frequencies and output type selections
will be preloaded according to the FSn pin
settings, but all four outputs will be held at
static LVPECL levels until the PLL has become
stable.
NOTE: After power up, changes to FS pins
will be blocked from controlling device
operation.
b. Once the PLL is stable, the Mixed Mode
Control pin (MMC) is checked:
i. If MMC is LOW, all CLK(n) outputs will
remain at static LVPECL levels.
ii. If MMC is HIGH and FS4A is LOW, CLK1,
CLK2, and CLK3 outputs will remain at
static LVPECL levels.
CLK4A/4B output frequency and output
levels will become active after PLL
stabilization time according to FS4A and
FS4B pin selection in Table 4.
After power up, changes to all pins will be
ignored.
iii. If MMC is HIGH and FS4A MID or HIGH,
CLK1, CLK2, and CLK3 output frequency
and type will become active after PLL
stabilization time according to their
respective FS1, FS2 and FS3 pin selection in
Table 3.
CLK4A/4B outputs remain at Static
LVPECL Levels.
After power up, changes to all pins will be
ignored except the SDA and SCL inputs.
iv. The FS4A and FS4B pins set the bus address
when MMC pin is LOW (see Table 6, I2C
Device Address Table).
c. The I2C interface can now be used to load
register files into the NB3H5150. In I2C Mode,
configuration of Output Enables, output
frequency, output levels of each output, specific
block power−down control, bypass mode, etc.
are all possible.
d. Any outputs which were held in static level
mode (described above) will be released for
operation.
CLK(n) outputs will be active at the programmed
frequencies and levels.
CLK(n) outputs will react to any subsequent changes to the
I2C bus.
If any output channel is not programmed, then output is
loaded from FSn pins.
A Power Cycle will clear all previous register information
and I2C mode will repeat to number 1 in the power up
sequence.
To simplify device configuration, ON Semiconductor
provides desktop software, that can be downloaded from
http://www.onsemi.com/pub/Collateral/NB3H5150_GUI.
ZIP which will operate in conjunction with the NB3H5150
evaluation board (EVB). The NB3H5150 GUI manual can
also be found on the web site.
When the software is connected to an NB3H5150 EVB,
it can control the selection of numerous clock output
frequencies for each of the four CLK outputs and the output
type as well as Output Enable/Disable.
I2C Programmable Selection of Output Frequency and
Level
Table 5 contains register files that produce various
combinations of output frequencies and output types.
Each register file can be loaded from GUI into the demo
board, or loaded into the I2C port of the device.
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NB3H5150 (ON Semiconductor)
2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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NB3H5150
Table 5. I2C OUTPUT FREQUENCY AND MODE SELECTION REGISTERS
Reg.FILE#
CLK1 (MHz)
CLK2 (MHz)
CLK3 (MHz)
1 100 LVPECL
125 LVPECL
2 100 LVPECL
100 LVPECL
3 25 LVCMOS
Disabled
4 25 LVCMOS
Disabled
5
25 LVCMOS
156.25 LVPECL
6 25 LVCMOS
100 LVPECL
7
156.25 LVPECL
156.25 LVPECL
8
50.00 LVPECL
125.00 LVPECL
9
Bypass LVCMOS
156.25 LVPECL
10 Bypass LVPECL 156.25 LVPECL
11 Bypass LVCMOS 156.25 LVPECL
12 Disabled
Disabled
156.25 LVPECL
125 LVPECL
156.25 LVPECL
100 LVPECL
156.25 LVPECL
100 LVPECL
156.25 LVPECL
156.25 LVPECL
100.00 LVPECL
156.25 LVPECL
156.25 LVPECL
Disabled
CLK4 (MHz)
155.52 LVPECL
125 LVPECL
70.656 LVPECL
Disabled
156.25 LVPECL
Disabled
156.25 LVPECL
133.33 LVCMOS
156.25 LVPECL
156.25 LVPECL
156.25 LVPECL
Disabled
Table 6. SDA, SCL AND MMC CONTROL PINS FOR OUTPUT FUNCTION
Outputs (Note 2)
Mode
Pin−Strap FS Mode
SDA
L
SCL/PD
L
MMC
X
Comments
Normal Operation
CLK1, CLK2,
CLK3
Toggle per Table 3
CLK4
Toggle per Table 4
Power−Down
L
H
X
Off Off
I2C
(Note 3)
Dynamic Dynamic
X
I2C Mode Is Active After
Mixed Mode Power−Up
Sequence
Active Per I2C Map Active Per I2C Map
H
Note 4
H
Note 4
L
Static LVPECL
Logic Levels
Static LVPECL
Logic Levels
Mixed Mode
H
Note 4
H
Note 4
H
FS4A = L
Static LVPECL
Logic Levels
Active per Table 4
H
Note 4
H
Note 4
H
FS4A =
M or H
Active per Table 3
Static LVPECL
Logic Levels
2. All outputs are static until after the PLL is stable.
3. Any changes to the device configuration after power−up are made by reading and writing to registers through the I2C interface.
4. Don’t care state unless device address is matched by controller address.
X = don’t care
Table 7. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Charge Device Model
Moisture Sensitivity (Note 5) 32−QFN
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
5. For additional information, see Application Note AND8003/D.
Value
> 2 kV
> 150 V
> 500 V
Level 1
UL 94 V−0 @ 0.125 in
245, 894
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NB3H5150 (ON Semiconductor)
2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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NB3H5150
Table 8. MAXIMUM RATINGS
Symbol
Parameter
Condition
Rating
Unit
VDD
AVDDn
VDDOn
VIO
Positive Power Supply – Core
Positive Power Supply – Analog
Positive Power Supply – Outputs
Positive Input/Output Voltage
GND = 0 V
GND = 0 V
GND = 0 V
GND = 0 V
3.63
3.63
3.63
−0.5 to VDD
+0.5
V
V
V
V
VI Positive Input Voltage SDA and SCL
TA Operating Temperature Range
Tstg Storage Temperature Range
θJ Maximum Junction Temperature
θJA Thermal Resistance (Junction−to−Ambient) (Note 6)
QFN−32
QFN−32
GND = 0 V
QFN−32
0 lfpm
500 lfpm
5.5
−40 to +85
−65 to +150
125
31
27
V
°C
°C
°C
°C/W
°C/W
θJC Thermal Resistance (Junction−to−Case) (Note 6)
QFN−32
12 °C/W
TJ Maximum Junction Temperature
125 °C
Tsol Wave Solder Pb−Free, 10 sec
265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
6. JEDEC standard multilayer board – 2S2P (2 signal, 2 power).
Table 9. DC CHARACTERISTICS
VDD = AVDDn = 3.3 V ±5% or 2.5 V ±5%; VDDOn = 3.3 V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; TA = −40°C to 85°C
Symbol
Characteristic
Min Typ Max
POWER SUPPLY / CURRENT (Note 12)
VDD/AVDDn Core Power Supply
VDDOn Output Power Supply
VDD = AVDDn = 3.3 V
3.135
3.3
3.465
VDD = AVDDn = 2.5 V
2.375
2.5
2.625
VDDOn = 3.3 V
3.135
3.3
3.465
VDDOn = 2.5 V
2.375
2.5
2.625
VDDOn = 1.8 V (LVCMOS only)
1.71
1.8
1.89
IDD/IADDn
Core and Input Power Supply Current for VDD and AVDDn
VDD = 3.3 V
CLK4 Integer
CLK4 Frac−N
VDD = 2.5 V
CLK4 Integer
CLK4 Frac−N
60 75
75 90
55 70
70 85
IDDOn
Output Buffer Power Supply Current for VDDOn
Incremental IDDO Current by One Output Bank and Output Type
LVPECL − One differential LVPECL output pair (CLKnA & CLKnB)
Frequency Independent
VDDO = 3.3 V
VDDO = 2.5 V
40 50
40 50
LVCMOS − Two LVCMOS outputs (CLKnA & CLKnB)
f = 50 MHz
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
20 25
17 23
15 21
IDDPWRDN Power Down Current SCL/PD = High
100
LVPECL OUTPUTS (Note 7 and 8) VDDOn = 3.3 V ±5% or 2.5 V ±5%; See Figure 10
VOH Output HIGH Voltage
VDDO − 1.200
VDDO − 0.895
VOL Output LOW Voltage
VDDO − 2.000
VDDO − 1.600
VSWING VOUT PK−PK Voltage Swing
550 720 900
Unit
V
mA
mA
mA
V
V
mV
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2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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NB3H5150
Table 9. DC CHARACTERISTICS
VDD = AVDDn = 3.3 V ±5% or 2.5 V ±5%; VDDOn = 3.3 V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; TA = −40°C to 85°C
Symbol
Characteristic
Min Typ Max Unit
LVCMOS OUTPUT; See Figure 12
VOH Output HIGH Voltage IOH = 12 mA
VDDO – 0.5
VOL Output LOW Voltage IOL = 12 mA
GND
ROUT
Output Impedance
CRYSTAL INPUT DRIVEN SINGLE−ENDED (REFMODE = 1) (see Figure 3 and 5) (Note 9)
15
VDDO
0.5
V
V
W
VIHSE CLK_XTAL1 Single−Ended Input HIGH Voltage
200
VILSE
CLK_XTAL1 Single−Ended Input LOW Voltage
GND
Vth Input Threshold Reference Voltage Range
100
VISE
Single−Ended Input Voltage (VIH – VIL)
200
CRYSTAL INPUTS DRIVEN DIFFERENTIALLY (REFMODE = 1) (see Figure 4 and 6) (Note 11)
VDD
VIHSE − 200
VDD − 100
VDD
mV
mV
mV
mV
VIHD
VILD
VID
VCMR
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (VIHD – VILD)
Input Common Mode Range (Differential Configuration)
(Note 10) (Figure 8)
100
GND
100
50
VDD
VIHD – 100
VDD
VDD − 50
mV
mV
mV
mV
IIH Input HIGH Current CLK_XTAL1 and CLKb_XTAL2
IIL Input LOW Current CLK_XTAL1 & CLKb_XTAL2
LVCMOS − CONTROL AND SDA & SCL/PD INPUTS
−10 10 mA
−10 10 mA
VIH Input HIGH Voltage for MMC & REFMODE Pins
VDD = 3.3 V
VDD = 2.5 V
2.1
1.75
VDD
V
VIH Input HIGH Voltage for SDA & SCL/PD Pins
VDD = 3.3 V
VDD = 2.5 V
2.1
1.75
5.5 V
VIL Input LOW Voltage for Control Pins and SDA & SCL/PD VDD = 3.3 V
VDD = 2.5 V
GND
0.7
0.7
V
IIH
IIL
VIHtri
Input HIGH Current
Input LOW Current
Tri−Level Input High Voltage (FSn pins)
VIMtri Tri−Level Input Med Voltage (FSn pins)
VDD = 3.3 V
VDD = 2.5 V
VDD = 3.3 V
−150
−150
VDD x 75%
2.48
1.88
VDD x 40%
1.32
150
150
VDD
VDD
VDD
VDD x 60%
1.98
mA
mA
V
V
VILtri
Tri−Level Input Low Voltage (FSn pins)
VDD = 2.5 V
1.00
GND
1.67
VDD x 25%
V
RIN Input Impedance
VDD = 3.3 V
VDD = 2.5 V
0.00
0.00
0.83
V
0.63
10 kW
CIN Input Capacitance − Crystal pins; REFMODE = H
2 pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
7. LVPECL Outputs loaded with 50 W to VDDO – 2 V for proper operation.
8. LVPECL Output parameters vary 1:1 with VDDO.
9. VIH, VIL, Vth, and VISE parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VDD.
11. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
12. IDD / VDD is independent of IDDOn/ VDDOn
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NB3H5150
Table 10. AC CHARACTERISTICS
VDD = AVDDn = 3.3 V ±5% or 2.5 V ±5%; VDDO = 3.3V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; TA = −40°C to 85°C (Note 13)
Symbol
Characteristic
Min Typ Max
fCLKIN
fINBP
fCLK1,2,3
External Clock / Crystal Input Frequency − PLL Mode
External Clock Input Frequency – PLL Bypass Mode I2C Mode;
fin = fout
CLK1, CLK2, CLK3 Typical Output Clock Frequencies; fin = 25 MHz
−1000 ppm
1
25
25
33.33
50
100
125
156.25
+1000 ppm
50
fCLK4
CLK4 Outputs Typical Output Clock Frequencies; fin = 25 MHz
Resolution of 1 Hz
Integer
Frac−N
66.66
106.23
133.33
155.52
161.1328
fSDA/SCL Serial Data and Clock Rates
100k
tPWSCL
twm
tDC
FN
Serial Clock Pulse Width
Time SCL/PD Pin must be Held Low to “Wake−up” the Device
Output Clock Duty Cycle (Crystal or Reference Duty Cycle = 50%)
PLL Mode; <1 ns tf / tf
LVPECL fout = 156.25 MHz
LVCMOS fout = 33.33 MHz
PLL Bypass Mode; Input Duty Cycle = 50%, VINPP 1.2 V
Phase Noise (Integer−N)
fout = 156.25 MHz, fin = 25 MHz Crystal, LVPECL
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
1
100
47.5
47.5
45
50
50
−115
−130
−140
−145
−153
−153
52.5
52.5
55
FN Phase Noise (Integer−N)
fout = 100 MHz, fin = 25 MHz Crystal, LVCMOS
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
−120
−136
−142
−145
−156
−156
FN Phase Noise (Frac−N)
fout = 155.52 MHz, fin = 25 MHz Crystal, LVPECL
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
−115
−127
−131
−135
−152
−153
FN Phase Noise (Frac−N)
fout = 133.33 MHz, fin = 25 MHz Crystal, LVCMOS
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
−117
−126
−126
−131
−153
−153
tjit(F)
tjit(F)
tpd
RMS Phase Jitter − 25 MHz Crystal (Note 15)
Integration Range:12 kHz − 20 MHz
fout = 156.25 MHz, Integer CLKn
fout = 155.52 MHz; Frac−N CLK4
Additive RMS Phase Jitter (PLL Bypass in I2C Mode)
Integration Range:12 kHz − 5 MHz
fout = 25 MHz, CLK1
LVCMOS
Input to Output Propagation Delay (PLL Bypass in I2C Mode)
25 MHz
300
1000
50
5
Unit
MHz
MHz
MHz
MHz
bps
ms
ns
%
dBc
dBc
dBc
dBc
fs
fs
ns
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NB3H5150
Table 10. AC CHARACTERISTICS
VDD = AVDDn = 3.3 V ±5% or 2.5 V ±5%; VDDO = 3.3V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; TA = −40°C to 85°C (Note 13)
Symbol
Characteristic
Min Typ Max
Unit
PSRR
Ripple Induced Phase Spur Level
100 kHz & 1 MHz, 100 mVpp, Ripple Injected on VDD/AVDDn
100 MHz
dBc
−60
tr /tf Output Rise/Fall Times (CLKnA/CLKnB), 20% − 80% of VDDOn
fout = 156.25 Mhz
LVPECL
120
fout = 33.33 Mhz @ VDDO = 3.3 V
LVCMOS – 5 pF
500
ps
200 300
800 1000
VINPP
Stabilization
Time
Input Voltage Swing (Differential Configuration) (Note 14)
Stabilization Time From Power−up VDD = 3.3 V to First Edge Out
Upon Reprogram – (Pin−Strap mode), Change of Configuration
Power−up to Static Output Levels – (Pin−Strap mode)
Power−up to I2C Ready
100
1200
mV
5 6 ms
3
13
5
tPWRDWN Time to Power Down, SCL/PD Low−to−High
50 100 200 ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
13. Measured by using a 25 MHz crystal as clock source. All LVPECL outputs are loaded with an external RL = 50 W to VDDO – 2 V (Figure 9);
LVCMOS outputs loaded with RS = 33 W, CL = 5 pF, 5” 50 W trace, (Figure 11).
14. Input and output voltage swings are single−ended measurements operating in a differential mode.
15. VDD = 3.3 V, VDDO = 2.5 V (LVPECL) or 1.8 V (LVCMOS).
VIH
Vth
VIL
CLK_XTAL1
Vth CLK_XTAL2
Figure 3. Differential Input Driven Single−Ended
CLK_XTAL1
CLK_XTAL2
Figure 4. Differential Inputs Driven Differentially
VDD
Vthmax
VIHmax
VILmax
Vth CLK_XTAL1
Vthmin
GND
VIH
Vth
VIL
VIHmin
VILmin
Figure 5. Vth Diagram
CLK_XTAL2
CLK_XTAL1
VID = |VIHD(CLK) − VILD(CLK)|
VIHD
VILD
Figure 6. Differential Inputs Driven Differentially
VDD
VCMmax
VCMR
CLK_XTAL2
CLK_XTAL1
VCMmin
GND
VIHDmax
VILDmax
VID = VIHD − VILD
VIHDtyp
VILDtyp
VIHDmin
VILDmin
Figure 7. VCMR Diagram
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NB3H5150 (ON Semiconductor)
2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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3.3 V or 2.5 V
VDD and AVDDn
NB3H5150
LDOn
VDDOn
Figure 8. NB3H5150 Power Supply Filter Schemes
Locate VDDOn
0.1 mF Capacitors
on Top Layer Next
to Device Pins.
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2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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NB3H5150
Table 11. RECOMMENDED CRYSTAL SPECIFICATIONS
Crystal
Fundamental AT−Cut
Frequency
25 MHz
Load Capacitance
16 pF − 20 pF
Shunt Capacitance, C0
7 pF Max
Equivalent Series Resistance
50 W Max
Initial Accuracy at 25°C
± 20 ppm
Temperature Stability
± 30 ppm
Aging
± 20 ppm
C0/C1 Ratio
250 Max
Crystal max Drive Level
100 mW
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NB3H5150
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 9. Typical Termination for LVPECL Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Figure 10. Optional LVPECL output Loading and Termination
Figure 11. Typical LVCMOS Output Test Setup for Evaluation
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NB3H5150
Interfacing from 3.3 V LVPECL to LVDS
Since the output levels VOH and VOL of 3.3 V LVPECL
are more positive than the input range of LVDS receiver, a
special interface is required. (See Figures 12 and 13).
Furthermore, the open emitter design of the ECL output
structure needs proper termination, which can be
implemented with a resistor divider network to generate
proper LVDS DC levels (eq. 1).
RE1 ) RE2 + RE
(eq. 1)
The resistor divider network will divide the output
common mode voltage of LVPECL (VCM(LVPECL)) to
input common mode voltage of LVDS (VCM(LVDS)).
RE2
RE1 ) RE2
+
VCM(LVDS)
VCM(LVPECL)
(eq. 2)
Where:
RE1 = partial emitter current bias resistor
RE2 = partial emitter current bias resistor
RE = RE1 + RE2, the total emitter current bias resistor
(see AND8020)
VCM(LVPECL) = Common Mode Voltage
VCM(LVDS) = Common Mode Voltage
3.3 V LVPECL output will be able to drive an LVDS
receiver with or without an internal 100 W termination
resistor.
3.3 V
ZO
LVPECL
ZO
VCC
ZO
3.3 V
ZO
LVPECL
ZO
RE1
RE2
VCC
ZO
RE1
ZO
RT
100 W
LVDS
RE2
Figure 13. Interfacing LVPECL to LVDS with Internal
100 W Termination Resistor
Examples:
For 50 W controlled impedance, the resistor values for
3.3V LVPECL converted to LVDS voltage levels are as
follows:
RE1 = 55 W
RE2 = 95 W
RE1 + RE2 = RE = 150 W
RT = 100 W
VCM(LVPECL) = 1.9 V
VCM(LVDS) = 1.2 V
RE1
RE1
ZO
RT LVDS
100 W
RE2 RE2
Figure 12. Interfacing 3.3 V LVPECL to LVDS
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NB3H5150
Interfacing from 2.5 V LVPECL to LVDS
Provided that the LVDS receiver can tolerate large input
voltage peak to peak amplitude, the 2.5 V LVPECL output
can be directly interfaced to an LVDS receiver using proper
ECL termination. The 2.5 V LVPECL output will be able to
drive an LVDS receiver with or without internal 100 W
termination resistor. (See Figures 14, 15 and 16).
2.5 V
VCC
ZO
LVPECL
ZO
RT
100 W
LVDS
Furthermore, a series termination can be used to reduce
the amplitude of the signal as described in AND8020
application note, by placing RS resistor between the driver
and the transmission line. (See Figures 17, 18 and 19).
2.5 V
RS ZO
VCC
LVPECL
RS’ ZO
RT LVDS
100 W
RE RE
RE RE
Figure 14. Interfacing 2.5 V LVPECL to LVDS with
External 100 W Termination Resistor
2.5 V
LVPECL
VCC
ZO
ZO
RT
100 W
LVDS
Figure 17. Interfacing 2.5 V LVPECL to LVDS with
Series RS and External 100 W Termination Resistor
2.5 V
RS
LVPECL
RS
RE RE
VCC
ZO
RT
100 W
LVDS
ZO
RE RE
Figure 15. Interfacing 2.5 V LVPECL to LVDS with
Internal 100 W Termination Resistor
1.50 V
2.5 V LVPECL
Output
720 mV
LVDS
Input
0.78 V
Where RE = 75 W
Figure 16. PSPICE Simulation Levels of 2.5V LVPECL
to LVDS Interface with Example Resistor Values
Figure 18. Interfacing 2.5 V LVPECL to LVDS with
Series RS and Internal 100 W Termination Resistor
1.30 V
2.5 V LVPECL
Output
430 mV
LVDS
Input
0.87 V
Where RE = 75 W
RS = 43 W
Figure 19. PSPICE Simulation Levels of 2.5V LVPECL
to LVDS Interface with Series RS Resistor
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NB3H5150
Figure 20. Via Layout Recommendation for Exposed Pad, QFN−32 Package
The exposed pad on the NB3H5150 QFN−32 package carries all of the power supply return currents. It is therefore important
that the necessary current capability be satisfied, as well as the thermal transfer from the die to the PCB. Figure 20 shows a
recommended via layout pattern for the exposed pad. Via spacing = 0.02”, filled vias preferred.
ORDERING INFORMATION
Device
Marking
Tables
Package
Shipping
NB3H5150MNTXG
NB3H
5150
3&4
QFN−32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB3H5150 (ON Semiconductor)
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NB3H5150
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 485CE
ISSUE O
D
PIN ONE
ÉÉÉÉÉÉÉÉÉREFERENCE
A LL
B
L1
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
0.15 C
0.15 C TOP VIEW
0.10 C
DETAIL B (A3)
0.08 C
NOTE 4
SIDE VIEW A1
EXPOSED Cu
MOLD CMPD
ÉÇÇÉÇÇÉÇÇDETAIL B
ALTERNATE
A CONSTRUCTION
C
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN MAX
A 0.80 1.00
A1 −−− 0.05
A3 0.20 REF
b 0.20 0.30
D 5.00 BSC
D2 3.40 3.60
E 5.00 BSC
E2 3.40 3.60
e 0.50 BSC
K 0.20 −−−
L 0.30 0.50
L1 −−− 0.15
DETAIL A
8
D2
K
17
E2
32X L
1 24
32 25
e
e/2
BOTTOM VIEW
32X b
0.10 M
0.05 M
C A-B B
C NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
5.30
3.70
32X
0.62
3.70 5.30
0.50
PITCH
32X
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Email: orderlit@onsemi.com
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
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19
NB3H5150/D




NB3H5150.pdf
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