NB3N111K (ON Semiconductor)
3.3V Differential 1:10 Fanout Clock Driver

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NB3N111K
3.3V Differential 1:10
Fanout Clock Driver with
HCSL Outputs
Description
The NB3N111K is a differential 1:10 Clock fanout buffer with
Highspeed Current Steering Logic (HCSL) outputs optimized for
ultra low propagation delay variation. The NB3N111K is designed
with PCI Express HCSL clock distribution and FBDIMM applications
in mind.
Inputs can directly accept differential LVPECL, LVDS, and HCSL
signals per Figures 7, 8, and 9. Singleended LVPECL, HCSL,
LVCMOS, or LVTTL levels are accepted with a proper external Vth
reference supply per Figures 4 and 10. Input pins incorporate separate
internal 50 W termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 1) to GND per Figure 6. Outputs can also interface to LVDS
receivers when terminated per Figure 11.
The NB3N111K specifically guarantees low output–to–output
skew. Optimal design, layout, and processing minimize skew within a
device and from device to device. System designers can take
advantage of the NB3N111K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
Typical Input Clock Frequency 100, 133, 166, or 400 MHz
220 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd 100 ps Maximum Propagation Delay Variation per Diff Pair
0.1 ps Typical RMS Additive Phase Jitter
LVDS Output Levels Optional with Interface Termination
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
Typical HCSL Output Levels (700 mV PeaktoPeak)
LVDS Output Levels with Interface Termination
These are PbFree Devices
Applications
Clock Distribution
PCIe I, II, III
Networking
High End Computing
Routers
End Products
Servers
FBDIMM Memory Card
© Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 5
1
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1 32
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM*
1
NB3N
111K
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
VTCLK
CLK
CLK
VTCLK
VCC
GND
IREF
RREF
Q0
Q0
Q1
Q1
Q8
Q8
Q9
Q9
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Publication Order Number:
NB3N111K/D


NB3N111K (ON Semiconductor)
3.3V Differential 1:10 Fanout Clock Driver

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NB3N111K
Exposed Pad (EP)
32 31 30 29 28 27 26 25
IREF 1
VTCLK 2
CLK 3
CLK 4
VTCLK 5
Q9 6
Q9 7
GND 8
NB3N111K
24 VCC
23 Q3
22 Q3
21 Q4
20 Q4
19 Q5
18 Q5
17 VCC
9 10 11 12 13 14 15 16
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O
Description
1 IREF
Use the IREF pin to set the output drive. Connect a 475 W RREF
resistor from the IREF pin to GND to produce 2.6 mA of IREF current. A
current mirror multiplies IREF by a factor of 5.4x to force 14 mA through
a 50 W output load. See Figures 6 and 12.
2, 5 VTCLK,
VTCLK
Internal 50 W Termination Resistor connection Pins. In the differential
configuration when the input termination pins are connected to the
common termination voltage, and if no signal is applied then the device
may be susceptible to selfoscillation.
3 CLK LVPECL, HCSL, Clock and Data (TRUE) Input
LVDS Input
4 CLK LVPECL, HCSL, Clock and Data (INVERT) Input
LVDS Input
6, 10, 12, 14, 18, 20,
22, 26, 28, 30
Q[90]
HCSL or LVDS
(Note 1) Output
Output (INVERT) (Note 1)
7, 11, 13, 15, 19, 21,
23, 27, 29, 31
Q[90]
HCSL or LVDS
(Note 1) Output
Output (TRUE) (Note 1)
8 GND Supply Ground. GND pin must be externally connected to power supply
to guarantee proper operation.
9, 16, 17, 24, 25, 32
VCC
Positive Voltage Supply pin. VCC pins must be externally connected to a
power supply to guarantee proper operation.
Exposed Pad
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see
case drawing) must be attached to a sufficient heatsinking conduit for
proper thermal operation and electrically connected to the circuit board
ground (GND).
1. Outputs can also interface to LVDS receiver when terminated per Figure 11.
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NB3N111K (ON Semiconductor)
3.3V Differential 1:10 Fanout Clock Driver

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NB3N111K
Table 2. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity (Note 2)
QFN32
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value
>2 kV
200 V
Level 1
UL 94 V0 @ 0.125 in
286
Table 3. MAXIMUM RATINGS (Note 3)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
VI
VINPP
IOUT
Positive Power Supply
Positive Input
Differential Input Voltage
Output Current
GND = 0 V
GND = 0 V
Continuous
Surge
4.6
GND 0.3 VI VCC
VCC
50
100
V
V
V
mA
mA
TA Operating Temperature Range
QFN32
Tstg Storage Temperature Range
qJA
Thermal Resistance (JunctiontoAmbient) (Note 3) 0 lfpm
500 lfpm
QFN32
QFN32
40 to +85
65 to +150
31
27
°C
°C
°C/W
°C/W
qJC Thermal Resistance (JunctiontoCase)
2S2P (Note 3)
QFN32
12 °C/W
Tsol Wave Solder
PbFree
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard 516, multilayer board 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB3N111K (ON Semiconductor)
3.3V Differential 1:10 Fanout Clock Driver

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NB3N111K
Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = 40°C to +85°C Note 4)
Symbol
Characteristic
Min Typ
Max
Unit
IGND GND Supply Current (All Outputs Loaded)
ICC Power Supply Current (All Outputs Loaded)
IIH Input HIGH Current
IIL Input LOW Current
RTIN Internal Input Termination Resistor
DIFFERENTIAL INPUT DRIVEN SINGLEENDED
150
45
60
210
2.0
2.0
50
90
260
150
55
mA
mA
mA
mA
W
Vth Input Threshold Reference Voltage Range (Note 5)
VIH Single*Ended Input HIGH Voltage
VIL Single*Ended Input LOW Voltage
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8 and 9)
350
Vth + 150
GND
VCC 1000
VCC
Vth 150
mV
mV
mV
VIHD Differential Input HIGH Voltage
VILD Differential Input LOW Voltage
VID Differential Input Voltage (VIHD * VILD)
VCMR Input Common Mode Range
HCSL OUTPUTS (Figure 4)
425
GND
150
350
VCC 850
VCC 1000
VCC 850
VCC 1000
mV
mV
mV
mV
VOH Output HIGH Voltage
600 740
900
mV
VOL Output LOW Voltage
150
0
150
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurements taken with outputs loaded 50 W to GND. Connect a 475 W resistor from IREF (Pin 1) to GND. See Figure 6.
5. Vth is applied to the complementary input when operating in single ended mode per Figure 4.
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NB3N111K (ON Semiconductor)
3.3V Differential 1:10 Fanout Clock Driver

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NB3N111K
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; 40°C to +85°C (Note 6)
Symbol
Characteristic
Min Typ Max Unit
VOUTPP
tPLH,
tPHL
DtPLH,
DtPHL
tSKEW
Output Voltage Amplitude (@ VINPPmin) fin 400 MHz
Propagation Delay (See Figure 3a)
Propagation Delay Variation Per Each Diff Pair
(Note 7) (See Figure 3a)
Duty Cycle Skew (Note 8)
Within Device Skew
Device to Device Skew (Note 9)
CLK/CLK to Qx/Qx 550
725 1000
800 1100
mV
ps
CLK/CLK to Qx/Qx
ps
100
20 ps
100
150
tJITq
VINPP
Additive Integrated Phase Jitter at Fc = 100 MHz (Note 10)
Input Voltage Swing/Sensitivity
(Differential Configuration)
0.1 ps
0.150
VCC
0.85
V
VCROSS
DVCROSS
tr , tf
Absolute Crossing Magnitude Voltage (See Figure 3b)
Variation in Magnitude of VCROSS (See Figure 3b)
Absolute Magnitude in Output Risetime and Falltime (from 175 mV to 525 mV)
(See Figure 3b)
250
Qx, Qx 150
550
150
220 400
mV
mV
ps
Dtr, Dtf Variation in Magnitude of Risetime and Falltime (SingleEnded) (See Figure 3b) Qx, Qx
125 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Measured by forcing VINPP (MIN) from a 50% duty cycle. Measurement taken with all outputs loaded 50 W to GND. Connect a 475 W resistor
from IREF (Pin 1) to GND. See Figure 6.
7. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges per Figure 3.
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpwand Tpw+.
9. Skew is measured between outputs under identical transition conditions @ 50 MHz.
10. Phase noise integrated from 12 kHz to 20 MHz.
Qx
525 mV
CLK
CLK
tPLH
Q
Qx
VINPP = VIH(CLK) VIL(CLK)
= VIH(CLK) VIL(CLK)
Qx
175 mV
525 mV
tr
tf
tPHL
trMAX
175 mV
tfMAX
Qx
VOUTPP = VOH(Qx) VOL(Qx)
= VOH(Qx) VOL(Qx)
trMIN
trMAX trMIN = Dtr
tfMIN
tfMAX tfMIN = Dtf
(b) tr, tf and Dtr, Dtf
Qx
Q
DtPLH
DtPHL
(a) Propagation Delay and
Propagation Delay Variation
VCROSS
DVCROSS
Qx
Figure 3. AC Reference Measurement(c) VCROSS and DVCROSS
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NB3N111K (ON Semiconductor)
3.3V Differential 1:10 Fanout Clock Driver

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NB3N111K
CLK
Vth
CLK
Vth
Figure 4. SingleEnded Interconnect
Vth Reference Voltage
VCC
VCMRmax
VCMR
VCMRmin
IN
IN
VIHDmax
VILDmax
VID = VIHD VILD
VIHDtyp
VILDtyp
VIHDmin
VILDmin
VEE
Figure 5. Vth Diagram
Qx RS1B Z0 = 50 W
HCSL
Driver
RS2B
Z0 = 50 W
IREF Qx
RREFA
CL1C
2 pF
CL2C
2 pF
Receiver
RL1D
50 W
RL2D
50 W
A. Connect 475 W resistor RREF from IREF pin to GND.
B. RS1, RS2: 0 W for Test and Evaluation. Select to Minimizing Ringing.
C. CL1, CL2: Receiver Input Simulation (for test only not added to application circuit)
Load capacitance only.
D. DL1, DL2 Termination and Load Resistors Located at Receiver Inputs.
Figure 6. Typical Termination Configuration for Output Driver and Device Evaluation
VCC = 3.3 V / 2.5 V
VCC = 3.3 V
LVPECL
Driver
Z0 = 50 W CLK
VTCLK
VTCLK
Z0 = 50 W CLK
NB3N111K
50 W*
50 W*
VTCLK = VTCLK = VCC 2.0 V
GND
GND
*RTIN, Internal Input Termination Resistor
Figure 7. LVPECL Interface
VCC = 3.3 V / 2.5 V / 1.8 V
VCC = 3.3 V
LVDS
Driver
Z0 = 50 W CLK
VTCLK
VTCLK
Z0 = 50 W CLK
NB3N111K
50 W*
50 W*
GND
VTCLK = VTCLK
GND
*RTIN, Internal Input Termination Resistor
Figure 8. LVDS Interface
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NB3N111K (ON Semiconductor)
3.3V Differential 1:10 Fanout Clock Driver

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VCC = 3.3 V / 2.5 V / 1.8 V
VCC
HCSL
Driver
Z0 = 50 W CLK
GND
VTCLK
VTCLK
Z0 = 50 W CLK
NB3N111K
50 W*
50 W*
GND
VTCLK = VTCLK = GND
GND
NB3N111K
VCC = 3.3 V / 2.5 V / 1.8 V
VCC
LVCMOS/
LVTTL
Driver
GND
Z0 = 50 W CLK
VTCLK
VTCLK
CLK
Vth
NB3N111K
50 W*
50 W*
VTCLK = OPEN
VTCLK = OPEN
CLK = Vth
GND
*RTIN, Internal Input Termination Resistor
Figure 9. Standard 50 W Load HCSL Interface
*RTIN, Internal Input Termination Resistor
Figure 10. LVCMOS/LVTTL Interface
Qx
NB3N111K
HCSL
Device Qx
IREF
RREF
Zo = 50 W
100 W
Zo = 50 W
RL = 150 W
100 W
RL = 150 W
LVDS
Device
GND
Figure 11. HCSL Interface Termination to LVDS
2.6 mA
14 mA
IREF
RREF
475 W
Qx
RL1 50 W
Qx
RL2 50 W
Figure 12. HCSL Simplified Output Structure
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NB3N111K (ON Semiconductor)
3.3V Differential 1:10 Fanout Clock Driver

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NB3N111K
ORDERING INFORMATION
Device
Package
Shipping
NB3N111KMNG
QFN32
(PbFree)
74 Units / Rail
NB3N111KMNR4G
QFN32
(PbFree)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB3N111K (ON Semiconductor)
3.3V Differential 1:10 Fanout Clock Driver

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NB3N111K
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM01
ISSUE O
PIN ONE
ÉÉÉÉLOCATION
D
A
B
E
2 X 0.15 C
TOP VIEW
2 X 0.15 C
0.10 C
32 X 0.08 C
(A3)
SIDE VIEW A1
A
SEATING
PLANE
C
L
32 X
EXPOSED PAD
9
D2
16 17
K
32 X
8
E2
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN NOM MAX
A 0.800 0.900 1.000
A1 0.000 0.025 0.050
A3 0.200 REF
b 0.180 0.250 0.300
D 5.00 BSC
D2 2.950 3.100 3.250
E 5.00 BSC
E2 2.950 3.100 3.250
e 0.500 BSC
K 0.200 −−− −−−
L 0.300 0.400 0.500
SOLDERING FOOTPRINT*
5.30
32 X
0.63
3.20
1
32
32 X b
0.10 C A B
0.05 C
24
25
e
BOTTOM VIEW
3.20 5.30
32 X
0.28
28 X
0.50 PITCH
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 8002829855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81358171050
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB3N111K/D




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