HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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DATA SHEET
( DOC No. HX8357-D00/D01-DS )
HX8357-D00/D01
320RGB x 480 dot, 16M color,
with internal GRAM,
TFT Mobile Single Chip Driver
Temporary Version 00 April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
April, 2012
1. General Description ................................................................................................................................. 9
2. Features................................................................................................................................................... 10
2.1 Display ........................................................................................................................................... 10
2.2 Display module .............................................................................................................................. 10
2.3 Display control interface .................................................................................................................11
2.4 Input power .....................................................................................................................................11
2.5 Miscellaneous .................................................................................................................................11
3. Block Diagram ........................................................................................................................................ 12
3.1 Block diagram ................................................................................................................................ 12
3.2 Pin description ............................................................................................................................... 13
3.3 Pin assignment .............................................................................................................................. 16
4. Interface................................................................................................................................................... 17
4.1 MIPI DBI-B interface...................................................................................................................... 18
4.2 Serial data transfer interface (MIPI DBI TYPE-C) ......................................................................... 34
4.2.1 Serial data write mode.......................................................................................................... 34
4.2.2 Read operation in serial peripheral interface........................................................................ 35
4.2.3 DBI TYPE-C interface data color coding .............................................................................. 36
4.2.4 Break and pause sequences ................................................................................................ 38
4.3 MIPI DPI interface (display pixel interface) ................................................................................... 40
4.4 DSI system interface (For HX8357-D01 only) ............................................................................... 45
4.4.1 DSI layer definitions.............................................................................................................. 46
4.4.2 DSI protocol .......................................................................................................................... 47
5. Functional Description .......................................................................................................................... 59
5.1 Display data GRAM mapping ........................................................................................................ 59
5.1.1 Address counter (AC) ........................................................................................................... 59
5.1.2 System interface to GRAM write direction............................................................................ 60
5.1.3 Source, gate and memory map ............................................................................................ 62
5.1.4 Fully display, partial display, vertical scrolling display .......................................................... 63
5.2 Tearing effect output line ............................................................................................................... 70
5.2.1 Tearing effect line modes...................................................................................................... 70
5.2.2 Tearing effect line timing....................................................................................................... 72
5.2.3 Example 1: MPU write is faster than panel read .................................................................. 73
5.2.4 Example 2: MPU write is slower than panel read................................................................. 74
5.3 Checksums .................................................................................................................................... 75
5.4 Oscillator........................................................................................................................................ 78
5.5 Source driver ................................................................................................................................. 79
5.6 Gate driver ..................................................................................................................................... 80
5.7 LCD power generation circuit ........................................................................................................ 81
5.7.1 Power supply circuit.............................................................................................................. 81
5.7.2 LCD power generation scheme............................................................................................ 82
5.8 Gamma characteristic correction function ..................................................................................... 83
5.8.1 Gamma characteristic correction function ............................................................................ 84
5.8.2 Gray voltage generator for digital gamma correction ........................................................... 87
5.9 Power function ............................................................................................................................... 88
5.9.1 Power on/off sequence......................................................................................................... 88
5.9.2 Power levels definition.......................................................................................................... 91
5.9.3 Deep standby mode set up flow ........................................................................................... 92
5.10 Input / output pin state ................................................................................................................... 93
5.10.1 Output pins ........................................................................................................................... 93
5.10.2 Input pins .............................................................................................................................. 93
5.11 Sleep out – command and self-diagnostic functions of display module........................................ 94
5.11.1 Register loading detection .................................................................................................... 94
5.11.2 Functionality detection.......................................................................................................... 95
5.12 Content adaptive brightness control (CABC) function................................................................... 96
5.12.1 Module architectures ............................................................................................................ 97
5.12.2 Brightness control block ....................................................................................................... 98
Himax Confidential
-P.2-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
April, 2012
5.12.3 Minimum brightness setting of CABC function ..................................................................... 99
5.12.4 Display dimming ................................................................................................................. 102
5.13 OTP programing .......................................................................................................................... 103
5.13.1 OTP table............................................................................................................................ 103
5.13.2 OTP programming flow....................................................................................................... 104
6. Command Set ....................................................................................................................................... 105
6.1 Command set list ......................................................................................................................... 105
6.1.1 Standard command ............................................................................................................ 105
6.1.2 User define command list table ...........................................................................................110
6.2 Command description...................................................................................................................114
6.2.1 NOP .....................................................................................................................................114
6.2.2 Software reset (01h) ............................................................................................................115
6.2.3 Read display identification information (04h) ......................................................................116
6.2.4 RDNUMPE: Read Number of the Errors on DSI (05h) .......................................................117
6.2.5 Read red color (06h)............................................................................................................118
6.2.6 Read green color (07h)........................................................................................................119
6.2.7 Read blue color (08h) ......................................................................................................... 120
6.2.8 Read display power mode (0Ah) ........................................................................................ 121
6.2.9 Read display MADCTL (0Bh) ............................................................................................. 123
6.2.10 Read display pixel format (0Ch) ......................................................................................... 125
6.2.11 Read display image mode (0Dh) ........................................................................................ 127
6.2.12 Read display signal mode (0Eh) ........................................................................................ 129
6.2.13 Read display self-diagnostic result (0Fh) ........................................................................... 130
6.2.14 Sleep in (10h) ..................................................................................................................... 131
6.2.15 Sleep out (11h) ................................................................................................................... 133
6.2.16 Partial mode on (12h) ......................................................................................................... 135
6.2.17 Normal display mode on (13h) ........................................................................................... 136
6.2.18 Display inversion off (20h) .................................................................................................. 137
6.2.19 Display inversion on (21h) .................................................................................................. 138
6.2.20 All pixel off (22h) ................................................................................................................. 139
6.2.21 All pixel on (23h) ................................................................................................................. 140
6.2.22 Gamma set (26h)................................................................................................................ 141
6.2.23 Display off (28h).................................................................................................................. 142
6.2.24 Display on (29h) ................................................................................................................. 143
6.2.25 Column address set (2Ah).................................................................................................. 144
6.2.26 Page address set (2Bh)...................................................................................................... 146
6.2.27 Memory write (2Ch) ............................................................................................................ 148
6.2.28 Memory read (2Eh)............................................................................................................. 149
6.2.29 Partial area (30h) ................................................................................................................ 150
6.2.30 Vertical scrolling definition (33h)......................................................................................... 152
6.2.31 Tearing effect line off (34h) ................................................................................................. 155
6.2.32 Tearing effect line on (35h) ................................................................................................. 156
6.2.33 Memory access control (36h) ............................................................................................. 157
6.2.34 Vertical scrolling start address (37h) .................................................................................. 159
6.2.35 Idle mode off (38h) ............................................................................................................. 161
6.2.36 Idle mode on (39h) ............................................................................................................. 162
6.2.37 Interface pixel format (3Ah) ................................................................................................ 164
6.2.38 Write_memory_contiune (3Ch)........................................................................................... 165
6.2.39 Raed_memory_continue (3Eh) .......................................................................................... 166
6.2.40 Set tear scan line (44h) ...................................................................................................... 167
6.2.41 Get Scan Lines (45h).......................................................................................................... 168
6.2.42 Write display brightness value (51h) .................................................................................. 169
6.2.43 Read display brightness value (52h) .................................................................................. 170
6.2.44 Write control display (53h).................................................................................................. 171
6.2.45 Read control value display (54h) ........................................................................................ 172
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.3-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
April, 2012
6.2.46 Write content adaptive brightness control (55h)................................................................. 173
6.2.47 Read content adaptive brightness control (56h) ................................................................ 174
6.2.48 Write CABC minimum brightness (5Eh) ............................................................................. 175
6.2.49 Read CABC minimum brightness (5Fh) ............................................................................. 176
6.2.50 Read automatic brightness control self-diagnostic result (68h) ......................................... 177
6.2.51 Read Black/White Low Bits (70h) ....................................................................................... 178
6.2.52 Read Bkx (71h)................................................................................................................... 179
6.2.53 Read Bky (72h)................................................................................................................... 180
6.2.54 Read Wx (73h) ................................................................................................................... 181
6.2.55 Read Wy (74h) ................................................................................................................... 182
6.2.56 Read Red/Green Low Bits (75h) ........................................................................................ 183
6.2.57 Read Rx (76h) .................................................................................................................... 184
6.2.58 Read Ry (77h) .................................................................................................................... 185
6.2.59 Read Gx (78h) .................................................................................................................... 186
6.2.60 Read Gy (79h) .................................................................................................................... 187
6.2.61 Read Blue/AColur Low Bits (7Ah) ...................................................................................... 188
6.2.62 Read Bx (7Bh) .................................................................................................................... 189
6.2.63 Read By (7Ch) .................................................................................................................... 190
6.2.64 Read Ax (7Dh) .................................................................................................................... 191
6.2.65 Read Ay (7Eh) .................................................................................................................... 192
6.2.66 Read_DDB_start (A1h)....................................................................................................... 193
6.2.67 Read_DDB_continue (A8h) ................................................................................................ 194
6.2.68 Read first checksum (AAh)................................................................................................. 195
6.2.69 Read continue checksum (AFh) ......................................................................................... 196
6.2.70 Read ID1 (DAh) .................................................................................................................. 197
6.2.71 Read ID2 (DBh) .................................................................................................................. 198
6.2.72 Read ID3 (DCh) .................................................................................................................. 199
6.2.73 SETOSC: set internal oscillator (B0h) ................................................................................ 200
6.2.74 SETPOWER: set power control (B1h)................................................................................ 201
6.2.75 SETDISPLAY: set display related register (B2h)................................................................ 205
6.2.76 SETRGB: set RGB interface (B3h) .................................................................................... 207
6.2.77 SETCYC: set display cycle register (B4h).......................................................................... 210
6.2.78 SETBGP (B5h) ................................................................................................................... 212
6.2.79 SETCOM: set VCOM voltage related register (B6h) .......................................................... 214
6.2.80 SETOTP: set OTP setting (B7h)......................................................................................... 216
6.2.81 SETEXTC: enable extension command (B9h) ................................................................... 217
6.2.82 SETSTBA (C0h) ................................................................................................................. 218
6.2.83 SETDGC: set DGC related setting (C1h) ........................................................................... 220
6.2.84 SETID: set ID (C3h)............................................................................................................ 221
6.2.85 SETDDB: Set DDB (C4h) ................................................................................................... 222
6.2.86 SETCABC: set CABC related setting (C9h) ....................................................................... 223
6.2.87 SETPanel: set panel characteristic (CCh) .......................................................................... 224
6.2.88 SETGamma: set gamma curve (E0h) ................................................................................ 225
6.2.89 SETIMAGE: set image function (E9h)................................................................................ 227
6.2.90 SETMESSI: Set Command type (EAh) .............................................................................. 228
6.2.91 SETCOLOR: set color (EBh) .............................................................................................. 229
6.2.92 SETREADINDEX: set SPI read index (FEh) ...................................................................... 231
6.2.93 GETSPIREAD: SPI Read Command Data (FFh)............................................................... 232
6.2.94 GETICID: IC ID Read Command Data (D0h)..................................................................... 233
7. Layout Recommendation .................................................................................................................... 234
7.1 Maximum layout resistance ......................................................................................................... 235
7.2 External components connection ................................................................................................ 236
8. Electrical Characteristic ...................................................................................................................... 237
8.1 Absolute maximum ratings .......................................................................................................... 237
8.2 DC characteristics ....................................................................................................................... 238
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.4-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
April, 2012
8.3 AC characteristics........................................................................................................................ 239
8.4 DBI Type B interface characteristic ............................................................................................. 239
8.4.1 DBI Type C interface characteristics .................................................................................. 240
8.4.2 DPI interface characteristics............................................................................................... 241
8.4.3 Reset input timing............................................................................................................... 243
8.4.4 DSI D-PHY electrical characteristics .................................................................................. 246
9. Ordering Information............................................................................................................................ 254
10. Revision History ................................................................................................................................... 254
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.5-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
April, 2012
Figure 4.1: DBI-B system interface protocol, write to register or GRAM .......................................... 18
Figure 4.2: DBI-B system interface protocol, read from register or GRAM....................................... 18
Figure 4.3: Example of DBI-B System 8-bit bus Interface ................................................................ 19
Figure 4.4: Write data for RGB 5-6-5 (65k colors) bits input in 8-bit parallel interface ..................... 19
Figure 4.5: Write data for RGB 6-6-6-bits(262k colors) input in 8-bit parallel interface .................... 20
Figure 4.6: Write data for RGB 8-8-8-bits(16M colors) input in 8-bit parallel interface..................... 21
Figure 4.7: Example of DBI-B system 9-bit bus interface ................................................................. 22
Figure 4.8: Write data for RGB 5-6-5 (65k colors) bits input in 9-bit parallel interface ..................... 22
Figure 4.9: Write data for RGB 6-6-6 (262k colors) bits input in 9-bit parallel interface ................... 23
Figure 4.10: Example of DBI-B System 16-bit bus interface ............................................................ 24
Figure 4.11: Write data for RGB 5-6-5 (65k colors) bits input in 16-bit parallel interface ................. 25
Figure 4.12: Write data for RGB 6-6-6 (262k colors) bits input in 16-bit parallel interface ............... 26
Figure 4.13: Write data for RGB 8-8-8 (16M colors) bits input in 16-bit parallel interface ................ 27
Figure 4.14: Example of DBI-B system 18-bit parallel bus interface ................................................ 28
Figure 4.15 Write data for RGB 6-6-6 (262k colors) bits input in 18-bit parallel interface ................ 29
Figure 4.16: Example of DBI-B system 24-bit parallel bus interface ................................................ 30
Figure 4.17 Write data for RGB 8-8-8 (16M colors) bits input in 24-bit parallel interface ................. 31
Figure 4.18: DBI type C – serial interface protocol 3 wire/ 4 wire, write mode ................................. 34
Figure 4.19: Command read operation in serial peripheral interface................................................ 35
Figure 4.20: Write data for RGB 5-6-5-bit input of DBI TYPE-C OPTION 1 ..................................... 36
Figure 4.21: Write data for RGB 5-6-5-bit input of DBI TYPE-C OPTION 3 ..................................... 36
Figure 4.22: Write data for RGB 6-6-6-bit input of DBI TYPE-C OPTION 1 ..................................... 36
Figure 4.23: Write data for RGB 6-6-6-bit input of DBI TYPE-C OPTION 3 ..................................... 36
Figure 4.24: Display module data transfer recovery ......................................................................... 38
Figure 4.25: Break during parameter ................................................................................................ 38
Figure 4.26: Display module data transfer pause ............................................................................. 39
Figure 4.27: PCLK cycle ................................................................................................................... 40
Figure 4.28: General timing diagram................................................................................................. 41
Figure 4.29: DPI timing diagram ....................................................................................................... 41
Figure 4.30: 16-bit data bus color order on DPI interface ................................................................. 42
Figure 4.31: 18-bit data bus color order on DPI interface ................................................................. 43
Figure 4.32: DSI transmitter and receiver interface .......................................................................... 45
Figure 4.33: Transmitter and receiver interface ................................................................................ 46
Figure 4.34: DSI multiple HS transmission packets.......................................................................... 47
Figure 4.35: Structure of the short packet......................................................................................... 47
Figure 4.36: Structure of the long packet.......................................................................................... 48
Figure 4.37: Format of data ID .......................................................................................................... 48
Figure 4.38: Show short- / long-packet transmission command sequence ...................................... 49
Figure 5.1: Image data sending order from host............................................................................... 60
Figure 5.2: MY,MX,MV Setting of GRAM control.............................................................................. 60
Figure 5.3: Memory map 320RGBx480 dot ...................................................................................... 62
Figure 5.4: Memory map of full display ............................................................................................. 63
Figure 5.5: Vertical scrolling .............................................................................................................. 66
Figure 5.6: Memory map of vertical scrolling example 1................................................................... 66
Figure 5.7: Memory map of vertical scrolling example 2................................................................... 67
Figure 5.8: Memory map of vertical scrolling example 3................................................................... 67
Figure 5.9: Display of vertical scroll example 1................................................................................. 68
Figure 5.10: Display of vertical scroll example 2............................................................................... 69
Figure 5.11: TE mode 1 output.......................................................................................................... 70
Figure 5.12: TE delay output............................................................................................................. 70
Figure 5.13: TE mode 2 output ......................................................................................................... 71
Figure 5.14: TE output waveform...................................................................................................... 71
Figure 5.15: Waveform of tearing effect signal ................................................................................. 72
Figure 5.16: Timing of tearing effect signal....................................................................................... 72
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.6-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
April, 2012
Figure 5.17: Timing of MPU write is faster than panel read .............................................................. 73
Figure 5.18: Display of MPU write is faster than panel read............................................................. 73
Figure 5.19: Timing of MPU write is slower than panel read............................................................. 74
Figure 5.20: Display of MPU write is slower than panel read ........................................................... 74
Figure 5.21: HX8357-D00/D01 internal clock circuit ......................................................................... 78
Figure 5.22: Source channels of ZigZag inversion mode ................................................................. 79
Figure 5.23: Scan direction of Gate Driver........................................................................................ 80
Figure 5.24: Block diagram of HX8357-D00/D01 power circuit ........................................................ 81
Figure 5.25: LCD power generation scheme .................................................................................... 82
Figure 5.26: Gamma adjustments different of source driver with digital gamma correction ............. 83
Figure 5.27: Gamma resister stream and gamma reference voltage ............................................... 84
Figure 5.28: Relationship between GRAM data and output level (normal white panel REV_Panel=“0”)
................................................................................................................................................... 85
Figure 5.29: Gamma curve according to GC0 to GC3 bit ................................................................. 86
Figure 5.30: Block diagram of digital gamma correction................................................................... 87
Figure 5.31: Case 1 – NRESET line is held high or unstable by host at power on........................... 89
Figure 5.32: NRESET line is held low by host at power on .............................................................. 90
Figure 5.33: Power flow chart for different power modes ................................................................. 91
Figure 5.34: Deep standby mode setting flow................................................................................... 92
Figure 5.35: RDDSDR register loading detection flow...................................................................... 94
Figure 5.36: Functionality detection flow........................................................................................... 95
Figure 5.37: CABC block diagram..................................................................................................... 96
Figure 5.38: CABC_PWM_OUT output duty..................................................................................... 98
Figure 5.39: RDABCSDR register loading detection flow ............................................................... 100
Figure 5.40: RDABCSDR functionality detection flow..................................................................... 101
Figure 5.41: Dimming function ........................................................................................................ 102
Figure 5.42: OTP programming sequence...................................................................................... 104
Figure 7.1: Layout recommendation of HX8357-D00/D01.............................................................. 234
Figure 8.1: DBI Type B interface characteristics ............................................................................. 239
Figure 8.2: DBI Type C interface characteristics............................................................................. 240
Figure 8.3: General timings for RGB I/F-2 ...................................................................................... 242
Figure 8.4: Reset input timing ......................................................................................................... 243
Figure 8.5: tACC and tOH measurement condition set-up ............................................................. 244
Figure 8.6: tACC and tOH minimum condition set-up..................................................................... 244
Figure 8.7: tACC and tOH maximum value measurement.............................................................. 245
Figure 8.8: Electrical functions of a fully D-PHY transceiver .......................................................... 246
Figure 8.9: Shows both the HS and LP signal levels ...................................................................... 246
Figure 8.10: Input glitch rejections of low-power receivers ............................................................. 249
Figure 8.11: DDR clock definition.................................................................................................... 251
Figure 8.12: Data to clock timing definitions ................................................................................... 252
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.7-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Tables
April, 2012
Table 4.1: Interface selection ............................................................................................................ 17
Table 4.2: 8-bit interface GRAM write table....................................................................................... 32
Table 4.3: 9-bit interface GRAM write table....................................................................................... 32
Table 4.4: 16-bit interface GRAM write table .................................................................................... 32
Table 4.5: 18-bit interface GRAM write table .................................................................................... 32
Table 4.6: 24-bit interface GRAM write table .................................................................................... 32
Table 4.7: 8-bit parallel interface GRAM read table .......................................................................... 33
Table 4.8: 16-bit parallel interface GRAM read table ........................................................................ 33
Table 4.9: 9-bit parallel interface GRAM read table .......................................................................... 33
Table 4.10: 18-bit parallel interface GRAM read table ...................................................................... 33
Table 4.11: 24-bit parallel interface GRAM read table ...................................................................... 33
Table 4.12: DBI TYPE-C interface GRAM write table ....................................................................... 37
Table 4.13: 16-/18- DPI color mapping ............................................................................................. 42
Table 4.14: 24-DPI color mapping..................................................................................................... 42
Table 4.15: Data types for processor-sourced packets..................................................................... 50
Table 4.16: Shows the error report bit definitions.............................................................................. 57
Table 4.17: Complete set of peripheral-to-processor data types ...................................................... 57
Table 5.1: Addresses counter range.................................................................................................. 59
Table 5.2: MY.MX.MV Setting of GRAM address mapping .............................................................. 60
Table 5.3: Address direction settings ................................................................................................ 61
Table 5.4: Memory map of full display............................................................................................... 63
Table 5.5: Memory map of partial display ......................................................................................... 65
Table 5.6: AC characteristics of tearing effect signal ........................................................................ 72
Table 5.7 Adoptability of capacitor..................................................................................................... 81
Table 5.8: Characteristics of output pins ........................................................................................... 93
Table 5.9: Characteristics of input pins ............................................................................................. 93
Table 8.1: Absolute maximum ratings ............................................................................................. 237
Table 8.2: DBI Type B interface characteristics .............................................................................. 239
Table 8.3: DBI Type C interface characteristics .............................................................................. 240
Table 8.4: DPI interface characteristics-1 ....................................................................................... 241
Table 8.5: DPI interface characteristics-2 ....................................................................................... 242
Table 8.6: Reset input timing........................................................................................................... 243
Table 8.7: LP transmitter DC specifications .................................................................................... 247
Table 8.8: LP transmitter AC specifications .................................................................................... 247
Table 8.9: HS receiver DC specifications ........................................................................................ 248
Table 8.10: HS receiver AC specifications ...................................................................................... 248
Table 8.11: LP receiver DC specifications....................................................................................... 249
Table 8.12: LP receiver AC specifications....................................................................................... 249
Table 8.13: Contention detector DC specifications ......................................................................... 250
Table 8.14: Reverse HS data transmission timing parameters....................................................... 251
Table 8.15: Data to clock timing specifications ............................................................................... 253
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.8-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver
Temporary Version 00
1. General Description
April, 2012
This document describes Himax’s HX8357-D00/D01 supports HVGA resolution
driving controller. The HX8357-D00/D01 is designed to provide a single-chip solution
that combines a source driver, power supply circuit to drive a TFT-LCD panel with
320RGBx480 dots at maximum.
The HX8357-D00/D01 can be operated in low-voltage condition for the interface and
integrated internal boosters that produce the liquid crystal voltage, breeder resistance
and the voltage follower circuit for liquid crystal driver. In addition, The
HX8357-D00/D01 also supports various functions to reduce the power consumption
of a TFT-LCD panel via software control.
The HX8357-D00/D01 supports several interface modes, including MPU MIPI DBI
Type B interface mode and MIPI DPI/DBI Type C interface mode. The HX8357-D01
also supports MIPI DSI (Display Serial Interface) interface mode. The interface mode
is selected by the external hardware pins IM2~0.
The HX8357-D00/D01 is suitable for any small portable battery-driven and long-term
driving products, such as small PDAs, digital cellular phones and bi-directional
pagers.
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.9-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
2. Features
2.1Display
Resolution:
320(H) x RGB(H) x 480(V)
Temporary DATA SHEET V00
Display Color modes
Normal Display Mode On
1. DBI Interface
a. 65k colors (R(5),G(6),B(5))
b. 262k colors (R(6),G(6),B(6))
c. Virtual 24 bits colors (R(8),G(8),B(8))
2. DPI Interface
a. 65k colors (R(5),G(6),B(5))
b. 262k colors (R(6),G(6),B(6))
c. 16M colors (R(8),G(8),B(8))
3. MIPI Interface (For HX8357-D01 only)
a. 65k colors (R(5),G(6),B(5))
b. 262k colors (R(6),G(6),B(6))
c. Virtual 24 bits colors (R(8),G(8),B(8))
Idle Mode On
8 (R(1),G(1),B(1)) colors
2.2Display module
Frame Memory area 320 (H) x 480 (V) x 18 bits
On module DC/DC converter
VSP = 5.2 V for two time pump (Power supply for driver circuit range)
VSP = 6.2 V for three time pump (Power supply for driver circuit range)
VSN = -5.2 V for two time pump (Power supply for driver circuit range)
VSN = -6.2 V for three time pump (Power supply for driver circuit range)
VSPR =3.3V to 5.8V (Positive Source output voltage range)
VSNR= -3.3V to -5.8V (Negative Source output voltage range)
VGH = +10.0 to +15.3V (Positive Gate output voltage range)
VGL = -7.5 to -12.8V (Negative Gate output voltage range)
VCOM=-2.5V to 0V
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April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
2.3Display control interface
Temporary DATA SHEET V00
MIPI-DBI 8-/9-/16-/18-/24-bit MPU parallel interface.
MIPI-DBI Serial data transfer interface.
MIPI-DPI 8-/16-/18-/24-data lines parallel video (RGB) interface.
MIPI-DSI interface.(for Display Serial Interface Version 1.01 and D-PHY Version
1.00)
2.4Input power
Logic power supply (IOVCC): 1.65V ~ 3.3V
Analog power supply (VCI): 2.5V ~ 3.3V
2.5Miscellaneous
Low power consumption, suitable for battery operated systems
Image sticking eliminated function
CMOS compatible inputs
One chip solution for COG assembly
Support 24-bits Input Image function
Support 1-dot/2-dot/4-dot/column inversion/Zig-Zag inversion
Support Area scrolling
Support Partial display mode
Support Deep standby mode
Support normal black/normal white LCD
Support wide view angle display
On-chip OTP (One-time-programming) and MTP(four-time-programming for ID
and VCOM register)
Built-in internal OTP power
Support Content Adaptive Brightness Control(CABC) function
Support Color enhancement function
Support Digital 3-Gamma function
Operating temperature range : -40~ 85
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April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
3. Block Diagram
3.1Block diagram
Temporary DATA SHEET V00
Himax Confidential
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April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
3.2Pin description
Temporary DATA SHEET V00
Signals
IM2,IM1,IM0
Interface Logic Pin
I/O
Pin Connected
Number with
System interface select.
IM2 IM1
I
3
VSSD/
IOVCC
00
00
01
01
10
10
11
11
Description
IM0 Interface
0 DBI TYPE-B 18-bit/24-bit
1 DBI TYPE-B 9-bit
0 DBI TYPE-B 16-bit
1 DBI TYPE-B 8-bit
0 Not use
1 DBI TYPE-C Option 1
0 MIPI DSI (For HX8357-D01 only)
1 DBI TYPE-C Option 3
CSX
WRX_SCL
RDX
DCX
VSYNC
HSYNC
DE
PCLK
RESX
DIN_SDA
DOUT
DB17~0
DB18
TS0_DB19
TS1_DB20
TS2_DB21
TS3_DB22
TS4_DB23
If not used, please fix this pin to IOVCC or VSSD level.
Chip select signal.
I1
MPU
Low: chip can be accessed;
High: chip cannot be accessed.
Fix it to IOVCC when not used.
DBI Type-B mode: Serves as a write signal and write data at the low level.
I1
MPU DBI Type-C mode: it servers as SCL (Serial Clock)
Fix it to IOVCC or VSSD level when not used.
I1
MPU
DBI Type-B: Serves as a read signal and read data at the low level.
If not used, please fix this pin at IOVCC or GND level
I1
MPU
DBI Type-B, Type-C Option 3: Data / Command Selection pin
If not used, please fix this pin at IOVCC or GND level.
I1
MPU
Vertical synchronizing signal in DPI interface.
Let to open or connected to VSSD.
I1
MPU
Horizontal synchronizing signal in DPI interface.
Let to open or connected to VSSD.
I1
MPU
A data ENABLE signal in DPI I/F mode.
Let to open or connected to VSSD.
I1
MPU
Data enable signal in DPI interface.
Let to open or connected to VSSD.
I
1
MPU or Reset pin. Setting either pin low initializes the LSI. Must be reset
reset circuit after power is supplied.
I/O 1
Serial data input pin and output pin in serial bus system interface.
MCU The data is inputted on the rising edge of the SCL signal.
If not used, please let it open
Serial data output.
O1
MPU
If SDO_EN=0, DOUT is not use.
If SDO_EN=1, DOUT is serial data output.
Let it to open in MPU interface mode.
I/O 24
MPU
24-bit bi-directional data bus.
The unused pins let to open or connected to VSSD.
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-P.13-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
Signals
S1~S961
G1~G480
VCOM
TE
CABC_PWM1
CABC_PWM2
CABC_ON
Output Part
I/O
Pin
Number
Connected
with
Description
O 961
LCD
Output voltages applied to the liquid crystal.
O 480
LCD
Gate driver output pins. These pins output VGH, VGL.(If not used,
should be open).
O
13
TFT common The power supply of common voltage in TFT driving. Connect this pin
electrode to the common electrode in TFT panel.
O1
MPU
Tearing effect output.
If not used, please open this pin.
O
1
Backlight
Circuit/MPU
CABC backlight control PWM signal output.
O1
Backlight
Circuit
CABC backlight control PWM signal output.
O1
Backlight LED Driver Enable Signal.
Circuit If not used, please open this pin.
Signals
C11A,C11B
C13A, C13B
C12A,C12B
C14A,C14B
C22A,C22B
Input/Output Part
I/O
Pin
Number
Connected
with
Description
I/O
11,11
10,10
Step-up Connect to the step-up capacitors for step up circuit 1
Capacitor operation (VSP).
I/O
6,6
13,14
Step-up Connect to the step-up capacitors for step up circuit 3
Capacitor operation (VSN).
I/O 12,13
Step-up Connect to the step-up capacitors for step up circuit 1
Capacitor operation (VGH/VGL).
Signals
IOVCC
VCI
VSSD
VSSA
VDDD
NVDDDOUT
VSPROUT
VSNROUT
VSP
VSN
VGH
VGL
VCOMDC
Power Part
I/O
Pin
Number
Connected
with
Description
P 7 Power Supply Digital IO Pad power supply.
P 22 Power Supply Analog power supply.
P 13
Ground Digital ground.
P8
Ground Analog ground.
O
11
Stabilizing
capacitor
For internal logic voltage. Connect to a stabilizing capacitor.
O 10
Open For internal logic voltage
O4
Open Internal generated stable power for source driver unit.
O7
Open Internal generated stable power for source driver unit.
O
9
Stabilizing An output from the step-up circuit1.
capacitor Connect a stabilizing capacitor between VSSA and VSP.
O
11
Stabilizing An output from the step-up circuit3.
capacitor Connect a stabilizing capacitor between VSSA and VSN.
O
8
Stabilizing A positive power output from the step-up circuit 2 for the gate
capacitor line drive circuit.
A negative power output from the step-up circuit 2 for the gate
O
10
Schottkey
barrier diode
line drive circuit.
Connect a schottkey barrier diode between VSSA and VGL.
O3
Open An output of VCOM level.
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-P.14-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
Signals
HSI_DP,
HSI_DN
HSI_CP,
HSI_CN
HSI_VSS
HSI_LDO
High speed interface parts
I/O
Pin
Number
Connected
with
Description
I/O 2/2
DSI Host
High speed interface data differential signal input/output pins.
If not used, please open or connect it to VSSA
I 2/2
DSI Host
High speed interface CLOCK differential signal input pins.
If not used, please open or connect it to VSSA
P4
Ground
High speed interface analogy ground. HSI_VSS=0V. When using the
COG method, connect to VSSA on the FPC to prevent noise.
High speed interface regulator output pin.
O3
Capacitor Connect to a stabilizing capacitor between HSI_VSS and HSI_LDO
If not used, please open these pins.
Signals
TEST1
TEST2
TEST3
OSC
TESTDP
VTEST
NVTEST
DUMMY1~30
DUMMY31~69
DUMMY_VCL
Test pin and others
I/O
Pin
Number
Connected
with
Description
I1
Open
Test pin input (Internal pull low).
If not used, please open or connect it to VSSA
I1
Open
Test pin input (Internal pull low).
If not used, please open or connect it to VSSA
I1
Open
Test pin input (Internal pull low).
If not used, please open or connect it to VSSA
I1
Open A test pin. Please let it open
O1
Open A test pin. Please let it open
O1
Open A test pin. Please let it open
O1
Open Gamma voltage of Panel test pin output. Must be left open.
Dummy pads. Please let it open
- 69
Open Dummy1 can be used as COG bonding resistance
measurement
-9
Open Dummy pads. Please let it open
Himax Confidential
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-P.15-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
3.3Pin assignment
TBD
Temporary DATA SHEET V00
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.16-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
4. Interface
Temporary DATA SHEET V00
The HX8357-D supports MIPI interfaces: DBI (Display Bus Interface), DPI (Display Pixel
Interface), DSI (Display Serial Interface). Where DBI supports (24-/18-/16-/9-/8-bit interface)
Parallel Interface (Type B) and Serial interface (Type C Option 1/ Option 3). The interface
mode can be selected by IM2-0 pins setting as show in Table 4.1.
IM2 IM1 IM0
Interface
WRX_SCL
Data Bus use
Command/
Parament
GRAM
0 0 0 DBI TYPE-B 18-bit (DB_EN=’0’) WRX
DB7-DB0
DB17-DB0: 18-bits Data
0 0 0 DBI TYPE-B 24-bit(DB_EN=’1’) WRX
DB7-DB0
DB23-DB0: 24-bits Data
0 0 1 DBI TYPE-B 9-bit
WRX
DB7-DB0
DB8-DB0: 9-bits Data
0 1 0 DBI TYPE-B 16-bit
WRX
DB7-DB0
DB15-DB0: 16-bits Data
0 1 1 DBI TYPE-B 8-bit
WRX
DB7-DB0
DB7-DB0: 8-bit Data
1 0 0 Not use
--
1 0 1 DBI TYPE-C Option 1
SCL
SDA
1 1 0 MIPI DSI
(For HX8357-D01 only)
-
HSI_CP/N , HSI_D0P/N
1 1 1 DBI TYPE-C Option 3
SCL
SDA
Table 4.1: Interface selection
The HX8357-D includes an index register (IR), which is stored the index data of internal
control register and GRAM. When DCX=”L”, the command via DBI interface write into register.
When DCX=”H”, GRAM data via R2Ch register can be written through data bus. When the
data is written into the GRAM from the MPU, it is first written into the write-data latch and then
automatically written into the GRAM by internal operation. Data is read through the read-data
latch when reading from the GRAM.
When data is read from the GRAM to the MPU, it is first read from GRAM to the read-data
latch and then data is read to MPU through the read-data latch in next read operation.
Therefore, the read data in data bus in first read operation is invalid, and the read data is valid
from second read in data bus.
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-P.17-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
4.1MIPI DBI-B interface
Temporary DATA SHEET V00
The selection of DBI interface IM2~IM0 pin to select DBI interface mode. The parallel
interface timing diagram is described in Figure 4.1 and Figure 4.2.
Figure 4.1: DBI-B system interface protocol, write to register or GRAM
Figure 4.2: DBI-B system interface protocol, read from register or GRAM
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.18-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
DBI TYPE-B 8-bit Parallel Bus System Interface
Temporary DATA SHEET V00
The DBI-B system 8-bit bus parallel data transfer can be used by setting “IM2-0” pins
to “011”. The Figure4.3 is the example of interface with 8-bit DBI-B microcomputer
system interface.
Figure 4.3: Example of DBI-B System 8-bit bus Interface
8-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colors, 3AH=”05h”
There is 1-pixel (3 sub-pixels) per 2-bytes.
RESX 1‘ ’
CSX
DCX
WRX
RDX 1‘ ’
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
0
0
Pixel n
Pixel n+1
16-bits
16- bits
16-to-18 bit Conversion
Frame
Memory
18- bits
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Figure 4.4: Write data for RGB 5-6-5 (65k colors) bits input in 8-bit parallel interface
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.19-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
8-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 3AH=”06h”
There is 1-pixel (3 sub-pixels) per 3-bytes.
Figure 4.5: Write data for RGB 6-6-6-bits(262k colors) input in 8-bit parallel interface
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.20-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
8-bits data bus for 24-bits/pixel (RGB 8-8-8-bits input), 16M-colors, 3AH=”07h”
There is 1-pixel (3 sub-pixels) per 3-bytes.
NRESET 1
NCS
DNC
NWR
NRD 1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
0
0
R1, Bit 7
R1, Bit 6
R1, Bit 5
R1, Bit 4
R1, Bit 3
R1, Bit 2
R1, Bit 1
R1, Bit 0
Pixel n
G1, Bit 7
G1, Bit 6
G1, Bit 5
G1, Bit 4
G1, Bit 3
G1, Bit 2
G1, Bit 1
G1, Bit 0
B1, Bit 7
B1, Bit 6
B1, Bit 5
B1, Bit 4
B1, Bit 3
B0, Bit 2
B0, Bit 1
B0, Bit 0
R2, Bit 7
R2, Bit 6
R2, Bit 5
R2, Bit 4
R2, Bit 3
R2, Bit 2
R2, Bit 1
R2, Bit 0
Pixel n+1
24-to-18 conversion
Frame
Memory
18- bits
18- bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Figure 4.6: Write data for RGB 8-8-8-bits(16M colors) input in 8-bit parallel interface
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.21-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
DBI TYPE-B 9-bit Parallel Bus System Interface
Temporary DATA SHEET V00
The DBI-B system 9-bit bus parallel data transfer can be used by setting “IM2-0” pins
to “001”. The Figure4.7 is the example of interface with 9-bit DBI-B microcomputer
system interface.
Figure 4.7: Example of DBI-B system 9-bit bus interface
9-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colors, 3AH=”05h”
There is 1-pixel (3 sub-pixels) per 2-bytes.
RESX 1‘ ’
CSX
DCX
WRX
RDX 1‘ ’
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
x
0
0
1
0
1
1
0
0
Pixel n
Pixel n+1
16-bits
16- bits
16-to-18 bit Conversion
Frame
Memory
18- bits
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Figure 4.8: Write data for RGB 5-6-5 (65k colors) bits input in 9-bit parallel interface
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.22-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
9-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 3AH=”06h”
There is 1-pixel (3 sub-pixels) per 2-bytes
RESX 1‘ ’
CSX
DCX
WRX
RDX 1‘ ’
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Pixel n
Pixel n+1
Frame
Memory
18-bits
18- bits
R1 G1 B1 R2 G2 B2 R3G3 B3
Figure 4.9: Write data for RGB 6-6-6 (262k colors) bits input in 9-bit parallel interface
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.23-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
DBI TYPE-B 16-bit Parallel Bus System Interface
Temporary DATA SHEET V00
The DBI-B system 16-bit bus parallel data transfer can be used by setting “IM2-0”pins to “010”.
The Figure4.10 is the example of interface with 16-bit DBI-B microcomputer system interface.
Figure 4.10: Example of DBI-B System 16-bit bus interface
Himax Confidential
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April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
16-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colors, 3AH=”05h”
There is 1-pixel (3 sub-pixels) per 1-byte
Figure 4.11: Write data for RGB 5-6-5 (65k colors) bits input in 16-bit parallel interface
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.25-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
16-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 3AH=”06h”
There are 2-pixels (6 sub-pixels) per 3-bytes
RESX 1‘ ’
CSX
DCX
WRX
RDX 1‘ ’
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
-
-
-
-
-
-
-
-
0
0
1
0
1
1
0
0
Frame
Memory
Pixel n
18-bits
Pixel n+1
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Figure 4.12: Write data for RGB 6-6-6 (262k colors) bits input in 16-bit parallel interface
Himax Confidential
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in whole or in part without prior written permission of Himax.
-P.26-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
16-bits data bus for 18-bits/pixel (RGB 8-8-8-bits input), 16M-colors, 3AH=”07h”
There are 2-pixels (6 sub-pixels) per 3-bytes
NRESET 1‘ ’
NCS
DNC
NWR
NRD 1‘ ’
DB15
-
DB14
-
DB13
-
DB12
-
DB11
-
DB10
-
DB9
-
DB8
-
DB7
0
DB6
0
DB5
1
DB4
0
DB3
1
DB2
1
DB1
0
DB0
0
Pixel n
Pixel n+1
Frame
Memory
24-to-18 bit Conversion
18- bits
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Figure 4.13: Write data for RGB 8-8-8 (16M colors) bits input in 16-bit parallel interface
Himax Confidential
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April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
DBI TYPE-B 18-bit Parallel Bus System Interface
Temporary DATA SHEET V00
The DBI-B system 18-bit bus parallel data transfer can be used by setting “IM2-0”pins
to “000” and register setting DB_EN=’0’. The Figure 4.14 is the example of interface
with 18-bit DBI-B microcomputer system interface.
Figure 4.14: Example of DBI-B system 18-bit parallel bus interface
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.28-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
18-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 3AH=”06h”
There is 1-pixel (6 sub-pixels) per 1-byte
Figure 4.15 Write data for RGB 6-6-6 (262k colors) bits input in 18-bit parallel interface
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.29-
April, 2012


HX8357-D00 (Himax)
TFT Mobile Single Chip Driver

No Preview Available !

Click to Download PDF File for PC

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
DBI TYPE-B 24-bit Parallel Bus System Interface
Temporary DATA SHEET V00
The DBI-B system 24-bit bus parallel data transfer can be used by setting “IM2-0”pins
to “000” and register setting DB_EN=’1’. The Figure 4.16 is the example of interface
with 24-bit DBI-B microcomputer system interface.
Figure 4.16: Example of DBI-B system 24-bit parallel bus interface
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.30-
April, 2012




HX8357-D00.pdf
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