MC54HC374A (Motorola)
Octal 3-State Non-Inverting D Flip-Flop

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State
Non-Inverting D Flip-Flop
High–Performance Silicon–Gate CMOS
The MC54/74HC374A is identical in pinout to the LS374. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising edge
of the clock. The Output Enable input does not affect the states of the
flip–flops, but when Output Enable is high, the outputs are forced to the
high–impedance state; thus, data may be stored even when the outputs are
not enabled.
The HC374A is identical in function to the HC574A which has the input
pins on the opposite side of the package from the output. This device is
similar in function to the HC534A which has inverting outputs.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
CLOCK 11
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
NONINVERTING
OUTPUTS
OUTPUT ENABLE 1
PIN 20 = VCC
PIN 10 = GND
FUNCTION TABLE
Output
Enable
L
L
L
H
Inputs
Clock
L,H,
X
Output
DQ
HH
LL
X No Change
XZ
X = don’t care
Z = high impedance
8/96
© Motorola, Inc. 1996
3–1
MC54/74HC374A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
20
1
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
ORDERING INFORMATION
MC54HCXXXAJ
Ceramic
MC74HCXXXAN
Plastic
MC74HCXXXADW SOIC
MC74HCXXXASD SSOP
MC74HCXXXADT
TSSOP
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
1
2
20 VCC
19 Q7
D0 3
18 D7
D1 4
17 D6
Q1 5
16 Q6
Q2 6
15 Q5
D2 7
14 D5
D3 8
13 D4
Q3 9
GND 10
12 Q4
11 CLOCK
REV 7


MC54HC374A (Motorola)
Octal 3-State Non-Inverting D Flip-Flop

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MC54/74HC374A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
± 20
V
V
mA
DC Output Current, per Pin
± 35 mA
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
SSOP or TSSOP Package†
± 75
750
500
450
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Plastic DIP, SOIC, SSOP or TSSOP Package)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Ceramic DIP)
– 65 to + 150
260
300
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC DC Supply Voltage (Referenced to GND)
2.0 6.0 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA Operating Temperature, All Package Types
– 55 + 125 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Input Rise and Fall Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 1)
VCC = 2.0 V 0 1000 ns
VCC = 4.5 V 0
500
VCC = 6.0 V 0
400
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH
Parameter
Minimum High–Level Input
Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL MaximumLow–LevelInput
Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
Minimum High–Level Output
Voltage
Test Conditions
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout|
v|Iout|
v|Iout|
2.4 mA
6.0 mA
7.8 mA
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
1.50 1.50 1.50
2.10 2.10 2.10
3.15 3.15 3.15
4.20 4.20 4.20
0.50 0.50 0.50
0.90 0.90 0.90
1.35 1.35 1.35
1.80 1.80 1.80
1.90 1.90 1.90
4.40 4.40 4.40
5.90 5.90 5.90
2.48 2.34 2.20
2.98 3.84 3.70
5.48 5.34 5.20
Unit
V
V
V
V
MOTOROLA
3–2 High–Speed CMOS Logic Data
DL129 — Rev 6


MC54HC374A (Motorola)
Octal 3-State Non-Inverting D Flip-Flop

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MC54/74HC374A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIOZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
Parameter
Test Conditions
Maximum Low–Level Output
Voltage
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout|
v|Iout|
v|Iout|
2.4 mA
6.0 mA
7.8 mA
Maximum Input Leakage Current Vin = VCC or GND
Maximum Three–State
Leakage Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
VCC
V
2.0
4.5
6.0
3.0
4.5
6.0
6.0
6.0
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
0.10 0.10 0.10
0.10 0.10 0.10
0.10 0.10 0.10
0.26 0.33 0.40
0.26 0.33 0.40
0.26 0.33 0.40
± 0.1
± 1.0
± 1.0
± 0.5
± 5.0
± 10
Unit
V
V
µA
µA
4 40 160 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
VCC
V
v v– 55 to
25_C
85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfmax
Maximum Clock Frequency (50% Duty Cycle)
2.0 6 5 4 MHz
3.0 15
10
8
4.5 30 24 20
6.0 35 28 24
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Input Clock to Q
(Figures 1 and 5)
2.0 125 155 190 ns
3.0 80
110 130
4.5 25 31 38
6.0 21 26 32
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0 150 190 225 ns
3.0 100 125 150
4.5 30 38 45
6.0 26 33 38
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0 150 190 225 ns
3.0 100 125 150
4.5 30 38 45
6.0 26 33 38
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0 75
3.0 27
4.5 15
6.0 13
95 110 ns
32 36
19 22
16 19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin MaximumInputCapacitance
10 10 10 pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCout
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
15 15 15 pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
34 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA


MC54HC374A (Motorola)
Octal 3-State Non-Inverting D Flip-Flop

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MC54/74HC374A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTSIMyÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎttrmttsI,whNutbfÎÎÎÎÎÎÎÎGoÎÎÎÎÎÎÎÎÎlRÎÎÎÎEÎÎÎÎÎÎÎÎÎÎÎÎÎMMMMQiiiannnxUiiiÎÎÎÎmmmÎÎÎÎÎÎÎÎÎÎÎÎiÎmIuuuRummmEmÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMPSHInueoEpltlÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎsudNueptTTWRTiSmÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎiiimsde(etCe,haC,ÎÎÎÎLÎÎÎÎÎÎÎÎÎÎÎÎPÎ,nDlCao=darlcoa5tFÎÎÎÎkÎÎÎÎÎÎÎÎaÎÎÎÎÎcm0atktlopoel TFtDÎÎÎÎCÎÎÎÎÎÎÎÎÎÎÎÎÎe,imarlIonteacpÎÎÎÎÎÎÎÎÎÎÎÎsÎÎÎÎÎkut trÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ= tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ= 6.0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎns)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎF3311igÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVV2346234623462346oC................l0050005000500050CtÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎs ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎM5555541621195....i00003200000n5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎto 21ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎM854Î50000_a0000Cx0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaMÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ555565117211Îr...iv50315753a0000nnÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt8Îe5e_1Md854C0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ000ÎaL0000xi0mÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎit M555576119311ÎÎÎÎvÎÎÎÎÎÎÎÎÎÎÎÎ....iÎ505302850000n12ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ51M_8540C000aÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0Î000x0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎUnnnnnssssÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎiÎt
SWITCHING WAVEFORMS
CLOCK
Q
tr
90%
50%
tf
10%
tW
1/fmax
tPLH
90%
tPHL
50%
10%
tTLH tTHL
Figure 1.
VCC
GND
OUTPUT
ENABLE
Q
Q
50%
tPZL tPLZ
50%
tPZH tPHZ
50%
Figure 2.
VCC
GND
HIGH
IMPEDANCE
10% VOL
90% VOH
HIGH
IMPEDANCE
DATA
CLOCK
VALID
50%
tsu th
50%
Figure 3.
VCC
GND
VCC
GND
MOTOROLA
3–4 High–Speed CMOS Logic Data
DL129 — Rev 6


MC54HC374A (Motorola)
Octal 3-State Non-Inverting D Flip-Flop

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DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
MC54/74HC374A
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 k
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 4.
* Includes all probe and jig capacitance
Figure 5.
EXPANDED LOGIC DIAGRAM
D0
3
D
Q
D1
4
D
Q
D2
7
D
Q
D3
8
D
Q
D4
13
D
Q
D5
14
D
Q
D6
17
D
Q
D7
18
D
Q
11
Clock
Output 1
Enable
CCCCCCCC
2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA


MC54HC374A (Motorola)
Octal 3-State Non-Inverting D Flip-Flop

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MC54/74HC374A
20
1
A
F
H
D
SEATING
PLANE
–A–
20
1
–T–
SEATING
PLANE
E
GF
11
10
B
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
CL
N
K
G
J
M
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C 3.81 5.08 0.150 0.200
D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC
0.100 BSC
H 0.51 1.27 0.020 0.050
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 7.62 BSC
0.300 BSC
M 0_ 15_ 0_ 15_
N 0.25 1.02 0.010 0.040
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
11 ISSUE E
B
10
CL
K
N
D 20 PL
0.25 (0.010) M T A M
M
J 20 PL
0.25 (0.010) M
TBM
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 1.010 1.070 25.66 27.17
B 0.240 0.260 6.10 6.60
C 0.150 0.180 3.81 4.57
D 0.015 0.022 0.39 0.55
E 0.050 BSC
1.27 BSC
F 0.050 0.070 1.27 1.77
G 0.100 BSC
2.54 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.140 2.80 3.55
L 0.300 BSC
7.62 BSC
M 0_ 15_ 0_ 15_
N 0.020 0.040 0.51 1.01
DW SUFFIX
–A–
20 11
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–B– 10X P
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
0.010 (0.25) M B M
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
1 10
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
20X D
0.010 (0.25) M T A S B S
J
F
18X G
C
–T–
SEATING
PLANE
K
M
R X 45_
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC
0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
MOTOROLA
3–6 High–Speed CMOS Logic Data
DL129 — Rev 6


MC54HC374A (Motorola)
Octal 3-State Non-Inverting D Flip-Flop

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MC54/74HC374A
OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C–03
ISSUE B
20X K REF
0.12 (0.005) M T U S V S
0.25 (0.010)
N
L/2 20
L
PIN 1
IDENT
1
11
10
A
–V–
0.20 (0.008) M T U S
B
–U–
M
N
F
DETAIL E
J ÇÇÉÉÇÇÉÉK ÇÇÉÉ J1
K1
SECTION N–N
0.076 (0.003)
–T– SEATING
PLANE
C
D
G
–W–
DETAIL E
H
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR INTRUSION SHALL NOT
REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 7.07 7.33 0.278 0.288
B 5.20 5.38 0.205 0.212
C 1.73 1.99 0.068 0.078
D 0.05 0.21 0.002 0.008
F 0.63 0.95 0.024 0.037
G 0.65 BSC
0.026 BSC
H 0.59 0.75 0.023 0.030
J 0.09 0.20 0.003 0.008
J1 0.09 0.16 0.003 0.006
K 0.25 0.38 0.010 0.015
K1 0.25 0.33 0.010 0.013
L 7.65 7.90 0.301 0.311
M 0_ 8_ 0_ 8_
0.15 (0.006) T U S
2X L/2 20
L
PIN 1
IDENT
1
0.15 (0.006) T U S
C
D
0.100 (0.004)
–T– SEATING
PLANE
20X K REF
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
0.10 (0.004) M T U S V S
11
B
–U–
J J1ÍÍÍÍÍÍKKÍÍÍ1 ÍÍÍ
SECTION N–N
10
N 0.25 (0.010)
AM
–V–
N
F
DETAIL E
GH
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
–W–
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 6.40 6.60 0.252 0.260
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
High–Speed CMOS Logic Data
DL129 — Rev 6
3–7
MOTOROLA


MC54HC374A (Motorola)
Octal 3-State Non-Inverting D Flip-Flop

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MC54/74HC374A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Affirmative Action Employer.
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MOTOROLA
*MC74HC374A/D*MC74HC374A/D
3–8 High–Speed CMOS Logic Data
DL129 — Rev 6




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