M30626MJP-XXXGP (Renesas Technology)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0001-0241
Rev.2.41
Jan 10, 2006
1. Overview
The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin
plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level
of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing
capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-
speed arithmetic/logic operations.
1.1 Applications
Audio, cameras, television, home appliance, office/communications/portable/industrial equipment, automobile,
etc.
Specifications written in this manual are believed to be accurate,
but are not guaranteed to be entirely free of error. Specifications in
this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
Rev.2.41 Jan 10, 2006 Page 1 of 96
REJ03B0001-0241


M30626MJP-XXXGP (Renesas Technology)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
1.2 Performance Outline
Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version).
Table 1.1 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version)
CPU
Peripheral
Function
Item
Number of Basic Instructions
Minimum Instruction Execution
Time
Operating Mode
Address Space
Memory Capacity
Port
Multifunction Timer
Serial Interface
A/D Converter
D/A Converter
DMAC
CRC Calculation Circuit
Watchdog Timer
Interrupt
Clock Generation Circuit
Electric
Characteristics
Oscillation Stop Detection
Function
Voltage Detection Circuit
Supply Voltage
Power Consumption
Flash memory Program/Erase Supply Voltage
version
Program and Erase Endurance
Operating Ambient Temperature
Package
Performance
M16C/62P
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip, memory expansion and microprocessor mode
1 Mbyte (Available to 4 Mbytes by memory space expansion
function)
See Table 1.4 to 1.5 Product List
Input/Output : 113 pins, Input : 1 pin
Timer A : 16 bits x 5 channels,
Timer B : 16 bits x 6 channels,
Three phase motor control circuit
3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
10-bit A/D converter: 1 circuit, 26 channels
8 bits x 2 channels
2 channels
CCITT-CRC
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Stop detection of main clock oscillation, re-oscillation detection
function
Available (option(4))
VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7µA (VCC1=VCC2=3V, stop mode)
3.3±0.3 V or 5.0±0.5 V
100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
-20 to 85°C,
-40 to 85°C (3)
128-pin plastic mold LQFP
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Rev.2.41 Jan 10, 2006 Page 2 of 96
REJ03B0001-0241


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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.2 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version)
Item Performance
M16C/62P
M16C/62PT(4)
CPU
Number of Basic Instructions 91 instructions
Minimum Instruction
Execution Time
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operating Mode
Single-chip, memory expansion
and microprocessor mode
Single-chip
Address Space
1 Mbyte (Available to 4 Mbytes by 1 Mbyte
memory space expansion function)
Memory Capacity
See Table 1.4 to 1.7 Product List
Peripheral
Function
Port
Multifunction Timer
Input/Output : 87 pins, Input : 1 pin
Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels,
Three phase motor control circuit
Serial Interface
3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
A/D Converter
10-bit A/D converter: 1 circuit, 26 channels
D/A Converter
8 bits x 2 channels
DMAC
2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer
15 bits x 1 channel (with prescaler)
Interrupt
Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Detection Function
Stop detection of main clock oscillation, re-oscillation detection function
Voltage Detection Circuit Available (option (5))
Absent
Electric
Supply Voltage
Characteristics
VCC1=3.0 to 5.5 V, VCC2=2.7V to
VCC1 (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to
VCC1 (f(BCLK=10MHz)
VCC1=VCC2=4.0 to 5.5V
(f(BCLK=24MHz)
Power Consumption
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz,
wait mode)
0.7µA (VCC1=VCC2=3V, stop mode)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
2.0µA (VCC1=VCC2=5V, f(XCIN)=32kHz,
wait mode)
0.8µA (VCC1=VCC2=5V, stop mode)
Flash memory
version
Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V
5.0±0.5 V
Program and Erase
Endurance
100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature
-20 to 85°C,
-40 to 85°C (3)
T version : -40 to 85°C
V version : -40 to 125°C
Package
100-pin plastic mold QFP, LQFP
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. Use the M16C/62PT on VCC1=VCC2
5. All options are on request basis.
Rev.2.41 Jan 10, 2006 Page 3 of 96
REJ03B0001-0241


M30626MJP-XXXGP (Renesas Technology)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.3 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version)
Item Performance
M16C/62P
M16C/62PT(4)
CPU
Number of Basic Instructions 91 instructions
Minimum Instruction
Execution Time
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operating Mode
Single-chip mode
Address Space
1 Mbyte
Memory Capacity
See Table 1.4 to 1.7 Product List
Peripheral
Function
Port
Multifunction Timer
Input/Output : 70 pins, Input : 1 pin
Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer),
Timer B : 16 bits x 6 channels (Timer B1 is internal timer)
Serial Interface
2 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
1 channel
Clock synchronous, I2C bus(1), IEBus(2)
2 channels
Clock synchronous (1 channel is only transmission)
A/D Converter
10-bit A/D converter: 1 circuit, 26 channels
D/A Converter
8 bits x 2 channels
DMAC
2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer
15 bits x 1 channel (with prescaler)
Interrupt
Internal: 29 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Detection Function
Stop detection of main clock oscillation, re-oscillation detection function
Voltage Detection Circuit Available (option (4))
Absent
Electric
Supply Voltage
Characteristics
VCC1=3.0 to 5.5 V, (f(BCLK=24MHz) VCC1=4.0 to 5.5V, (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, (f(BCLK=10MHz)
Power Consumption
14 mA (VCC1=5V, f(BCLK)=24MHz)
8 mA (VCC1=3V, f(BCLK)=10MHz)
1.8µA (VCC1=3V, f(XCIN)=32kHz,
wait mode)
14 mA (VCC1=5V, f(BCLK)=24MHz)
2.0µA (VCC1=5V, f(XCIN)=32kHz,
wait mode)
0.8µA (VCC1=5V, stop mode)
0.7µA (VCC1=3V, stop mode)
Flash memory
version
Program/Erase Supply Voltage 3.3 ± 0.3V or 5.0 ± 0.5V
5.0 ± 0.5V
Program and Erase
Endurance
100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature
-20 to 85°C,
-40 to 85°C (3)
T version : -40 to 85°C
V version : -40 to 125°C
Package
80-pin plastic mold QFP
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Rev.2.41 Jan 10, 2006 Page 4 of 96
REJ03B0001-0241


M30626MJP-XXXGP (Renesas Technology)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
1.3 Block Diagram
Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram,
Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram.
888888
8
Port P0
Port P1
Port P2 Port P3
<VCC2 ports>(4)
Port P4
Internal peripheral functions
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
A/D converter
(10 bits X 8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O
(8 bits X 3 channels)
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
Port P5
Port P6
<VCC1 ports>(4)
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Clock synchronous serial I/O
(8 bits X 2 channels)
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
M16C/60 series16-bit CPU core
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
Memory
ROM (1)
RAM (2)
Multiplier
<VCC1 ports>(4)
Port P11 Port P14
(3) (3)
<VCC2 ports>(4)
Port P12 Port P13
(3) (3)
82
88
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Figure 1.1
M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram
Rev.2.41 Jan 10, 2006 Page 5 of 96
REJ03B0001-0241


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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
8 8 8 4 88
Port P0
Port P2
Port P3
(4)
Port P4
Port P5 Port P6
Internal peripheral functions
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
A/D converter
(10 bits X 8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O (2 channels)
UART
(1 channel)
(3)
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Clock synchronous serial I/O
(8 bits X 2 channels)
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
M16C/60 series16-bit CPU core
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
Memory
ROM (1)
RAM (2)
Multiplier
1. Overview
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).
4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Figure 1.2
M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram
Rev.2.41 Jan 10, 2006 Page 6 of 96
REJ03B0001-0241


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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
1.4 Product List
Table 1.4 to 1.7 list the product list, Figure 1.3 shows the Type No., Memory Size, and Package, Table 1.8 lists the
Product Code of Flash Memory version and ROMless version for M16C/62P, and Table 1.9 lists the Product Code
of Flash Memory version for M16C/62PT. Figure 1.4 shows the Marking Diagram of Flash Memory version and
ROM-less version for M16C/62P (Top View), and Figure 1.5 shows the Marking Diagram of Flash Memory
version for M16C/62PT (Top View) at the time of ROM order.
Table 1.4 Product List (1) (M16C/62P)
Type No.
ROM Capacity
M30622M6P-XXXFP
48 Kbytes
M30622M6P-XXXGP
M30622M8P-XXXFP
64 Kbytes
M30622M8P-XXXGP
M30623M8P-XXXGP
M30622MAP-XXXFP
96 Kbytes
M30622MAP-XXXGP
M30623MAP-XXXGP
M30620MCP-XXXFP
128 Kbytes
M30620MCP-XXXGP
M30621MCP-XXXGP
M30622MEP-XXXFP
192 Kbytes
M30622MEP-XXXGP
M30623MEP-XXXGP
M30622MGP-XXXFP
256 Kbytes
M30622MGP-XXXGP
M30623MGP-XXXGP
M30624MGP-XXXFP
M30624MGP-XXXGP
M30625MGP-XXXGP
M30622MWP-XXXFP
320 Kbytes
M30622MWP-XXXGP
M30623MWP-XXXGP
M30624MWP-XXXFP
M30624MWP-XXXGP
M30625MWP-XXXGP
M30626MWP-XXXFP
M30626MWP-XXXGP
M30627MWP-XXXGP
RAM Capacity Package Type (1)
4 Kbytes
PRQP0100JB-A
PLQP0100KB-A
4 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
5 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
10 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
12 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
12 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
20 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
16 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
24 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
31 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
As of Dec. 2005
Remarks
Mask ROM version
(D): Under development
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
Rev.2.41 Jan 10, 2006 Page 7 of 96
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.5 Product List (2) (M16C/62P)
As of Dec. 2005
Type No.
M30622MHP-XXXFP
M30622MHP-XXXGP
M30623MHP-XXXGP
M30624MHP-XXXFP
M30624MHP-XXXGP
M30625MHP-XXXGP
M30626MHP-XXXFP
M30626MHP-XXXGP
M30627MHP-XXXGP
M30626MJP-XXXFP
M30626MJP-XXXGP
M30627MJP-XXXGP
M30622F8PFP
M30622F8PGP
M30623F8PGP
M30620FCPFP
M30620FCPGP
M30621FCPGP
M3062LFGPFP(3)
M3062LFGPGP(3)
M30625FGPGP
M30626FHPFP
M30626FHPGP
M30627FHPGP
M30626FJPFP
M30626FJPGP
M30627FJPGP
M30622SPFP
M30622SPGP
M30620SPFP
M30620SPGP
M30624SPFP
M30624SPGP
M30626SPFP
M30626SPGP
ROM Capacity
RAM
Capacity
384 Kbytes
16 Kbytes
24 Kbytes
31 Kbytes
(D) 512 Kbytes
(D)
(D)
64K+4 Kbytes
31 Kbytes
4 Kbytes
128K+4 Kbytes 10 Kbytes
(D) 256K+4 Kbytes 20 Kbytes
(D)
384K+4 Kbytes 31 Kbytes
512K+4 Kbytes 31 Kbytes
(D)
(D)
(D)
(D)
4 Kbytes
10 Kbytes
20 Kbytes
31 Kbytes
Package Type (1)
Remarks
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
Mask ROM version
Flash memory
version (2)
ROM-less version
(D): Under development
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
3. Please use M3062LFGPFP and M3062LFGPGP for your new system instead of M30624FGPFP
and M30624FGPGP. The M16C/62P Group (M16C/62P, M16C/62PT) hardware manual is still good
for M30624FGPFP and M30624FGPGP.
M30624FGPFP
M30624FGPGP
256K+4 Kbytes 20 Kbytes
PRQP0100JB-A Flash memory version
PLQP0100KB-A
Rev.2.41 Jan 10, 2006 Page 8 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.6 Product List (3) (T version (M16C/62PT))
As of Dec. 2005
Type No.
ROM Capacity
RAM
Capacity
Package Type (1)
Remarks
M3062CM6T-XXXFP (D) 48 Kbytes
M3062CM6T-XXXGP (D)
M3062EM6T-XXXGP (P)
4 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
Mask ROM T Version
version (High reliability
85°C version)
M3062CM8T-XXXFP (D) 64 Kbytes
4 Kbytes PRQP0100JB-A
M3062CM8T-XXXGP (D)
PLQP0100KB-A
M3062EM8T-XXXGP (P)
PRQP0080JA-A
M3062CMAT-XXXFP (D) 96 Kbytes
5 Kbytes PRQP0100JB-A
M3062CMAT-XXXGP (D)
PLQP0100KB-A
M3062EMAT-XXXGP (P)
PRQP0080JA-A
M3062AMCT-XXXFP (D) 128 Kbytes 10 Kbytes PRQP0100JB-A
M3062AMCT-XXXGP (D)
PLQP0100KB-A
M3062BMCT-XXXGP (P)
PRQP0080JA-A
M3062CF8TFP
M3062CF8TGP
M3062AFCTFP
(D) 64 K+4 Kbytes 4 Kbytes PRQP0100JB-A
PLQP0100KB-A
(D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A
Flash
memory
version (2)
M3062AFCTGP
(D)
PLQP0100KB-A
M3062BFCTGP
(P)
PRQP0080JA-A
M3062JFHTFP
(D) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A
M3062JFHTGP
(D)
PLQP0100KB-A
(D): Under development
(P): Under planning
NOTES:
1. The old package type numbers of each package type are as follows.
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
Rev.2.41 Jan 10, 2006 Page 9 of 96
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.7 Product List (4) (V version (M16C/62PT))
As of Dec. 2005
Type No.
ROM Capacity
RAM
Capacity
Package Type(1)
Remarks
M3062CM6V-XXXFP (P) 48 Kbytes
M3062CM6V-XXXGP (P)
M3062EM6V-XXXGP (P)
4 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
Mask ROM V Version
version (High reliability
125°C version)
M3062CM8V-XXXFP (P) 64 Kbytes
4 Kbytes PRQP0100JB-A
M3062CM8V-XXXGP (P)
PLQP0100KB-A
M3062EM8V-XXXGP (P)
PRQP0080JA-A
M3062CMAV-XXXFP (P) 96 Kbytes
5 Kbytes PRQP0100JB-A
M3062CMAV-XXXGP (P)
PLQP0100KB-A
M3062EMAV-XXXGP (P)
PRQP0080JA-A
M3062AMCV-XXXFP (D) 128 Kbytes 10 Kbytes PRQP0100JB-A
M3062AMCV-XXXGP (D)
PLQP0100KB-A
M3062BMCV-XXXGP (P)
PRQP0080JA-A
M3062AFCVFP
M3062AFCVGP
M3062BFCVGP
(D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A
(D) PLQP0100KB-A
(P) PRQP0080JA-A
Flash
memory
version (2)
M3062JFHVFP
(P) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A
M3062JFHVGP
(P)
PLQP0100KB-A
(D): Under development
(P): Under planning
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
Rev.2.41 Jan 10, 2006 Page 10 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Type No.
M3062 6 MH P - XXX FP
Package type:
FP : Package
GP : Package
PRQP0100JB-A (100P6S-A)
PRQP0080JA-A (80P6S-A),
PLQP0100KB-A (100P6Q-A),
PLQP0128KB-A (128P6Q-A),
ROM No.
Omitted for flash memory version and
ROMless version
Classification
P : M16C/62P
T : T version (M16C/62PT)
V : V version (M16C/62PT)
ROM capacity:
6: 48 Kbytes
8: 64 Kbytes
A: 96 Kbytes
C: 128 Kbytes
E: 192 Kbytes
G: 256 Kbytes
W: 320 Kbytes
H: 384 Kbytes
J: 512 Kbytes
Memory type:
M: Mask ROM version
F: Flash memory version
S: ROM-less version
Shows RAM capacity, pin count, etc
Numeric, Alphabet (L) : M16C/62P
Alphabet (L is excluded.) : M16C/62PT
M16C/62(P) Group
M16C Family
Figure 1.3 Type No., Memory Size, and Package
Rev.2.41 Jan 10, 2006 Page 11 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P
Product
Code
Flash memory
Version
ROM-less
version
D3
D5
D7
D9
U3
U5
U7
U9
D3
D5
U3
U5
Package
Lead-
included
Lead-free
Lead-
included
Lead-free
Internal ROM
(User ROM Area Without Block A,
Block 1)
Program
and Erase
Endurance
Temperature
Range
100 0°C to 60°C
1,000
100
1,000
−−
−−
Internal ROM
(Block A, Block 1)
Program
and Erase
Endurance
100
Temperature
Range
0°C to 60°C
10,000
100
-40°C to 85°C
-20°C to 85°C
0°C to 60°C
10,000
-40°C to 85°C
-20°C to 85°C
−−
Operating
Ambient
Temperature
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
M1 6 C
M3 0 6 2 6 F H P F P
B D5
XXXXXXX
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Chip version and product code
B : Shows chip version.
Henceforth, whenever it changes a version, it continues with B, C, and D.
D5 : Shows Product code. (See table 1.8 Product Code)
Date code seven digits
The product without marking of chip version of the flash memory version and the ROMless version
corresponds to the chip version “A”.
Figure 1.4
Marking Diagram of Flash Memory version and ROM-less version for M16C/62P (Top View)
Rev.2.41 Jan 10, 2006 Page 12 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.9
Flash
memory
Version
Product Code of Flash Memory version for M16C/62PT
Product
Code
Package
T Version
B
Lead-
V Version
included
T Version
B7
V Version
T Version
U Lead-free
V Version
T Version U7
V Version
Internal ROM
(User ROM Area
Without Block A, Block 1)
Program
and Erase
Endurance
Temperature
Range
100 0°C to 60°C
1,000
100
1,000
Internal ROM
(Block A, Block 1)
Program
and Erase
Endurance
Temperature
Range
Operating
Ambient
Temperature
100 0°C to 60°C -40°C to 85°C
-40°C to 125°C
10,000 -40°C to 85°C -40°C to 85°C
-40°C to 125°C -40°C to 125°C
100 0°C to 60°C -40°C to 85°C
-40°C to 125°C
10,000 -40°C to 85°C -40°C to 85°C
-40°C to 125°C -40°C to 125°C
M1 6 C
M3 0 6 2 J F HT F P
Y YY X X X X X XX
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Date code seven digits
Product code. (See table 1.9 Product Code)
“ ” : Product code “B”
“ P B F ” : Product code “U”
“ B 7 ” : Product code “B”
“ U 7 ” : Product code “U7”
Figure 1.5
NOTES:
1. : Blank
Marking Diagram of Flash Memory version for M16C/62PT (Top View)
Rev.2.41 Jan 10, 2006 Page 13 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
1.5 Pin Configuration
Figures 1.6 to 1.9 show the Pin Configuration (Top View).
PIN CONFIGURATION (top view)
1. Overview
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
103 64
104 <VCC2> (2)
105
63
62
106 61
107 60
108 59
109 58
110 57
111 56
112 55
113 54
114 53
115 M16C/62P Group (M16C/62P) 52
116 51
117 50
118 49
119 48
120 47
121 46
122 45
123 44
124 43
125 42
126 <VCC1> (2)
127
41
40
128 39
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
P12_5
P12_6
P12_7
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P13_0
P13_1
P13_2
P13_3
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P13_4
P13_5
P13_6
P13_7
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
VSS
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
Figure 1.6 Pin Configuration (Top View)
Package : PLQP0128KB-A (128P6Q-A)
Rev.2.41 Jan 10, 2006 Page 14 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.10 Pin Characteristics for 128-Pin Package (1)
Pin No. Control Pin
1 VREF
2 AVCC
Port
Interrupt Pin
Timer Pin
UART Pin
3 P9_7
4 P9_6
5 P9_5
6 P9_4
7 P9_3
8 P9_2
9 P9_1
10 P9_0
11 P14_1
12 P14_0
13 BYTE
14 CNVSS
15 XCIN
P8_7
16 XCOUT P8_6
17 RESET
18 XOUT
19 VSS
20 XIN
21 VCC1
22 P8_5 NMI
23 P8_4 INT2
24 P8_3 INT1
25 P8_2 INT0
26 P8_1
27 P8_0
28 P7_7
29 P7_6
30 P7_5
31 P7_4
32 P7_3
33 P7_2
34 P7_1
35 P7_0
36 P6_7
37 VCC1
38 P6_6
39 VSS
40 P6_5
41 P6_4
42 P6_3
43 P6_2
44 P6_1
45 P6_0
46 P13_7
47 P13_6
48 P13_5
49 P13_4
50 P5_7
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
SIN4
SOUT4
CLK4
SOUT3
SIN3
CLK3
ZP
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA0IN/TB5IN
TA0OUT
CTS2/RTS2
CLK2
RXD2/SCL2
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
CTS0/RTS0
Analog Pin Bus Control Pin
ADTRG
ANEX1
ANEX0
DA1
DA0
RDY/CLKOUT
Rev.2.41 Jan 10, 2006 Page 15 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.11 Pin Characteristics for 128-Pin Package (2)
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Control Pin Port
P5_6
P5_5
P5_4
P13_3
P13_2
P13_1
P13_0
P5_3
P5_2
P5_1
P5_0
P12_7
P12_6
P12_5
P4_7
P4_6
P4_5
VCC2
VSS
P4_4
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P12_4
P12_3
P12_2
P12_1
P12_0
P3_0
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
Interrupt Pin
Timer Pin
UART Pin
96 P1_7 INT5
97 P1_6 INT4
98 P1_5 INT3
99 P1_4
100 P1_3
1. Overview
Analog Pin
Bus Control Pin
ALE
HOLD
HLDA
BCLK
RD
WRH/BHE
WRL/WR
CS3
CS2
CS1
CS0
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
A8(/-/D7)
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
D15
D14
D13
D12
D11
Rev.2.41 Jan 10, 2006 Page 16 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.12 Pin Characteristics for 128-Pin Package (3)
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
Control Pin Port
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
Interrupt Pin
Timer Pin
UART Pin
120 P10_7 KI3
121 P10_6 KI2
122 P10_5 KI1
123
124
125
126
127 AVSS
128
P10_4
P10_3
P10_2
P10_1
KI0
P10_0
1. Overview
Analog Pin
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
Bus Control Pin
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Rev.2.41 Jan 10, 2006 Page 17 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
PIN CONFIGURATION (top view)
1. Overview
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81 50
82 <VCC2> (2) 49
83 48
84 47
85 46
86 45
87 44
88 43
89 M16C/62P Group 42
90 41
91 (M16C/62P, M16C/62PT) 40
92 39
93 38
94 37
95 36
96 35
97 34
98
99
<VCC1> (2)
33
32
100 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
Figure 1.7 Pin Configuration (Top View)
Package : PRQP0100JB-A (100P6S-A)
Rev.2.41 Jan 10, 2006 Page 18 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
PIN CONFIGURATION (top view)
1. Overview
P1_2/D10
P1_1/D9
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76 50
77
78
<VCC2> (2)
49
48
79 47
80 46
81 45
82 44
83 43
84 42
85 41
86 40
87 M16C/62P Group 39
88 38
89 (M16C/62P, M16C/62PT) 37
90 36
91 35
92 34
93 33
94 32
95 31
96 30
97 29
98
<VCC1> (2)
28
99 27
100 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT (1)
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_2/CLK2/TA1OUT/V
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
Package : PLQP0100KB-A (100P6Q-A)
Figure 1.8 Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006 Page 19 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.13 Pin Characteristics for 100-Pin Package (1)
Pin No.
Control Pin Port
FP GP
1 99
P9_6
2 100
P9_5
31
P9_4
42
P9_3
53
P9_2
64
P9_1
75
P9_0
8 6 BYTE
9 7 CNVSS
10 8 XCIN
P8_7
11 9 XCOUT P8_6
12 10 RESET
13 11 XOUT
14 12 VSS
15 13 XIN
16 14 VCC1
17 15
P8_5
18 16
P8_4
19 17
P8_3
20 18
P8_2
21 19
P8_1
22 20
P8_0
23 21
P7_7
24 22
P7_6
25 23
P7_5
26 24
P7_4
27 25
P7_3
28 26
P7_2
29 27
P7_1
30 28
P7_0
31 29
P6_7
32 30
P6_6
33 31
P6_5
34 32
P6_4
35 33
P6_3
36 34
P6_2
37 35
P6_1
38 36
P6_0
39 37
P5_7
40 38
P5_6
Interrupt Pin Timer Pin
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
NMI
INT2
INT1
INT0
ZP
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA0IN/TB5IN
TA0OUT
UART Pin
SOUT4
CLK4
SOUT3
SIN3
CLK3
CTS2/RTS2
CLK2
RXD2/SCL2
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
CTS0/RTS0
41 39
42 40
43 41
44 42
45 43
46 44
47 45
48 46
49 47
50 48
P5_5
P5_4
P5_3
P5_2
P5_1
P5_0
P4_7
P4_6
P4_5
P4_4
Analog Pin Bus Control Pin
ANEX1
ANEX0
DA1
DA0
RDY/CLKOUT
ALE
HOLD
HLAD
BCLK
RD
WRH/BHE
WRL/WR
CS3
CS2
CS1
CS0
Rev.2.41 Jan 10, 2006 Page 20 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.14 Pin Characteristics for 100-Pin Package (2)
Pin No.
Control Pin Port
FP GP
51 49
P4_3
52 50
P4_2
53 51
P4_1
54 52
P4_0
55 53
P3_7
56 54
P3_6
57 55
P3_5
58 56
P3_4
59 57
P3_3
60 58
P3_2
61 59
P3_1
62 60 VCC2
63 61
P3_0
64 62 VSS
65 63
P2_7
66 64
P2_6
67 65
P2_5
68 66
P2_4
69 67
P2_3
70 68
P2_2
71 69
P2_1
72 70
P2_0
73 71
P1_7
74 72
P1_6
75 73
P1_5
76 74
P1_4
77 75
P1_3
78 76
P1_2
Interrupt Pin
INT5
INT4
INT3
Timer Pin
UART Pin
79 77
P1_1
80 78
81 79
82 80
83 81
84 82
85 83
86 84
87 85
88 86
89 87
90 88
91 89
92 90
93 91
94 92
95 93
96 94 AVSS
97 95
98 96 VREF
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
P10_1
KI3
KI2
KI1
KI0
P10_0
99 97 AVCC
100 98
P9_7
SIN4
1. Overview
Analog Pin Bus Control Pin
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8(/-/D7)
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AN0
ADTRG
Rev.2.41 Jan 10, 2006 Page 21 of 96
REJ03B0001-0241


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M16C/62P Group (M16C/62P, M16C/62PT)
PIN CONFIGURATION (top view)
1. Overview
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1
P0_0/AN0_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61 40
62 39
63 38
64 37
65 36
66 35
67 34
68 33
69 M16C/62P Group 32
70 31
71 (M16C/62P, M16C/62PT) 30
72 29
73 28
74 27
75 26
76 25
77 24
78 23
79 22
80 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P4_3
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT (1)
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_6/TA3OUT
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
Package : PRQP0080JA-A (80P6S-A)
Figure 1.9 Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006 Page 22 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.15 Pin Characteristics for 80-Pin Package (1)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Control Pin Port
P9_5
P9_4
P9_3
CNVSS
(BYTE)
XCIN
XCOUT
P9_2
P9_0
P8_7
P8_6
RESET
XOUT
VSS
XIN
VCC1
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
P7_6
P7_1
P7_0
P6_7
P6_6
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
Interrupt Pin Timer Pin
TB4IN
TB3IN
TB2IN
TB0IN
NMI
INT2
INT1
INT0
ZP
TA4IN
TA4OUT
TA3IN
TA3OUT
TA0IN/TB5IN
TA0OUT
UART Pin
CLK4
SOUT3
CLK3
RXD2/SCL2
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
CTS0/RTS0
Analog Pin
ANEX0
DA1
DA0
34 P5_5
35 P5_4
36 P5_3
37 P5_2
38 P5_1
39 P5_0
40 P4_3
41 P4_2
42 P4_1
43 P4_0
44 P3_7
45 P3_6
46 P3_5
47 P3_4
48 P3_3
49 P3_2
50 P3_1
Bus Control Pin
CLKOUT
Rev.2.41 Jan 10, 2006 Page 23 of 96
REJ03B0001-0241


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M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.16 Pin Characteristics for 80-Pin Package (2)
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Control Pin Port
P3_0
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
Interrupt Pin
KI3
KI2
KI1
KI0
Timer Pin
UART Pin
74 P10_1
75 AVSS
76
77 VREF
P10_0
78 AVCC
79
80
P9_7
P9_6
SIN4
SOUT4
1. Overview
Analog Pin Bus Control Pin
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
ADTRG
ANEX1
Rev.2.41 Jan 10, 2006 Page 24 of 96
REJ03B0001-0241


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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
1.6 Pin Description
Table 1.17 Pin Description (100-pin and 128-pin Version) (1)
Signal Name
Power supply
input
Analog power
supply input
Reset input
CNVSS
External data
bus width
select input
Bus control
pins (4)
Pin Name
VCC1,VCC2
VSS
AVCC
AVSS
RESET
CNVSS
BYTE
D0 to D7
D8 to D15
A0 to A19
A0/D0 to
A7/D7
A1/D0 to
A8/D7
I/O
Type
I
I
I
I
I
I/O
I/O
O
I/O
I/O
Power
Supply(3)
Description
Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC1 VCC2. (1, 2)
VCC1 Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
VCC1 The microcomputer is in a reset state when applying “L” to the this pin.
VCC1
Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode.
VCC1
Switches the data bus in external memory space. The data bus is
16 bits long when the this pin is held "L" and 8 bits long when the
this pin is held "H". Set it to either one. Connect this pin to VSS
when an single-chip mode.
VCC2 Inputs and outputs data (D0 to D7) when these pins are set as the
separate bus.
VCC2 Inputs and outputs data (D8 to D15) when external 16-bit data bus
is set as the separate bus.
VCC2 Output address bits (A0 to A19).
VCC2 Input and output data (D0 to D7) and output address bits (A0 to A7) by
timesharing when external 8-bit data bus are set as the multiplexed bus.
VCC2
Input and output data (D0 to D7) and output address bits (A1 to A8)
by timesharing when external 16-bit data bus are set as the
multiplexed bus.
CS0 to CS3 O
VCC2 Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to
specify an external space.
WRL/WR
O VCC2 Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or
WRH/BHE
BHE and WR can be switched by program.
RD WRL, WRH and RD are selected
The WRL signal becomes "L" by writing data to an even address in
an external memory space.
The WRH signal becomes "L" by writing data to an odd address in
an external memory space.
The RD pin signal becomes "L" by reading data in an external
memory space.
WR, BHE and RD are selected
The WR signal becomes "L" by writing data in an external memory space.
The RD signal becomes "L" by reading data in an external memory space.
The BHE signal becomes "L" by accessing an odd address.
Select WR, BHE and RD for an external 8-bit data bus.
ALE O VCC2 ALE is a signal to latch the address.
HOLD
I VCC2 While the HOLD pin is held "L", the microcomputer is placed in a
hold state.
HLDA
O VCC2 In a hold state, HLDA outputs a "L" signal.
RDY
I VCC2 While applying a "L" signal to the RDY pin, the microcomputer is
placed in a wait state.
I : Input O : Output I/O : Input and output
Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be
interfaced using the different voltage as VCC1.
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 = VCC2.
3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
4. Bus control pins in M16C/62PT cannot be used.
Rev.2.41 Jan 10, 2006 Page 25 of 96
REJ03B0001-0241


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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.18 Pin Description (100-pin and 128-pin Version) (2)
Signal Name Pin Name
Main clock
input
XIN
Main clock
output
XOUT
Sub clock input XCIN
Sub clock
output
XCOUT
BCLK output (2) BCLK
Clock output CLKOUT
INT interrupt
input
INT0 to INT2
NT3 to INT5
NMI interrupt
input
Key input
interrupt input
Timer A
Timer B
Three-phase
motor control
output
Serial interface
NMI
KI0 to KI3
TA0OUT to
TA4OUT
TA0IN to
TA4IN
ZP
TB0IN to
TB5IN
U, U, V, V,
W, W
CTS0 to
CTS2
RTS0 to
RTS2
CLK0 to
CLK4
RXD0 to
RXD2
SIN3, SIN4
TXD0 to
TXD2
SOUT3,
SOUT4
CLKS1
I2C mode
SDA0 to
SDA2
SCL0 to
SCL2
I/O
Type
I
O
I
O
O
O
I
I
I
I
I/O
I
I
I
O
I
O
I/O
I
I
O
O
O
I/O
I/O
Power
Supply(1)
Description
VCC1
VCC1
I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (3). To use
the external clock, input the clock from XIN and leave XOUT open.
VCC1
VCC1
VCC2
VCC2
VCC1
VCC2
VCC1
VCC1
I/O pins for a sub clock oscillation circuit. Connect a crystal
oscillator between XCIN and XCOUT (3). To use the external clock,
input the clock from XCIN and leave XCOUT open.
Outputs the BCLK signal.
The clock of the same cycle as fC, f8, or f32 is outputted.
Input pins for the INT interrupt.
Input pin for the NMI interrupt. Pin states can be read by the P8_5
bit in the P8 register.
Input pins for the key input interrupt.
VCC1
VCC1
These are timer A0 to timer A4 I/O pins. (however, output of
TA0OUT for the N-channel open drain output.)
These are timer A0 to timer A4 input pins.
VCC1 Input pin for the Z-phase.
VCC1 These are timer B0 to timer B5 input pins.
VCC1 These are Three-phase motor control output pins.
VCC1 These are send control input pins.
VCC1 These are receive control output pins.
VCC1 These are transfer clock I/O pins.
VCC1 These are serial data input pins.
VCC1
VCC1
VCC1
These are serial data input pins.
These are serial data output pins. (however, output of TXD2 for the
N-channel open drain output.)
These are serial data output pins.
VCC1
VCC1
VCC1
This is output pin for transfer clock output from multiple pins
function.
These are serial data I/O pins. (however, output of SDA2 for the N-
channel open drain output.)
These are transfer clock I/O pins. (however, output of SCL2 for the
N-channel open drain output.)
I : Input O : Output I/O : Input and output
NOTES:
1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
2. This pin function in M16C/62PT cannot be used.
3. Ask the oscillator maker the oscillation characteristic.
Rev.2.41 Jan 10, 2006 Page 26 of 96
REJ03B0001-0241


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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.19 Pin Description (100-pin and 128-pin Version) (3)
Signal Name Pin Name
Reference
voltage input
A/D converter
VREF
AN0 to AN7,
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
ADTRG
ANEX0
D/A converter
I/O port
Input port
ANEX1
DA0, DA1
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
P12_0 to
P12_7 (2),
P13_0 to
P13_7 (2)
P6_0 to P6_7,
P7_0 to P7_7,
P9_0 to P9_7,
P10_0 to
P10_7,
P11_0 to
P11_7 (2)
P8_0 to P8_4,
P8_6, P8_7,
P14_0,
P14_1(2)
P8_5
I/O Power
Type Supply(1)
Description
I VCC1 Applies the reference voltage for the A/D converter and D/A
converter.
I VCC1 Analog input pins for the A/D converter.
I VCC1 This is an A/D trigger input pin.
I/O VCC1 This is the extended analog input pin for the A/D converter, and is
the output in external op-amp connection mode.
I VCC1 This is the extended analog input pin for the A/D converter.
O VCC1 This is the output pin for the D/A converter.
I/O VCC2 8-bit I/O ports in CMOS, having a direction register to select an
input or output.
Each pin is set as an input port or output port. An input port can
be set for a pull-up or for no pull-up in 4-bit unit by program.
I/O VCC1 8-bit I/O ports having equivalent functions to P0.
(however, output of P7_0 and P7_1 for the N-channel open drain
output.)
I/O VCC1 I/O ports having equivalent functions to P0.
I VCC1 Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I : Input O : Output I/O : Input and output
NOTES:
1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
2. Ports P11 to P14 in M16C/62P (100-pin version) and M16C/62PT (100-pin version) cannot be used.
Rev.2.41 Jan 10, 2006 Page 27 of 96
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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.20 Pin Description (80-pin Version) (1) (1)
Signal Name Pin Name
Power supply
input
Analog power
supply input
Reset input
CNVSS
VCC1, VSS
AVCC
AVSS
RESET
CNVSS
(BYTE)
I/O
Type
I
I
I
I
Main clock
input
XIN
Main clock
output
XOUT
Sub clock input XCIN
Sub clock
output
XCOUT
Clock output CLKOUT
INT interrupt INT0 to INT2
input
NMI interrupt
input
Key input
interrupt input
Timer A
Timer B
Serial interface
NMI
KI0 to KI3
TA0OUT,
TA3OUT,
TA4OUT
TA0IN, TA3IN,
TA4IN
ZP
TB0IN, TB2IN
to TB5IN
CTS0 to CTS1
RTS0 to RTS1
CLK0, CLK1,
CLK3, CLK4
RXD0 to RXD2
SIN4
TXD0 to TXD2
I
O
I
O
O
I
I
I
I/O
I
I
I
I
O
I/O
I
I
O
SOUT3,
SOUT4
CLKS1
O
O
I2C mode
SDA0 to SDA2 I/O
SCL0 to SCL2 I/O
Power
Description
Supply
Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. (1, 2)
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC2
VCC1
Applies the power supply for the A/D converter. Connect the
AVCC pin to VCC1. Connect the AVSS pin to VSS.
The microcomputer is in a reset state when applying “L” to the this pin.
Switches processor mode. Connect this pin to VSS to when after a
reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode. As for the BYTE pin of the 80-pin
versions, pull-up processing is performed within the microcomputer.
I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (3). To use
the external clock, input the clock from XIN and leave XOUT
open.
I/O pins for a sub clock oscillation circuit. Connect a crystal
oscillator between XCIN and XCOUT (3). To use the external
clock, input the clock from XCIN and leave XCOUT open.
The clock of the same cycle as fC, f8, or f32 is outputted.
Input pins for the INT interrupt.
VCC1 Input pin for the NMI interrupt.
VCC1 Input pins for the key input interrupt.
VCC1 These are Timer A0,Timer A3 and Timer A4 I/O pins. (however,
output of TA0OUT for the N-channel open drain output.)
VCC1 These are Timer A0, Timer A3 and Timer A4 input pins.
VCC1 Input pin for the Z-phase.
VCC1 These are Timer B0, Timer B2 to Timer B5 input pins.
VCC1
VCC1
VCC1
These are send control input pins.
These are receive control output pins.
These are transfer clock I/O pins.
VCC1
VCC1
VCC1
VCC1
These are serial data input pins.
This is serial data input pin.
These are serial data output pins. (however, output of TXD2 for
the N-channel open drain output.)
These are serial data output pins.
VCC1
VCC1
VCC1
This is output pin for transfer clock output from multiple pins
function.
These are serial data I/O pins. (however, output of SDA2 for the
N-channel open drain output.)
These are transfer clock I/O pins. (however, output of SCL2 for
the N-channel open drain output.)
I : Input O : Output I/O : Input and output
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin.
3. Ask the oscillator maker the oscillation characteristic.
Rev.2.41 Jan 10, 2006 Page 28 of 96
REJ03B0001-0241


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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
Table 1.21 Pin Description (80-pin Version) (2)
Signal Name Pin Name
Reference
voltage input
A/D converter
VREF
AN0 to AN7,
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
ADTRG
ANEX0
D/A converter
I/O port (1)
Input port
ANEX1
DA0, DA1
P0_0 to P0_7,
P2_0 to P2_7,
P3_0 to P3_7,
P5_0 to P5_7,
P6_0 to P6_7,
P10_0 to
P10_7
P8_0 to P8_4,
P8_6, P8_7,
P9_0,
P9_2 to P9_7
P4_0 to P4_3,
P7_0, P7_1,
P7_6, P7_7
P8_5
I/O Power
Type Supply(1)
Description
I VCC1 Applies the reference voltage for the A/D converter and D/A
converter.
I VCC1 Analog input pins for the A/D converter.
I VCC1 This is an A/D trigger input pin.
I/O VCC1 This is the extended analog input pin for the A/D converter, and is
the output in external op-amp connection mode.
I VCC1 This is the extended analog input pin for the A/D converter.
O VCC1 This is the output pin for the D/A converter.
I/O VCC1 8-bit I/O ports in CMOS, having a direction register to select an
input or output.
Each pin is set as an input port or output port. An input port can
be set for a pull-up or for no pull-up in 4-bit unit by program.
I/O VCC1 I/O ports having equivalent functions to P0.
I/O VCC1 I/O ports having equivalent functions to P0.
(however, output of P7_0 and P7_1 for the N-channel open drain
output.)
I VCC1 Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I : Input O : Output I/O : Input and output
NOTES:
1. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the
direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Rev.2.41 Jan 10, 2006 Page 29 of 96
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M30626MJP-XXXGP (Renesas Technology)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/62P Group (M16C/62P, M16C/62PT)
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
b31
R2
R3
b15 b8 b7 b0
R0H
R0L
R1H
R1L
R2
Data Registers (1)
R3
A0
Address Registers (1)
A1
FB Frame Base Registers (1)
b19 b15
INTBH
INTBL
b0
Interrupt Table Register
b19 b0
PC Program Counter
b15 b0
USP
User Stack Pointer
ISP Interrupt Stack Pointer
SB Static Base Register
b15 b0
FLG Flag Register
b15
IPL
b8 b7
b0
U I OB S Z D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTES:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
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