VT1620A (VIA)
VinylUSB USB2.0 FS Audio Codec

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Data Sheet
VT1620A
VinylUSB USB2.0 FS Audio Codec
April 22, 2010
Revision 1.01


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VT1620A VinylUSB USB2.0 FS Audio Codec
Revision History
Rev
1.0
1.01
Date
Dec. 8, 09
Apr. 22, 10
Initial
TL
TL
Note
Initial external release
Corrected typo in functional block diagram
Updated legal page
i


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VT1620A VinylUSB USB2.0 FS Audio Codec
ii
Table of Contents
Revision History ........................................................................................................................ i
Table of Contents ..................................................................................................................... ii
List of Figures..........................................................................................................................iii
List of Tables ...........................................................................................................................iii
1 Product Features ................................................................................................................... 1
2 Overview.............................................................................................................................. 2
3 Pinout .................................................................................................................................. 3
4 Pin List................................................................................................................................. 4
5 Pin Description...................................................................................................................... 5
5.1 USB Interface ............................................................................................................... 5
5.2 I2C Interface ................................................................................................................ 5
5.3 Button & LED Interface .................................................................................................. 5
5.4 S/PDIF Interface ........................................................................................................... 5
5.5 Clock Interface ............................................................................................................. 5
5.6 SPI Interface ................................................................................................................ 5
5.7 Codec Interface ............................................................................................................ 6
5.8 Power & Ground............................................................................................................ 6
5.9 GPIO (General Purpose Input/Output) Interface................................................................ 6
5.10 Test Mode Interface ..................................................................................................... 6
6 Memory Map......................................................................................................................... 7
6.1 Program Memory Space ................................................................................................. 7
6.2 Data Memory Space ...................................................................................................... 7
6.3 MCU Internal Registers .................................................................................................. 7
6.4 Configuration Registers and Data Memory ........................................................................ 8
7 Audio Capabilities .................................................................................................................. 9
7.1 Multiple Audio Configuration Support ............................................................................... 9
7.2 Audio Topologies ......................................................................................................... 10
7.3 Default Microphone Array Geometry Descriptor............................................................... 12
7.4 Default Manufacturer String ......................................................................................... 14
7.5 Default Product String ................................................................................................. 14
7.6 User Customization ..................................................................................................... 14
8 Clock and Crystal Networks .................................................................................................. 17
8.1 External Clock Source or Crystal Networks ..................................................................... 17
8.2 Internal Clock Generation ............................................................................................ 18
8.3 Clock Divisor Settings.................................................................................................. 19
9 Electrical Specification ......................................................................................................... 20
9.1 Absolute Maximum Ratings .......................................................................................... 20
9.2 Recommended Operating Conditions ............................................................................. 20
9.3 Electrical Parameters ................................................................................................... 20
10 Mechanical Specification ..................................................................................................... 22


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VT1620A VinylUSB USB2.0 FS Audio Codec
iii
List of Figures
Figure 1 – VT1620A Functional Block Diagram ............................................................................. 2
Figure 2 – VT1620A Pin Diagram for LQFP-48 (Top View) .............................................................. 3
Figure 3 – Audio Topology of USB Dongle .................................................................................. 10
Figure 4 – Audio Topology of USB Headset ................................................................................ 10
Figure 5 – Audio Topology of USB Speaker ................................................................................ 11
Figure 6 – Audio Topology of USB Microphone............................................................................ 11
Figure 7 – Audio Topology of USB Mic-Array .............................................................................. 11
Figure 8 – Microphone Array Coordinate System ........................................................................ 13
Figure 9 – VT1620A Clock and Crystal Networks ........................................................................ 17
Figure 10 – VT1620A Clock Generator ...................................................................................... 18
Figure 11 – VT1620A LQFP-48 Package (7 mm×7 mm)............................................................... 22
List of Tables
Table 1 – VT1620A Pin List ........................................................................................................ 4
Table 2 – Program Memory Space of VT1620A ............................................................................. 7
Table 3 – Memory Map of MCU Internal Registers ......................................................................... 7
Table 4 – Memory Map of Configuration Registers and Data Memory............................................... 8
Table 5 – Settings of CONFIG [2:0] for VT1620A .......................................................................... 9
Table 6 – VT1620A Configuration Options.................................................................................... 9
Table 7 – Microphone Array Information.................................................................................... 12
Table 8 – Settings of FSEL [1:0] for VT1620A versus EEPROM Types............................................. 14
Table 9 – EEPROM Data Structure ............................................................................................ 15
Table 10 – Clock Divisor Settings ............................................................................................. 19


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VT1620A VinylUSB USB2.0 FS Audio Codec
1
1 Product Features
VT1620A
VinylUSB USB2.0 FS Audio Codec
USB Interface
USB transceiver integrated
USB 2.0 full speed compliant
USB audio device class specification
v1.0 compliant
USB Device Firmware Upgrade v1.1
compliant
Supports one Control Endpoint, one
Isochronous Out Endpoint, one
Isochronous In Endpoint, one
Feedback Endpoint and one Interrupt
Endpoint.
Alternative zero bandwidth setting to
save USB bus bandwidth while the
device in idle status
USB HID volume, mute, and GIO
support
Supports suspend, resume and remote
wake-up
Adaptive clock generator for audio
streaming synchronization
USB Feedback endpoint support to
enable lossless audio quality
MCU
Embedded 8032 with ICE mode
support
Built-in 16k ROM for firmware; no
extra Flash required
Optional External Serial Flash for
firmware, Max. 64k
External Serial Flash for vendor
specific VID, PID and Serial Number
I2C Interface
Supports both slave mode and master
mode
Supports wait-states
Up to 400 kb/s data transfer rate
Audio Capabilities
SPDIF TX audio interface (1 port)
ΠFull duplex 16-, 20-, 24-bit mono-
or 2-channel
Π44.1 kHz, 48 kHz, 96 kHz, 192 kHz
sampling rates
Embedded Audio CODEC
ΠADC SNR 90 dB and THD -80 dB
ΠDAC SNR 95 dB and THD -85 dB
Π2-ch 16/24-bit ADC, supporting
44.1 kHz, 48 kHz, 96 kHz, 192 kHz
sampling rates
Π2-ch 16/24-bit DAC, supporting
44.1 kHz, 48 kHz, 96 KHz, 192
kHz sampling rates
ΠLeft / Right channel exchange for
both ADC and DAC.
ΠNoise Gate
ΠALC for ADC
ΠEmbedded headphone amplifier
Audio Device Configuration
MIC-Array: 2-ch microphone
MIC-Array & mono speaker: 2-ch
microphone & 2-ch stereo output
Headset: 1-ch microphone & 2-ch
stereo output
VoIP: 1-ch microphone & 2-ch stereo
output & HID
Capless headphone
AA path support
Specific and General IO Interface
Record-mute LED
Device-in-operation LED
Buzz output
General IO pins
Miscellaneous
Single 6-MHz Crystal input with
on-chip PLL.
USB bus-powered device, with built-in
5-V to 3.3-V and 5-V to 2-V regulator
Independent sample rate for playback
and recording.


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VT1620A VinylUSB USB2.0 FS Audio Codec
2
2 Overview
The VT1620A VinylUSB chip is a Universal Serial Bus Audio Codec for intermediate consumer headphone
or IP phone applications. It conforms to the USB 2.0 Specification and supports Full-Speed mode.
VT1620A supports USB Audio Class 1.0, and hence can enable driverless product. Featuring with S/PDIF
TX interface, VT1620A’s stereo I/O supports most popular digital audio sampling resolutions. VT1620A
requires only one 6-MHz crystal to generate all necessary clock frequencies for internal clock operation.
VT1620A also integrates 5-V to 3.3-V and 5-V to 2-V regulator; together with 16-k built-in ROM, it
provides customer with extremely cost-competitive BOM solution.
Figure 1 shows the functional block diagram for VT1620A VinylUSB Audio Codec.
1
Figure 1 – VT1620A Functional Block Diagram


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VT1620A VinylUSB USB2.0 FS Audio Codec
3 Pinout
3
HP_COM
LINEOR
LINEOL
HPGND
HPVDD
AVDD50
AGND
PDRGL33
AVDD
AVSS
VREF
VMID
37
38
39
40
41
42
43
44
45
46
47
48
24 BUSYLED
23 MUTEREC
22 VOLDN
21 VOLUP
20 GPIO1
19 GPIO2
18 GPIO3
17 GPIO4
16 GPIO5
15 CONFIG2
14 SFCS
13 SFCLK
Figure 2 – VT1620A Pin Diagram for LQFP-48 (Top View)


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VT1620A VinylUSB USB2.0 FS Audio Codec
4
4 Pin List
Table 1 – VT1620A Pin List
Pin I/O Pin Name
1 A MICBIAS
2 A MICIN2
3 A MICIN1
4 A PDRGL20
5 P DVDD33
6 P DVDD50
7 P DVSS
8 P DVDD20
9 A DP
10 A DM
11 I SFDI
12 O SFDO
Pin I/O Pin Name
13 O SFCLK
14 O SFCS
15 B CONFIG2
16 B GPIO5
17 B GPIO4
18 B GPIO3
19 B GPIO2
20 B GPIO1
21 B VOLUP
22 B VOLDN
23 B MUTEREC
24 B BUSYLED
Note:
I = Input;
O = Output
A = Analog
B = Bi-directional
P = Power / Ground
Pin I/O Pin Name
Pin I/O Pin Name
25 A XI
37 A HP_COM
26 A XO
38 A LINEOR
27 B MUTELED
39 A LINEOL
28 B SPDIFO/BUZZ 40 P HPGND
29 I TESTMODE
41 P HPVDD
30 B FSEL1
42 P AVDD50
31 B MUTEPLY
43 P AGND
32 B FSEL0
44 A PDRGL33
33 B I2CSCL_S
45 P AVDD
34 B I2CSDA_S
46 P AVSS
35 B CONFIG1
47 A VREF
36 B CONFIG0
48 A VMID


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VT1620A VinylUSB USB2.0 FS Audio Codec
5 Pin Description
5.1 USB Interface
Pin Name Type
DP A
DM A
Pin #
9
10
Signal Description
USB Bus DPlus.
USB Bus DMinus.
5.2 I2C Interface
Pin Name Type
I2CSCL_S B
I2CSDA_S B
Pin #
33
34
Signal Description
I2C Slaver SCL.
I2C Slaver SDA.
5.3 Button & LED Interface
Pin Name Type
Pin #
VOLUP
B
21
VOLDN
B
22
MUTEREC B
23
MUTEPLY
B
31
BUSYLED B
24
MUTELED B
27
Signal Description
Volume Up.
Volume Down.
Mute Record.
Mute Play.
Busy LED.
Mute LED.
5.4 S/PDIF Interface
Pin Name
Type
SPDIFO/BUZZ B
Pin #
28
Signal Description
S/PDIF Output Signal; Buzz Output.
5.5 Clock Interface
Pin Name
Type
XO A
XI A
Pin #
26
25
Signal Description
Clock Out.
Clock In. 6 MHz.
5.6 SPI Interface
Pin Name
Type
SFCS
O
SFDI
I
SFDO
O
SFCLK
O
Pin #
14
11
12
13
Signal Description
Serial Flash Chip Selects. Active-low.
Serial Flash Controller Data Input.
Serial Flash Controller Data Output.
Serial Flash Clock.
5


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VT1620A VinylUSB USB2.0 FS Audio Codec
5.7 Codec Interface
Pin Name
Type
MICIN1
A
MICIN2
A
MICBIAS
A
LINEOR
A
LINEOL
A
HP_COM
A
VREF
A
VMID
A
PDRGL33
A
PDRGL20
A
Pin #
3
2
1
38
39
37
47
48
44
4
Signal Description
Microphone Input 1.
Microphone Input 2.
Microphone Bias.
Line-out Right.
Line-out Left.
Line-out Bias.
Reference Voltage Decoupling Capacitor.
Mid-rail Voltage Decoupling Capacitor.
PD 5 ~ 3.3 V RGL.
PD 5 ~ 2.0 V RGL.
6
5.8 Power & Ground
Pin Name
Type
AVDD50
P
AVDD
P
HPVDD
P
AVSS
P
AGND
P
DVDD50
P
DVDD33
P
DVDD20
P
DVSS
P
Pin #
42
45
41
46
43
6
5
8
7
Signal Description
USB 5 V Power for Analog Part Regulator.
RGL Output for Analog Audio Circuit.
RGL Output for Headphone Driver Supply.
Analog Ground for Audio Circuit.
Reference Ground for Internal Analog Circuit.
USB 5 V Power for Digital Part Regulator.
RGL 3.3 V Output for Digital Part.
RGL 2.0 V Output for Digital Part.
Ground for Digital Part.
5.9 GPIO (General Purpose Input/Output) Interface
Pin Name
Type
Pin #
Signal Description
GPIO[5:1]
B
16; 17;
18; 19;
20
General Purpose Input/Output.
*FSEL[1:0]
B
30; 32
Flash Type Select.
**CONFIG[2:0] B
15; 35;
36
Device Type Select.
Note:
* Refer to Table 8 – Settings of FSEL [1:0] for VT1620A versus EEPROM Types for detailed EEPROM
selection.
** Refer to Table 5 – Settings of CONFIG [2:0] for VT1620A for detailed device type selection.
5.10 Test Mode Interface
Pin Name
Type
TESTMODE
I
Pin #
29
Signal Description
TESTMODE.


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VT1620A VinylUSB USB2.0 FS Audio Codec
7
6 Memory Map
The 8051 family’s memory is organized in a Harvard structure, which means the program memory and
data memory are located in the separate address spaces. The 16 address lines can access up to 64k byte
space.
6.1 Program Memory Space
Since the 8032 core embedded in VT1620A is a ROMless version of 8051, all the program memories used
by VT1620A are considered as “External memory” in the point of view of 8032 core.
Table 2 – Program Memory Space of VT1620A
Byte Address Range
0x0000 – 0x0FFF
0x1000 – 0x3FFF
0x4000 – 0xFFFF
On-chip (Note 1.)
Built-in ROM /
EP1/2 Buffer (Note 2.)
Built-in ROM
--
Off-chip (Note 1.) Size in bytes
Serial Flash
4k
Data Access
8 bits R/W
Serial Flash
Serial Flash
12k
48k
8 bits R/W
8 bits R/W
Note:
1. When boot from ROM is selected by the strapping option, on-chip space will be used as the program
memory. When boot from ROM is not selected by the strapping option, off-chip space will be used
as the program memory.
2. When updating firmware in the off-chip program memory, EP1/2 SRAM is used as the temporary
program memory storage. Under this mode, the lowest 4k address will be mapped to EP1/2 buffer.
6.2 Data Memory Space
The 256 bytes of internal registers and up to 64k bytes of external data memory can be accessed by the
8032 core. (The boundary of internal/external is the 8032 core.)
6.3 MCU Internal Registers
Please refer to the following Table 3 for the memory map of MCU Internal Registers.
1
Table 3 – Memory Map of MCU Internal Registers
Byte Address Range
0x0000 – 0x001F
0x0020 – 0x002F
0x0030 – 0x007F
0x0080 – 0x00FF
On-chip
4 banks of R0-R7
Bit addressable 0x00-0x7F
Rest of lower 128
Direct/indirect addressing
Upper 128
indirect addressing only
SFR
direct addressing
Off-chip
--
--
--
--
Size in Bytes
32
16
80
128
Data Access
8 bits R/W
1/8 bits R/W
8 bits R/W
8 bits R/W
1/8 bits R/W


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VT1620A VinylUSB USB2.0 FS Audio Codec
8
6.4 Configuration Registers and Data Memory
Please refer to the following Table 4 for the memory map of Configuration Registers and Data Memory.
1
Table 4 – Memory Map of Configuration Registers and Data Memory
Byte Address Range
0x0000 – 0x00FF
0x0100 – 0x01FF
0x0200 – 0x02FF
0x0300 – 0x03FF
0x0400 – 0x04FF
0x0500 – 0x05FF
0x0600 – 0x06FF
0x0700 – 0x07FF
0x0800 – 0x09FF
0x0A00 – 0x0AFF
0x0B00 – 0x0DFF
0x0E00 – 0x0EFF
0x0F00 – 0x0FFF
0x1000 – 0x10FF
0x1100 – 0x3FFF
0x4000 – 0x47FF
0x4800 – 0x4FFF
0x5000 – 0xFFFF
On-chip
System Configuration
Interrupt Controller
USB Controller
Serial Flash Controller
Endpoint Data Buffer
Controller
I2S Audio Controller
I2C Controller
SPDIF Register Set
RESERVED
CODEC Register Set
RESERVED
GPIO Controller
RESERVED
UGM
RESERVED
EP1 Buffer
EP2 Buffer
RESERVED
Off-chip
--
--
--
--
--
--
--
--
RESERVED
--
RESERVED
--
RESERVED
--
RESERVED
--
--
RESERVED
Size in bytes
256
256
256
256
256
256
256
256
512
256
768
256
256
256
8K
2k
2k
44K
Data Access
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W
8 bits R/W


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VT1620A VinylUSB USB2.0 FS Audio Codec
9
7 Audio Capabilities
7.1 Multiple Audio Configuration Support
VT1620A integrates two channel audio ADC and two channel audio DAC. VT1620A supports various audio
sample rates. Table 5 shows the settings of CONFIG [2:0] that allows VT1620A to be configured for
applications of different product categories. Table 6 shows the detailed configuration options of VT1620A.
Table 5 – Settings of CONFIG [2:0] for VT1620A
Configuration
USB Dongle
USB Headset
USB Speaker
USB Microphone
USB MicArray
CONFIG2
0
0
0
0
1
CONFIG1
0
0
1
1
0
CONFIG0
0
1
0
1
0
Note:
USB Dongle is the default configuration. For the values not included in the above table, i.e. 101, 110,
and 111, VT1620 will be configured as USB Dongle.
Table 6 – VT1620A Configuration Options
USB Dongle
2-In/2-Out
USB Headset USB Speaker USB Mic
1-In/2-Out
2-Out
2-In
SPDIF
Channel
N/A N/A N/A
Stereo
Stereo
Stereo
N/A
44.1/48k 16 bit 44.1/48k 16 bit 44.1/48k 16 bit
USB
Mic-Array
2-In/2-Out
N/A
Stereo
Playback
Sample
Rate/
Bit
Width
44.1/48k 24 bit
96k 16 bit
96k 24 bit
44.1/48k 24 bit
96k 16 bit
96k 24 bit
44.1/48k 24 bit
96k 16 bit
96k 24 bit
N/A
44.1/48k
16 bit
Channel
Record
Sample
Rate/
Bit
Width
A-A Path
Mic-Array
HID
192k 16 bit
192k 16 bit
192k 16 bit
Stereo
Mono
N/A
44.1/48k 16 bit 44.1/48k 16 bit
44.1/48k 24 bit 44.1/48k 24 bit N/A
96k 16 bit
96k 24 bit
96k 16 bit
96k 24 bit
N/A
N/A N/A N/A
●●●
Stereo
Stereo
44.1k/48k 44.1k/48k
16 bit
16 bit
N/A N/A
N/A
N/A


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VT1620A VinylUSB USB2.0 FS Audio Codec
10
7.2 Audio Topologies
The following Figure 3 to
1
Figure 7 illustrate the audio topologies of VT1620A, including USB dongle, USB headset, USB speaker,
USB microphone, and USB Mic-Array.
7.2.1 USB Dongle
VT1620A supports volume control (-40 dB ~ 0 dB) and mute control for speaker output path; MIC boost
(+20 dB), volume control (0 ~ 30 dB), and mute control for microphone input path; volume control (0 ~
30 dB) and mute control for AA path in the USB dongle application.
Figure 3 – Audio Topology of USB Dongle
7.2.2 USB Headset
The topology of the USB headset is the same as the USB dongle.
USB OUT
IT
Mixer
Volume/Mute
Volume/Mute
Speaker
OT
MIC IN
IT
MIC Boost
Volume/Mute
Mixer
Figure 4 – Audio Topology of USB Headset
USB IN
OT


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VT1620A VinylUSB USB2.0 FS Audio Codec
11
7.2.3 USB Speaker
VT1620A supports volume control (-40 dB ~ 0 dB) and mute control in the USB speaker application.
Figure 5 – Audio Topology of USB Speaker
7.2.4 USB Microphone
VT1620A supports the volume control (0 dB ~ 30 dB) and mute control functions in the USB microphone
application.
Figure 6 – Audio Topology of USB Microphone
7.2.5 USB Mic-Array
VT1620A supports volume control (-40 dB ~ 0 dB), and mute control for the speaker output path; MIC
boost (+20 dB), volume control (0 ~ 30 dB), and mute control for microphone input path in the USB
Mic-Array application.
Figure 7 – Audio Topology of USB Mic-Array


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VT1620A VinylUSB USB2.0 FS Audio Codec
7.3 Default Microphone Array Geometry Descriptor
Please refer to the following Table 7 for the register summary information of Microphone Array.
12
Table 7 – Microphone Array Information
Offset
0
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
Field
guidMicArrayID
wDescriptorLength
wVersion
bmMicArrayType
wWorkVertAngBeg
wWorkVertAngEnd
wWorkHorAngBeg
wWorkHorAngEnd
wWorkFreqBandLo
wWorkFreqBandHi
wNumberOfMics
wMicrophoneType(0)
wXCoordinate(0)
wYCoordinate(0)
wZCoordinate(0)
wMicVertAngle(0)
wMicHorAngle(0)
wMicType(1)
wXCoordinate(1)
wYCoordinate(1)
wZCoordinate(1)
wMicVertAngle(1)
wMicHorAngle(1)
Size
16
bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
Value
Description
07FE86C1-8948- A unique ID that marks the beginning of the
4db5-B184-C516 microphone array information in the
2D4AD314h
memory.
003Ch
The length in bytes of the microphone array
information, including the GUID and length
fields.
0100h
The version number of the microphone
array specification, followed by this
descriptor.
0000h
The microphone array type.
When the following bits are set to one, it
indicates the associated array type:
D0: Linear.
D1: Planar.
D2: 3D.
D15...3: Reserved
0000h
The start of the work volume vertical angle.
0000h
The end of the work volume vertical angle.
DDE9h
The beginning of the work volume
horizontal angle.
2217h
The end of the work volume horizontal
angle.
0050h
The lower bound of the work frequency
range.
1D4Ch
The upper bound of the work frequency
range.
0002h
The number of individual microphone
definitions that follow.
0000h
A number that uniquely identifies the type
of microphone 0:
00: Omni-Directional
01: SubCardioid
02: Cardioid
03: SuperCardioid
04: HyperCardioid
05: 8 Shaped
0F - FF: Vendor defined
0000h
The x-coordinate of microphone 0.
FFCEh
The y-coordinate of microphone 0.
0000h
The z-coordinate of microphone 0.
0000h
The main response axis (MRA) vertical
angle of microphone 0.
0000h
The MRA horizontal angle of microphone 0.
0000h
A number that uniquely identifies the type
of microphone 1:
00: Omni-Directional
01: SubCardioid
02: Cardioid
03: SuperCardioid
04: HyperCardioid
05: 8 Shaped
0F - FF: Vendor defined
0000h
The x-coordinate of microphone 1.
0032h
The y-coordinate of microphone 1.
0000h
The z-coordinate of microphone 1.
0000h
The MRA vertical angle of microphone 1.
0000h
The MRA horizontal angle of microphone 1.


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VT1620A VinylUSB USB2.0 FS Audio Codec
13
Note:
1. The offset and size values are in bytes.
2. All angles are expressed in the units of 1/10000 radians. For example, 0.8727 radians is expressed
as 8727 (0x2217). The value can range from -31416 to 31416, inclusive.
3. X-y-z coordinates are expressed in millimeters. The value can range from 32767 to 32767,
inclusive.
4. The coordinate system’s orientation, axes, and the positive directions of the angles are shown in
the following Figure 8.
5. Frequency values are expressed in Hz. The range of frequency values is bounded only by the size
of the field and assumes that only typical values are used.
Figure 8 – Microphone Array Coordinate System


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7.4 Default Manufacturer String
y Default Manufacturer String: VIA Technologies Inc.
7.5 Default Product String
y USB Dongle: VIA USB Dongle
y USB Headset: VIA USB Headset
y USB Speaker: VIA USB Speaker
y USB Microphone: VIA USB Microphone
y USB Mic-Array: VIA USB MicArray
14
7.6 User Customization
The manufacturer can change default VID/PID, manufacturer string, product string, serial number string,
and microphone array geometry descriptor (for USB Mic-array configuration only) by an external EERPOM.
Table 8 shows the settings of FSEL [1:0] for VT1620A versus EEPROM types. The EEPROM data
structure is defined in Table 9.
Table 8 – Settings of FSEL [1:0] for VT1620A versus EEPROM Types
EEPROM Type
Internal ROM, without EEPROM
Internal ROM, with EEPROM of 1-byte address
Internal ROM, with EEPROM of 2-byte address
Internal ROM, with EEPROM of 3-byte address
FSEL1
0
0
1
1
FSEL0
0
1
0
1
Note:
According to the size of EEPROM, the address can be 1 byte, 2 bytes, or 3 bytes. For example, usually the
EEPROM of 2k-bit or less uses 1-byte address, and the EEPROM of 1M-bit or more uses 3-byte address.
For the EEPROM of 1-byte address, FSEL=01
For the EEPROM of 2-byte address, FSEL=10
For the EEPROM of 3-byte address, FSEL=11
If no customized information is needed, FSEL should be set to 00.


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15
Byte Index
0
1
2
3
4
5
VID
Info
6
7
PID
Info
8
9
Table 9 – EEPROM Data Structure
Description
Magic Number1: “V”, 0x56
Magic Number2: “T”, 0x54
Total Data Length Low Byte
Total Data Length High Byte
Bit [3:0]: System Configuration
Bit [4]:
1 — — Support remote wakeup;
0 — — Not support remote wakeup
Bit [7:5]: Reserved.
Reserved
If Byte 7 Bit [7] == 1, Byte 6 is the offset Bit [7:0] of VID low byte in EEPROM, and
VID high byte is the next byte after VID low byte.
If Byte 7 Bit [7] == 0, Byte6 is reserved.
If Byte 5 Bit [7] == 1, Byte 7 Bit [6:0] is the offset Bit [14:8] of VID low byte.
If Byte 5 Bit [7] == 0, Byte 7 Bit [6:0] is reserved.
Bit [7]:
1 —— There is VID in EEPROM;
0 —— No VID in EEPROM
If Byte 9 Bit [7] == 1, Byte 8 is the offset Bit [7:0] of PID low byte in EEPROM, and
PID high byte is the next byte after PID low byte.
If Byte 9 Bit [7] == 0, Byte 8 is reserved.
If Byte 9 Bit [7] == 1, Byte 9 Bit [6:0] is the offset Bit [14:8] of PID low byte.
If Byte 9 Bit [7] == 0, Byte 9 Bit [6:0] is reserved.
Bit [7]:
1 —— There is PID in EEPROM;
0 —— No PID in EEPROM


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16
Byte Index
Device
String
Info
10
11
Vendor
String
Info
12
13
14
15
SN
Info
16
17
18
19
20
Mic-Array
Info
21
22
23
24
Structure
of
Patch
Register
25
n
n+1
n+2
n+3
Description
If Byte 11 Bit [7] == 1, Byte 10 is the offset Bit [7:0] of Product string in EEPROM.
If Byte 11 Bit [7] == 0, Byte 10 is reserved.
If Byte 11 Bit [7] == 1, Byte 11 Bit [6:0] is the offset Bit [14:8] of Product string.
If Byte 11 Bit [7] == 0, Byte 11 Bit [6:0] is reserved.
Bit [7]:
1 —— There is Product string in EEPROM;
0 —— No Product string
If Byte 11 Bit [7] == 1, Byte 12 is the length of Product string.
If Byte 11 Bit [7] == 0, Byte 12 is reserved.
Reserved
If Byte 15 Bit [7] == 1, Byte 14 is the offset Bit [7:0] of Manufacturer string.
If Byte 15 Bit [7] == 0, Byte 14 is reserved.
If Byte 15 Bit [7] == 1, Byte 15 Bit [6:0] is the offset Bit [14:8] of Manufacturer
string.
If Byte 15 Bit [7] == 0, Byte 15 Bit [6:0] is reserved.
Bit [7]:
1 —— There is Manufacturer string in EEPROM;
0 —— No Manufacturer string
If Byte 15 Bit [7] == 1, Byte 16 is the length of Manufacturer string.
If Byte 15 Bit [7] == 0, Byte 16 is reserved.
Reserved
If Byte 19 Bit [7] == 1, Byte 18 is the offset Bit [7:0] of Serial Number.
If Byte 19 Bit [7] == 0, Byte 18 is reserved.
If Byte 19 Bit [7] == 1, Byte 19 Bit [6:0] is the offset Bit [14:8] of Serial Number.
If Byte 19 Bit [7] == 0, Byte 19 Bit [6:0] is reserved.
Bit [7]:
1 —— There is Serial Number in EEPROM;
0 —— No Serial Number
If Byte 19 Bit [7] == 1, Byte 20 is the length of Serial Number.
If Byte 19 Bit [7] == 0, Byte 20 is reserved.
Reserved
If Byte 23 Bit [7] == 1, Byte 22 is the offset Bit [7:0] of Microphone Array geometry
descriptor.
If Byte 23 Bit [7] == 0, Byte 22 is reserved.
If Byte 23 Bit [7] == 1, Byte 23 Bit [6:0] is the offset Bit [14:8] of Microphone Array
geometry descriptor.
If Byte 23 Bit [7] == 0, Byte 23 Bit [6:0] is reserved.
Bit [7]:
1 —— There is Microphone Array geometry descriptor in EEPROM;
0 —— No Microphone Array geometry descriptor
If Byte 23 Bit [7] == 1, Byte 24 is the length of Microphone Array geometry
descriptor.
If Byte 23 Bit [7] == 0, Byte 24 is reserved.
Reserved
Register Index Low Byte
Register Index High Byte
Register Patch State
Register Content


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17
8 Clock and Crystal Networks
8.1 External Clock Source or Crystal Networks
The VT1620A needs one external clock source or crystal networks:
y A 6-MHz clock (or crystal network) provides the fundamental input clock source for the VT1620A.
A PLL_48M module takes this 6-MHz clock input, and generates a 48-MHz clock output which is the
root of all VT1620A clocks. In this PLL_48M module, an Oscillator and a PLL are integrated together.
y There are two PLLs (PLL24576 and PLL112896) in the system that utilizes the 24-MHz clock source.
They use the 48-MHz clock output from PLL_48M divided by 2. The purpose of these two PLLs is to
provide clock source for the VT1620A Codec related circuitry to generate accurate clocks for all
kinds of popular Audio sample rates.
y PLL24576 generates the 245.76-MHz clock output, base on this clock, the bit clock and 128-fs over
sampling clock can be generated for 16-kHz, 48-kHz, 96-kHz, 192-kHz sample rate audio
recording.
y PLL112896 generates the 112.896-MHz clock output; base on this clock, the bit clock and 128-fs
over sampling clock can be generated for the 44.1-kHz sample rate audio recording.
y All the clocks for the rest functional blocks are generated from the 48-MHz clock.
y The VT1620A can also take the 24.576-MHz and 11.2896-MHz clock directly from the external
source. However, this is the backup solution in case there is any problem to generate these two
clocks internally.
The Strapping Option Bit [3] determines whether the source of the 6-MHz input clock is supplied by an
external clock source or by an external crystal network.
When the Strapping Option value is a one, then an external 6-MHz clock source should drive the XI signal
pin of the VT1620A, while the XO signal pin of the VT1620A should be left as No Connection. In such case,
the built-in OSC in PLL_48M module will be bypassed and stopped.
When the Strapping Option value is a zero, then the following external 6-MHz crystal network is
recommended to provide the 6-MHz clock source for the VT1620A:
VT1620A
PLL_48M
OSC
XI XO
C1 C2
C1: 12 pF
C2: 12 pF
Crystal: 6 MHz
Crystal
Figure 9 – VT1620A Clock and Crystal Networks


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18
8.2 Internal Clock Generation
The following Figure 10 illustrates the clocks generated in the system.
1
The divisors A to I are all even number clock divisors. They are software programmable. Together with
the clock gating control units, VT1620A clock generator module provides FW with methods to fully control
each clock and thus enable flexible system support for different applications.
BypassOSC
XO
OSC
6M
PLL
(X8)
XI
PLL_48M
OSCCLK_UNEN
CKGT
EXTCLK48M
EXTCKS
CKGT
OSCCLK
CLK48M
DIV
/J
DIV
/2
DIV
/A
CLK_SEL
DIV
/K
BUFCKS
CKGT
BUFCKS
CKGT
CKGT
CKGT
CKGT
CKGT
CLKBUFPLY
CLKBUFREC
CLKHD48M
CLKHD24M
CLKMCU
CLK48K
DIV
/B
DIV
/C
DIV
/D
CKGT
CKGT
CKGT
CLK1M
CLK1K
CLK6M
EXTCLKAUD
SEL112896
EXTAUDCKS
EXTSDMCKS
DIV EXTCLKSDM
/2 DIV CKGT
PLL24576
DIV /M
/E
DIV CKGT
/F
DIV
/L
EXTAUDCKS SEL24576 CLK_LOCK EXTSDMCKS
CKGT
CKGT
CLKREC512FS
PLL112896
DIV DIV CKGT CLKREC256FS
/G /H
DIV CKGT
/I CLKREC64FS
Figure 10 – VT1620A Clock Generator


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8.3 Clock Divisor Settings
Refer to the following Table 10 for VT1620A clock divisor settings.
1
19
Table 10 – Clock Divisor Settings
Divisor Clock Division Range
A 1, 2, 4, 6, …… 62
B 1, 2, 4, 6, …… 62
C 1, 2, 4, 6, …… 510
D 1, 2, 4, 6, …… 62
E 5, 10, 20, 30, …… 310
F 1, 2, 4, 6, …… 62
G 5, 10, 20, 30, …… 310
H 1, 2, 4, 6, …… 62
I 5,10,20,30,……310
J8
K 250
L 10
M 1, 2, 4, 6, …… 62
Adaptive Clock
No
No
No
No
Yes
No
No
No
No
Yes
No
No
No
Default Setting
4
48
256
8
10
4
10
2
8
8
250
10
2
Default Clock Frequency
12 MHz
1 MHz
3.9 kHz
6 MHz
24.576 MHz
6.144 MHz
24.576 MHz
12.288 MHz
3.072 MHz
48 MHz
48 kHz
12.288 MHz
12.288 MHz


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20
9 Electrical Specification
9.1 Absolute Maximum Ratings
Condition
Supply Voltage AVDD50, DVDD50.
Voltage Range Analog Input
Operating Temperature Range ,TA
Storage Temperature after Soldering
ESD (HBM)
MIN
-0.3 V
AGND-0.3 V
-25 °C
0 °C
2 kV
MAX
6V
AVDD + 0.3 V
+85 °C
+125 °C
9.2 Recommended Operating Conditions
Parameter
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Voltage
Digital Supply Voltage
Operating Temperature Range
Symbol
AVDD50.
DVDD50
AVDD, HPVDD,
DVDD33
DVDD20
TA
MIN
4.4
4.4
3.13
1.9
0
NOM
5
5
3.3
2.0
25
MAX
5.25
5.25
3.47
2.1
85
Unit
V
V
V
V
°C
9.3 Electrical Parameters
Parameter
Symbol Test Conditions MIN
Analog Inputs (MIC INPUT1, MIC INPUT2, to ADC out
Full Scale Input
Signal Level
(for ADC 0 dB Input
at 0 dB Gain)
VINFS
AVDD=HPVDD =
3.3V
Input Resistance
MIC INPUT1 to
ADC, MIC BOOST
Gain = 0 dB
MIC INPUT1 to
ADC, MICBOOST
Gain = +30 dB
Input Capacitance
Signal to Noise Ratio SNR
(A-weighted)
AVDD=HPVDD =
3.3 V
Dynamic Range
-60 dBFs
Total Harmonic
Distortion
THD
-1 dBFs Input,
AVDD=HPVDD =
3.3V
ADC Channel
Separation
1 kHz Signal
TYP
1.0
55
3.4
10
90
90
-80
94
MAX
92
92
Unit
V rms
kΩ
pF
dB
dB
dB
dB


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21
Parameter
Symbol Test Conditions MIN
TYP
MAX
Analog In to Analog Outputs (LOUT, ROUT)
0 dB Full Scale
Output Voltage
HPVDD/
3.3
Mute Attenuation
1 kHz, Full Scale
Signal
96
Channel Separation
Analog in
to Analog out
100
Signal to Noise Ratio SNR
(A-weighted)
AVDD=HPVDD =
3.3 V
97
Total Harmonic
Distortion
THD
AVDD=HPVDD =
3.3V
-91
DAC to Line-Out (L/ROUT with 10 k~ / 50 pF Load)
Signal to Noise Ratio SNR
(A-weighted)
AVDD=HPVDD =
3.3 V
95
Total Harmonic
Distortion
THD
AVDD=HPVDD = 55
3.3 V
-85
Channel Separation
10 kHz Signal
93
DAC to Headphone Output (LOUT/ROUT, Using Capacitors)
Output Power per
Channel
PO
Output power is highly correlated with THD.
Total Harmonic plus
Noise
THD+N
HPVDD=3.3 V,
RL=32~ ,
-3 dBFS Input
(FS=515 mV)
-85
HPVDD=3.3 V,
RL=16~ ,
-3 dBFS Input
(FS=334 mV)
-82
Signal to Noise Ratio SNR
(A-weighted)
HPVDD = 3.3 V
95
Channel Separation
10 kHz Signal
66
Analogue Reference Levels
USB Bus Power
VBUS
4.4 5
5.25
Middle Rail Reference VMID
Voltage
–3%
AVDD/H +3%
PVDD
Buffered Reference
Voltage
VREF
–3%
AVDD/H +3%
PVDD
Microphone Bias
Bias Voltage
VMICBIAS 3 mA Load
Current
–5%
0.9×AV + 5%
DD
Bias Current Source IMICBIAS
3
Output Noise Voltage Vn
1 k to 20 kHz
15
Digital Input / Output
Input HIGH Level
VIH
0.7×DV
DD33
Input LOW Level
VIL
0.3×DVDD33
Output HIGH Level VOH
IOL=1 mA
0.9×DV
DD33
Output LOW Level
VOL
IOH-1 mA
0.1×DVDD33
Unit
Vrms
dB
dB
dB
dB
dB
dB
dB
dB
dB
V
V
V
V
mA
nV/~Hz
V
V
V
V


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10 Mechanical Specification
22
Figure 11 – VT1620A LQFP-48 Package (7 mm×7 mm)


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Copyright © 2009-2010 VIA Technologies Incorporated. All Rights Reserved. No part of this document
may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any
language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or
otherwise without the prior written permission of VIA Technologies Incorporated. The material in this
document is for information only and is subject to change without notice. VIA Technologies Incorporated
reserves the right to make changes in the product design without reservation and without notice to its
users.
All trademarks are the properties of their respective owners.
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies, Inc.
VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the
products described in this document. The information provided by this document is believed to be
accurate and reliable as of the publication date of this document. However, VIA Technologies assumes no
responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility
for the use or misuse of the information in this document and for any patent infringements that may arise
from the use of this document. The information and product specifications within this document are
subject to change at any time, without notice and without obligation to notify any person of such change.
VIA Technologies Incorporated
Taiwan Office:
1st Floor, No. 531
Chung-Cheng Road, Hsin-Tien
Taipei, Taiwan
Tel (886-2) 2218-5452
Fax (886-2) 2218-5453
URL http://www.via.com.tw
6
VIA Technologies Incorporated
USA Office:
940 Mission Court
Fremont, CA 94539
USA
Tel (510) 683-3300
Fax (510) 683-3301 or (510) 687-4654
URL http://www.viatech.com
6




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