MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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t
High Slew Rate, Wide
Bandwidth, JFET Input
Operational Amplifiers
These devices are a new generation of high speed JFET input monolithic
operational amplifiers. Innovative design concepts along with JFET
technology provide wide gain bandwidth product and high slew rate.
Well–matched JFET input devices and advanced trim techniques ensure low
input offset errors and bias currents. The all NPN output stage features large
output voltage swing, no deadband crossover distortion, high capacitive
drive capability, excellent phase and gain margins, low open loop output
impedance, and symmetrical source/sink AC frequency response.
This series of devices is available in fully compensated or
decompensated (AVCL2) and is specified over a commercial temperature
range. They are pin compatible with existing Industry standard operational
amplifiers, and allow the designer to easily upgrade the performance of
existing designs.
Wide Gain Bandwidth: 8.0 MHz for Fully Compensated Devices
Wide Gain Bandwidth: 16 MHz for Decompensated Devices
High Slew Rate: 25 V/µs for Fully Compensated Devices
High Slew Rate: 50 V/µs for Decompensated Devices
High Input Impedance: 1012
Input Offset Voltage: 0.5 mV Maximum (Single Amplifier)
Large Output Voltage Swing: –14.7 V to +14 V for
Large Output Voltage Swing: VCC/VEE = ±15 V
Low Open Loop Output Impedance: 30 @ 1.0 MHz
Low THD Distortion: 0.01%
Excellent Phase/Gain Margins: 55°/7.6 dB for Fully Compensated
Devices
Op Amp
Function
Single
Dual
Quad
ORDERING INFORMATION
Fully
Compen-
sated
AVCL2
Compensated
Operating
Temperature
Range
MC34081BD MC34080BD
MC34081BP
MC34082P
MC34080BP
MC34083BP
TA = 0° to +70°C
MC34084DW MC34085BDW
MC34084P MC34085BP
TA = 0° to +70°C
Package
SO–8
Plastic DIP
Plastic DIP
SO–16L
Plastic DIP
Output 1 1
2
Inputs 1
3+1
VCC 4
5
Inputs 2
6
+
–2
Output 2 7
NC 8
16 Output 4
4+
15
14
Inputs 4
13 VEE
+ 12
3 – 11
Inputs 3
10 Output 3
9 NC
PIN CONNECTIONS
Order this document by MC34080/D
MC34080
thru
MC34085
HIGH PERFORMANCE
JFET INPUT
OPERATIONAL AMPLIFIERS
8
1
P SUFFIX
PLASTIC PACKAGE
CASE 626
8
1
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
PIN CONNECTIONS
Offset Null 1
8 NC
Inv. Input 2 –
Noninv. Input 3 +
7 VCC
6 Output
VEE 4
5 Offset Null
(Single, Top View)
Output 1 1
2
Inputs 1
3+
VEE 4
8 VCC
7 Output 2
6
+5
Inputs 2
(Dual, Top View)
14
1
P SUFFIX
PLASTIC PACKAGE
CASE 646
16
1
DW SUFFIX
PLASTIC PACKAGE
CASE 751G
(SO–16L)
Output 1 1
2
Inputs 1
3+1
VCC 4
Inputs 2 5 +
6–2
Output 2 7
14 Output 4
13
4 + 12
Inputs 4
11 VEE
+ 10
3– 9
Inputs 3
8 Output 3
(Quad, Top View)
MOTOROLA ANALOG IC DEVICE DATA
© Motorola, Inc. 1996
Rev 0
1


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
MAXIMUM RATINGS
Rating
Symbol
Value
Supply Voltage (from VCC to VEE)
VS +44
Input Differential Voltage Range
VIDR
(Note 1)
Input Voltage Range
VIR (Note 1)
Output Short Circuit Duration (Note 2)
tSC Indefinite
Operating Ambient Temperature Range
TA 0 to +70
Operating Junction Temperature
TJ +125
Storage Temperature Range
Tstg – 65 to +165
NOTES: 1. Either or both input voltages must not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature
(TJ) is not exceeded.
Unit
V
V
V
sec
°C
°C
°C
Representative Schematic Diagram
(Each Amplifier)
200 µA
50 µA
850 µA
Q1
VCC
Inputs
+
J1 J2
5.0
+ CC pF
20
Q8 CF pF
+
Q5
Q2
R3 R4
Q9 Q10 1.0 k 1.0 k
D3
500 R6
50 µA
500
Q11
D4
100 µA
1
Null Adjust
5 RM
(MC34080, 081)*
*Pins 1 & 5 (MC34080,081) should not be directly grounded or connected to VCC.
D1 R1
240
D2
Q6
18
RSC 700
R2
Output
Q7
CM
3.0
pF
Q3 Q4
300 µA
R7
66 k
VEE
2 MOTOROLA ANALOG IC DEVICE DATA


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = – 15 V, TA = Tlow to Thigh [Note 3], unless otherwise noted.)
Characteristics
Symbol Min Typ Max
Input Offset Voltage (Note 4)
Single
TA = +25°C
TA = 0° to +70°C (MC34080B, MC34081B)
Dual
TA = +25°C
TA = 0° to +70°C (MC34082, MC34083)
Quad
TA = +25°C
TA = 0° to +70°C (MC34084, MC34085)
Average Temperature Coefficient of Offset Voltage
Input Bias Current (VCM = 0 Note 5)
TA = +25°C
TA = 0° to +70°C
Input Offset Current (VCM = 0 Note 5)
TA = +25°C
TA = 0° to +70°C
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 k)
TA = +25°C
TA = Tlow to Thigh
Output Voltage Swing
RL = 2.0 k, TA = +25°C
RL = 10 k, TA = +25°C
RL = 10 k, TA = Tlow to Thigh
RL = 2.0 k, TA = +25°C
RL = 10 k, TA = +25°C
RL = 10 k, TA = Tlow to Thigh
Output Short Circuit Current (TA = +25°C)
Input Overdrive = 1.0 V, Output to Ground
Source
Sink
VIO
VIO/T
IIB
IIO
AVOL
VOH
VOL
ISC
— 0.5 2.0
— — 4.0
— 1.0 3.0
— — 5.0
— 6.0 12
— — 14
— 10 —
— 0.06 0.2
— — 4.0
— 0.02 0.1
— — 2.0
25 80 —
15 — —
13.2 13.7
13.4 13.9
13.4 —
— –14.1 –13.5
— –14.7 –14.1
— — –14.0
20 31 —
20 28 —
Input Common Mode Voltage Range
TA = +25°C
VICR
(VEE +4.0) to
(VCC – 2.0)
Common Mode Rejection Ratio (RS 10 k, TA = +25°C)
CMRR
70 90
Power Supply Rejection Ratio (RS = 100 , TA = 25°C)
PSRR
70 86 —
Power Supply Current
Single
TA = +25°C
TA = Tlow to Thigh
Dual
TA = +25°C
TA = Tlow to Thigh
Quad
TA = +25°C
TA = Tlow to Thigh
ID
— 2.5 3.4
— — 4.2
— 4.9 6.0
— — 7.5
— 9.7 11
— — 13
NOTES: (continued)
3. Tlow = 0°C for MC34080B
0°C for MC34081B
Thigh = +70°C for MC34080B
+70°C for MC34081B
0°C for MC34084
+70°C for MC34084
0°C for MC34085
+70°C for MC34085
4. See application information for typical changes in input offset voltage due to solderability and temperature cycling.
5. Limits at TA = +25°C are guaranteed by high temperature (Thigh) testing.
Unit
mV
µV/°C
nA
nA
V/mV
V
mA
V
dB
dB
mA
MOTOROLA ANALOG IC DEVICE DATA
3


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = – 15 V, TA = +25°C, unless otherwise noted.)
Characteristics
Symbol Min Typ
Max
Unit
Slew Rate (Vin = –10 V to +10 V, RL = 2.0 k, CL = 100 pF)
Compensated AV = +1.0
AV = –1.0
Decompensated AV = +2.0
AV = –1.0
Settling Time (10 V Step, AV = –1.0)
To 0.10% (±1/2 LSB of 9–Bits)
To 0.01% (±1/2 LSB of 12–Bits)
Gain Bandwidth Product (f = 200 kHz)
Compensated
Decompensated
SR
ts
GBW
20 25 —
— 30 —
35 50 —
— 50 —
— 0.72 —
— 1.6 —
6.0 8.0
12 16
V/µs
µs
MHz
Power Bandwidth (RL = 2.0 k, VO = 20 Vpp, THD = 5.0%)
Compensated AV = +1.0
Decompensated AV = – 1.0
Phase Margin (Compensated)
RL = 2.0 k
RL = 2.0 k, CL = 100 pF
BWp
φm
— 400 —
— 800 —
kHz
De-
— 55 — grees
— 39 —
Gain Margin (Compensated)
RL = 2.0 k
RL = 2.0 k, CL = 100 pF
Equivalent Input Noise Voltage
RS = 100 , f = 1.0 kHz
Am dB
— 7.6 —
— 4.5 —
en — 30 — nV/Hz
Equivalent Input Noise Current (f = 1.0 kHz)
In — 0.01 — pA/ Hz
Input Capacitance
Input Resistance
Total Harmonic Distortion
AV = +10, RL = 2.0 k, 2.0 VO 20 Vpp, f = 10 kHz
Ci
ri
THD
— 5.0 —
— 1012 —
— 0.05 —
pF
%
Channel Separation (f = 10 kHz)
— 120 —
dB
Open Loop Output Impedance (f = 1.0 MHz)
Zo
— 35 —
Figure 1. Input Common Mode Voltage Range
versus Temperature
0
VCC/VEE = ±3.0 V to ±22 V
VIO = 5.0 mA
–1.0
VCC
3.0
2.0
1.0
0
–55
VEE
–25 0 25 50 75 100
TA, AMBIENT TEMPERATURE (°C)
125
Figure 2. Input Bias Current
versus Temperature
100 k
10 k
VCC/VEE = ±15 V
VCM = 0 V
1.0 k
100
10
1.0
–55 –25 0 25 50 75 100
TA, AMBIENT TEMPERATURE (°C)
125
4 MOTOROLA ANALOG IC DEVICE DATA


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
Figure 3. Input Bias Current versus
Input Common Mode Voltage
140
120
VCC/VEE = ±15 V
TA = 25°C
100
80
60
40
20
–12
–8.0 –4.0 0 4.0 8.0
VIC, INPUT COMMON MODE VOLTAGE (V)
12
Figure 4. Output Voltage Swing
versus Supply Voltage
50
40
RL Connected to Ground
TA = 25°C
30
RL = 10 k
20
RL = 2.0 k
10
0
0 ±5.0 ±10 ±15 ±20
VCC |VEE|, SUPPLY VOLTAGE (V)
±25
Figure 5. Output Saturation versus
Load Current
0
VCC
–1.0
Source
–2.0
VCC/VEE = +15 V to +22 V
TA = 25°C
–3.0
1.0 Sink
VEE
0
0 4.0 8.0 12
IL, LOAD CURRENT (±mA)
16
Figure 6. Output Saturation vesus
Load Resistance to Ground
0
VCC
–2.0
–4.0
VCC/VEE = ±15 V
TA = 25°C
2.0
1.0
0
300
VEE
3.0 k 30 k
RL, LOAD RESISTANCE TO GROUND ()
300 k
Figure 7. Output Saturation versus
Load Resistance to VCC
0
VCC
–0.4
–0.8
2.0
1.0
0
300
VCC/VEE = +15 V
RL to VCC
TA = 25°C
VEE
3.0 k 30 k
RL, LOAD RESISTANCE TO VCC ()
300 k
Figure 8. Output Short Circuit Current
versus Temperature
40
30 Source
Sink
20
10
0
–55
VCC/VEE = ±15 V
RL 0.1
Vin = 1.0 V
–25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
MOTOROLA ANALOG IC DEVICE DATA
5


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
Figure 9. Output Impedance versus Frequency
80
VCC/VEE = ±15 V
VCM = 0
60
VO = 0
IO = ±0.5 mA
TA = 25°C
Compensated
40 Units Only
Figure 10. Output Impedance versus Frequency
80
VCC/VEE = ±15 V
VCM = 0
60
VO = 0
IO = ±0.5 mA
TA = 25°C
Decompensated
40 Units Only
20
0
1.0 k
AV = 1000
AV = 100
AV = 1.0
AV = 10
10 k 100 k 1.0 M
f, FREQUENCY (Hz)
10 M
20
0
1.0 k
AV = 1000
10 k
AV = 100 AV = 10
100 k
1.0 M
f, FREQUENCY (Hz)
AV = 2.0
10 M
28
24
20
16
12
8.0
4.0
0
10 k
Figure 11. Output Voltage Swing
versus Frequency
Compensated
Units AV = +1.0
VCC/VEE = ±15 V
RL = 2.0 k
THD = 1.0%
TA = 25°C
Decompensated
Units AV = –1.0
100 k
1.0 M
f, FREQUENCY (Hz)
10 M
Figure 12. Output Distortion versus Frequency
0.5
AV = 1000
0.4
VCC/VEE = ±15 V
VO = 2.0 Vpp
0.3 RL = 2.0 k
TA = 25°C
*Compensated
0.2 Units Only
AV = 100
0.1
AV = 10
0 AV = 1.0*
10
100
1.0 k 10 k
100 k
f, FREQUENCY (Hz)
Figure 13. Open Loop Voltage Gain
versus Temperature
1.08 VCC/VEE = ±15 V
VO = –10 V to +10 V
1.04
RL = 10 k
f 10 Hz
1.00
0.96
0.92
–55
–25 0 25 50 75
TA, AMBIENT TEMPERATURE (°C)
100
125
6 MOTOROLA ANALOG IC DEVICE DATA


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
Figure 14. Open Loop Voltage Gain and
Phase versus Frequency
100
80
60 Phase
VCC/VEE = ±15 V
VO = 0 V
RL = 2.0 k
TA = 25°C
0
45
Gain
90
40
135
20
Solid Line Curves — Compensated Units
Dashed Line Curves — Decompensated Units
180
0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
f, FREQUENCY (Hz)
Figure 15. Open Loop Voltage Gain and
Phase versus Frequency
20
10
0 VCC/VEE = ±15 V
VO = 0 V
TA = 25°C
–10
Phase
Margin
= 54°
–20 1 — Gain, RL = 2.0 k
2 — Gain, RL = 2.0 k, CL = 100 pF
–30 3 — Phase, RL = 2.0 k
4 — Phase, RL = 2.0 k, CL = 100 pF
–40 Compensated Units Only
1.0 2.0 3.0 5.0 7.0 10
4
f, FREQUENCY (Hz)
Gain
Margin
= 7.6 dB
1
2
3
20 30
100
120
140
160
180
200
50
Figure 16. Open Loop Voltage Gain and
Phase versus Frequency
20
10
VCC/VEE = ±15 V
0 VO = 0 V
TA = 25°C
–10
Phase
Margin
= 43°
–20 1 — Gain, RL = 2.0 k
2 — Gain, RL = 2.0 k, CL = 100 pF
–30 3 — Phase, RL = 2.0 k
4 — Phase, RL = 2.0 k, CL = 100 pF
–40 Decompensated Units Only
1.0 2.0 3.0 5.0 7.0 10
f, FREQUENCY (Hz)
Gain
Margin
= 5.5 dB
20 30
100
120
140
160
180
200
50
Figure 17. Normalized Gain Bandwidth
Product versus Temperature
1.20
1.10 VCC/VEE = ±15 V
RL = 2.0 k
1.00
0.90
0.80
–55
–25 0
25 50 75
TA, AMBIENT TEMPERATURE (°C)
100
125
Figure 18. Percent Overshoot versus
Load Capacitance
100
Decompensated
80 Units AV = +2.0
60
Compensated
40 Units AV = +1.0
VCC/VEE = ±15 V
20
RL = 2.0 k
VO = 100 mVpp
VO = –10 V to +10 V
0 TA = 25°C
10 100 1.0k
CL, LOAD CAPACITANCE (pF)
Figure 19. Phase Margin versus
Load Capacitance
70
60
Compensated
Units AV = +1.0
50
40
RVCC/VEE = ±15 V
RL = 2.0 k to
VO = 100 mVpp
VO = –10 V to +10 V
TA = 25°C
30
20
Decompensated
10 Units AV = +2.0
010 100 1.0k
CL, LOAD CAPACITANCE (pF)
MOTOROLA ANALOG IC DEVICE DATA
7


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
Figure 20. Gain Margin versus Load Capacitance
10
8.0
Compensated
Units AV = +1.0
VCC/VEE = ±15 V
RL = 2.0 k to
VO = 100 mVpp
VO = –10 V to +10 V
TA = 25°C
6.0
4.0
Decompensated
2.0 Units AV = +2.0
0
10 100 10 k
CL, LOAD CAPACITANCE (pF)
Figure 21. Phase Margin versus Temperature
60
50 Solid Line Curves–Compensated Units AV = +1.0
CL = 10 pF Dashed Line Curves–Decompensated Units AV = +2.0
40
30 CL = 100 pF
20
CL = 360 pF
10
0
–55
VCC/VEE = ±15 V
CL = 200 pF RL = 2.0 k to
–25 0
25 50
VO = 100 mVpp
VO = –10 V to +10 V
75 100 125
TA, AMBIENT TEMPERATURE (°C)
Figure 22. Gain Margin versus Temperature
10
Solid Line Curves–Compensated Units AV = +1.0
Dashed Line Curves–Decompensated Units AV = +2.0
8.0
6.0 CL = 10 pF VCC/VEE = ±15 V VO = 100 mVpp
RL = 2.0 k to
VO = –10 V to +10 V
4.0
2.0
0
–55
CL = 100 pF
CL = 200 pF
CL = 360 pF
–25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
Figure 23. Normalized Slew Rate
versus Temperature
1.40
VCC/VEE = ±15 V
AV = +1.0 for Compensated Units
1.20 AV = –1.0 for Decompensated Units
RL = 2.0 k
CL = 100 pF
1.00 VO = –10 V to +10 V
0.80
0.60
–55 –25
0
25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
8 MOTOROLA ANALOG IC DEVICE DATA


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
MC34084 Transient Response
AV = +1.0, RL = 2.0 k, VCC/VEE = ±15 V, TA = 25°C
Figure 24. Small Signal
CL = 10 pF
Figure 25. Large Signal
CL = 100 pF
0
0
0.2 µs/Div
0.5 µs/Div
MC34085 Transient Response
AV = +2.0, RL = 2.0 k, VCC/VEE = ±15 V, TA = 25°C
Figure 26. Small Signal
CL = 10 pF
Figure 27. Large Signal
CL = 100 pF
00
0.2 µs/Div
0.5 µs/Div
MOTOROLA ANALOG IC DEVICE DATA
9


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
Figure 28. Common Mode Rejection Ratio
versus Frequency
100
TA = 25°C
80 TA = 125°C
TA = –55°C
VCC/VEE = ±15 V
VS = 3.0 V
VO = 0 V
60
40 VCC ± VCC
+
20
VO
Compensated Units AV = +1.0
0 VEE ± VEE
Decompensated Units AV = +2.0
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
Figure 29. Power Supply Rejection Ratio
versus Frequency
120
VCC/VEE = ±15 V
100 VS = 3.0 V
VO = 0 V
80 TA = 25°C
60
VCC ± VCC
Positive
Supply
40 +
VO
20 Negative
VEE ± VEE
Supply
0
0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
Figure 30. Power Supply Rejection Ratio
versus Temperature
110
100
90
80
70
–55
Negative
Supply
VCC/VEE = ±15 V
VS = 3.0 V
VO = 0 V
f 10 Hz
VCC ± VCC
+
VO
Positive
Supply
VEE ± VEE
Compensated Units AV = +1.0
Decompensated Units AV = +2.0
–25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
Figure 31. Normalized Supply Current
versus Supply Voltage
1.20
TA = 125°C
1.10
1.00
0.90
0.80
0.70
0
TA = 25°C
Supply Current
Normalized to
VCC/VEE = ±15 V, TA = 25°C
RL =
VO = 0
±5.0 ±10 ±15
VS, SUPPLY VOLTAGE (V)
TA = –55°C
±20 ±25
Figure 32. Channel Separation versus Frequency
120
100
80
60
40
VCC/VEE = ±15 V
20 TA = 25°C
0
10 k 100 k
1.0 M
f, FREQUENCY (Hz)
10 M
100
80
60
40
20
0
10
Figure 33. Spectral Noise Density
VCC/VEE = ±15 V
VCM = 0
TA = 25°C
100 1.0 k
10 k
f, FREQUENCY (Hz)
100 k
10 MOTOROLA ANALOG IC DEVICE DATA


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
APPLICATIONS INFORMATION
The bandwidth and slew rate of the MC34080 series is
nearly double that of currently available general purpose
JFET op–amps. This improvement in AC performance is due
to the P–channel JFET differential input stage driving a
compensated miller integration amplifier in conjunction with
an all NPN output stage.
The all NPN output stage offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. With a 10 k load resistance, the op amp can typically
swing within 1.0 V of the positive rail (VCC), and within 0.3 V
of the negative rail (VEE), providing a 28.7 p–p swing from
±15 V supplies. This large output swing becomes most
noticeable at lower supply voltages. If the load resistance is
referenced to VCC instead of ground, the maximum possible
output swing can be achieved for a given supply voltage. For
light load currents, the load resistance will pull the output to
VCC during the positive swing and the NPN output transistor
will pull the output very near VEE during the negative swing.
The load resistance value should be much less than that of
the feedback resistance to maximize pull–up capability.
The all NPN transistor output stage is also inherently
fast, contributing to the operation amplifier’s high
gain–bandwidth product and fast settling time. The
associated high frequency output impedance is 50 (typical)
at 8.0 MHz. This allows driving capacitive loads from 0 pF to
300 pF without oscillations over the military temperature
range, and over the full range of output swing. The 55°C
phase margin and 7.6 dB gain margin as well as the general
gain and phase characteristics are virtually independent of
the sink/source output swing conditions. The high frequency
characteristics of the MC34080 series is especially useful for
active filter applications.
The common mode input range is from 2.0 V below the
positive rail (VCC) to 4.0 V above the negative rail (VEE). The
amplifier remains active if the inputs are biased at the positive
rail. This may be useful for some applications in that single
supply operation is possible with a single negative supply.
However, a degradation of offset voltage and voltage gain
may result.
Phase reversal does not occur if either the inverting or
noninverting input (or both) exceeds the positive common
mode limit. If either input (or both) exceeds the negative
common mode limit, the output will be in the high state. The
input stage also allows a differential up to ±44 V, provided the
maximum input voltage range is not exceeded. The supply
voltage operating range is from ±5.0 V to ±22 V.
For optimum frequency performance and stability, careful
component placement and printed circuit board layout should
be exercised. For example, long unshielded input or output
leads may result in unwanted input–output coupling. In order
to reduce the input capacitance, resistors connected to the
input pins should be physically close to these pins. This not
only minimizes the input pole for optimum frequency
response, but also minimizes extraneous “pickup” at
this node.
Supply decoupling with adequate capacitance close to the
supply pin is also important, particularly over temperature,
since many types of decoupling capacitors exhibit large
impedance changes over temperature.
Primarily due to the JFET inputs of the op amp, the input
offset voltage may change due to temperature cycling and
board soldering. After 20 temperature cycles (– 55° to
165°C), the typical standard deviation for input offset voltage
is 559 µV in the plastic packages. With respect to board
soldering (260°C, 10 seconds), the typical standard deviation
for input offset voltage is 525 µV in the plastic package.
Socketed devices should be used over a minimal
temperature range for optimum input offset voltage
performance.
Figure 34. Offset Nulling Circuit
VCC
3+ 7
6
2– 5
1
4
5.0 k
VEE
MOTOROLA ANALOG IC DEVICE DATA
11


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
NOTE 2
85
14
F
–A–
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
–B–
L
–T–
SEATING
PLANE
H
C
J
N
DK
M
G
0.13 (0.005) M T A M B M
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
G 2.54 BSC
0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
L 7.62 BSC
0.300 BSC
M ––– 10_ ––– 10_
N 0.76 1.01 0.030 0.040
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE R
AD
C
8
E
1
5
H
4
0.25 M B M
Be
C
h X 45 _
q
A
SEATING
PLANE
A1 B
0.10
0.25 M C B S A S
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS
DIM MIN MAX
A 1.35 1.75
A1 0.10 0.25
B 0.35 0.49
C 0.18 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 BSC
H 5.80 6.20
h 0.25 0.50
L 0.40 1.25
q 0_ 7_
12 MOTOROLA ANALOG IC DEVICE DATA


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
14
1
A
F
HG
8
B
7
C
N
SEATING
PLANE
D
K
L
J
M
–A–
16 9
DW SUFFIX
PLASTIC PACKAGE
CASE 751G–02
(SO–16L)
ISSUE A
–B– 8X P
0.010 (0.25) M B M
18
16X D
0.010 (0.25) M T A S B S
J
F
14X G
C
–T–
K
SEATING
PLANE
R X 45_
M
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC
2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC
7.62 BSC
M 0_ 10_ 0_ 10_
N 0.015 0.039 0.39 1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 10.15 10.45 0.400 0.411
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC
0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
MOTOROLA ANALOG IC DEVICE DATA
13


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
NOTES
14 MOTOROLA ANALOG IC DEVICE DATA


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
NOTES
MOTOROLA ANALOG IC DEVICE DATA
15


MC34085BDW (Motorola)
HIGH SLEW RATE WIDE BANDWIDTH JFET INPUT OPERATIONAL AMPLIFIERS

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MC34080 thru MC34085
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
16
MOTOROLA ANALOG IC DEVICE DATA
*MC34080/MC3D408*0/D




MC34085BDW.pdf
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