ST72325J6 (STMicroelectronics)
8-bit MCU

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ST72325xx
8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS,
5 timers, SPI, SCI, I2C interface
Features
Memories
– 16K to 60K dual voltage High Density Flash
(HDFlash) or up to 32K ROM with read-out
protection capability. In-Application Program-
ming and In-Circuit Programming for HDFlash
devices
– 512 to 2048 bytes RAM
– HDFlash endurance: 100 cycles, data reten-
tion: 40 years at 85°C
Clock, reset and supply management
– Enhanced low voltage supervisor (LVD) for
main supply and auxiliary voltage detector
(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator os-
cillators, internal RC oscillator and bypass for
external clock
– PLL for 2x frequency multiplication
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
– Clock Security System
Interrupt management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– Top Level Interrupt (TLI) pin on 64-pin devices
– 9/6 external interrupt lines (on 4 vectors)
Up to 48 I/O ports
– 48/36/32/24 multifunctional bidirectional I/O
lines
– 34/26/22/17 alternate function lines
– 16/13/12/10 high sink outputs
5 timers
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
LQFP64
10 x 10
LQFP44 LQFP48 LQFP32
10 x 10 7 x 7
7x7
LQFP64
14 x 14
SDIP42
600 mil
SDIP32
400 mil
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and pulse generator modes
– 8-bit PWM Auto-reload timer with: 2 input cap-
tures, 4 PWM outputs, output compare and
time base interrupt, external clock with event
detector
3 Communication interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
– I2C multimaster interface
1 Analog peripheral (low current coupling)
– 10-bit ADC with up to 16 robust input ports
Instruction set
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
Development tools
– Full hardware/software development package
– DM (Debug module)
Table 1. Device summary
Features
ST72325S4 /
ST72325J4 / ST72325K4
ST72325S6 /
ST72325J6 / ST72325K6
ST72325R9 /
ST72325J7
ST72325AR9 /
ST72325C9 /ST72325J9
Program memory - bytes
Flash/ROM 16K
Flash/ROM 32K
Flash 48K
Flash 60K
RAM (stack) - bytes
512 (256)
1024(256)
1536 (256)
2048(256)
Operating Voltage
3.8V to 5.5V
Temp. Range
up to -40°C to +125°C
Package
LQFP48(S), LQFP44/SDIP42 (J), LQFP48(S) , LQFP44/ SDIP42 (J),
LQFP32/DIP32 (K)
LQFP32/DIP32 (K)
LQFP44 (J)
LQFP64 14x14(R), LQFP64
10x10(AR), LQFP48(C),
LQFP44 (J)
October 2008
Rev 4
1/197
1


ST72325J6 (STMicroelectronics)
8-bit MCU

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Click to Download PDF File for PC

Table of Contents
1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 43
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 9. 7. . 45
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2/197
1


ST72325J6 (STMicroelectronics)
8-bit MCU

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Table of Contents
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . . 61
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.4.6 Summary of Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Table of Contents
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.5.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.5.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 9. 7. 142
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 145
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.3.4 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.4.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.5.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 156
12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . 158
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.10.1 8-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.12.1 Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.12.2 General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.12.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
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13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
14 ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 181
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 183
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.3.4 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.1 ALL DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.1.1 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
15.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . 193
15.1.4 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.5 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.7 I2C Multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
15.1.8 Pull-up always active on PE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
15.1.9 ADC accuracy 16/32K Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
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ST72325xx
1 DESCRIPTION
The ST72F325 Flash and ST72325 ROM devices
are members of the ST7 microcontroller family de-
signed for mid-range applications.
They are derivatives of the ST72321 and ST72324
devices, with enhanced characteristics and robust
Clock Security System.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set and are available with Flash or ROM pro-
gram memory. The ST7 family architecture offers
both power and flexibility to software developers,
enabling the design of highly efficient and compact
application code.
The on-chip peripherals include an A/D converter,
a PWM Autoreload timer, 2 general purpose tim-
ers, I2C bus, SPI interface and an SCI interface.
For power economy, microcontroller can switch
dynamically into WAIT, SLOW, ACTIVE-HALT or
Figure 1. Device Block Diagram
HALT mode when the application is in idle or
stand-by state.
Typical applications are consumer, home, office
and industrial products.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
Main Differences with ST72321:
– LQFP48 and LQFP32 packages
– Clock Security System
– Internal RC, Readout protection, LVD and PLL
without limitations
– Negative current injection not allowed on I/O port
PB0 (instead of PC6).
– External interrupts have Exit from Active Halt
mode capability.
RESET
VPP
TLI
VSS
VDD
EVD
OSC1
OSC2
8-BIT CORE
ALU
CONTROL
LVD
AVD
OSC
MCC/RTC/BEEP
PROGRAM
MEMORY
(16K - 60K Bytes1))
RAM
(512 - 2048 Bytes1))
WATCHDOG
DEBUG MODULE
I2C
PF7:0
(8 bits on AR devices)
(6 bits on C/J devices)
(5 bits on K devices)
PORT F
TIMER A
BEEP
PORT A
PORT B
PWM ART
PE7:0
(8 bits on AR devices)
(2 bits on C/J/K devices)
PORT E
SCI
PORT C
TIMER B
PD7:0
(8 bits on AR devices)
(6 bits on C/J devices)
(2 bits on K devices)
VAREF
VSSA
PORT D
10-BIT ADC
SPI
1) ROM devices have up to 32 Kbytes of program memory and up to 1 Kbyte of RAM.
PA7:0
(8 bits on AR devices)
(5 bits on C/J devices)
(4 bits on K devices)
PB7:0
(8 bits on AR devices)
(5 bits on C/J devices)
(3 bits on K devices)
PC7:0
(8 bits)
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ST72325xx
2 PIN DESCRIPTION
Figure 2. 64-Pin LQFP 14x14 and 10x10 Package Pinout
(HS) PE4
(HS) PE5
(HS) PE6
(HS) PE7
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / (HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4
45
ei0
5 44
6
7 ei2
43
42
8 41
9 40
10
11 ei3
39
38
12 37
13 36
14 35
15 ei1 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1
VDD_1
PA3 (HS)
PA2
PA1
PA0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
VSS_0
VDD_0
(HS) 20mA high sink capability
eix associated external interrupt vector
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Figure 3. 48-Pin LQFP 7x7 Device Pinout
ST72325xx
PE2
(HS) PE4
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / (HS) PB4
ARTIC1 / PB5
AIN0 / PD0
AIN1 / PD1
AIN3 / PD2
AIN4 / PD3
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3
4 ei2
34
33
5 32
6 ei3
ei0 31
7 30
8 29
9
10
11 ei1
12
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
VSS_1
VDD_1
PA3 (HS)
PA2
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
Legend
= Pin not connected in ST72325S devices
(HS) 20mA high sink capability
eix associated external interrupt vector
Caution: 48-pin ‘C’ devices have unbonded pins that require software initialization. Refer
to Note 4 on page 16 for details on initializing the I/O registers for these devices.
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ST72325xx
Figure 4. 44/42-Pin LQFP Package Pinouts
RDI / PE1
PB0
PB1
PB2
PB3
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3
4 ei2
ei0 31
30
5 29
6 ei3
28
7 27
8 26
9 25
10 ei1
24
11 23
12 13 14 15 16 17 18 19 20 21 22
VSS_1
VDD_1
PA3 (HS)
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
10/197
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
AIN5 / PD5
VAREF
VSSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
(HS) PF2
AIN10 / OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
AIN13 / OCMP1_B / PC1
ICAP2_B/ (HS) PC2
ICAP1_B / (HS) PC3
ICCDATA / MISO / PC4
AIN14 / MOSI / PC5
1 ei3
2
3
4
5
6
7
8
9
10
11 ei1
12
13
14
15
16
17
18
19
20
21
42
41
ei2 40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
ei0 24
23
22
PB3
PB2
PB1
PB0
PE1 / RDI
PE0 / TDO
VDD_2
OSC1
OSC2
VSS_2
RESET
VPP / ICCSEL
PA7 (HS) / SCLI
PA6 (HS) / SDAI
PA5 (HS)
PA4 (HS)
VSS_1
VDD_1
PA3 (HS)
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
(HS) 20mA high sink capability
eix associated external interrupt vector


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Figure 5. 32-Pin LQFP/DIP Package Pinouts
ST72325xx
VAREF
VSSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
32 31 30 29 28 27 26 25
1
ei3 ei2
2
24
23
3
ei1
4
22
21
5 20
6 19
7 18
8 ei0 17
9 10 11 12 13 14 15 16
OSC1
OSC2
VSS_2
RESET
VPP / ICCSEL
PA7 (HS)/SCLI
PA6 (HS) / SDAI
PA4 (HS)
(HS) PB4
AIN0 / PD0
AIN1 / PD1
VAREF
VSSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
AIN13 / OCMP1_B / PC1
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3
ICCDATA/ MISO / PC4
AIN14 / MOSI / PC5
1 ei3
2
3
4
5
6
ei1
7
8
9
10
11
12
13
14
15
16
32
ei2
31
30
29
28
27
26
25
24
23
22
21
20
ei0 19
18
17
PB3
PB0
PE1 / RDI
PE0 / TDO
VDD_2
OSC1
OSC2
VSS_2
RESET
VPP / ICCSEL
PA7 (HS) / SCLI
PA6 (HS) / SDAI
PA4 (HS)
PA3 (HS)
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
(HS) 20mA high sink capability
eix associated external interrupt vector
11/197


ST72325J6 (STMicroelectronics)
8-bit MCU

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ST72325xx
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 142.
Legend / Abbreviations for Table 2 and Table 3:
Type:
I = input, O = output, S = supply
Input level:
A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
– Output:
OD = open drain 2), PP = push-pull
Refer to “I/O PORTS” on page 50 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
= Pin not connected in ST72325S devices
Table 2. LQFP64/48/44 and SDIP42 Device Pin Descriptions
Pin n°
Pin Name
Level
Port
Main
Input
Output function
(after
reset)
Alternate function
1 2 - - - PE4 (HS)
2 -4) - - - PE5 (HS)
3 -4) - - - PE6 (HS)
4 -4) - - - PE7 (HS)
I/O CT HS X X
I/O CT HS X X
I/O CT HS X X
I/O CT HS X X
X X Port E4
X X Port E5
X X Port E6
X X Port E7
PWM Output 3
5 3 3 2 39 PB0/PWM3
I/O CT
X ei2
X X Port B0 Caution: Negative cur-
rent injection not al-
lowed on this pin
6 4 4 3 40 PB1/PWM2
7 5 5 4 41 PB2/PWM1
8 6 6 5 42 PB3/PWM0
I/O CT
I/O CT
I/O CT
X ei2
X ei2
X ei2
9 7 7 6 1 PB4 (HS)/ARTCLK I/O CT HS X ei3
X X Port B1 PWM Output 2
X X Port B2 PWM Output 1
X X Port B3 PWM Output 0
X
X
Port B4
PWM-ART External
Clock
10 8 - - - PB5 / ARTIC1
I/O CT
X ei3
X
X
Port B5
PWM-ART Input Cap-
ture 1
11 -4) - - - PB6 / ARTIC2
12 -4) - - - PB7
13 9 9 7 2 PD0/AIN0
14 19 10 8 3 PD1/AIN1
15 11 11 9 4 PD2/AIN2
16 12 12 10 5 PD3/AIN3
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
X ei3
X
X
Port B6
PWM-ART Input Cap-
ture 2
X ei3 X X Port B7
XX
X X X Port D0 ADC Analog Input 0
XX
X X X Port D1 ADC Analog Input 1
XX
X X X Port D2 ADC Analog Input 2
XX
X X X Port D3 ADC Analog Input 3
12/197


ST72325J6 (STMicroelectronics)
8-bit MCU

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ST72325xx
Pin n°
Pin Name
Level
Port
Main
Input
Output function
(after
reset)
Alternate function
17 13 13 11 6 PD4/AIN4
18 14 14 12 7 PD5/AIN5
19 -4) - - - PD6/AIN6
20 -4) - - - PD7/AIN7
21 15 15 13 8 VAREF6)
22 16 16 14 9 VSSA6)
23 - - - - VDD_36)
24 - - - - VSS_36)
25 17 17 15 10 PF0/MCO/AIN8
I/O CT
I/O CT
I/O CT
I/O CT
I
S
S
S
I/O CT
XX
XX
XX
XX
X ei1
X X X Port D4 ADC Analog Input 4
X X X Port D5 ADC Analog Input 5
X X X Port D6 ADC Analog Input 6
X X X Port D7 ADC Analog Input 7
Analog Reference Voltage for
ADC
Analog Ground Voltage
Digital Main Supply Voltage
Digital Ground Voltage
X
X
X
Port F0
Main clock
out (fOSC/2)
ADC Ana-
log
Input 8
26 18 18 16 11 PF1 (HS)/BEEP
27 19 19 17 12 PF2 (HS)
28 -4) -
-
-
PF3/OCMP2_A/
AIN9
I/O CT HS X ei1
X X Port F1 Beep signal output
I/O CT HS X ei1 X X Port F2
Timer A ADC Ana-
I/O CT
XX
X X X Port F3 Output
log
Compare 2 Input 9
29
20
20
18
13
PF4/OCMP1_A/
AIN10
I/O CT
XX
Timer A ADC Ana-
X X X Port F4 Output
log
Compare 1 Input 10
30 -4) -
-
-
PF5/ICAP2_A/
AIN11
I/O CT
XX
Timer A In- ADC Ana-
X X X Port F5 put Cap- log
ture 2
Input 11
31 21 21 19 14 PF6 (HS)/ICAP1_A I/O CT HS X X
32
22
22
20
15
PF7 (HS)/
EXTCLK_A
I/O CT HS X X
33 23 23 21 - VDD_06)
34 24 24 22 - VSS_06)
S
S
35
25
25
23
16
PC0/OCMP2_B/
AIN12
I/O CT
XX
X X Port F6 Timer A Input Capture 1
X
X
Port F7
Timer A External Clock
Source
Digital Main Supply Voltage
Digital Ground Voltage
Timer B ADC Ana-
X X X Port C0 Output
log
Compare 2 Input 12
36
26
26
24
17
PC1/OCMP1_B/
AIN13
I/O CT
XX
Timer B ADC Ana-
X X X Port C1 Output
log
Compare 1 Input 13
37 27 27 25 18 PC2 (HS)/ICAP2_B I/O CT HS X X
38 28 28 26 19 PC3 (HS)/ICAP1_B I/O CT HS X X
39
29
29
27
20
PC4/MISO/ICCDA-
TA
I/O CT
XX
X X Port C2 Timer B Input Capture 2
X X Port C3 Timer B Input Capture 1
X
X
Port C4
SPI Master
In / Slave
Out Data
ICC Data
Input
40 30 30 28 21 PC5/MOSI/AIN14 I/O CT
XX
SPI Master ADC Ana-
X X X Port C5 Out / Slave log
In Data
Input 14
41 31 31 29 22 PC6/SCK/ICCCLK I/O CT
XX
X
X
Port C6
SPI Serial
Clock
ICC Clock
Output
13/197


ST72325J6 (STMicroelectronics)
8-bit MCU

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ST72325xx
Pin n°
Pin Name
42 32 32 30 23 PC7/SS/AIN15
43 -4) - - - PA0
44 -4) - - - PA1
45 33 - - - PA2
46 34 34 31 24 PA3 (HS)
47 35 35 32 25 VDD_16)
48 36 36 33 26 VSS_16)
49 37 37 34 27 PA4 (HS)
50 38 38 35 28 PA5 (HS)
51 39 39 36 29 PA6 (HS)/SDAI
52 40 40 37 30 PA7 (HS)/SCLI
53 41 41 38 31 VPP/ ICCSEL
54 42 42 39 32 RESET
55 - - - - EVD
56 - - - - TLI
57 43 43 40 33 VSS_26)
58 44 44 41 34 OSC23)
59 45 45 42 35 OSC13)
60 46 46 43 36 VDD_26)
61 47 47 44 37 PE0/TDO
62 48 48 1 38 PE1/RDI
63 1 - - - PE2
64 -4) - - - PE3
Level
Port
Main
Input
Output function
(after
reset)
Alternate function
I/O CT
XX
SPI Slave ADC Ana-
X X X Port C7 Select (ac- log
tive low) Input 15
I/O CT
X
I/O CT
X
I/O CT
X
I/O CT HS X
S
ei0
ei0
ei0
ei0
X X Port A0
X X Port A1
X X Port A2
X X Port A3
Digital Main Supply Voltage
S Digital Ground Voltage
I/O CT HS X X
I/O CT HS X X
I/O CT HS X
I/O CT HS X
I
X X Port A4
X X Port A5
T Port A6
T Port A7
I2C Data 1)
I2C Clock 1)
Must be tied low. In flash program-
ming mode, this pin acts as the
programming voltage input VPP.
See Section 12.9.2 for more de-
tails. High voltage must not be ap-
plied to ROM devices
I/O CT
Top priority non maskable inter-
rupt.
External voltage detector
I CT
S
X Top level interrupt input pin
Digital Ground Voltage
I/O
Resonator oscillator inverter out-
put
I
External clock input or Resonator
oscillator inverter input
S Digital Main Supply Voltage
I/O CT
I/O CT
I/O CT
I/O CT
XX
XX
XX
XX
X X Port E0
X X Port E1
X4) X4) Port E2
X X Port E3
SCI Transmit Data Out
SCI Receive Data In
14/197


ST72325J6 (STMicroelectronics)
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ST72325xx
Table 3. LQFP32/DIP32 Device Pin Description
Pin n°
Pin Name
Level
Port
Input
Output
Main
function
(after
reset)
Alternate function
1 4 VAREF6)
2 5 VSSA6)
3 6 PF0/MCO/AIN8
4 7 PF1 (HS)/BEEP
5
8
PF4/OCMP1_A/
AIN10
I
S
I/O CT
X ei1
I/O CT HS X ei1
I/O CT
XX
Analog Reference Voltage for ADC
Analog Ground Voltage
X
X
X
Port F0
Main clock out
(fOSC/2)
ADC Analog
Input 8
X X Port F1 Beep signal output
XX
X
Port F4
Timer A Output
Compare 1
ADC Analog
Input 10
6 9 PF6 (HS)/ICAP1_A I/O CT HS X X
7
10
PF7 (HS)/
EXTCLK_A
I/O CT HS X X
X X Port F6 Timer A Input Capture 1
X X Port F7 Timer A External Clock Source
8
11
PC0/OCMP2_B/
AIN12
I/O CT
XX
XX
X
Port C0
Timer B Output
Compare 2
ADC Analog
Input 12
9
12
PC1/OCMP1_B/
AIN13
I/O CT
XX
XX
X
Port C1
Timer B Output
Compare 1
ADC Analog
Input 13
10 13 PC2 (HS)/ICAP2_B I/O CT HS X X
11 14 PC3 (HS)/ICAP1_B I/O CT HS X X
12
15
PC4/MISO/ICCDA-
TA
I/O CT
XX
X X Port C2 Timer B Input Capture 2
X X Port C3 Timer B Input Capture 1
X
X
Port C4
SPI Master In /
Slave Out Data
ICC Data Input
13 16 PC5/MOSI/AIN14 I/O CT
XX
XX
X
Port C5
SPI Master Out / ADC Analog
Slave In Data Input 14
14 17 PC6/SCK/ICCCLK I/O CT
XX
X
X
Port C6
SPI Serial Clock
ICC Clock
Output
15 18 PC7/SS/AIN15
I/O CT
XX
XX
X
Port C7
SPI Slave Select ADC Analog
(active low)
Input 15
16 19 PA3 (HS)
17 20 PA4 (HS)
18 21 PA6 (HS)/SDAI
19 22 PA7 (HS)/SCLI
I/O CT HS X
ei0
I/O CT HS X X
I/O CT HS X
I/O CT HS X
20 23 VPP/ ICCSEL
I
X X Port A3
X X Port A4
T Port A6 I2C Data 1)
T Port A7 I2C Clock 1)
Must be tied low. In flash programming
mode, this pin acts as the programming
voltage input VPP. See Section 12.9.2 for
more details. High voltage must not be ap-
plied to ROM devices
21 24 RESET
22 25 VSS_26)
23 26 OSC23)
I/O CT
S
I/O
Top priority non maskable interrupt.
Digital Ground Voltage
Resonator oscillator inverter output
24 27 OSC13)
25 28 VDD_26)
26 29 PE0/TDO
27 30 PE1/RDI
I
S
I/O CT
I/O CT
XX
XX
External clock input or Resonator oscillator
inverter input
Digital Main Supply Voltage
X X Port E0 SCI Transmit Data Out
X X Port E1 SCI Receive Data In
15/197


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8-bit MCU

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ST72325xx
Pin n°
Pin Name
Level
Port
Input
Output
Main
function
(after
reset)
Alternate function
28 31 PB0/PWM3
I/O CT
X ei2
PWM Output 3
X X Port B0 Caution: Negative current injec-
tion not allowed on this pin
29 32 PB3/PWM0
I/O CT
X ei2 X X Port B3 PWM Output 0
30 1 PB4 (HS)/ARTCLK I/O CT HS X ei3
X X Port B4 PWM-ART External Clock
31 2 PD0/AIN0
I/O CT
XX
X X X Port D0 ADC Analog Input 0
32 3 PD1/AIN1
I/O CT
XX
X X X Port D1 ADC Analog Input 1
Notes for Table 2 and Table 3:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See See “I/O PORTS” on page 50. and Section 12.8 I/O PORT PIN CHARACTER-
ISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-
lator; see Section 1 DESCRIPTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for
more details.
4. On the chip, each I/O port may have up to 8 pads:
– In all devices except 48-pin ST72325C, pads that are not bonded to external pins are forced by hardware
in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to
avoid added current consumption.
– In 48-pin ST72325C devices, unbonded pads PA0, PA1, PB6, PB7, PD6, PD7, PE3, PE5, PE6, PE7,
PF3 and PF5) are in input floating configuration after reset. To avoid added current consumption, the
application must force these ports in input pull-up state by writing to the OR and DDR registers after re-
set. This initialization is not necessary in 48-pin ST72325S devices.
5. Pull-up always activated on PE2 see limitation Section 15.1.8.
6. It is mandatory to connect all available VDD and VREF pins to the supply voltage and all VSS and VSSA
pins to ground.
16/197


ST72325J6 (STMicroelectronics)
8-bit MCU

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ST72325xx
3 REGISTER & MEMORY MAP
As shown in Figure 6, the MCU is capable of ad-
dressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register locations, up to 2Kbytes of RAM
and up to 60Kbytes of user program memory. The
RAM space includes up to 256 bytes for the stack
from 0100h to 01FFh.
The highest address bytes contain the user reset
and interrupt vectors.
Figure 6. Memory Map
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
seved area can have unpredictable effects on the
device.
Related Documentation
AN 985: Executing Code in ST7 RAM
0000h
007Fh
0080h
HW Registers
(see Table 4)
087Fh
0880h
0FFFh
1000h
FFDFh
FFE0h
FFFFh
RAM
(2048, 1536, 1024,
or 512 Bytes)
Reserved
Program Memory
(60,48, 32 or 16K)
Interrupt & Reset Vectors
(see Table 9)
0080h
00FFh
0100h
01FFh
0200h
027Fh
or 047Fh
or 067Fh
or 087Fh
Short Addressing
RAM (zero page)
256 Bytes Stack
16-bit Addressing
RAM
1000h
4000h
60 KBytes
48 KBytes
8000h
32 KBytes
C000h
16 KBytes
FFFFh
17/197


ST72325J6 (STMicroelectronics)
8-bit MCU

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ST72325xx
Table 4. Hardware Register Map
Address
Block
Register
Label
Register Name
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
Port A
Port B
Port C
Port D
Port E
Port F
I2C
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
SPIDR
SPI SPICR
SPICSR
ISPR0
ISPR1
ITC
ISPR2
ISPR3
EICR
FLASH
FCSR
WATCHDOG WDGCR
SICSR
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Port C Data Register
Port C Data Direction Register
Port C Option Register
Port D Data Register
Port D Data Direction Register
Port D Option Register
Port E Data Register
Port E Data Direction Register
Port E Option Register
Port F Data Register
Port F Data Direction Register
Port F Option Register
I2C Control Register
I2C Status Register 1
I2C Status Register 2
I2C Clock Control Register
I2C Own Address Register 1
I2C Own Address Register2
I2C Data Register
Reserved Area (2 Bytes)
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register
Flash Control/Status Register
Watchdog Control Register
System Integrity Control/Status Register
Reset
Status
00h1)
00h
00h
00h1)
00h
00h
00h1)
00h
00h
00h1)
00h
00h
00h1)
00h
00h
00h1)
00h
00h
00h
00h
00h
00h
00h
00h
00h
Remarks
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W2)
R/W2)
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
xxh R/W
0xh R/W
00h R/W
FFh R/W
FFh R/W
FFh R/W
FFh R/W
00h R/W
00h R/W
7Fh R/W
000x 000x b R/W
18/197


ST72325J6 (STMicroelectronics)
8-bit MCU

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ST72325xx
Address
002Ch
002Dh
002Eh
to
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
Block
MCC
TIMER A
TIMER B
SCI
Register
Label
Register Name
Reset
Status
Remarks
MCCSR
Main Clock Control / Status Register
00h R/W
MCCBCR Main Clock Controller: Beep Control Register 00h R/W
Reserved Area (3 Bytes)
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
00h
00h
xxxx x0xx b
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
Reserved Area (1 Byte)
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
00h
00h
xxxx x0xx b
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
C0h
xxh
00h
x000 0000b
00h
00h
---
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
19/197


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8-bit MCU

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ST72325xx
Address
Block
Register
Label
Register Name
Reset
Status
Remarks
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
to
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
DM3)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
Reserved Area (18 Bytes)
ADC
PWM ART
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR
ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
ARTICR2
PWM AR Timer Duty Cycle Register 3
PWM AR Timer Duty Cycle Register 2
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
AR Timer Input Capture Control/Status Reg.
AR Timer Input Capture Register 1
AR Timer Input Capture Register 1
Reserved Area (2 Bytes)
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h Read Only
00h Read Only
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h Read Only
00h Read Only
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see ICC Protocol Reference manual.
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ST72325xx
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu-
al sectors and programmed on a Byte-by-Byte ba-
sis using an external VPP supply.
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
Three Flash programming modes:
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be pro-
grammed or erased without removing the de-
vice from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
Read-out protection
Register Access Security System (RASS) to
prevent accidental programming or erasing
4.3 Structure
The Flash memory is organised in sectors and can
be used for both code and data storage.
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 5). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes
(see Figure 7). They are mapped in the upper part
of the ST7 addressing space so the reset and in-
terrupt vectors are located in Sector 0 (F000h-
FFFFh).
Table 5. Sectors available in Flash devices
Flash Size (bytes)
4K
8K
> 8K
Available Sectors
Sector 0
Sectors 0,1
Sectors 0,1, 2
4.3.1 Read-out Protection
Read-out protection, when selected, provides a
protection against Program Memory content ex-
traction and against write access to Flash memo-
ry. Even if no protection can be considered as to-
tally unbreakable, the feature provides a very high
level of protection for a general purpose microcon-
troller.
In flash devices, this protection is removed by re-
programming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
Read-out protection selection depends on the de-
vice type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option
specified in the Option List.
Figure 7. Memory Map and Sector Address
4K 8K 10K 16K 24K 32K 48K 60K
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
2 Kbytes
8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes
4 Kbytes
4 Kbytes
FLASH
MEMORY SIZE
SECTOR 2
SECTOR 1
SECTOR 0
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ST72325xx
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC Interface
ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure 8).
These pins are:
– RESET: device reset
– VSS: device power supply ground
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
– ICCSEL/VPP: programming voltage
– OSC1(or OSCIN): main clock input for exter-
nal source (optional)
ValD, Ds:eeapFpiglicuaretio8n,
board power
Note 3)
supply
(option-
Figure 8. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
(See Note 3)
APPLICATION
POWER SUPPLY
CL2
OPTIONAL
(See Note 4)
CL1
ICC Cable
APPLICATION BOARD
ICC CONNECTOR
HE10 CONNECTOR TYPE
9 7 5 31
10 8 6 4 2
APPLICATION
RESET SOURCE
See Note 2
10kΩ
See Note 1
APPLICATION
I/O
ST7
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
2. During the ICC session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up re-
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the OSC1 or OS-
CIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.
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ST72325xx
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (In-Circuit Programming)
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see Figure 8). For more details on
the pin locations, refer to the device pinout de-
scription.
4.6 IAP (In-Application Programming)
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase pro-
tected to allow recovery in case errors occur dur-
ing the programming operation.
4.7 Related Documentation
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
4.7.1 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read / Write
Reset Value: 0000 0000 (00h)
70
00000000
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
Figure 9. Flash Control/Status Register Address and Reset Value
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0029h
FCSR
Reset Value
0
0
00
0
0
0
0
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ST72325xx
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
5.2 MAIN FEATURES
Enable executing 63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect
addressing mode)
Two 8-bit index registers
16-bit stack pointer
Low power HALT and WAIT modes
Priority maskable hardware interrupts
Non-maskable software/hardware interrupts
Figure 10. CPU Registers
7
0
RESET VALUE = XXh
70
RESET VALUE = XXh
70
RESET VALUE = XXh
15
PCH
87
PCL
0
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
70
1 1 I1 H I0 N Z C
RESET VALUE = 1 1 1 X 1 X X X
15 8 7
0
RESET VALUE = STACK HIGHER ADDRESS
5.3 CPU REGISTERS
The six CPU registers shown in Figure 1 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
X = Undefined Value
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ST72325xx
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
0
C
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic Management Bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
sult 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
Interrupt Software Priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
I1 I0
10
01
00
11
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more
details.
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ST72325xx
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
15 8
00000001
70
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 2).
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 2.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 11. Stack Manipulation Example
CALL
Subroutine
Interrupt
Event
PUSH Y
POP Y
IRET
RET
or RSP
@ 0100h
SP
SP
PCH
@ 01FFh PCL
SP
CC
A
X
PCH
PCL
PCH
PCL
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
Y
CC
A
X
PCH
PCL
PCH
PCL
SP
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
SP
PCL
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ST72325xx
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 13.
For more details, refer to dedicated parametric
section.
Main features
Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
System Integrity Management (SI)
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply
– Clock Security System (CSS) with Clock Filter
and Backup Safe Oscillator (enabled by op-
tion byte)
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an fOSC2 of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then fOSC2 = fOSC/2.
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 154.
Figure 12. PLL Block Diagram
PLL x 2
fOSC
/2
0
fOSC2
1
PLL OPTION BIT
Figure 13. Clock, Reset and Supply Block Diagram
SYSTEM INTEGRITY MANAGEMENT
OSC2
OSC1
MULTI-
OSCILLATOR
(MO)
fOSC
fOSC2
PLL
(option)
CLOCK SECURITY SYSTEM
(CSS)
CLOCK
FILTER
SAFE
OSC
fOSC2
MAIN CLOCK
CONTROLLER
fCPU
WITH REALTIME
CLOCK (MCC/RTC)
RESET
VSS
VDD
EVD
RESET SEQUENCE
MANAGER
(RSM)
AVD Interrupt Request
SICSR
AVD AVD AVD LVD
S IE F RF
0
CSS CSS WDG
IE D RF
WATCHDOG
TIMER (WDG)
CSS Interrupt Request
LOW VOLTAGE
DETECTOR
(LVD)
0 AUXILIARY VOLTAGE
DETECTOR
1
(AVD)
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6.2 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
three different source types coming from the multi-
oscillator block:
an external source
4 crystal or ceramic resonator oscillators
an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 6. Refer to the
electrical characteristics section for more details.
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to section 14.1 on page 181 for more details on the
frequency ranges). In this mode of the multi-oscil-
lator, the resonator and the load capacitors have
to be placed as close as possible to the oscillator
pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-
tance values must be adjusted according to the
selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
This oscillator allows a low cost solution for the
main clock of the ST7 using only an internal resis-
tor and capacitor. Internal RC oscillator mode has
the drawback of a lower frequency accuracy and
should not be used in applications that require ac-
curate timing.
In this mode, the two oscillator pins have to be tied
to ground.
Table 6. ST7 Clock Sources
Hardware Configuration
ST7
OSC1
OSC2
EXTERNAL
SOURCE
ST7
OSC1
OSC2
CL1 CL2
LOAD
CAPACITORS
ST7
OSC1
OSC2
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ST72325xx
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (selected by
option byte)
RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application
(see section 14.1 on page 181).
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 15. Reset Block Diagram
Figure 14. RESET Sequence Phases
Active Phase
RESET
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed.
For this reason, it is recommended to keep the
RESET pin in low state until programming mode is
entered, in order to avoid unwanted behavior.
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
“CONTROL PIN CHARACTERISTICS” on
page 162 for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized (see Figure 16). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
VDD
RESET
RON
Filter
INTERNAL
RESET
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
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ST72325xx
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
If the external RESET pulse is shorter than
tw(RSTL)out (see short ext. Reset in Figure 16), the
signal on the RESET pin may be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in Figure 16). Starting from the external RE-
SET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least
tw(RSTL)out.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until VDD is over the minimum
level specified for the selected fOSC frequency.
(see “OPERATING CONDITIONS” on page 144)
Figure 16. RESET Sequences
VDD
VIT+(LVD)
VIT-(LVD)
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC net-
work connected to the RESET pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
Power-On RESET
Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 16.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
RUN
LVD
RESET
ACTIVE PHASE
RUN
SHORT EXT.
RESET
ACTIVE
PHASE
RUN
LONG EXT.
RESET
ACTIVE
PHASE
RUN
WATCHDOG
RESET
ACTIVE
PHASE
RUN
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
tw(RSTL)out
th(RSTL)in
tw(RSTL)out
th(RSTL)in
DELAY
tw(RSTL)out
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU)
VECTOR FETCH
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