IRFU1018EPbF (International Rectifier)
Power MOSFET

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Applications
l High Efficiency Synchronous Rectification in
SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
Benefits
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche SOA
l Enhanced body diode dV/dt and dI/dt
Capability
PD - 97129
IRFR1018EPbF
IRFU1018EPbF
HEXFET® Power MOSFET
D VDSS
60V
RDS(on) typ.
7.1m:
max. 8.4m:
G
ID (Silicon Limited)
79A c
S ID (Package Limited)
56A
D-Pak
I-Pak
IRFR1018EPbF IRFU1018EPbF
G
Gate
Absolute Maximum Ratings
Symbol
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current d
Maximum Power Dissipation
Linear Derating Factor
VGS Gate-to-Source Voltage
dv/dt
TJ
TSTG
Peak Diode Recovery f
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy e
Avalanche Current d
Repetitive Avalanche Energy g
Thermal Resistance
Symbol
Parameter
RθJC
RθJA
RθJA
Junction-to-Case k
Junction-to-Ambient (PCB Mount) jk
Junction-to-Ambient k
Notes  through ‰ are on page 2
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D
Drain
Max.
79c
56c
56
315
110
0.76
± 20
21
-55 to + 175
300
S
Source
Units
A
W
W/°C
V
V/ns
°C
88
47
11
Typ.
–––
–––
–––
Max.
1.32
40
110
mJ
A
mJ
Units
°C/W
1
3/8/08


IRFU1018EPbF (International Rectifier)
Power MOSFET

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IRFR/U1018EPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
IDSS Drain-to-Source Leakage Current
IGSS Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
60 ––– ––– V VGS = 0V, ID = 250μA
––– 0.073 ––– V/°C Reference to 25°C, ID = 5mAd
––– 7.1 8.4 mΩ VGS = 10V, ID = 47A g
2.0 ––– 4.0 V VDS = VGS, ID = 100μA
––– ––– 20 μA VDS = 60V, VGS = 0V
––– ––– 250
VDS = 48V, VGS = 0V, TJ = 125°C
––– ––– 100 nA VGS = 20V
––– ––– -100
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
gfs
Qg
Qgs
Qgd
Qsync
RG(int)
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Forward Transconductance
110
Total Gate Charge
–––
Gate-to-Source Charge
–––
Gate-to-Drain ("Miller") Charge
–––
Total Gate Charge Sync. (Qg - Qgd)
–––
Internal Gate Resistance
–––
Turn-On Delay Time
–––
Rise Time
–––
Turn-Off Delay Time
–––
Fall Time
–––
Input Capacitance
–––
Output Capacitance
–––
Reverse Transfer Capacitance
–––
Effective Output Capacitance (Energy Related)h –––
Effective Output Capacitance (Time Related)g –––
–––
46
10
12
34
0.73
13
35
55
46
2290
270
130
390
630
–––
69
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S VDS = 50V, ID = 47A
nC ID = 47A
VDS = 30V
VGS = 10V g
ID = 47A, VDS =0V, VGS = 10V
Ω
ns VDD = 39V
ID = 47A
RG = 10Ω
VGS = 10V g
VGS = 0V
VDS = 50V
pF ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V i
VGS = 0V, VDS = 0V to 60V h
Diode Characteristics
Symbol
Parameter
IS Continuous Source Current
(Body Diode)
ISM Pulsed Source Current
(Body Diode) d
VSD Diode Forward Voltage
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
IRRM Reverse Recovery Current
ton Forward Turn-On Time
Min. Typ. Max. Units
Conditions
––– ––– 79c
––– ––– 315
A MOSFET symbol
showing the
integral reverse
D
G
p-n junction diode.
S
––– ––– 1.3 V TJ = 25°C, IS = 47A, VGS = 0V g
––– 26 39 ns TJ = 25°C
VR = 51V,
––– 31 47
TJ = 125°C
––– 24 36 nC TJ = 25°C
IF = 47A
di/dt = 100A/μs g
––– 35 53
TJ = 125°C
––– 1.8 ––– A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Calculated continuous current based on maximum allowable junction … Pulse width 400μs; duty cycle 2%.
temperature. Bond wire current limit is 56A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
‚ Repetitive rating; pulse width limited by max. junction
temperature.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.08mH
RG = 25Ω, IAS = 47A, VGS =10V. Part not recommended for
† Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
‰ Rθ is measured at TJ approximately 90°C.
use above this value.
„ I2SD 47A, di/dt 1668A/μs, VDD V(BR)DSS, TJ 175°C.
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IRFU1018EPbF (International Rectifier)
Power MOSFET

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1000
100
TOP
BOTTOM
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
10 4.5V
1
0.1
60μs PULSE WIDTH
Tj = 25°C
1 10
VDS, Drain-to-Source Voltage (V)
100
Fig 1. Typical Output Characteristics
1000
100
TJ = 175°C
10
TJ = 25°C
1
VDS = 25V
60μs PULSE WIDTH
0.1
23456789
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
4000
3000
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Ciss
2000
1000
Coss
Crss
0
1 10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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IRFR/U1018EPbF
1000
100
TOP
BOTTOM
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
4.5V
10
1
0.1
60μs PULSE WIDTH
Tj = 175°C
1 10
VDS, Drain-to-Source Voltage (V)
100
Fig 2. Typical Output Characteristics
2.5
ID = 47A
VGS = 10V
2.0
1.5
1.0
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance vs. Temperature
16
ID= 47A
12
VDS= 48V
VDS= 30V
VDS= 12V
8
4
0
0 10 20 30 40 50 60
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3


IRFU1018EPbF (International Rectifier)
Power MOSFET

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IRFR/U1018EPbF
1000
100
TJ = 175°C
10
TJ = 25°C
1
VGS = 0V
0.1
0.0 0.5 1.0 1.5 2.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
80
LIMITED BY PACKAGE
60
40
20
0
25
50 75 100 125 150
TC, Case Temperature (°C)
175
Fig 9. Maximum Drain Current vs. Case Temperature
0.8
0.6
0.4
0.2
0.0
0
10 20 30 40 50
VDS, Drain-to-Source Voltage (V)
60
Fig 11. Typical COSS Stored Energy
4
10000
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100 1msec
100μsec
10
LIMITED BY PACKAGE
1 Tc = 25°C
Tj = 175°C
Single Pulse
0.1
0.1 1
10msec
DC
10
100
VDS, Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
80
Id = 5mA
75
70
65
60
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
Fig 10. Drain-to-Source Breakdown Voltage
400
350
ID
TOP 5.3A
11A
300 BOTTOM 47A
250
200
150
100
50
0
25
50 75 100 125 150 175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFU1018EPbF (International Rectifier)
Power MOSFET

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IRFR/U1018EPbF
10
1
D = 0.50
0.20
0.1 0.10
0.05
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
τJ
τJ
τ1
τ1
R1R1
CiC=iτi/Ri/iRi
R2R2
τ2
τ2
R3R3
R4R4
τC
Ri (°C/W)
0.026741
τι (sec)
0.000007
τ3 τ4 τ 0.28078 0.000091
τ3 τ4 0.606685 0.000843
0.406128 0.005884
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
0.01
10 0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
1 Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
1.0E-02
1.0E-01
100
TOP
Single Pulse
BOTTOM 10% Duty Cycle
80 ID = 47A
60
40
20
0
25
50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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IRFU1018EPbF (International Rectifier)
Power MOSFET

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IRFR/U1018EPbF
4.5
ID = 1.0A
4.0 ID = 1.0mA
ID = 250μA
3.5 ID = 100μA
3.0
14
IF = 32A
12 VR = 51V
TJ = 25°C
10 TJ = 125°C
8
2.5 6
2.0 4
1.5 2
1.0
-75 -50 -25 0 25 50 75 100 125 150 175
TJ , Temperature ( °C )
Fig 16. Threshold Voltage vs. Temperature
14
IF = 47A
12 VR = 51V
TJ = 25°C
10 TJ = 125°C
8
6
4
2
0
0 200 400 600 800 1000
diF /dt (A/μs)
Fig. 17 - Typical Recovery Current vs. dif/dt
320
280
IF = 32A
VR = 51V
240 TJ = 25°C
TJ = 125°C
200
160
120
80
40
0
0 200 400 600 800 1000
diF /dt (A/μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
320
280
IF = 47A
VR = 51V
240 TJ = 25°C
TJ = 125°C
200
0
0 200 400 600 800 1000
diF /dt (A/μs)
Fig. 19 - Typical Stored Charge vs. dif/dt
160
120
80
40
0
0 200 400 600 800 1000
diF /dt (A/μs)
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFU1018EPbF (International Rectifier)
Power MOSFET

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IRFR/U1018EPbF
+
‚
-

RG
D.U.T +
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
ƒ Circuit Layout Considerations
Low Stray Inductance
-
Ground Plane
Low Leakage Inductance
Current Transformer
-„ +
*
dv/dt controlled by RG
Driver same type as D.U.T.
VDD
**
+
ISD controlled by Duty Factor "D"
-
D.U.T. - Device Under Test
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
Inductor Curent
Forward Drop
Ripple 5%
V*G*S*=10V
VDD
ISD
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
V(BR)DSS
15V tp
VDS
L
DRIVER
RG
2V0GVS
tp
D.U.T
IAS
0.01Ω
+
-
VDD
A
Fig 22a. Unclamped Inductive Test Circuit
IAS
Fig 22b. Unclamped Inductive Waveforms
VDS
VGS
RG
RD
D.U.T.
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
+-VDD
Fig 23a. Switching Time Test Circuit
L
VCC
DUT
0
210K S
VDS
90%
10%
VGS
td(on) tr
td(off) tf
Fig 23b. Switching Time Waveforms
Id
Vgs
Vds
Vgs(th)
Fig 24a. Gate Charge Test Circuit
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Qgodr
Qgd Qgs2 Qgs1
Fig 24b. Gate Charge Waveform
7


IRFU1018EPbF (International Rectifier)
Power MOSFET

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IRFR/U1018EPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
E XAMPL E :
T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 1234
AS S EMBLED ON WW 16, 2001
IN T HE AS S EMBLY LINE "A"
INT ERNAT IONAL
RECT IF IER
L OGO
Note: "P" in as s embly line pos ition
indicates "Lead-F ree"
"P" in as s embly line pos ition indicates
"Lead-F ree" qualification to the cons umer-level
AS S EMBLY
LOT CODE
OR
INT ERNAT IONAL
RECT IF IER
LOGO
AS S EMBLY
LOT CODE
IR F R 120
12 34
IR F R 120
116A
12 34
PART NUMBER
DAT E CODE
YEAR 1 = 2001
WEEK 16
LINE A
PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-F REE
PRODUCT (OPT IONAL)
P = DES IGNAT ES LEAD-F REE
PRODUCT QUALIF IED T O T HE
CONS UMER LEVEL (OPT IONAL)
YEAR 1 = 2001
WEEK 16
A = AS S EMBLY S IT E CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
8
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IRFU1018EPbF (International Rectifier)
Power MOSFET

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I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
IRFR/U1018EPbF
I-Pak (TO-251AA) Part Marking Information
EXAMPLE:
THIS IS AN IRFU120
WITH AS S EMBLY
LOT CODE 5678
AS S EMBLED ON WW 19, 2001
IN T HE AS S EMBLY LINE "A"
Note: "P" in as s embly line pos ition
indicates Lead-Free"
INT ERNAT IONAL
RE CT IF IE R
LOGO
AS S EMBLY
LOT CODE
OR
INT ERNAT IONAL
RE CT IF IE R
LOGO
AS S EMBLY
LOT CODE
IR F U120
56 78
IR F U120
119A
56 78
PART NUMBER
DATE CODE
YEAR 1 = 2001
WEEK 19
LINE A
PART NUMBER
DATE CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 1 = 2001
WEEK 19
A = AS S EMBLY S ITE CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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9


IRFU1018EPbF (International Rectifier)
Power MOSFET

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IRFR/U1018EPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 )
7.9 ( .312 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
13 INCH
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
Data and specifications subject to change without notice.
This product has been designed for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.3/08
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