G1-233P-85-1.8 (National Semiconductor)
Processor Series Low Power Integrated x86 Solution

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April 2000
Geode™ GX1 Processor Series
Low Power Integrated x86 Solution
General Description
The National Semiconductor® Geode™ GX1 processor
series is a line of integrated processors specifically
designed to power information appliances for entertain-
ment, education, and business. Serving the needs of con-
www.DataSheet4Ussuo.cmluomteiorsn
and business professionals alike, it’s the perfect
for IA (information appliance) applications such as
thin clients, interactive set-top boxes, and personal internet
access devices.
The Geode GX1 processor series is divided into three main
categories as defined by the core operating voltage. Avail-
able with core voltages of 2.0V, 1.8V, and 1.6V, it offers
extremely low typical power consumption (1.2W, 1.0W, and
0.8W, respectively) leading to longer battery life and
enabling small form-factor, fanless designs. Typical power
consumption is defined as an average, measured running
Microsoft Windows at 80% Active Idle (Suspend-on-Halt)
with a display resolution of 800x600x8 bpp at 75 Hz.
Geode™ GX1 Processor Internal Block Diagram
SYSCLK
Clock Module
SYSCLK
multiplied
by “A”
Core
Clocks
X-Bus
Clocks
16 KB
Unified L1
Cache
(128)
C-Bus (64)
x86 Compatible Core
Integer
TLB Unit
Instruction
Fetch
MMU
Load/Store
INT/NMI
Interrupt
Control
FP_Error
Floating Point
Unit
INTR
IRQ13
SMI#
SUSP#
SUSPA#
Power
Management
Control
Core Suspend
Core Acknowledge
X-Bus Suspend
X-Bus Acknowledge
X-Bus (32)
Arbiter
Write
Buffers
X-Bus
Controller
Read
Buffers
Arbiter
PCI Host
Controller
2D Accelerator
VGA
BLT Engine
ROP Unit
X-Bus CLK
divide by “B”
Display Controller
Compression Buffer
Palette RAM
Timing Generator
3
REQ/GNT
Pairs
PCI
Bus
4
SDRAM
Clocks
64-bit
SDRAM
RGB
YUV
Geode™ Graphics
Companion Interface
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode, WebPAD, and VSA, are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor Corporation
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Processor Series Low Power Integrated x86 Solution

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While the x86 core provides maximum compatibility with
the vast amount of Internet content available, the intelligent
integration of several other functions, such as audio and
graphics, offers a true system-level multimedia solution.
The Geode GX1 processor core is a proven x86 design
that offers competitive performance. It contains integer and
floating point execution units based on sixth-generation
technology. The integer core contains a single, five-stage
execution pipeline and offers advanced features such as
operand forwarding, branch target buffers, and extensive
write buffering. Accesses to the 16 KB write-back L1 cache
are dynamically reordered to eliminate pipeline stalls when
fetching operands.
In addition to the advanced CPU features, the GX1 proces-
sor integrates a host of functions typically implemented
www.DataSheet4Uwat.iocthor mecoxtnetraninasl
components. A
a VGA (video
full function graphics acceler-
graphics array) controller, bit-
BLT engine, and a ROP (raster operations) unit for
complete GUI (Graphical User Interface) acceleration
under most operating systems. A display controller con-
tains additional video buffering to enable >30 fps MPEG1
playback and video overlay when used with a National
Semiconductor Geode I/O or graphics companion chip
(e.g., CS5530 or CS9211). Graphics and system memory
accesses are supported by a tightly coupled SDRAM con-
troller which eliminates the need for an external L2 cache.
A PCI host controller supports up to three bus masters for
additional connectivity and multimedia capabilities.
The GX1 processor also incorporates Virtual System
Architecture® (VSA™) technology. VSA technology
enables the XpressGRAPHICS and XpressAUDIO sub-
systems. Software handlers are available that provide full
compatibility for industry standard VGA and 16-bit audio
functions that are transparent at the operating system level.
Together the National Semiconductor I/O companion and
GX1 processor Geode devices provide a scalable, flexible,
low-power, system-level solution well suited for a wide
array of information appliances ranging from hand-held
personal information access devices to digital set-top
boxes and thin clients.
Features
General Features
 Packaging:
— 352-Terminal Ball Grid Array (BGA) or
— 320-Pin Staggered Pin Grid Array (SPGA)
 0.18-micron four layer metal CMOS process
 Split rail design:
— Available 1.6V, 1.8V, or 2.0V core
— 3.3V I/O interface
 Fully static design
 Low Typical Power Consumption:
— 0.8W @ 1.6V/200 MHz
— 1.2W @ 2.0V/300 MHz
Note:
Typical power consumption is defined as an aver-
age, measured running Windows at 80% Active
Idle (Suspend-on-Halt) with a display resolution of
800x600x8 bpp @ 75 Hz.
 Speeds offered up to 300 MHz
 Unified Memory Architecture
— Frame buffer and video memory reside in main
memory
— Minimizes PCB (Printed Circuit Board) area require-
ments
— Reduces system cost
 Compatible with multiple Geode I/O companion devices
provided by National Semiconductor
32-Bit x86 Processor
 Supports Intel’s MMX instruction set extension for the
acceleration of multimedia applications
 16 KB unified L1 cache
 Six-stage pipelined integer unit
 Integrated Floating Point Unit (FPU)
 Memory Management Unit (MMU) adheres to standard
paging mechanisms and optimizes code fetch perfor-
mance:
— Load-store reordering gives priority to memory reads
— Memory-read bypassing eliminates unnecessary or
redundant memory reads
 Re-entrant System Management Mode (SMM)
enhanced for VSA technology
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G1-233P-85-1.8 (National Semiconductor)
Processor Series Low Power Integrated x86 Solution

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Flexible Power Management
 Supports a wide variety of standards:
— APM (Advanced Power Management) for Legacy
power management
— ACPI (Advanced Configuration and Power Interface)
for Windows power management
– Direct support for all standard processor (C0-C4)
states
— OnNOW design initiative compliant
 Supports a wide variety of hardware and software
controlled modes:
— Active Idle (core-only stopped, display active)
— Standby (core and all integrated functions halted)
— Sleep (core and integrated functions halted and all
external clocks stopped)
www.DataSheet4U.comSuspend Modulation (automatic throttling of CPU
core via Geode I/O or graphics companion chip)
– Programmable duty cycle for optimal performance/
thermal balancing
— Several dedicated and programmable wake-up
events (via Geode I/O or graphics companion chip)
PCI Host Controller
 Several arbitration schemes supported
 Directly supports up to three PCI bus masters, more with
external logic
 Synchronous to CPU core
 Allows external PCI master accesses to main memory
concurrent with CPU accesses to L1 cache
Virtual Systems Architecture Technology
 Innovative architecture allowing OS independent (soft-
ware) virtualization of hardware functions
 Provides XpressGRAPHICS subsystem:
— High performance legacy VGA core compatibility
Note: The GUI acceleration is pure hardware.
 Provides 16-bit XpressAUDIO subsystem:
— 16-bit stereo FM synthesis
— OPL3 emulation
— Supports MPU-401 MIDI interface
— Hardware assist provided via Geode I/O companion
chip
 Additional hardware functions can be supported as
needed
2D Graphics Accelerator
 Accelerates BitBLTs, line draw, text:
— Bresenham vector engine
 Supports all 256 Raster Operations (ROPs)
 Supports transparent BLTs and page flipping for
Microsoft’s DirectDraw
 Runs at core clock frequency
 Full VGA and VESA mode support
 Special "driver level” instructions utilize internal
scratchpad for enhanced performance
Display Controller
 Display Compression Technology (DCT) architecture
greatly reduces memory bandwidth consumption of
display refresh
 Supports a separate video buffer and data path to
enable video acceleration in Geode I/O and graphics
companion chips
 Internal palette RAM for gamma correction
 Direct interface to Geode I/O and graphics companion
chips for CRT and TFT flat panel support eliminates the
need for an external RAMDAC
 Hardware cursor
 Supports up to 1280x1024x8 bpp and 1024x768x16 bpp
XpressRAM
 SDRAM interface tightly coupled to CPU core and
graphics subsystem for maximum efficiency
 64-Bit wide memory bus
 Support for:
— Two 168-pin unbuffered DIMMs
— Up to 16 simultaneously open banks
— 16-byte reads (burst length of two)
— Up to 512 MB total memory supported
Diverse Operating System Support
 Microsoft’s Windows 2000, Windows 95, Windows 98,
and Windows NT in non PC applications; along with
Windows CE and Windows NTE
 WindRiver System’s VxWorks
 QNX Software Systems’ QNX
 Linux
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Table of Contents
1.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 INTEGER UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 FLOATING POINT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 WRITE-BACK CACHE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5 INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.6 INTEGRATED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.6.1
1.6.2
1.6.3
1.6.4
Graphics Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
XpressRAM Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
www.DataSheet4U.com 1.7
GEODE GX1/CS5530 SYSTEM DESIGNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.7.1 Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory Controller Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Video Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power, Ground, and No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Internal Test and Measurement Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.0 Processor Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1 CORE PROCESSOR INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 INSTRUCTION SET OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.1 Lock Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3 REGISTER SETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.1 Application Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.1.1 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.1.2 Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.1.3 Instruction Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.1.4 EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.2 System Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.2.1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.2.2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.2.3 Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.2.4 TLB Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.2.5 Cache Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.3 Model Specific Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3.4 Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.4 ADDRESS SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.1 I/O Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.2 Memory Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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Table of Contents (Continued)
3.5
3.6
www.DataSheet4U.com
3.7
3.8
3.9
3.10
3.11
OFFSET, SEGMENT, AND PAGING MECHANISMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.5.1 Offset Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.5.2 Segment Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.5.2.1
3.5.2.2
3.5.2.3
3.5.2.4
Real Mode Segment Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Virtual 8086 Mode Segment Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Segment Mechanism in Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Segment Selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.5.3 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.5.3.1 Global and Local Descriptor Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.5.3.2 Segment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.5.3.3 Task, Gate, Interrupt, and Application and System Descriptors . . . . . . . . . . . . . . . . . 71
3.5.4 Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
INTERRUPTS AND EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.6.2 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.6.3 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6.3.1 Interrupt Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6.3.2 Interrupt Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6.4 Interrupt and Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.6.5 Exceptions in Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.6.6 Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SYSTEM MANAGEMENT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.7.1 SMM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.7.2 SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.7.3 SMM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.7.4 SMM Memory Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.7.5 SMM Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.7.6 SMM Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.7 SMI Generation for Virtual VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.8 SMM Service Routine Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.9 SMI Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.9.1 CPU States Related to SMM and Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
HALT AND SHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.9.1 Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.9.2 I/O Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.9.3 Privilege Level Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.9.3.1 Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.9.4 Initialization and Transition to Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
VIRTUAL 8086 MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.10.1 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.10.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.10.3 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.10.4 Entering and Leaving Virtual 8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
FLOATING POINT UNIT OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.11.1 FPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.11.2 FPU Tag Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.11.3 FPU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.11.4 FPU Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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Table of Contents (Continued)
4.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.1
4.2
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4.3
4.4
INTEGRATED FUNCTIONS PROGRAMMING INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1.1 Graphics Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.3 Graphics Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.4 Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.1 Initialization of Scratchpad RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.2 Scratchpad RAM Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.3 BLT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.5 Display Driver Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.1.6 CPU_READ/CPU_WRITE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.1 FPU Error Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.2 A20M Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.3 SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.4 640 KB to 1 MB Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.5 Internal Bus Interface Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.1 Memory Array Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.3.2 Memory Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.3.3 SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.3.3.1 SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.3.4 Memory Controller Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3.5 Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.1 High Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.2 Auto Low Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.3 Physical Address to DRAM Address Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.6 Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.3.7 SDRAM Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
GRAPHICS PIPELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4.1 BitBLT/Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4.2 Master/Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.3 Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.3.1 Monochrome Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.3.2 Dither Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.3.3 Color Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.4 Source Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.5 Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.6 Graphics Pipeline Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Table of Contents (Continued)
4.5
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4.6
4.7
DISPLAY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.5.1 Display FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.5.2 Compression Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.5.3 Hardware Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.5.4 Display Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.5.5 Dither and Frame Rate Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.5.6 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.5.7 Graphics Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.5.7.1 DC Memory Organization Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.5.7.2 Frame Buffer and Compression Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . 140
4.5.7.3 VGA Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.5.8 Display Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.5.8.1 Configuration and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
4.5.9 Memory Organization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
4.5.10 Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
4.5.11 Cursor Position and Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.5.12 Palette Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4.5.13 FIFO Diagnostic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.5.14 CS5530 Display Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
4.5.14.1 CS5530 Video Port Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
VIRTUAL VGA SUBSYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
4.6.1 Traditional VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
4.6.1.1
4.6.1.2
4.6.1.3
4.6.1.4
4.6.1.5
VGA Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
VGA Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Video Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
VGA Video BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.6.2 Virtual VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.6.2.1
4.6.2.2
4.6.2.3
4.6.2.4
4.6.2.5
4.6.2.6
4.6.2.7
4.6.2.8
Datapath Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
GX1 VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
VGA Range Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
VGA Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
VGA Write/Read Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
VGA Address Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
VGA Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
4.6.3 VGA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
4.6.4 Virtual VGA Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
PCI CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.7.1 X-Bus PCI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.7.2 X-Bus PCI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.7.3 PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.7.4 Generating Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.7.5 Generating Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.7.6 PCI Configuration Space Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.7.7 PCI Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
4.7.8 PCI Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.7.8.1
4.7.8.2
4.7.8.3
4.7.8.4
PCI Read Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
PCI Halt Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
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Table of Contents (Continued)
5.0 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.1
5.2
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5.3
POWER MANAGEMENT FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.1.1 System Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.1.2 Suspend-on-Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.1.3 CPU Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.1.3.1 Suspend Modulation for Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
5.1.3.2 Suspend Modulation for Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
5.1.4 3 Volt Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
5.1.5 GX1 Processor Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
5.1.6 Advanced Power Management (APM) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SUSPEND MODES AND BUS CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
5.2.1 Timing Diagram for Suspend-on-Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
5.2.2 Initiating Suspend with SUSP# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
5.2.3 Stopping the Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.2.4 Serial Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
POWER MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.1 PART NUMBERS/PERFORMANCE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.2 ELECTRICAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
6.2.1
6.2.2
6.2.3
6.2.4
Power/Ground Connections and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
6.2.1.1 Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
NC-Designated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
6.3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.4 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.5 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.5.1 Input/Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.5.2 DC Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.5.2.1 Definition of CPU Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.5.2.2 Definition and Measurement Techniques of CPU Current Parameters. . . . . . . . . . . 191
6.5.2.3 Definition of System Conditions for Measuring “On” Parameters . . . . . . . . . . . . . . . 192
6.5.2.4 DC Current Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.6 I/O CURRENT DE-RATING CURVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.6.1
6.6.2
6.6.3
Display Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Memory Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
I/O Current De-rating Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.7 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.1 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.1.1 Heatsink Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
7.2 MECHANICAL PACKAGE OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
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Table of Contents (Continued)
8.0 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
8.1
www.DataSheet4U.com
8.2
8.3
8.4
8.5
8.6
GENERAL INSTRUCTION SET FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
8.1.1 Prefix (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
8.1.2 Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
8.1.2.1
8.1.2.2
8.1.2.3
8.1.2.4
w Field (Operand Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
d Field (Operand Direction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
s Field (Immediate Data Field Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
eee Field (MOV-Instruction Register Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.1.3 mod and r/m Byte (Memory Addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.1.4 reg Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.1.4.1 sreg2 Field (ES, CS, SS, DS Register Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.1.4.2 sreg3 Field (FS and GS Segment Register Selection) . . . . . . . . . . . . . . . . . . . . . . . 216
8.1.5 s-i-b Byte (Scale, Indexing, Base) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.1.5.1 ss Field (Scale Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.1.5.2 index Field (Index Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
8.1.5.3 Base Field (s-i-b Present) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
CPUID INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.2.1 Standard CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.2.1.1 CPUID Instruction with EAX = 0000 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.2.1.2 CPUID Instruction with EAX = 0000 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
8.2.1.3 CPUID Instruction with EAX = 0000 0002h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
8.2.2 Extended CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.2.2.1
8.2.2.2
8.2.2.3
8.2.2.4
CPUID Instruction with EAX = 8000 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
CPUID Instruction with EAX = 8000 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
CPUID Instruction with EAX = 8000 0002h, 8000 0003h, 8000 0004h . . . . . . . . . . 221
CPUID Instruction with EAX = 8000 0005h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
PROCESSOR CORE INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.3.1 Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.3.2 Clock Counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.3.3 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
FPU INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
MMX INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
EXTENDED MMX INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
A.1 ORDER INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
A.2 DATA BOOK REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
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1.0 Architecture Overview
The Geode GX1 processor series represents the sixth gen-
eration of x86-compatible 32-bit processors with sixth-gen-
eration features. The decoupled load/store unit allows
reordering of load/store traffic to achieve higher perfor-
mance. Other features include single-cycle execution, sin-
gle-cycle instruction decode, 16 KB write-back cache, and
clock rates up to 300 MHz. These features are made possi-
ble by the use of advanced-process technologies and pipe-
lining.
The GX1 processor has low power consumption at all clock
frequencies. Where additional power savings are required,
designers can make use of Suspend Mode, Stop Clock
capability, and System Management Mode (SMM).
The GX1 processor is divided into major functional blocks
www.DataSheet4U(a.csosmhown in Figure 1-1):
Integer Unit
Floating Point Unit (FPU)
Write-Back Cache Unit
Memory Management Unit (MMU)
Internal Bus Interface Unit
Integrated Functions
Instructions are executed in the integer unit and in the float-
ing point unit. The cache unit stores the most recently used
data and instructions and provides fast access to this infor-
mation for the integer and floating point units.
Write-Back
Cache Unit
C-Bus
MMU
Integer
Unit
Internal Bus Interface Unit
X-Bus
FPU
Integrated
Functions
Graphics
Pipeline
Memory
Controller
Display
Controller
PCI
Controller
SDRAM Port
CS5530
(CRT/LCD TFT)
Figure 1-1. Internal Block Diagram
PCI Bus
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Architecture Overview (Continued)
1.1 INTEGER UNIT
The integer unit consists of:
• Instruction Buffer
• Instruction Fetch
Instruction Decoder and Execution
The pipelined integer unit fetches, decodes, and executes
x86 instructions through the use of a five-stage integer
pipeline.
The instruction fetch pipeline stage generates, from the on-
chip cache, a continuous high-speed instruction stream for
use by the processor. Up to 128 bits of code are read dur-
ing a single clock cycle.
www.DataSheet4UB.rcaonmch prediction logic within the prefetch unit generates a
predicted target address for unconditional or conditional
branch instructions. When a branch instruction is detected,
the instruction fetch stage starts loading instructions at the
predicted address within a single clock cycle. Up to 48
bytes of code are queued prior to the instruction decode
stage.
The instruction decode stage evaluates the code stream
provided by the instruction fetch stage and determines the
number of bytes in each instruction and the instruction
type. Instructions are processed and decoded at a maxi-
mum rate of one instruction per clock.
The address calculation function is pipelined and contains
two stages, AC1 and AC2. If the instruction refers to a
memory operand, AC1 calculates a linear memory address
for the instruction.
The AC2 stage performs any required memory manage-
ment functions, cache accesses, and register file
accesses. If a floating point instruction is detected by AC2,
the instruction is sent to the floating point unit for process-
ing.
The execution stage, under control of microcode, executes
instructions using the operands provided by the address
calculation stage.
Write-back, the last stage of the integer unit, updates the
register file within the integer unit or writes to the load/store
unit within the memory management unit.
1.2 FLOATING POINT UNIT
The floating point unit (FPU) interfaces to the integer unit
and the cache unit through a 64-bit bus. The FPU is x87-
instruction-set compatible and adheres to the IEEE-754
standard. Because almost all applications that contain FPU
instructions also contain integer instructions, the GX1 pro-
cessor’s FPU achieves high performance by completing
integer and FPU operations in parallel.
FPU instructions are dispatched to the pipeline within the
integer unit. The address calculation stage of the pipeline
checks for memory management exceptions and accesses
memory operands for use by the FPU. Once the instruc-
tions and operands have been provided to the FPU, the
FPU completes instruction execution independently of the
integer unit.
1.3 WRITE-BACK CACHE UNIT
The 16 KB write-back unified (data/instruction) cache is
configured as four-way set associative. The cache stores
up to 16 KB of code and data in 1024 cache lines.
The GX1 processor provides the ability to allocate a portion
of the L1 cache as a scratchpad, which is used to acceler-
ate the Virtual Systems Architecture technology algorithms
as well as for some graphics operations.
1.4 MEMORY MANAGEMENT UNIT
The memory management unit (MMU) translates the linear
address supplied by the integer unit into a physical address
to be used by the cache unit and the internal bus interface
unit. Memory management procedures are x86-compati-
ble, adhering to standard paging mechanisms.
The MMU also contains a load/store unit that is responsible
for scheduling cache and external memory accesses. The
load/store unit incorporates two performance-enhancing
features:
• Load-store reordering that gives memory reads
required by the integer unit a priority over writes to
external memory.
• Memory-read bypassing that eliminates unnecessary
memory reads by using valid data from the execution
unit.
1.5 INTERNAL BUS INTERFACE UNIT
The internal bus interface unit provides a bridge from the
GX1 processor to the integrated system functions (i.e.,
memory subsystem, display controller, graphics pipeline)
and the PCI bus interface.
When external memory access is required, the physical
address is calculated by the memory management unit and
then passed to the internal bus interface unit, which trans-
lates the cycle to an X-Bus cycle (the X-Bus is a proprietary
internal bus which provides a common interface for all of
the integrated functions). The X-Bus memory cycle is arbi-
trated between other pending X-Bus memory requests to
the SDRAM controller before completing.
In addition, the internal bus interface unit provides configu-
ration control for up to 20 different regions within system
memory with separate controls for read access, write
access, cacheability, and PCI access.
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Architecture Overview (Continued)
1.6 INTEGRATED FUNCTIONS
The GX1 processor integrates the following functions tradi-
tionally implemented using external devices:
High-performance 2D graphics accelerator
Separate CRT and TFT control from the display
controller
SDRAM memory controller
PCI bridge
The processor has also been enhanced to support VSA
technology implementation.
The GX1 processor implements a Unified Memory Archi-
www.DataSheet4Ute.ccotumre (UMA). By using DCT (Display Compression Tech-
nology) architecture, the performance degradation inherent
in traditional UMA systems is eliminated.
1.6.1 Graphics Accelerator
The graphics accelerator is a full-featured GUI accelerator.
The graphics pipeline implements a bitBLT engine for
frame buffer bitBLTs and rectangular fills. Additional
instructions in the integer unit may be processed, as the
bitBLT engine assists the CPU in the bitBLT operations that
take place between system memory and the frame buffer.
This combination of hardware and software is used by the
display driver to provide very fast bidirectional transfers
between system memory and the frame buffer. The bitBLT
engine also draws randomly oriented vectors, and scan-
lines for polygon fill. All of the pipeline operations described
in the following list can be applied to any bitBLT operation.
• Pattern Memory: Render with 8x8 dither, 8x8 mono-
chrome, or 8x1 color pattern.
• Color Expansion: Expand monochrome bitmaps to full
depth 8- or 16-bit colors.
• Transparency: Suppresses drawing of background
pixels for transparent text.
• Raster Operations: Boolean operation combines
source, destination, and pattern bitmaps.
1.6.2 Display Controller
The display port is a direct interface to the Geode I/O com-
panion (i.e., CS5530) which drives a TFT flat panel display,
LCD panel, or a CRT display.
The display controller (video generator) retrieves image
data from the frame buffer, performs a color-look-up if
required, inserts the cursor overlay into the pixel stream,
generates display timing, and formats the pixel data for out-
put to a variety of display devices. The display controller
contains DCT architecture that allows the GX1 processor
to refresh the display from a compressed copy of the frame
buffer. DCT architecture typically decreases the screen
refresh bandwidth requirement by a factor of 15 to 20, min-
imizing bandwidth contention.
1.6.3 XpressRAM Memory Subsystem
The memory controller drives a 64-bit SDRAM port directly.
The SDRAM memory array contains both the main system
memory and the graphics frame buffer. Up to four module
banks of SDRAM are supported. Each module bank can
have two or four component banks depending on the mem-
ory size and organization. The maximum configuration is
four module banks with four component banks, each pro-
viding a total of 16 open banks. The maximum memory
size is 512 MB.
The memory controller handles multiple requests for mem-
ory data from the GX1 processor, the graphics accelerator
and the display controller. The memory controller contains
extensive buffering logic that helps minimize contention for
memory bandwidth between graphics and CPU requests.
The memory controller cooperates with the internal bus
controller to determine the cacheability of all memory refer-
ences.
1.6.4 PCI Controller
The GX1 processor incorporates a full-function PCI inter-
face module that includes the PCI arbiter. All accesses to
external I/O devices are sent over the PCI bus, although
most memory accesses are serviced by the SDRAM con-
troller. The internal bus interface unit contains address
mapping logic that determines if memory accesses are tar-
geted for the SDRAM or for the PCI bus. The PCI bus in a
GX1 based system is 3.3 volt only. Do not connect 5 volt
devices on this bus.
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Architecture Overview (Continued)
1.7 GEODE GX1/CS5530 SYSTEM DESIGNS
A GX1 processor and Geode CS5530 I/O companion
based design provides high performance using 32-bit x86
processing. The two chips integrate video, audio and mem-
ory interface functions normally performed by external
hardware. The CS5530 enables the full features of the GX1
processor with MMX support. These features include full
VGA and VESA video, 16-bit stereo sound, IDE interface,
ISA interface, SMM power management, and IBM’s AT
compatibility logic. In addition, the CS5530 provides an
Ultra DMA/33 interface, MPEG1 assist, and AC97 Version
2.0 compliant audio.
www.DataSheet4U.com
Figure 1-2 shows a basic block system diagram which also
includes the Geode CS9211 graphics companion for
designs that need to interface to a Dual Scan Super
Twisted Pneumatic (DSTN) panel (instead of a TFT panel).
Figure 1-3 shows an example of a CS9211 interface in a
typical GX1/CS5530 based system design. The CS9211
converts the digital RGB output of the CS5530 to the digital
output suitable for driving a color DSTN flat panel LCD. It
can drive all standard color DSTN flat panels up to a
1024x768 resolution.
Figures 1-4 and 1-5 show the signal connections between
the GX1 processor and the CS5530. For connections to the
CS9211, refer to the CS9211 data book.
SDRAM
USB
(2 Ports)
MD[63:0]
Clocks
Speakers
CD
ROM
Audio
AC97
Codec
Geode™
CS5530
I/O Companion
Micro-
phone
GPIO
14.31818
MHz Crystal
SDRAM
Port
YUV Port
(Video)
Geode™
GX1
Processor
Serial
Packet
RGB Port
(Graphics)
PCI Interface
CRT
3.3V PCI Bus
Graphics Data
Video Data
Analog RGB
Digital RGB (to TFT or DSTN Panel)
TFT
Panel
IDE Control
Super
I/O
BIOS
IDE
Devices
Geode™
CS9211
Graphics
Companion
DC-DC & Battery
ISA Bus
DSTN Panel
Figure 1-2. Geode™ GX1/CS5530 System Block Diagram
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Architecture Overview (Continued)
.
Pixel Data 18
Geode™
GX1
Processor
Geode™
CS5530 I/O
Companion
Pixel Port 18
Timing Control 4
Serial
Configuration 4
Geode™
CS9211
Graphics
Companion
Addr & Control 21
MemData 16
DRAM/SDRAM
256Kx16
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8
Video Port (YUV)
24 4
3 Control
LCD Power
Panel Timing
Panel Data
DSTN/TFT
LCD
Figure 1-3. Geode™ CS9211 Interface System Diagram
Exclusive
Interconnect
Signals
(Do not connect to
any other device)
Geode™ GX1
Processor
Nonexclusive
Interconnect
Signals
(May also connect
to other 3.3V circuitry)
SYSCLK
SERIALP
IRQ13
SMI#
PCLK
DCLK
CRT_HSYNC
CRT_VSYNC
PIXEL[17:0]
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_VAL
VID_CLK
VID_DATA[7:0]
VID_RDY
RESET
INTR
SUSP#
SUSPA#
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ0#
GNT0#
(Note)
GX_CLK
PSERIAL
IRQ13
SMI#
PCLK
DCLK
HSYNC
VSYNC
PIXEL[23:0]
FP_HSYNC Not needed if
FP_VSYNC CRT only (no TFT)
ENA_DISP
VID_VAL
VID_CLK
VID_DATA[7:0]
VID_RDY
CPU_RST
INTR
Geode™ CS5530
SUSP#
SUSPA#
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ#
GNT#
I/O Companion
Note: Refer to Figure 1-5 for interconnection of the pixel lines.
Figure 1-4. Geode™ GX1/CS5530 Signal Connections
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Architecture Overview (Continued)
Geode™ GX1
Processor
PIXEL17
PIXEL16
PIXEL15
R
PIXEL14
PIXEL13
PIXEL12
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PIXEL11
PIXEL10
PIXEL9
G PIXEL8
PIXEL7
PIXEL6
PIXEL5
PIXEL4
PIXEL3
B PIXEL2
PIXEL1
PIXEL0
PIXEL23
PIXEL22
PIXEL21
PIXEL20
PIXEL19
PIXEL18
PIXEL17
PIXEL16
PIXEL15
PIXEL14
PIXEL13
PIXEL12
PIXEL11
PIXEL10
PIXEL9
PIXEL8
PIXEL7
PIXEL6
PIXEL5
PIXEL4
PIXEL3
PIXEL2
PIXEL1
PIXEL0
Geode™ CS5530
I/O Companion
Figure 1-5. PIXEL Signal Connections
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Architecture Overview (Continued)
1.7.1 Reference Designs
As described previously, the GX1 series of integrated pro-
cessors is designed specifically to work with National’s
Geode I/O and graphics companion devices. To help define
and drive the emerging information appliance market, sev-
eral reference systems have been developed by National
Semiconductor. These GX1 processor based reference
systems provide optimized and targeted solutions for three
main segments of the information appliance market: Per-
sonal Internet Access, Thin Client, and Set-top Box. Con-
tact your local National Semiconductor sales or field
support representative for further information on reference
designs for the information appliance market.
www.DataSheet4U.com
NSC
LM4549
Codec
Geode™
GX1
Processor
Control
Data
SDRAM
PCMCIA
Flash
Card
Optional
Embedded OS
Applications
Bootloader
Run-Time Diagnostics
Storage
Ultra DMA/33
USB Port
Geode™
CS5530
I/O
Companion
3.3V PCI Bus
RF Interface
ISA Bus
Buttons
Pwr Mgmt Microcontroller
DC Sense
Backlight
DSTN
Linear
Flash
(8 MB)
Embedded OS
Applications
Bootloader
Run-Time Diagnostics
Storage
Geode™
CS9211
Graphics
Companion
Li Batteries/
Charger
Touch
Control
512 KB DRAM
Figure 1-6. Example WebPAD™ System Diagram
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Architecture Overview (Continued)
SDRAM SO-DIMM
TFT
USB (2x)
CRT
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Geode™
GX1
Processor
Video
3.3V PCI Bus
Geode™
CS5530
I/O
Companion
NSC
LM4546
Codec
MIC In
Audio Out
NSC
DP83815
Ethernet
Controller
Reset
PWR CTL
CPU Core
Power
Termination
ISA Bus
Power
Clock
Generator
MK1491-06
Termination
64 MB Flash
NSC
PC97317IBW/VUL
SuperI/O
Figure 1-7. Example Thin Client System Diagram
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Architecture Overview (Continued)
CPU Temp.
Sensor
NSC
LM75
www.DataSheet4U.com
AC3
Anlg
MIC
1
IN
MIC
2
IN
Headphone
Output
Audio Line
Output
Tuner
FM In
LM4548
Codec
CD In
Geode™
GX1
Processor
3.3V PCI Bus
DMA
Arbiter
Riser Slot
Optional
LAN PCI
Card
LAN /
WAN
Geode™
CS5530
I/O
Companion
SDRAM
C-CUBE
“ZIVA”
IGS 50x5
Graphics
Optional
V .90
Modem
ISA Slot
Riser Slot
SAA7112
SGRAM
SGRAM
Video Port
Composite
Video In
VGA
S-Video
PAL or
NTSC
2.5” UDMA33
Hard Drive
Flash
BIOS
ISA Bus
ROM Slot
WinCE ROM
Module
Notebook DVD
Drive
Notebook
Floppy
Drive
Internal Assembly Options
NSC
PC97317VUL-ICF
SuperI/O
9638
SPDIF
Audio
Line
Out
TV Tuner
TV
Tuner
Module
TDA9851
CATV In
AC3
Digital
PCM1723
Tuner FM Out
TDA8006
Smartcard
LPT Mouse Front
(IR) Panel
COM
Keybd
(IR)
USB
Ports
AC3
Anlg
Figure 1-8. Example Set-Top Box System Diagram
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2.0 Signal Definitions
This section describes the external interface of the Geode GX1 processor. Figure 2-1 shows the signals organized by their
functional interface groups (internal test and electrical pins are not shown).
System
Interface
Signals
SYSCLK
CLKMODE[2:0]
RESET
INTR
IRQ13
SMI#
SUSP#
SUSPA#
SERIALP
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PCI
Interface
Signals
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ[2:0]#
GNT[2:0]#
Geode™
GX1
Processor
MD[63:0]
MA[12:0]
BA[1:0]
RASA#, RASB#
CASA#, CASB#
CS[3:0]#
WEA#, WEB#
DQM[7:0]
CKEA, CKEB
SDCLK[3:0]
SDCLK_IN
SDCLK_OUT
PCLK
VID_CLK
DCLK
CRT_HSYNC
CRT_VSYNC
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_RDY
VID_VAL
VID_DATA[7:0]
PIXEL[17:0]
Memory
Controller
Interface
Signals
Video
Interface
Signals
Figure 2-1. Functional Block Diagram
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Signal Definitions (Continued)
2.1 PIN ASSIGNMENTS
The tables in this section use several common abbrevia-
tions. Table 2-1 lists the mnemonics and their meanings.
Figure 2-2 shows the pin assignment for the 352 BGA with
Table 2-2 and Table 2-3 listing the pin assignments sorted
by pin number and alphabetically by signal name, respec-
tively.
Figure 2-3 shows the pin assignment for the 320 SPGA
with Table 2-4 and Table 2-5 listing the pin assignments
sorted by pin number and alphabetically by signal name,
respectively.
In Section 2.2 “Signal Descriptions” on page 31 a descrip-
www.DataSheet4Utio.cnomof each signal is provided within its associated func-
tional group.
Table 2-1. Pin Type Definitions
Mnemonic Definition
I
I/O
O
OD
PU
PD
s/t/s
VCC (PWR)
VSS (GND)
#
t/s
Standard input pin.
Bidirectional pin.
Totem-pole output.
Open-drain output structure that
allows multiple devices to share the
pin in a wired-OR configuration.
Pull-up resistor.
Pull-down resistor.
Sustained tri-state, an active-low tri-
state signal owned and driven by one
and only one agent at a time. The
agent that drives an s/t/s pin low
must drive it high for at least one
clock before letting it float. A new
agent cannot start driving an s/t/s
signal any sooner than one clock
after the previous owner lets it float.
A pull-up resistor on the motherboard
is required to sustain the inactive
state until another agent drives it.
Power pin.
Ground pin.
The "#" symbol at the end of a signal
name indicates that the active, or
asserted state occurs when the sig-
nal is at a low voltage level. When "#"
is not present after the signal name,
the signal is asserted when at a high
voltage level.
Tri-state signal.
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Signal Definitions (Continued)
Index Corner
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
VSS VSS AD27 AD24 AD21 AD16 VCC2 FRAM# DEVS# VCC3 PERR# AD15 VSS AD11 CBE0# AD6 VCC2 AD4 AD2 VCC3 AD0 AD1 TEST2 MD2 VSS VSS
B
VSS VSS AD28 AD25 AD22 AD18 VCC2 CBE2# TRDY# VCC3 LOCK# PAR AD14 AD12 AD9 AD7 VCC2 INTR AD3 VCC3 TEST1 TEST3 MD1 MD33 VSS VSS
C
AD29 AD31 AD30 AD26 AD23 AD19 VCC2 AD17 IRDY# VCC3 STOP# SERR# CBE1# AD13 AD10 AD8 VCC2 AD5 SMI# VCC3 TEST0 IRQ13 MD32 MD34 MD3 MD35
D
GNT0# TDI REQ2# VSS CBE3# VSS VCC2 VSS VSS VCC3 VSS VSS VSS VSS VSS VSS VCC2 VSS VSS VCC3 VSS MD0 VSS MD4 MD36 TDN
E
GNT2# SUSPA# REQ0# AD20
MD6 TDP MD5 MD37
F
TD0 GNT1# TEST VSS
VSS MD38 MD7 MD39
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VCC3 VCC3 VCC3 VCC3
VCC3 VCC3 VCC3 VCC3
H
TMS SUSP# REQ1# VSS
VSS MD8 MD40 MD9
J
FPVSY TCLK RESET VSS
VSS MD41 MD10 MD42
K
VCC2 VCC2 VCC2 VCC2
L
CKM1 FPHSY SERLP VSS
Geode™
VCC2 VCC2 VCC2 VCC2
VSS MD11 MD43 MD12
M
CKM2 VIDVAL CKM0 VSS
N
VSS PIX1 PIX0 VSS
P
GX1
Processor
VSS MD44 MD13 MD45
VSS MD14 MD46 MD15
VIDCLK PIX3 PIX2 VSS
R
PIX4 PIX5 PIX6 VSS
T
PIX7 PIX8 PIX9 VSS
352 BGA - Top View
VSS MD47 CASA# SYSCLK
VSS WEB# WEA# CASB#
VSS DQM0 DQM4 DQM1
U
VCC3 VCC3 VCC3 VCC3
V
PIX10 PIX11 PIX12 VSS
VCC3 VCC3 VCC3 VCC3
VSS DQM5 CS2# CS0#
W
PIX13 CRTHSY PIX14 VSS
VSS RASA# RASB# MA0
Y
VCC2 VCC2 VCC2 VCC2
AA
PIX15 PIX16 CRTVSY VSS
VCC2 VCC2 VCC2 VCC2
VSS MA1 MA2 MA3
AB
DCLK PIX17 VDAT6 VDAT7
MA4 MA5 MA6 MA7
AC
PCLK FLT# VDAT4 VSS NC VSS VCC2 VSS VSS VCC3 VSS VSS VSS VSS VSS VSS VCC2 VSS VSS VCC3 VSS DQM6 VSS MA8 MA9 MA10
AD
VRDY VDAT5 VDAT3 VDAT0 EDISP MD63 VCC2 MD62 MD29 VCC3 MD59 MD26 MD56 MD55 MD22 CKEB VCC2 MD51 MD18 VCC3 MD48 DQM3 CS1# MA11 BA0
BA1
AE
VSS VSS VDAT2 SCLK3 SCLK1 RWCLK VCC2 SCKIN MD61 VCC3 MD28 MD58 MD25 MD24 MD54 MD21 VCC2 MD20 MD50 VCC3 MD17 DQM7 CS3# MA12 VSS VSS
AF
VSS VSS VDAT1 SCLK0 SCLK2 MD31 VCC2 SCKOUT MD30 VCC3 MD60 MD27 MD57 VSS MD23 MD53 VCC2 MD52 MD19 VCC3 MD49 MD16 DQM2 CKEA VSS VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Note: Signal names have been abbreviated in this figure due to space constraints.
= GND terminal
= PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
Figure 2-2. 352 BGA Pin Assignment Diagram
(For order information, refer to Section A.1 “Order Information” on page 246.)
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Signal Definitions (Continued)
Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number
Pin
No. Signal Name
A1 VSS
A2 VSS
A3 AD27
A4 AD24
A5 AD21
A6 AD16
A7 VCC2
A8 FRAME#
A9 DEVSEL#
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A10 VCC3
A11 PERR#
A12 AD15
A13 VSS
A14 AD11
A15 C/BE0#
A16 AD6
A17 VCC2
A18 AD4
A19 AD2
A20 VCC3
A21 AD0
A22 AD1
A23 TEST2
A24 MD2
A25 VSS
A26 VSS
B1 VSS
B2 VSS
B3 AD28
B4 AD25
B5 AD22
B6 AD18
B7 VCC2
B8 C/BE2#
B9 TRDY#
B10 VCC3
B11 LOCK#
B12 PAR
B13 AD14
B14 AD12
B15 AD9
B16 AD7
B17 VCC2
B18 INTR
B19 AD3
B20 VCC3
B21 TEST1
B22 TEST3
Pin
No. Signal Name
B23 MD1
B24 MD33
B25 VSS
B26 VSS
C1 AD29
C2 AD31
C3 AD30
C4 AD26
C5 AD23
C6 AD19
C7 VCC2
C8 AD17
C9 IRDY#
C10 VCC3
C11 STOP#
C12 SERR#
C13 C/BE1#
C14 AD13
C15 AD10
C16 AD8
C17 VCC2
C18 AD5
C19 SMI#
C20 VCC3
C21 TEST0
C22 IRQ13
C23 MD32
C24 MD34
C25 MD3
C26 MD35
D1 GNT0#
D2 TDI
D3 REQ2#
D4 VSS
D5 C/BE3#
D6 VSS
D7 VCC2
D8 VSS
D9 VSS
D10 VCC3
D11 VSS
D12 VSS
D13 VSS
D14 VSS
D15 VSS
D16 VSS
D17 VCC2
D18 VSS
Pin
No. Signal Name
D19 VSS
D20 VCC3
D21 VSS
D22 MD0
D23 VSS
D24 MD4
D25 MD36
D26 TDN
E1 GNT2#
E2 SUSPA#
E3 REQ0#
E4 AD20
E23 MD6
E24 TDP
E25 MD5
E26 MD37
F1 TDO
F2 GNT1#
F3 TEST
F4 VSS
F23 VSS
F24 MD38
F25 MD7
F26 MD39
G1 VCC3
G2 VCC3
G3 VCC3
G4 VCC3
G23 VCC3
G24 VCC3
G25 VCC3
G26 VCC3
H1 TMS
H2 SUSP#
H3 REQ1#
H4 VSS
H23 VSS
H24 MD8
H25 MD40
H26 MD9
J1 FP_VSYNC
J2 TCLK
J3 RESET
J4 VSS
J23 VSS
J24 MD41
J25 MD10
J26 MD42
Pin
No. Signal Name
K1 VCC2
K2 VCC2
K3 VCC2
K4 VCC2
K23 VCC2
K24 VCC2
K25 VCC2
K26 VCC2
L1 CLKMODE1
L2 FP_HSYNC
L3 SERIALP
L4 VSS
L23 VSS
L24 MD11
L25 MD43
L26 MD12
M1 CLKMODE2
M2 VID_VAL
M3 CLKMODE0
M4 VSS
M23 VSS
M24 MD44
M25 MD13
M26 MD45
N1 VSS
N2 PIXEL1
N3 PIXEL0
N4 VSS
N23 VSS
N24 MD14
N25 MD46
N26 MD15
P1 VID_CLK
P2 PIXEL3
P3 PIXEL2
P4 VSS
P23 VSS
P24 MD47
P25 CASA#
P26 SYSCLK
R1 PIXEL4
R2 PIXEL5
R3 PIXEL6
R4 VSS
R23 VSS
R24 WEB#
R25 WEA#
R26 CASB#
Pin
No. Signal Name
T1 PIXEL7
T2 PIXEL8
T3 PIXEL9
T4 VSS
T23 VSS
T24 DQM0
T25 DQM4
T26 DQM1
U1 VCC3
U2 VCC3
U3 VCC3
U4 VCC3
U23 VCC3
U24 VCC3
U25 VCC3
U26 VCC3
V1 PIXEL10
V2 PIXEL11
V3 PIXEL12
V4 VSS
V23 VSS
V24 DQM5
V25 CS2#
V26 CS0#
W1 PIXEL13
W2 CRT_HSYNC
W3 PIXEL14
W4 VSS
W23 VSS
W24 RASA#
W25 RASB#
W26 MA0
Y1 VCC2
Y2 VCC2
Y3 VCC2
Y4 VCC2
Y23 VCC2
Y24 VCC2
Y25 VCC2
Y26 VCC2
AA1 PIXEL15
AA2 PIXEL16
AA3 CRT_VSYNC
AA4 VSS
AA23 VSS
AA24 MA1
AA25 MA2
AA26 MA3
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Signal Definitions (Continued)
Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number (Continued)
Pin
No. Signal Name
AB1 DCLK
AB2 PIXEL17
AB3 VID_DATA6
AB4 VID_DATA7
AB23 MA4
AB24 MA5
AB25 MA6
AB26 MA7
AC1 PCLK
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AC2 FLT#
AC3 VID_DATA4
AC4 VSS
AC5 NC
AC6 VSS
AC7 VCC2
AC8 VSS
AC9 VSS
AC10 VCC3
AC11 VSS
AC12 VSS
AC13 VSS
AC14 VSS
AC15 VSS
Pin
No. Signal Name
AC16 VSS
AC17 VCC2
AC18 VSS
AC19 VSS
AC20 VCC3
AC21 VSS
AC22 DQM6
AC23 VSS
AC24 MA8
AC25 MA9
AC26 MA10
AD1 VID_RDY
AD2 VID_DATA5
AD3 VID_DATA3
AD4 VID_DATA0
AD5 ENA_DISP
AD6 MD63
AD7 VCC2
AD8 MD62
AD9 MD29
AD10 VCC3
AD11 MD59
AD12 MD26
Pin
No. Signal Name
AD13 MD56
AD14 MD55
AD15 MD22
AD16 CKEB
AD17 VCC2
AD18 MD51
AD19 MD18
AD20 VCC3
AD21 MD48
AD22 DQM3
AD23 CS1#
AD24 MA11
AD25 BA0
AD26 BA1
AE1 VSS
AE2 VSS
AE3 VID_DATA2
AE4 SDCLK3
AE5 SDCLK1
AE6 RW_CLK
AE7 VCC2
AE8 SDCLK_IN
AE9 MD61
Pin
No. Signal Name
AE10 VCC3
AE11 MD28
AE12 MD58
AE13 MD25
AE14 MD24
AE15 MD54
AE16 MD21
AE17 VCC2
AE18 MD20
AE19 MD50
AE20 VCC3
AE21 MD17
AE22 DQM7
AE23 CS3#
AE24 MA12
AE25 VSS
AE26 VSS
AF1 VSS
AF2 VSS
AF3 VID_DATA1
AF4 SDCLK0
AF5 SDCLK2
AF6 MD31
Pin
No. Signal Name
AF7 VCC2
AF8 SDCLK_OUT
AF9 MD30
AF10 VCC3
AF11 MD60
AF12 MD27
AF13 MD57
AF14 VSS
AF15 MD23
AF16 MD53
AF17 VCC2
AF18 MD52
AF19 MD19
AF20 VCC3
AF21 MD49
AF22 MD16
AF23 DQM2
AF24 CKEA
AF25 VSS
AF26 VSS
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Signal Definitions (Continued)
Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name
Signal Name Type Pin No.1
AD0
I/O A21
AD1
I/O A22
AD2
I/O A19
AD3
I/O B19
AD4
I/O A18
AD5
I/O C18
AD6
I/O A16
AD7
I/O B16
AD8
I/O C16
AD9
I/O B15
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AD11
I/O C15
I/O A14
AD12
I/O B14
AD13
I/O C14
AD14
I/O B13
AD15
I/O A12
AD16
I/O A6
AD17
I/O C8
AD18
I/O B6
AD19
I/O C6
AD20
I/O E4
AD21
I/O A5
AD22
I/O B5
AD23
I/O C5
AD24
I/O A4
AD25
I/O B4
AD26
I/O C4
AD27
I/O A3
AD28
I/O B3
AD29
I/O C1
AD30
I/O C3
AD31
I/O C2
BA0 O AD25
BA1 O AD26
CASA#
O P25
CASB#
O R26
C/BE0#
I/O A15
C/BE1#
I/O C13
C/BE2#
I/O B8
C/BE3#
I/O D5
CKEA
O AF24
CKEB
O AD16
CLKMODE0
I
M3
CLKMODE1
I
L1
CLKMODE2
I
M1
CRT_HSYNC O
W2
CRT_VSYNC O
AA3
CS0#
O V26
CS1#
O AD23
CS2#
O V25
CS3#
O AE23
DCLK
I AB1
DEVSEL#
s/t/s A9 (PU)
Signal Name
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
ENA_DISP
FLT#
FP_HSYNC
FP_VSYNC
FRAME#
GNT0#
GNT1#
GNT2#
INTR
IRDY#
IRQ13
LOCK#
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
Type
O
O
O
O
O
O
O
O
O
I
O
O
s/t/s
O
O
O
I
s/t/s
O
s/t/s
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin No.1
T24
T26
AF23
AD22
T25
V24
AC22
AE22
AD5
AC2
L2
J1
A8 (PU)
D1
F2
E1
B18
C9 (PU)
C22
B11 (PU)
W26
AA24
AA25
AA26
AB23
AB24
AB25
AB26
AC24
AC25
AC26
AD24
AE24
D22
B23
A24
C25
D24
E25
E23
F25
H24
H26
J25
L24
L26
M25
N24
N26
AF22
AE21
AD19
AF19
Signal Name
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
NC
PAR
PCLK
PERR#
PIXEL0
PIXEL1
PIXEL2
PIXEL3
PIXEL4
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
--
I/O
O
s/t/s
O
O
O
O
O
Pin No.1
AE18
AE16
AD15
AF15
AE14
AE13
AD12
AF12
AE11
AD9
AF9
AF6
C23
B24
C24
C26
D25
E26
F24
F26
H25
J24
J26
L25
M24
M26
N25
P24
AD21
AF21
AE19
AD18
AF18
AF16
AE15
AD14
AD13
AF13
AE12
AD11
AF11
AE9
AD8
AD6
AC5
B12
AC1
A11 (PU)
N3
N2
P3
P2
R1
Signal Name
PIXEL5
PIXEL6
PIXEL7
PIXEL8
PIXEL9
PIXEL10
PIXEL11
PIXEL12
PIXEL13
PIXEL14
PIXEL15
PIXEL16
PIXEL17
RASA#
RASB#
REQ0#
REQ1#
REQ2#
RESET
RW_CLK
SDCLK_IN
SDCLK_OUT
SDCLK0
SDCLK1
SDCLK2
SDCLK3
SERIALP
SERR#
SMI#
STOP#
SUSP#
SUSPA#
SYSCLK
TCLK
TDI
TDN
TDO
TDP
TEST
TEST0
TEST1
TEST2
TEST3
TMS
TRDY#
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
Type Pin No.1
O R2
O R3
O T1
O T2
O T3
O V1
O V2
O V3
O W1
O W3
O AA1
O AA2
O AB2
O W24
O W25
I E3 (PU)
I H3 (PU)
I D3 (PU)
I J3
O AE6
I AE8
O AF8
O AF4
O AE5
O AF5
O AE4
O L3
OD C12 (PU)
I C19
s/t/s C11 (PU)
I H2 (PU)
O E2
I P26
I J2 (PU)
I D2 (PU)
O D26
O F1
O E24
I F3 (PD)
O C21
O B21
O A23
O B22
I H1 (PU)
s/t/s B9 (PU)
PWR
A7
PWR A17
PWR
B7
PWR B17
PWR
C7
PWR C17
PWR
D7
PWR D17
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Signal Definitions (Continued)
Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)
Signal Name Type Pin No.1
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
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VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
K1
K2
K3
K4
K23
K24
K25
K26
Y1
Y2
Y3
Y4
Y23
Y24
Y25
Y26
AC7
AC17
AD7
AD17
AE7
AE17
AF7
AF17
A10
A20
B10
B20
C10
C20
D10
D20
G1
G2
G3
G4
G23
Signal Name
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VID_CLK
VID_DATA0
VID_DATA1
VID_DATA2
VID_DATA3
VID_DATA4
VID_DATA5
VID_DATA6
VID_DATA7
VID_RDY
VID_VAL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Type
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
O
O
O
O
O
O
O
O
O
I
O
GND
GND
GND
GND
GND
GND
GND
Pin No.1
G24
G25
G26
U1
U2
U3
U4
U23
U24
U25
U26
AC10
AC20
AD10
AD20
AE10
AE20
AF10
AF20
P1
AD4
AF3
AE3
AD3
AC3
AD2
AB3
AB4
AD1
M2
A1
A2
A13
A25
A26
B1
B2
Signal Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin No.1
B25
B26
D4
D6
D8
D9
D11
D12
D13
D14
D15
D16
D18
D19
D21
D23
F4
F23
H4
H23
J4
J23
L4
L23
M4
M23
N1
N4
N23
P4
P23
R4
R23
T4
T23
V4
V23
Signal Name Type Pin No.1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
WEA#
WEB#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
O
O
W4
W23
AA4
AA23
AC4
AC6
AC8
AC9
AC11
AC12
AC13
AC14
AC15
AC16
AC18
AC19
AC21
AC23
AE1
AE2
AE25
AE26
AF1
AF2
AF14
AF25
AF26
R25
R24
1. PU/PD indicates pin is in-
ternally connected to a
weak (> 20-kohm) pull-up/-
down resistor.
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Signal Definitions (Continued)
Index Corner
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
A
VCC3
AD25
VSS
VCC2
AD16
VCC3 STOP# SERR#
VSS
AD11
AD8
VCC3
AD2
VCC2
VSS TEST0 VCC3
VSS
B
VSS
AD27 CBE3# AD21
AD19 CBE2# TRDY# LOCK# CBE1# AD13
AD9
AD6
AD3 SMI# AD1 TEST2 MD33 MD2
C
VCC3
AD31
AD26
AD23
VCC2
AD18 FRAME# VSS
PAR
VCC3
AD10
VSS
AD4
AD0
VCC2 IRQ13
MD1
MD34 VCC3
D
AD30
AD29
AD24
AD22
AD20
AD17 IRDY# PERR# AD14
AD12
AD7
INTR TEST1 TEST3 MD0 MD32 MD3 MD35
E
REQ0# REQ2# AD28 VSS VCC2 VCC2 VSS DEVSEL# AD15 VSS CBE0# AD5
VSS VCC2 VCC2 VSS
MD4 MD36 TDN
F
GNT0#
TDI
MD5 TDP
G
VSS CKMD2 VSS
VSS MD37 VSS
H
GNT2# SUSPA#
MD6 MD38
J
TDO VSS TEST
VCC2
VSS
MD7
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MD39
MD8
L
VCC2
VCC2
VCC2
VCC2 VCC2 VCC2
M
RESET SUSP#
MD40
MD9
N
VCC3
TMS
VSS
VSS MD41 VCC3
P
FPVSYNC TCLK
Q
SERIALP VSS
NC
Geode™
MD10 MD42
MD11 VSS MD43
R
CKMD1 FPHSYNC
S
CKMD0 VID_VAL PIX0
GX1
MD44 MD12
MD14 MD13 MD45
T
PIX1 PIX2
U
VSS
VCC3
VSS
Processor
MD15 MD46
VSS VCC3 VSS
V
PIX3 VID_CLK
SYSCLK MD47
W
PIX6 PIX5 PIX4
WEA# WEB# CASA#
X
NC PIX9
Y
PIX8 VSS PIX7
320 SPGA - Top View
DQM0 CASB#
DQM1 VSS DQM4
Z
NC PIX10
CS2# DQM5
AA
VCC3
PIX11
VSS
VSS
CS0#
VCC3
AB
PIX12 PIX13
RASB# RASA#
AC
VCC2
VCC2
VCC2
VCC2 VCC2 VCC2
AD
CRTHSYNC DCLK
MA2 MA0
AE
PIX14 VSS VCC2
VCC2
VSS
MA1
AF
PIX15 PIX16
MA4 MA3
AG
VSS
PIX17
VSS
VSS MA5 VSS
AH
CRTVSYNC VDAT6
MA10
MA8
MA6
AJ
PCLK FLT# VDAT5 VSS VCC2 MD31 VSS MD60 MD57 VSS MD22 MD52 VSS VCC2 VCC2 VSS BA1 MA9 MA7
AK
VRDY
VSS VDAT0 SDCLK0 SDCLK2 SDCLKIN MD29 MD27 MD56 MD55 MD21 MD20 MD50 MD16 DQM3 CS3#
VSS
BA0
AL
VCC2 VDAT4 VDAT2 SDCLK1 VCC2 RWCLK SDCLKOUT VSS
MD58 VCC3 MD23
VSS
MD19
MD49
VCC2
DQM6 CKEA
MA11
VCC3
AM
VDAT7 VDAT3 ENDIS SDCLK3 MD63 MD30 MD61 MD59 MD25 MD24 MD53 MD51 MD18 MD48 DQM7 DQM2 MA12
NC
AN
VSS
VCC2 VDAT1
VSS
VCC2 MD62 VCC3 MD28 MD26
VSS
MD54 CKEB VCC3 MD17 VCC2
VSS
CS1#
VCC3
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
Y
Z
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Note: Signal names have been abbreviated in this figure due to space constraints.
= Denotes GND terminal
= Denotes PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
Figure 2-3. 320 SPGA Pin Assignment Diagram
(For order information, refer to Section A.1 “Order Information” on page 246.)
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26
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Signal Definitions (Continued)
Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number
Pin
No. Signal Name
A3 VCC3
A5 AD25
A7 VSS
A9 VCC2
A11 AD16
A13 VCC3
A15 STOP#
A17 SERR#
A19 VSS
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A21 AD11
A23 AD8
A25 VCC3
A27 AD2
A29 VCC2
A31 VSS
A33 TEST0
A35 VCC3
A37 VSS
B2 VSS
B4 AD27
B6 C/BE3#
B8 AD21
B10 AD19
B12 C/BE2#
B14 TRDY#
B16 LOCK#
B18 C/BE1#
B20 AD13
B22 AD9
B24 AD6
B26 AD3
B28 SMI#
B30 AD1
B32 TEST2
B34 MD33
B36 MD2
C1 VCC3
C3 AD31
C5 AD26
C7 AD23
C9 VCC2
C11 AD18
C13 FRAME#
C15 VSS
C17 PAR
C19 VCC3
C21 AD10
C23 VSS
Pin
No. Signal Name
C25 AD4
C27 AD0
C29 VCC2
C31 IRQ13
C33 MD1
C35 MD34
C37 VCC3
D2 AD30
D4 AD29
D6 AD24
D8 AD22
D10 AD20
D12 AD17
D14 IRDY#
D16 PERR#
D18 AD14
D20 AD12
D22 AD7
D24 INTR
D26 TEST1
D28 TEST3
D30 MD0
D32 MD32
D34 MD3
D36 MD35
E1 REQ0#
E3 REQ2#
E5 AD28
E7 VSS
E9 VCC2
E11 VCC2
E13 VSS
E15 DEVSEL#
E17 AD15
E19 VSS
E21 C/BE0#
E23 AD5
E25 VSS
E27 VCC2
E29 VCC2
E31 VSS
E33 MD4
E35 MD36
E37 TDN
F2 GNT0#
F4 TDI
F34 MD5
F36 TDP
Pin
No. Signal Name
G1 VSS
G3 CLKMODE2
G5 VSS
G33 VSS
G35 MD37
G37 VSS
H2 GNT2#
H4 SUSPA#
H34 MD6
H36 MD38
J1 TDO
J3 VSS
J5 TEST
J33 VCC2
J35 VSS
J37 MD7
K2 REQ1#
K4 GNT1#
K34 MD39
K36 MD8
L1 VCC2
L3 VCC2
L5 VCC2
L33 VCC2
L35 VCC2
L37 VCC2
M2 RESET
M4 SUSP#
M34 MD40
M36 MD9
N1 VCC3
N3 TMS
N5 VSS
N33 VSS
N35 MD41
N37 VCC3
P2 FP_VSYNC
P4 TCLK
P34 MD10
P36 MD42
Q1 SERIALP
Q3 VSS
Q5 NC
Q33 MD11
Q35 VSS
Q37 MD43
R2 CLKMODE1
R4 FP_HSYNC
Pin
No. Signal Name
R34 MD44
R36 MD12
S1 CLKMODE0
S3 VID_VAL
S5 PIXEL0
S33 MD14
S35 MD13
S37 MD45
T2 PIXEL1
T4 PIXEL2
T34 MD15
T36 MD46
U1 VSS
U3 VCC3
U5 VSS
U33 VSS
U35 VCC3
U37 VSS
V2 PIXEL3
V4 VID_CLK
V34 SYSCLK
V36 MD47
W1 PIXEL6
W3 PIXEL5
W5 PIXEL4
W33 WEA#
W35 WEB#
W37 CASA#
X2 NC
X4 PIXEL9
X34 DQM0
X36 CASB#
Y1 PIXEL8
Y3 VSS
Y5 PIXEL7
Y33 DQM1
Y35 VSS
Y37 DQM4
Z2 NC
Z4 PIXEL10
Z34 CS2#
Z36 DQM5
AA1 VCC3
AA3 PIXEL11
AA5 VSS
AA33 VSS
AA35 CS0#
AA37 VCC3
Pin
No. Signal Name
AB2 PIXEL12
AB4 PIXEL13
AB34 RASB#
AB36 RASA#
AC1 VCC2
AC3 VCC2
AC5 VCC2
AC33 VCC2
AC35 VCC2
AC37 VCC2
AD2 CRT_HSYNC
AD4 DCLK
AD34 MA2
AD36 MA0
AE1 PIXEL14
AE3 VSS
AE5 VCC2
AE33 VCC2
AE35 VSS
AE37 MA1
AF2 PIXEL15
AF4 PIXEL16
AF34 MA4
AF36 MA3
AG1 VSS
AG3 PIXEL17
AG5 VSS
AG33 VSS
AG35 MA5
AG37 VSS
AH2 CRT_VSYNC
AH4 VID_DATA6
AH32 MA10
AH34 MA8
AH36 MA6
AJ1 PCLK
AJ3 FLT#
AJ5 VID_DATA5
AJ7 VSS
AJ9 VCC2
AJ11 MD31
AJ13 VSS
AJ15 MD60
AJ17 MD57
AJ19 VSS
AJ21 MD22
AJ23 MD52
AJ25 VSS
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Signal Definitions (Continued)
Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number (Continued)
Pin
No. Signal Name
AJ27 VCC2
AJ29 VCC2
AJ31 VSS
AJ33 BA1
AJ35 MA9
AJ37 MA7
AK2 VID_RDY
AK4 VSS
AK6 VID_DATA0
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AK8 SDCLK0
AK10 SDCLK2
AK12 SDCLK_IN
AK14 MD29
AK16 MD27
AK18 MD56
AK20 MD55
AK22 MD21
Pin
No. Signal Name
AK24 MD20
AK26 MD50
AK28 MD16
AK30 DQM3
AK32 CS3#
AK34 VSS
AK36 BA0
AL1 VCC2
AL3 VID_DATA4
AL5 VID_DATA2
AL7 SDCLK1
AL9 VCC2
AL11 RW_CLK
AL13 SDCLK_OUT
AL15 VSS
AL17 MD58
AL19 VCC3
Pin
No. Signal Name
AL21 MD23
AL23 VSS
AL25 MD19
AL27 MD49
AL29 VCC2
AL31 DQM6
AL33 CKEA
AL35 MA11
AL37 VCC3
AM2 VID_DATA7
AM4 VID_DATA3
AM6 ENA_DISP
AM8 SDCLK3
AM10 MD63
AM12 MD30
AM14 MD61
AM16 MD59
Pin
No. Signal Name
AM18 MD25
AM20 MD24
AM22 MD53
AM24 MD51
AM26 MD18
AM28 MD48
AM30 DQM7
AM32 DQM2
AM34 MA12
AM36 NC
AN1 VSS
AN3 VCC2
AN5 VID_DATA1
AN7 VSS
AN9 VCC2
AN11 MD62
AN13 VCC3
Pin
No. Signal Name
AN15 MD28
AN17 MD26
AN19 VSS
AN21 MD54
AN23 CKEB
AN25 VCC3
AN27 MD17
AN29 VCC2
AN31 VSS
AN33 CS1#
AN35 VCC3
AN37 VSS
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Signal Definitions (Continued)
Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name
Signal Name Type Pin. No.1
AD0
I/O C27
AD1
I/O B30
AD2
I/O A27
AD3
I/O B26
AD4
I/O C25
AD5
I/O E23
AD6
I/O B24
AD7
I/O D22
AD8
I/O A23
AD9
I/O B22
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AD11
I/O C21
I/O A21
AD12
I/O D20
AD13
I/O B20
AD14
I/O D18
AD15
I/O E17
AD16
I/O A11
AD17
I/O D12
AD18
I/O C11
AD19
I/O B10
AD20
I/O D10
AD21
I/O B8
AD22
I/O D8
AD23
I/O C7
AD24
I/O D6
AD25
I/O A5
AD26
I/O C5
AD27
I/O B4
AD28
I/O E5
AD29
I/O D4
AD30
I/O D2
AD31
I/O C3
BA0 O AK36
BA1 O AJ33
CASA#
O W37
CASB#
O X36
C/BE0#
I/O E21
C/BE1#
I/O B18
C/BE2#
I/O B12
C/BE3#
I/O B6
CKEA
O AL33
CKEB
O AN23
CLKMODE0
I
S1
CLKMODE1
I
R2
CLKMODE2
I
G3
CRT_HSYNC O
AD2
CRT_VSYNC O
AH2
CS0#
O AA35
CS1#
O AN33
CS2#
O Z34
CS3#
O AK32
DCLK
I AD4
DEVSEL#
s/t/s E15 (PU)
Signal Name
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
ENA_DISP
FLT#
FP_HSYNC
FP_VSYNC
FRAME#
GNT0#
GNT1#
GNT2#
INTR
IRDY#
IRQ13
LOCK#
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
Type Pin. No.1
O X34
O Y33
O AM32
O AK30
O Y37
O Z36
O AL31
O AM30
O AM6
I AJ3
O R4
O P2
s/t/s C13 (PU)
O F2
O K4
O H2
I D24
s/t/s D14 (PU)
O C31
s/t/s B16 (PU)
O AD36
O AE37
O AD34
O AF36
O AF34
O AG35
O AH36
O AJ37
O AH34
O AJ35
O AH32
O AL35
O AM34
I/O D30
I/O C33
I/O B36
I/O D34
I/O E33
I/O F34
I/O H34
I/O J37
I/O K36
I/O M36
I/O P34
I/O Q33
I/O R36
I/O S35
I/O S33
I/O T34
I/O AK28
I/O AN27
I/O AM26
I/O AL25
Signal Name
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
NC
NC
NC
NC
NC
NC
PAR
PCLK
PERR#
Type Pin. No.1
I/O AK24
I/O AK22
I/O AJ21
I/O AL21
I/O AM20
I/O AM18
I/O AN17
I/O AK16
I/O AN15
I/O AK14
I/O AM12
I/O AJ11
I/O D32
I/O B34
I/O C35
I/O D36
I/O E35
I/O G35
I/O H36
I/O K34
I/O M34
I/O N35
I/O P36
I/O Q37
I/O R34
I/O S37
I/O T36
I/O V36
I/O AM28
I/O AL27
I/O AK26
I/O AM24
I/O AJ23
I/O AM22
I/O AN21
I/O AK20
I/O AK18
I/O AJ17
I/O AL17
I/O AM16
I/O AJ15
I/O AM14
I/O AN11
I/O AM10
-- E37
-- F36
-- Q5
-- X2
-- Z2
-- AM36
I/O C17
O AJ1
s/t/s D16 (PU)
Signal Name
PIXEL0
PIXEL1
PIXEL2
PIXEL3
PIXEL4
PIXEL5
PIXEL6
PIXEL7
PIXEL8
PIXEL9
PIXEL10
PIXEL11
PIXEL12
PIXEL13
PIXEL14
PIXEL15
PIXEL16
PIXEL17
RASA#
RASB#
REQ0#
REQ1#
REQ2#
RESET
RW_CLK
SDCLK_IN
SDCLK_OUT
SDCLK0
SDCLK1
SDCLK2
SDCLK3
SERIALP
SERR#
SMI#
STOP#
SUSP#
SUSPA#
SYSCLK
TCLK
TDI
TDN
TDO
TDP
TEST
TEST0
TEST1
TEST2
TEST3
TDN
TDP
TMS
TRDY#
VCC2
Type Pin. No.1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
O
I
O
O
O
O
O
O
OD
I
s/t/s
I
O
I
I
I
O
O
O
I
O
O
O
O
O
O
I
s/t/s
PWR
S5
T2
T4
V2
W5
W3
W1
Y5
Y1
X4
Z4
AA3
AB2
AB4
AE1
AF2
AF4
AG3
AB36
AB34
E1 (PU)
K2 (PU)
E3 (PU)
M2
AL11
AK12
AL13
AK8
AL7
AK10
AM8
Q1
A17 (PU)
B28
A15 (PU)
M4 (PU)
H4
V34
P4 (PU)
F4 (PU)
E37
J1
F36
J5 (PD)
A33
D26
B32
D28
E37
F36
N3 (PU)
B14 (PU)
A9
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Signal Definitions (Continued)
Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)
Signal Name Type Pin. No.1
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
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VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
A29
C9
C29
E9
E11
E27
E29
J33
L1
L3
L5
L33
L35
L37
AC1
AC3
AC5
AC33
AC35
AC37
AE5
AE33
AJ9
AJ27
AJ29
AL1
AL9
AL29
AN3
Signal Name
VCC2
VCC2
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VID_CLK
VID_DATA0
VID_DATA1
VID_DATA2
VID_DATA3
VID_DATA4
VID_DATA5
VID_DATA6
VID_DATA7
Type Pin. No.1
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
O
O
O
O
O
O
O
O
O
AN9
AN29
A3
A13
A25
A35
C1
C19
C37
N1
N37
U3
U35
AA1
AA37
AL19
AL37
AN13
AN25
AN35
V4
AK6
AN5
AL5
AM4
AL3
AJ5
AH4
AM2
Signal Name
VID_RDY
VID_VAL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Type Pin. No.1
I
O
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AK2
S3
A7
A19
A31
A37
B2
C15
C23
E7
E13
E19
E25
E31
G1
G5
G33
G37
J3
J35
N5
N33
Q3
Q35
U1
U5
U33
U37
Y3
Signal Name Type Pin. No.1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
WEA#
WEB#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
O
O
Y35
AA5
AA33
AE3
AE35
AG1
AG5
AG33
AG37
AJ7
AJ13
AJ19
AJ25
AJ31
AK4
AK34
AL15
AL23
AN1
AN7
AN19
AN31
AN37
W33
W35
1. PU/PD indicates pin is
internally connected to a
weak (> 20-kohm)
pull-up/down resistor.
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