IDT74FCT821C (Integrated Device Technology)
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

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®
Integrated Device Technology, Inc.
HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS
IDT54/74FCT821A/B/C
IDT54/74FCT823A/B/C
IDT54/74FCT824A/B/C
IDT54/74FCT825A/B/C
FEATURES:
• Equivalent to AMD’s Am29821-25 bipolar registers in
pinout/function, speed and output drive over full tem-
perature and voltage supply extremes
• IDT54/74FCT821A/823A/824A/825A equivalent to
FASTspeed
• IDT54/74FCT821B/823B/824B/825B 25% faster than
FAST
• IDT54/74FCT821C/823C/824C/825C 40% faster than
FAST
• Buffered common Clock Enable (EN) and asynchronous
Clear input (CLR)
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT820 series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The IDT54/
74FCT821 are buffered, 10-bit wide versions of the popular
‘374 function. The IDT54/74FCT823 and IDT54/74FCT824
are 9-bit wide buffered registers with Clock Enable (EN) and
Clear (CLR) – ideal for parity bus interfacing in high-perform-
ance microprogrammed systems. The IDT54/74FCT825 are
8-bit buffered registers with all the ‘823 controls plus multiple
enables (OE1, OE2, OE3) to allow multiuser control of the
interface, e.g., CS, DMA and RD/WR. They are ideal for use
as an output port requiring HIGH IOL/IOH.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT821/823/825
D0 DN
EN
IDT54/74FCT824
D0
EN
DN
CLR
CP
D CL Q
CP Q
D CL Q
CP Q
CLR
CP
OE
Y0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
YN
2608 cnv* 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.19
OE
D CL Q
CP Q
D CL Q
CP Q
Y0 YN
2608 cnv* 02
MAY 1992
DSC-4618/2
1


IDT74FCT821C (Integrated Device Technology)
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

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IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
PIN CONFIGURATIONS
IDT54/74FCT821 10-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOGIC SYMBOLS
OE 1
24 VCC INDEX
D0 2
23 Y0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
3 22
4 P24-1 21
5 D24-1 20
6 E24-1 19
7 & 18
8 SO24-2 17
9 16
10 15
11 14
12 13
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
CP
D2
4
5
3
2
1
28 27 26
25
Y2
10
D
D
D3 6
D4 7
24 Y3
23 Y4
Q
CP
NC 8
L28-1
22 NC CP
D5 9
D6 10
21 Y5
20 Y6
OE
D7 11
19 Y7
1213 14 15 16 17 18
10
Y
DIP/SOIC/CERPACK
TOP VIEW
IDT54/74FCT823/824 9-BIT REGISTERS
LCC
TOP VIEW
OE 1
24 VCC INDEX
D0 2
23 Y0
D1
D2
D3
D4
D5
D6
D7
D8
CLR
GND
3 22
4 P24-1 21
5 D24-1 20
6 SO24-2 19
7 & 18
8 E24-1 17
9 16
10 15
11 14
12 13
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN
CP
D2
4
5
3
2
1
28 27 26
25
D3 6
24
D4 7
23
NC 8
D5 9
L28-1
22
21
D6 10
20
D7 11
19
1213 14 15 16 17 18
9
Y2 D
Y3
Y4
NC CP
Y5 EN
Y6 CLR
Y7 OE
D
Q
CP EN CLR
2608 cnv* 03
9
Y
DIP/SOIC/CERPACK
TOP VIEW
IDT54/74FCT825 8-BIT REGISTER
LCC
TOP VIEW
OE1
OE2
D0
D1
D2
D3
D4
D5
D6
D7
CLR
GND
1 24 VCC INDEX
2 23 OE3
3 22
4 P24-1 21
5 D24-1 20
6 E24-1 19
7 & 18
8 SO24-2 17
9 16
Y0
Y1
Y2
Y3
Y4
Y5
Y6
D1
4
5
3
2
1
28 27 26
25
D2 6
24
D3 7
23
NC 8
D4 9
L28-1
22
21
D5 10
20
10 15 Y7
11 14 EN
D6 11
19
1213 14 1516 17 18
12 13 CP
8
D
Y1
Y2 CP
Y3 EN
NC CLR
Y4 OE1
Y5
Y6 OE2
OE3
D
Q
CP EN CLR
2608 cnv* 04
8
Y
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
2608 cnv* 05
7.19 2


IDT74FCT821C (Integrated Device Technology)
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

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IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT SELECTOR GUIDE
Non-inverting
Inverting
Device
10-Bit
9-Bit
8-Bit
54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C
54/74FCT824A/B/C
2608 tbl 01
PIN DESCRIPTION
Name
DI
CLR
CP
YI , YI
I/O Description
I The D flip-flop data inputs.
I For both inverting and non-inverting
registers, when the clear input is LOW
and OE is LOW, the QI outputs are
LOW. When the clear input is HIGH,
data can be entered into the register.
I Clock Pulse for the Register; enters
data into the register on the LOW-to-
HIGH transition.
O The register three-state outputs.
EN I Clock Enable. When the clock enable
is LOW, data on the D I input is
transferred to the QI output on the
LOW-to-HIGH clock transition. When
the clock enable is HIGH, the QI
outputs do not change state,
regardless of the data or clock input
transitions.
OE I Output Control. When the OE input is
HIGH, the Y I outputs are in the high
impedance state. When the OE input is
LOW, the TRUE register data is
present at the Y I outputs.
2608 tbl 10
FUNCTION TABLE(1)
IDT54/74FCT821/823/825
Inputs
Internal/
Outputs
OE
CLR
EN
DI
CP
QI
YI Function
H H L L L Z High Z
HH LH H Z
HLXXX L Z
Clear
L LXXX L L
H H H X X NC Z
Hold
L H H X X NC NC
HH L L L Z
HH LH H Z
LHL L L L
LH LH HH
Load
NOTE:
2608 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, = LOW-to-HIGH
Transition, Z = High Impedance
FUNCTION TABLE(1)
IDT54/74FCT824
Inputs
Internal/
Outputs
OE
CLR
EN
DI
CP
QI
YI Function
H H L L H Z High Z
HH LH L Z
HLXXX L Z
L LXXX L L
Clear
H H H X X NC Z
L H H X X NC NC
Hold
HH L L H Z
HH LH L Z
LH L L HH
LHLHL L
Load
NOTE:
2608 tbl 03
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, = LOW-to-
HIGH Transition, Z = High Impedance
7.19 3


IDT74FCT821C (Integrated Device Technology)
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

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IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
–0.5 to +7.0
–0.5 to VCC
TA Operating
0 to +70
Temperature
TBIAS Temperature
–55 to +125
Under Bias
TSTG Storage
–55 to +125
Temperature
PT
Power Dissipation
0.5
Military
–0.5 to +7.0
–0.5 to VCC
–55 to +125
–65 to +135
–65 to +150
0.5
Unit
V
V
°C
°C
°C
W
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input
VIN = 0V
6 10 pF
Capacitance
COUT Output
VOUT = 0V
8 12 pF
Capacitance
NOTE:
2608 tbl 05
1. This parameter is measured at characterization but not tested.
IOUT
DC Output
Current
120 120 mA
NOTES:
2608 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2)
VIH Input HIGH Level
Guaranteed Logic HIGH Level
2.0 —
Max.
Unit
V
VIL Input LOW Level
Guaranteed Logic LOW Level
— — 0.8 V
II H Input HIGH Current
II L Input LOW Current
VCC = Max.
VI = VCC
VI = 2.7V
VI = 0.5V
— — 5 µA
— — 5(4)
— — –5(4)
VI = GND
— — –5
IOZH
IOZL
Off State (High Impedance)
Output Current
VCC = Max.
VO = VCC
VO = 2.7V
VO = 0.5V
— — 10 µA
— — 10(4)
— — –10(4)
VO = GND
— — –10
VIK Clamp Diode Voltage
IOS Short Circuit Current
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
— –0.7 –1.2 V
–75 –120 — mA
VOH Output HIGH Voltage
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
VCC = Min.
IOH = –300µA
VHC
VHC
VCC
VCC
V
VIN = VIH or VIL
IOH = –15mA MIL.
2.4 4.3 —
IOH = –24mA COM'L. 2.4 4.3
VOL Output LOW Voltage
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VCC = Min.
IOL = 300µA
— GND VLC
V
— GND VLC(4)
VIN = VIH or VIL
IOL = 32mA MIL.
— 0.3 0.5
IOL = 48mA COM'L.
— 0.3 0.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
2608 tbl 06
7.19 4


IDT74FCT821C (Integrated Device Technology)
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

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IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max. Unit
ICC
Quiescent Power Supply Current VCC = Max.
VIN VHC; V IN VLC
— 0.2 1.5 mA
ICC
Quiescent Power Supply Current VCC = Max.
TTL Inputs HIGH
VIN = 3.4V(3)
— 0.5 2.0 mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
VIN VHC
VIN VLC
— 0.15 0.25 mA/
MHz
OE = EN = GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
VIN VHC
— 1.7 4.0 mA
Outputs Open
VIN VLC
fCP = 10MHz
(FCT)
50% Duty Cycle
OE = EN = GND
VIN = 3.4V
— 2.2 6.0
One Bit Toggling
VIN = GND
at f i = 5MHz
50% Duty Cycle
VCC = Max.
VIN VHC
— 4.0 7.8(5)
Outputs Open
VIN VLC
fCP = 10MHz
(FCT)
50% Duty Cycle
OE = EN = GND
VIN = 3.4V
— 6.2 16.8(5)
Eight Bits Toggling
VIN = GND
at f i = 2.5MHz
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
2608 tbl 07
7.19 5


IDT74FCT821C (Integrated Device Technology)
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

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IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Parameter
tPLH
tPHL
tSU
tH
tSU
tH
tPHL
IDT54/74FCT821A/
IDT54/74FCT821B/
IDT54/74FCT821C/
823A/824A/825A
823B/824B/825B
823C/824C/825C
Test
Com'l. Mil. Com'l. Mil. Com'l. Mil.
Description
Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
Propagation Delay
CP to Y I (OE = LOW)
CL = 50pF
RL = 500
CL = 300pF(3)
RL = 500
— 10.0 — 11.5 — 7.5
— 20.0 — 20.0 — 15.0
— 8.5
— 16.0
— 6.0 — 7.0 ns
— 12.5 — 13.5
Set-up Time HIGH or LOW CL = 50pF
D i to CP
RL = 500
4.0 — 4.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns
Hold Time HIGH or LOW
D I to CP
2.0 — 2.0 — 1.5 — 1.5 — 1.5 — 1.5 — ns
Set-up Time HIGH or LOW
EN to CP
4.0 — 4.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns
Hold Time HIGH or LOW
EN to CP
2.0 — 2.0 — 0 — 0 — 0 — 0 — ns
Propagation Delay, CLR to
YI
— 14.0 — 15.0 — 9.0 — 9.5 — 8.0 — 8.5 ns
tREM
Recovery Time CLR to CP
6.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns
tW CP Pulse Width
HIGH or LOW
7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns
tW CLR Pulse Width
LOW
6.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns
tPZH
Output Enable Time OE
CL = 50pF — 12.0 — 13.0 — 8.0 — 9.0 — 7.0 — 8.0 ns
tPZL
to YI
RL = 500
CL = 300pF(3) — 23.0 — 25.0 — 15.0 — 16.0 — 12.5 — 13.5
RL = 500
tPHZ
tPLZ
Output Disable Time OE
to YI
CL = 5pF(3)
RL = 500
— 7.0 — 8.0 — 6.5 — 7.0 — 6.2 — 6.2 ns
CL = 50pF
RL = 500
— 8.0 — 9.0 — 7.5 — 8.0 — 6.5 — 6.5
NOTES:
2608 tbl* 08
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
7.19 6


IDT74FCT821C (Integrated Device Technology)
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

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IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC 7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500
50pF
500
RT CL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
2608 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t SU
t SU
tH
t REM
tH
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
3V
1.5V
0V
1.5V
tW
1.5V
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
t PLH
t PHL
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
t PZL
SWITCH
CLOSED
t PZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3.5V
1.5V
1.5V
0V
DISABLE
tPLZ
3V
1.5V
0V
3.5V
t PHZ
0.3V V OL
0.3V V OH
0V
NOTES
2608 drw 01
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate 1.0 MHz; ZO 50; tF 2.5ns;
tR 2.5ns.
7.19 7


IDT74FCT821C (Integrated Device Technology)
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

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IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
ORDERING INFORMATION
2523IDTcnv*XX11 FCT XXXX
Temp. Range
Device Type
X
Package
X
Process
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Blank
B
P
D
E
L
SO
821A
821B
821C
823A
823B
823C
824A
824B
824C
825A
825B
825C
54
74
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
10-Bit Non-Inverting Register
Fast 10-Bit Non-Inverting Register
Super Fast 10-Bit Non-Inverting Register
9-Bit Non-Inverting Register
Fast 9-Bit Non-Inverting Register
Super Fast 9-Bit Non-Inverting Register
9-Bit Inverting Register
Fast 9-Bit Inverting Register
Super Fast 9-Bit Inverting Register
8-Bit Non-Inverting Register
Fast 8-Bit Non-Inverting Register
Super Fast 8-Bit Non-Inverting Register
–55°C to +125°C
0°C to +70°C
2608 cnv* 11
7.19 8




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