MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F64G08CBAA[A/B], MT29F128G08C[E/F]AAA, MT29F128G08CFAAB,
MT29F256G08C[J/K/M]AAA, MT29F256G08CJAAB, MT29F512G08CUAAA,
MT29F64G08CBCAB, MT29F128G08CECAB, MT29F256G08C[K/M]CAB,
MT29F512G08CUCAB
Features
Open NAND Flash Interface (ONFI) 2.2-compliant1
Multiple-level cell (MLC) technology
Organization
Page size x8: 8640 bytes (8192 + 448 bytes)
Block size: 256 pages (2048K + 112K bytes)
Plane size: 2 planes x 2048 blocks per plane
Device size: 64Gb: 4096 blocks;
128Gb: 8192 blocks;
256Gb: 16,384 blocks;
512Gb: 32,786 blocks
Synchronous I/O performance
Up to synchronous timing mode 52
Clock rate: 10ns (DDR)
Read/write throughput per pin: 200 MT/s
Asynchronous I/O performance
Up to asynchronous timing mode 5
tRC/tWC: 20ns (MIN)
Up to asynchronous timing mode 5
Read/write throughput per pin: 50 MT/s
Array performance
Read page: 75µs (MAX)
Program page: 1300µs (TYP)
Erase block: 3.8ms (TYP)
Operating Voltage Range
VCC: 2.7–3.6V
VCCQ: 1.7–1.95V, 2.7–3.6V
Command set: ONFI NAND Flash Protocol
Advanced Command Set
Program cache
Read cache sequential
Read cache random
One-time programmable (OTP) mode
Multi-plane commands
Multi-LUN operations
Read unique ID
Copyback
First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 109).
RESET (FFh) required as first command after power-
on
Operation status byte provides software method for
detecting
Operation completion
Pass/fail condition
Write-protect status
Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
Copyback operations supported within the plane
from which data is read
Quality and reliability
Data retention: JESD47G compliant; see qualifica-
tion report
Endurance: 3000 PROGRAM/ERASE cycles
Operating temperature:
Commercial: 0°C to +70°C
Industrial (IT): –40ºC to +85ºC
Package
52-pad LGA
48-pin TSOP
100-ball BGA
Notes:
1. The ONFI 2.2 specification is available at
www.onfi.org.
2. BGA devices up to Synchronous timing
mode 5. TSOP devices up to Synchronous tim-
ing mode 4.
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1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.


MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 64G 08 C B A A A WP
Micron Technology
NAND Flash
29F = NAND Flash memory
Density
64G = 64Gb
128G = 128Gb
256G = 256Gb
512G = 512Gb
Device Width
08 = 8 bits
Level
Bit/Cell
C 2-bit
Classification
Die # of CE# # of R/B# I/O
B1
1
1 Common
E2
2
2 Separate
F2
2
2 Common
J4
2
2 Common
K4
2
2 Separate
M4
4
4 Separate
U8
4
4 Separate
Operating Voltage Range
A = VCC: 3.3V (2.7–3.6V), VCCQ: 3.3V (2.7–3.6V)
C = VCC: 3.3V (2.7–3.6V), VCCQ: 1.8V (1.7–1.95V)
Note: 1. Pb-free package.
ES :A
Design Revision
A = First revision
Production Status
Blank = Production
ES = Engineering sample
Reserved for Future Use
Blank
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Speed Grade (synchronous mode only)
-12 = 166 MT/s
-10 = 200 MT/s
Package Code
C5 = 52-pad VLGA 14mm x 18mm x 1.0mm1
H1 = 100-ball VBGA 12mm x 18mm x 1.0mm1
H2 = 100-ball TBGA 12mm x 18mm x 1.2mm1
H3 = 100-ball LBGA 12mm x 18mm x 1.4mm1
WP = 48-pin TSOP1 (CPL)
Interface
A = Async only
B = Sync/Async
Generation Feature Set
A = First set of device features
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
Contents
General Description ......................................................................................................................................... 9
Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9
Signal Assignments ......................................................................................................................................... 11
Package Dimensions ...................................................................................................................................... 14
Architecture ................................................................................................................................................... 19
Device and Array Organization ....................................................................................................................... 20
Bus Operation – Asynchronous Interface ........................................................................................................ 27
Asynchronous Enable/Standby ................................................................................................................... 27
Asynchronous Bus Idle ............................................................................................................................... 27
Asynchronous Commands .......................................................................................................................... 28
Asynchronous Addresses ............................................................................................................................ 29
Asynchronous Data Input ........................................................................................................................... 30
Asynchronous Data Output ........................................................................................................................ 31
Write Protect .............................................................................................................................................. 32
Ready/Busy# .............................................................................................................................................. 32
Bus Operation – Synchronous Interface ........................................................................................................... 37
Synchronous Enable/Standby ..................................................................................................................... 38
Synchronous Bus Idle/Driving .................................................................................................................... 38
Synchronous Commands ........................................................................................................................... 39
Synchronous Addresses .............................................................................................................................. 40
Synchronous DDR Data Input ..................................................................................................................... 41
Synchronous DDR Data Output .................................................................................................................. 42
Write Protect .............................................................................................................................................. 44
Ready/Busy# .............................................................................................................................................. 44
Device Initialization ....................................................................................................................................... 45
Activating Interfaces ....................................................................................................................................... 46
Activating the Asynchronous Interface ........................................................................................................ 46
Activating the Synchronous Interface .......................................................................................................... 46
Command Definitions .................................................................................................................................... 48
Reset Operations ............................................................................................................................................ 50
RESET (FFh) ............................................................................................................................................... 50
SYNCHRONOUS RESET (FCh) .................................................................................................................... 51
RESET LUN (FAh) ....................................................................................................................................... 52
Identification Operations ................................................................................................................................ 53
READ ID (90h) ............................................................................................................................................ 53
READ ID Parameter Tables ......................................................................................................................... 54
READ PARAMETER PAGE (ECh) .................................................................................................................. 55
Parameter Page Data Structure Tables ..................................................................................................... 56
READ UNIQUE ID (EDh) ............................................................................................................................ 67
Configuration Operations ............................................................................................................................... 68
SET FEATURES (EFh) ................................................................................................................................. 68
GET FEATURES (EEh) ................................................................................................................................. 69
Status Operations ........................................................................................................................................... 73
READ STATUS (70h) ................................................................................................................................... 74
READ STATUS ENHANCED (78h) ............................................................................................................... 75
Column Address Operations ........................................................................................................................... 76
CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 76
CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 77
CHANGE WRITE COLUMN (85h) ................................................................................................................ 78
CHANGE ROW ADDRESS (85h) ................................................................................................................... 79
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
Read Operations ............................................................................................................................................. 81
READ MODE (00h) ..................................................................................................................................... 83
READ PAGE (00h-30h) ................................................................................................................................ 84
READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 85
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 86
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 88
READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 89
Program Operations ....................................................................................................................................... 91
PROGRAM PAGE (80h-10h) ........................................................................................................................ 91
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 93
PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................. 95
Erase Operations ............................................................................................................................................ 97
ERASE BLOCK (60h-D0h) ............................................................................................................................ 97
ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 98
Copyback Operations ..................................................................................................................................... 99
COPYBACK READ (00h-35h) ...................................................................................................................... 100
COPYBACK PROGRAM (85h–10h) .............................................................................................................. 101
COPYBACK READ MULTI-PLANE (00h-32h) .............................................................................................. 101
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 102
One-Time Programmable (OTP) Operations ................................................................................................... 103
PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 104
PROTECT OTP AREA (80h-10h) .................................................................................................................. 105
READ OTP PAGE (00h-30h) ........................................................................................................................ 106
Multi-Plane Operations ................................................................................................................................. 107
Multi-Plane Addressing ............................................................................................................................. 107
Interleaved Die (Multi-LUN) Operations ........................................................................................................ 108
Error Management ........................................................................................................................................ 109
Shared Pages ................................................................................................................................................. 110
Output Drive Impedance ............................................................................................................................... 112
AC Overshoot/Undershoot Specifications ...................................................................................................... 115
Synchronous Input Slew Rate ........................................................................................................................ 116
Output Slew Rate ........................................................................................................................................... 117
Electrical Specifications ................................................................................................................................. 118
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 120
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) .................................. 121
Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) ............................................... 121
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 122
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 124
Electrical Specifications – Array Characteristics .............................................................................................. 127
Asynchronous Interface Timing Diagrams ...................................................................................................... 128
Synchronous Interface Timing Diagrams ........................................................................................................ 139
Revision History ............................................................................................................................................ 161
Rev. E Production – 3/11 ............................................................................................................................ 161
Rev. D Production – 12/10 ......................................................................................................................... 161
Rev. C – 7/10 ............................................................................................................................................. 161
Rev. B – 2/10 ............................................................................................................................................. 161
Rev. A – 11/09 ............................................................................................................................................ 161
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 26
Table 3: Asynchronous Interface Mode Selection ........................................................................................... 27
Table 4: Synchronous Interface Mode Selection ............................................................................................. 37
Table 5: Command Set .................................................................................................................................. 48
Table 6: Read ID Parameters for Address 00h ................................................................................................. 54
Table 7: Read ID Parameters for Address 20h .................................................................................................. 54
Table 8: Parameter Page Data Structure ......................................................................................................... 56
Table 9: Feature Address Definitions .............................................................................................................. 68
Table 10: Feature Address 01h: Timing Mode ................................................................................................. 70
Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 71
Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 71
Table 13: Feature Addresses 90h: Array Operation Mode ................................................................................. 72
Table 14: Status Register Definition ............................................................................................................... 73
Table 15: OTP Area Details ........................................................................................................................... 104
Table 16: Error Management Details ............................................................................................................. 109
Table 17: Shared Pages ................................................................................................................................. 110
Table 18: Output Drive Strength Test Conditions (VCCQ = 1.7–1.95V) .............................................................. 112
Table 19: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) .......................................................... 112
Table 20: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 113
Table 21: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 113
Table 22: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 114
Table 23: Overshoot/Undershoot Parameters ................................................................................................ 115
Table 24: Test Conditions for Input Slew Rate ................................................................................................ 116
Table 25: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 116
Table 26: Input Slew Rate (VCCQ= 2.7–3.6V) ................................................................................................... 116
Table 27: Test Conditions for Output Slew Rate ............................................................................................. 117
Table 28: Output Slew Rate (VCCQ = 1.7–1.95V) .............................................................................................. 117
Table 29: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 117
Table 30: Absolute Maximum Ratings by Device ............................................................................................ 118
Table 31: Recommended Operating Conditions ............................................................................................ 118
Table 32: Valid Blocks per LUN ..................................................................................................................... 118
Table 33: Capacitance: 100-Ball BGA Package ................................................................................................ 119
Table 34: Capacitance: 48-Pin TSOP Package ................................................................................................ 119
Table 35: Capacitance: 52-Pad LGA Package .................................................................................................. 119
Table 36: Test Conditions ............................................................................................................................. 120
Table 37: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 120
Table 38: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 121
Table 39: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 121
Table 40: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 122
Table 41: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 122
Table 42: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 124
Table 43: Array Characteristics ..................................................................................................................... 127
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
List of Figures
Figure 1: Part Numbering ................................................................................................................................ 2
Figure 2: 48-Pin TSOP Type 1 (Top View) ....................................................................................................... 11
Figure 3: 52-Pad LGA (Top View) ................................................................................................................... 12
Figure 4: 100-Ball BGA (Ball-Down, Top View) ................................................................................................ 13
Figure 5: 48-Pin TSOP – Type 1 CPL (Package Code: WP) ................................................................................ 14
Figure 6: 52-Pad VLGA .................................................................................................................................. 15
Figure 7: 100-Ball VBGA – 12mm x 18mm (Package Code: H1) ......................................................................... 16
Figure 8: 100-Ball TBGA – 12mm x 18mm (Package Code: H2) ......................................................................... 17
Figure 9: 100-Ball LBGA – 12mm x 18mm (Package Code: H3) ......................................................................... 18
Figure 10: NAND Flash Die (LUN) Functional Block Diagram ......................................................................... 19
Figure 11: Device Organization for Single-Die Package (TSOP/BGA) ............................................................... 20
Figure 12: Device Organization for Two-Die Package (TSOP) .......................................................................... 20
Figure 13: Device Organization for Two-Die Package (BGA/LGA) .................................................................... 21
Figure 14: Device Organization for Four-Die Package (TSOP) .......................................................................... 22
Figure 15: Device Organization for Four-Die Package with CE# and CE2# (BGA/LGA) ...................................... 23
Figure 16: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4# (BGA/LGA) .................. 24
Figure 17: Device Organization for Eight-Die Package (BGA/LGA) ................................................................... 25
Figure 18: Array Organization per Logical Unit (LUN) ..................................................................................... 26
Figure 19: Asynchronous Command Latch Cycle ............................................................................................ 28
Figure 20: Asynchronous Address Latch Cycle ................................................................................................ 29
Figure 21: Asynchronous Data Input Cycles ................................................................................................... 30
Figure 22: Asynchronous Data Output Cycles ................................................................................................. 31
Figure 23: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 32
Figure 24: READ/BUSY# Open Drain ............................................................................................................. 33
Figure 25: tFall and tRise (VCCQ = 2.7-3.6V) ...................................................................................................... 34
Figure 26: tFall and tRise (VCCQ = 1.7-1.95V) .................................................................................................... 34
Figure 27: IOL vs Rp (VCCQ = 2.7-3.6V) ............................................................................................................ 35
Figure 28: IOL vs Rp (VCCQ = 1.7-1.95V) .......................................................................................................... 35
Figure 29: TC vs Rp ........................................................................................................................................ 36
Figure 30: Synchronous Bus Idle/Driving Behavior ......................................................................................... 39
Figure 31: Synchronous Command Cycle ....................................................................................................... 40
Figure 32: Synchronous Address Cycle ........................................................................................................... 41
Figure 33: Synchronous DDR Data Input Cycles ............................................................................................. 42
Figure 34: Synchronous DDR Data Output Cycles ........................................................................................... 44
Figure 35: R/B# Power-On Behavior ............................................................................................................... 45
Figure 36: Activating the Synchronous Interface ............................................................................................. 47
Figure 37: RESET (FFh) Operation ................................................................................................................. 50
Figure 38: SYNCHRONOUS RESET (FCh) Operation ....................................................................................... 51
Figure 39: RESET LUN (FAh) Operation ......................................................................................................... 52
Figure 40: READ ID (90h) with 00h Address Operation .................................................................................... 53
Figure 41: READ ID (90h) with 20h Address Operation .................................................................................... 53
Figure 42: READ PARAMETER (ECh) Operation .............................................................................................. 55
Figure 43: READ UNIQUE ID (EDh) Operation ............................................................................................... 67
Figure 44: SET FEATURES (EFh) Operation .................................................................................................... 69
Figure 45: GET FEATURES (EEh) Operation ................................................................................................... 69
Figure 46: READ STATUS (70h) Operation ...................................................................................................... 75
Figure 47: READ STATUS ENHANCED (78h) Operation .................................................................................. 75
Figure 48: CHANGE READ COLUMN (05h-E0h) Operation ............................................................................. 76
Figure 49: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation ......................................................... 77
Figure 50: CHANGE WRITE COLUMN (85h) Operation ................................................................................... 78
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
Figure 51: CHANGE ROW ADDRESS (85h) Operation ..................................................................................... 80
Figure 52: READ PAGE (00h-30h) Operation ................................................................................................... 84
Figure 53: READ PAGE CACHE SEQUENTIAL (31h) Operation ........................................................................ 85
Figure 54: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 87
Figure 55: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 88
Figure 56: READ PAGE MULTI-PLANE (00h-32h) Operation ........................................................................... 90
Figure 57: PROGRAM PAGE (80h-10h) Operation ........................................................................................... 92
Figure 58: PROGRAM PAGE CACHE (80h–15h) Operation (Start) .................................................................... 94
Figure 59: PROGRAM PAGE CACHE (80h–15h) Operation (End) ..................................................................... 94
Figure 60: PROGRAM PAGE MULTI-PLANE (80h–11h) Operation ................................................................... 96
Figure 61: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 97
Figure 62: ERASE BLOCK MULTI-PLANE (60h–D1h) Operation ...................................................................... 98
Figure 63: COPYBACK READ (00h-35h) Operation ......................................................................................... 100
Figure 64: COPYBACK READ (00h–35h) with CHANGE READ COLUMN (05h–E0h) Operation ......................... 100
Figure 65: COPYBACK PROGRAM (85h–10h) Operation ................................................................................. 101
Figure 66: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) Operation ....................... 101
Figure 67: COPYBACK PROGRAM MULTI-PLANE (85h-11h) Operation .......................................................... 102
Figure 68: PROGRAM OTP PAGE (80h-10h) Operation ................................................................................... 104
Figure 69: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLUMN (85h) Operation ......................... 105
Figure 70: PROTECT OTP AREA (80h-10h) Operation .................................................................................... 106
Figure 71: READ OTP PAGE (00h-30h) Operation .......................................................................................... 106
Figure 72: Overshoot .................................................................................................................................... 115
Figure 73: Undershoot ................................................................................................................................. 115
Figure 74: RESET Operation ......................................................................................................................... 128
Figure 75: RESET LUN Operation .................................................................................................................. 128
Figure 76: READ STATUS Cycle ..................................................................................................................... 129
Figure 77: READ STATUS ENHANCED Cycle ................................................................................................. 129
Figure 78: READ PARAMETER PAGE ............................................................................................................. 130
Figure 79: READ PAGE ................................................................................................................................. 130
Figure 80: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 131
Figure 81: CHANGE READ COLUMN ............................................................................................................ 132
Figure 82: READ PAGE CACHE SEQUENTIAL ................................................................................................ 133
Figure 83: READ PAGE CACHE RANDOM ..................................................................................................... 134
Figure 84: READ ID Operation ...................................................................................................................... 135
Figure 85: PROGRAM PAGE Operation .......................................................................................................... 135
Figure 86: PROGRAM PAGE Operation with CE# “Don’t Care” ....................................................................... 136
Figure 87: PROGRAM PAGE Operation with CHANGE WRITE COLUMN ........................................................ 136
Figure 88: PROGRAM PAGE CACHE .............................................................................................................. 137
Figure 89: PROGRAM PAGE CACHE Ending on 15h ....................................................................................... 137
Figure 90: COPYBACK .................................................................................................................................. 138
Figure 91: ERASE BLOCK Operation .............................................................................................................. 138
Figure 92: SET FEATURES Operation ............................................................................................................ 139
Figure 93: READ ID Operation ...................................................................................................................... 140
Figure 94: GET FEATURES Operation ........................................................................................................... 141
Figure 95: RESET (FCh) Operation ................................................................................................................ 142
Figure 96: READ STATUS Cycle ..................................................................................................................... 143
Figure 97: READ STATUS ENHANCED Operation .......................................................................................... 144
Figure 98: READ PARAMETER PAGE Operation ............................................................................................. 145
Figure 99: READ PAGE Operation ................................................................................................................. 146
Figure 100: CHANGE READ COLUMN .......................................................................................................... 147
Figure 101: READ PAGE CACHE SEQUENTIAL (1 of 2) ................................................................................... 148
Figure 102: READ PAGE CACHE SEQUENTIAL (2 of 2) ................................................................................... 149
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
Figure 103: READ PAGE CACHE RANDOM (1 of 2) ......................................................................................... 150
Figure 104: READ PAGE CACHE RANDOM (2 of 2) ......................................................................................... 150
Figure 105: Multi-Plane Read Page (1 of 2) ..................................................................................................... 151
Figure 106: Multi-Plane Read Page (2 of 2) ..................................................................................................... 152
Figure 107: PROGRAM PAGE Operation (1 of 2) ............................................................................................. 153
Figure 108: PROGRAM PAGE Operation (2 of 2) ............................................................................................. 153
Figure 109: CHANGE WRITE COLUMN ......................................................................................................... 154
Figure 110: Multi-Plane Program Page .......................................................................................................... 155
Figure 111: ERASE BLOCK ............................................................................................................................ 156
Figure 112: COPYBACK (1 of 3) ..................................................................................................................... 156
Figure 113: COPYBACK (2 of 3) ..................................................................................................................... 157
Figure 114: COPYBACK (3 of 3) ..................................................................................................................... 157
Figure 115: READ OTP PAGE ........................................................................................................................ 158
Figure 116: PROGRAM OTP PAGE (1 of 2) ...................................................................................................... 159
Figure 117: PROGRAM OTP PAGE (2 of 2) ...................................................................................................... 159
Figure 118: PROTECT OTP AREA .................................................................................................................. 160
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
General Description
General Description
Micron NAND Flash devices include an asynchronous data interface for high-perform-
ance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer
commands, address, and data. There are five control signals used to implement the asyn-
chronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection (WP#) and monitor device status (R/B#).
This Micron NAND Flash device additionally includes a synchronous data interface for
high-performance I/O operations. When the synchronous interface is active, WE# be-
comes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe
(DQS).
This hardware interface creates a low pin-count device with a standard pinout that re-
mains the same from one density to another, enabling future upgrades to higher densi-
ties with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). For further details, see Device and Array Organization.
Asynchronous and Synchronous Signal Descriptions
Table 1: Asynchronous and Synchronous Signal Definitions
Asynchronous
Signal1
ALE
Synchronous
Signal1
ALE
CE# CE#
CLE CLE
DQx
DQx
DQS
RE# W/R#
WE#
CLK
WP#
R/B#
VCC
WP#
R/B#
VCC
Type
Input
Input
Input
I/O
I/O
Input
Input
Input
Output
Supply
Description2
Address latch enable: Loads an address from DQx into the address reg-
ister.
Chip enable: Enables or disables one or more die (LUNs) in a target1.
Command latch enable: Loads a command from DQx into the com-
mand register.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and
command information.
Data strobe: Provides a synchronous reference for data input and out-
put.
Read enable and write/read: RE# transfers serial data from the NAND
Flash to the host system when the asynchronous interface is active.
When the synchronous interface is active, W/R# controls the direction of
DQx and DQS.
Write enable and clock: WE# transfers commands, addresses, and seri-
al data from the host system to the NAND Flash when the asynchronous
interface is active. When the synchronous interface is active, CLK latches
command and address cycles.
Write protect: Enables or disables array PROGRAM and ERASE opera-
tions.
Ready/busy: An open-drain, active-low output that requires an exter-
nal pull-up resistor. This signal indicates target array activity.
VCC: Core power supply
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Rev. E 3/11 EN
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NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Asynchronous and Synchronous Signal Descriptions
Table 1: Asynchronous and Synchronous Signal Definitions (Continued)
Asynchronous
Signal1
VCCQ
VSS
VSSQ
NC
DNU
RFU
Synchronous
Signal1
VCCQ
VSS
VSSQ
NC
DNU
RFU
Type
Supply
Supply
Supply
Description2
VCCQ: I/O power supply
VSS: Core ground connection
VSSQ: I/O ground connection
No connect: NCs are not internally connected. They can be driven or
left unconnected.
Do not use: DNUs must be left unconnected.
Reserved for future use: RFUs must be left unconnected.
Notes:
1. See Device and Array Organization for detailed signal connections.
2. See Bus Operation – Asynchronous Interface (page 27) and Bus Operation – Synchro-
nous Interface (page 37) for detailed asynchronous and synchronous interface signal
descriptions.
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Rev. E 3/11 EN
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NAND Flash Memory

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Signal Assignments
Signal Assignments
Figure 2: 48-Pin TSOP Type 1 (Top View)
Sync Async
x8 x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
W/R#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
CLK
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1l
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Async
x8
Sync
x8
48
47
DNU/VSSQ2 DNU/VSSQ2
NC NC
46 NC
NC
45 NC
NC
44 DQ7 DQ7
43 DQ6 DQ6
42 DQ5 DQ5
41 DQ4 DQ4
40 NC
NC
39 DNU/VCCQ2 DNU/VCCQ2
38 DNU DNU
37 VCC
VCC
36 VSS
VSS
35 DNU DQS
34
33
DNU/VCCQ2 DNU/VCCQ2
NC NC
32 DQ3 DQ3
31 DQ2 DQ2
30 DQ1 DQ1
29 DQ0 DQ0
28 NC
NC
27 NC
NC
26 DNU DNU
25 DNU/VSSQ2 DNU/VSSQ2
Notes:
1. CE2# and R/B2# are available on dual die and quad die packages. They are NC for other
configurations.
2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.2. If not supplying VCCQ or
VSSQ to these pins, do not use them.
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Rev. E 3/11 EN
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NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Signal Assignments
Figure 3: 52-Pad LGA (Top View)
0
12 3 4 567
8
NC
OA CE4#2
A CE3#2
CLE-1
B VSS
OB NC
C ALE-1
CLE-21
D ALE-21
OC DNU
E WE#-21
WE#-1
F WP#-1
G DQ0-21
DQ0-1
H DQ1-1
J DQ1-21
DQ2-1
OD DNU/
VSS K
DQ3-1
L DQ2-21
OE NC
VSS
M VSS
N
DNU/
VCC
OF NC
DQ3-21
CE# R/B3#2
VCC
CE2#1
RE#-1
RE#-21
R/B# R/B2#1
VSS
WP#-21
DQ7-21
DQ7-1
DQ6-1
DQ6-21
DQ5-1
DQ4-1
DQ5-21
VCC
DQ4-21
DNU/
VCC
R/B4#2
NC
DNU
DNU
DNU/
VSS
NC
Top View, Pads Down
Notes:
1. These signals are available on dual, quad, and octal die packages. They are NC for other
configurations.
2. These signals are available on quad die four CE# or octal die packages. They are NC for
other configurations.
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Rev. E 3/11 EN
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Signal Assignments
Figure 4: 100-Ball BGA (Ball-Down, Top View)
1 2 3 4 5 6 7 8 9 10
A NC NC
B NC
NC NC
NC
A
B
D
RFU DNU NC WP#-23 NC
NC DNU RFU
D
E
RFU DNU NC WP#-1 NC
NC DNU RFU
E
F
VCC VCC VCC VCC VCC VCC VCC VCC
F
G
VSS VSS VSS VSS VSS VSS VSS VSS
G
H
Vssq Vccq RFU RFU R/B2#3 R/B4#4 Vccq Vssq
H
J
DQ0-23 DQ2-23 ALE-23 CE4#4 R/B# R/B3#4 DQ5-23 DQ7-23
J
K
DQ0-1 DQ2-1 ALE-1 CE3#4 CE2#3 CE# DQ5-1 DQ7-1
K
L
Vccq Vssq Vccq CLE-23 RE#-23 Vccq Vssq Vccq
L
(W/R#-2)
M
DQ1-23 DQ3-23 Vssq CLE-1 RE#-1 Vssq DQ4-23 DQ6-23
M
(W/R#-1)
N
DQ1-1 DQ3-1
RFU (DNQ/SA-123) RFU
WE#-23 DQ4-1 DQ6-1
(CLK-2)
N
P
Vssq Vccq RFU N/A1 RFU WE#-1 Vccq Vssq
P
(DQS-1)
(CLK-1)
PDF: 09005aef83d2277a
Rev. E 3/11 EN
T NC
U NC NC
NC
NC NC
T
U
1 2 3 4 5 6 7 8 9 10
Notes:
1. N/A: This signal is tri-stated when the asynchronous interface is active.
2. Signal names in parentheses are the signal names when the synchronous interface is active.
3. These signals are available on dual, quad, and octal die packages. They are NC for other
configurations.
4. These signals are available on quad die four CE# or octal die packages. They are NC for
other configurations.
13
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Package Dimensions
Package Dimensions
Figure 5: 48-Pin TSOP – Type 1 CPL (Package Code: WP)
20.00 ±0.25
18.40 ±0.08
0.25
for reference only
0.50 TYP
for reference
48 only
Mold compound:
Epoxy novolac
Plated lead finish:
100% Sn
1
Package width and length
do not include mold
protrusion. Allowable
protrusion is 0.25 per side.
12.00 ±0.08
24
0.15
+0.03
-0.02
25
See detail A
1.20 MAX
Note: 1. All dimensions are in millimeters.
0.10
0.10
+0.10
-0.05
0.27 MAX
0.17 MIN
0.25
Gage
plane
0.50 ±0.1
0.80
Detail A
PDF: 09005aef83d2277a
Rev. E 3/11 EN
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NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Package Dimensions
Figure 6: 52-Pad VLGA
See Detail B
Section A–A
40X Ø0.71
12X Ø11
6 CTR
4 CTR
8 7654 321 0
Seating
plane
0.1 A
A
See Note 1
Detail B2
Not to scale
Terminal
A1 ID
Substrate material: plastic laminate.
Mold compound: epoxy novolac.
Terminal A1 ID
OA
OB
OC
13 12 10
CTR CTR CTR
A
2
TYP OD
OE
OF
A
B
C
D
E
FA
G 18 ±0.1
H
J
K
L
M2
N TYP
2 TYP
10 CTR
14 ±0.1
1.0 MAX
including package bow.
Bottom side saw fiducials may or
may not be covered with soldermask.
Note: 1. All dimensions are in millimeters.
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Rev. E 3/11 EN
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Package Dimensions
Figure 7: 100-Ball VBGA – 12mm x 18mm (Package Code: H1)
Seating
plane
0.12 A
A
0.63 ±0.05
100X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-reflow
on Ø0.4 SMD ball pads.
12 ±0.1
10 9 8 7 6 5 4 3 2 1
Ball A1 ID
A
B
8
7
16 CTR
1 TYP
D
E
F
G
H
J 18 ±0.1
K
L
M
N
P
Ball A1 ID
T
U
1 TYP
1 TYP
9 CTR
1.0 MAX
Bottom side
saw fiducials
0.25 MIN
may or may not
be covered with soldermask.
Note: 1. All dimensions are in millimeters.
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Rev. E 3/11 EN
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Package Dimensions
Figure 8: 100-Ball TBGA – 12mm x 18mm (Package Code: H2)
Seating
plane
0.12 A
A
0.73 ±0.05
100X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-reflow
on Ø0.4 SMD ball pads.
12 ±0.1
10 9 8 7 6 5 4 3 2 1
Ball A1 ID
A
B
8
7
16 CTR
1 TYP
D
E
F
G
H
J 18 ±0.1
K
L
M
N
P
T
U
Bottom side
fiducials may
or may not be
covered with
soldermask.
1 TYP
1 TYP
9 CTR
Note: 1. All dimensions are in millimeters.
Ball A1 ID
1.2 MAX
0.25 MIN
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Rev. E 3/11 EN
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Package Dimensions
Figure 9: 100-Ball LBGA – 12mm x 18mm (Package Code: H3)
Seating
plane
0.12 A
A
0.98 ±0.05
100X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-
reflow on Ø0.40 SMD
ball pads.
16 CTR 10 CTR
12 ±0.1
10 9 8 7 6 5 4 3 2 1
Ball A1 ID
A
B
D
E
F
G
H
J 18 ±0.1
K
L
M
N
P
Ball A1 ID
1 TYP
T
U
1 TYP
9 CTR
1.4 MAX
Bottom side
saw fiducials
0.25 MIN
may or may not
be covered with soldermask.
Note: 1. All dimensions are in millimeters.
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Rev. E 3/11 EN
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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Architecture
Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
The commands received at the I/O control circuits are latched by a command register
and are transferred to control logic circuits for generating internal signals to control de-
vice operations. The addresses are latched by an address register and sent to a row
decoder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte, through a
data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations
and is erased using block-based operations. During normal page operations, the data
and cache registers act as a single register. During cache operations, the data and cache
registers operate independently to increase data throughput.
The status register reports the status of die (LUN) operations.
Figure 10: NAND Flash Die (LUN) Functional Block Diagram
Vcc Vss Vccq Vssq
Async Sync
DQ[7:0] DQ[7:0]
N/A DQS
I/O
control
Address register
Status register
Command register
CE#
CLE
ALE
WE#
RE#
WP#
CE#
CLE
ALE
CLK
W/R#
WP#
R/B# R/B#
Control
logic
CCoolluummnndDeeccooddee
NNAANNDDFFllaasshh
array A(2rrpalyanes)
DDaattaa rReeggisistteerr
CCaacchhee rReeggisistteerr
Notes: 1. N/A: This signal is tri-stated when the asynchronous interface is active.
2. Some devices do not include the synchronous interface.
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NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Device and Array Organization
Device and Array Organization
Figure 11: Device Organization for Single-Die Package (TSOP/BGA)
Async Sync
CE# CE#
CLE CLE
ALE ALE
WE# CLK
RE# W/R#
DQ[7:0] DQ[7:0]
N/A DQS
WP# WP#
Package
Target 1
LUN 1
R/B#
Figure 12: Device Organization for Two-Die Package (TSOP)
Async
Sync
Package
CE#
CLE
ALE
WE#
RE#
DQ[7:0]
N/A
WP#
CE#
CLE
ALE
CLK
W/R#
DQ[7:0]
DQS
WP#
Target 1
LUN 1
CE2#
CLE
ALE
WE#
RE#
DQ[7:0]
N/A
WP#
CE2#
CLE
ALE
CLK
W/R#
DQ[7:0]
DQS
WP#
Target 2
LUN 1
R/B#
R/B2#
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Rev. E 3/11 EN
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Device and Array Organization
Figure 13: Device Organization for Two-Die Package (BGA/LGA)
Async
CE#
CLE-1
ALE-1
WE#-1
RE#-1
DQ[7:0]-1
N/A
WP#-1
Sync
CE#
CLE-1
ALE-1
CLK-1
W/R#-1
DQ[7:0]-1
DQS-1
WP#-1
Package
Target 1
LUN 1
R/B#
CE2#
CLE-2
ALE-2
WE#-2
RE#-2
DQ[7:0]-2
N/A
WP#-2
CE2#
CLE-2
ALE-2
CLK-2
W/R#-2
DQ[7:0]-2
DQS-2
WP#-2
Target 2
LUN 1
R/B2#
Note: 1. LGA devices do not support the synchronous interface.
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NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Device and Array Organization
Figure 14: Device Organization for Four-Die Package (TSOP)
Async
Sync
CE#
CLE
ALE
WE#
RE#
DQ[7:0]
N/A
WP#
CE#
CLE
ALE
CLK
W/R#
DQ[7:0]
DQS
WP#
Package
Target 1
LUN 1
LUN 2
R/B#
CE2#
CLE
ALE
WE#
RE#
DQ[7:0]
N/A
WP#
CE2#
CLE
ALE
CLK
W/R#
DQ[7:0]
DQS
WP#
Target 2
LUN 1
LUN 2
R/B2#
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NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Device and Array Organization
Figure 15: Device Organization for Four-Die Package with CE# and CE2# (BGA/LGA)
Async
CE#
CLE-1
ALE-1
WE#-1
RE#-1
DQ[7:0]-1
N/A
WP#-1
Sync
CE#
CLE-1
ALE-1
CLK-1
W/R#-1
DQ[7:0]-1
DQS-1
WP#-1
Package
Target 1
LUN 1
LUN 2
R/B#
CE2#
CLE-2
ALE-2
WE#-2
RE#-2
DQ[7:0]-2
N/A
WP#-2
CE2#
CLE-2
ALE-2
CLK-2
W/R#-2
DQ[7:0]-2
DQS-2
WP#-2
Target 2
LUN 1
LUN 2
R/B2#
Note: 1. LGA devices do not support the synchronous interface.
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NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Device and Array Organization
Figure 16: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4# (BGA/LGA)
Async
Sync
CE# CE#
CLE-1
CLE-1
ALE-1
ALE-1
WE#-1
CLK-1
RE#-1 W/R#-1
DQ[7:0]-1 DQ[7:0]-1
N/A DQS-1
WP#-1 WP#-1
CE2#
CE2#
CLE-2
CLE-2
ALE-2
ALE-2
WE#-2
CLK-2
RE#-2 W/R#-2
DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
CE3#
CE3#
CLE-1
CLE-1
ALE-1
ALE-1
WE#-1
CLK-1
RE#-1 W/R#-1
DQ[7:0]-1 DQ[7:0]-1
N/A DQS-1
WP#-1 WP#-1
CE4#
CE4#
CLE-2
CLE-2
ALE-2
ALE-2
WE#-2
CLK-2
RE#-2 W/R#-2
DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
Package
Target 1
LUN 1
Target 2
LUN 1
Target 3
LUN 1
Target 4
LUN 1
R/B#
R/B2#
R/B3#
R/B4#
Note: 1. LGA devices do not support the synchronous interface.
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NAND Flash Memory

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Device and Array Organization
Figure 17: Device Organization for Eight-Die Package (BGA/LGA)
Async
Sync
CE# CE#
CLE-1
CLE-1
ALE-1
ALE-1
WE#-1 CLK-1
RE#-1 W/R#-1
DQ[7:0]-1 DQ[7:0]-1
N/A DQS-1
WP#-1 WP#-1
CE2#
CE2#
CLE-2
CLE-2
ALE-2
ALE-2
WE#-2 CLK-2
RE#-2 W/R#-2
DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
CE3#
CE3#
CLE-1
CLE-1
ALE-1
ALE-1
WE#-1 CLK-1
RE#-1 W/R#-1
DQ[7:0]-1 DQ[7:0]-1
N/A DQS-1
WP#-1 WP#-1
CE4#
CE4#
CLE-2
CLE-2
ALE-2
ALE-2
WE#-2 CLK-2
RE#-2 W/R#-2
DQ[7:0]-2 DQ[7:0]-2
N/A DQS-2
WP#-2 WP#-2
Package
Target 1
LUN 1
LUN 2
Target 2
LUN 1
LUN 2
Target 3
LUN 1
LUN 2
Target 4
LUN 1
LUN 2
R/B#
R/B2#
R/B3#
R/B4#
Note: 1. LGA devices do not support the synchronous interface.
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Device and Array Organization
Figure 18: Array Organization per Logical Unit (LUN)
Cache Registers
Data Registers
Logical Unit (LUN)
8640 bytes
8640 bytes
8192 448 8192 448
8192 448 8192 448
2048 blocks per plane
4096 blocks per LUN
1 Block
1 Block
Plane 0
(0, 2, 4, ..., 4094)
Plane 1
(1, 3, 5, ..., 4095)
DQ7
DQ0
1 page = (8K + 448 bytes)
1 block = (8K + 448) bytes x 256 pages
= (2048K + 112K1) Bbyltoecs k
1 plane = (2048K + 112K) bytes x 2048 blocks
= 34,560Mb
1 LUN = 34,560Mb x 2 planes
= 69,120Mb
Table 2: Array Addressing for Logical Unit (LUN)
Cycle
First
Second
Third
Fourth
Fifth
DQ7
CA7
LOW
PA7
BA15
LOW
DQ6
CA6
LOW
PA6
BA14
LOW
DQ5
CA5
CA133
PA5
BA13
LOW
DQ4
CA4
CA12
PA4
BA12
LA05
DQ3
CA3
CA11
PA3
BA11
BA19
DQ2
CA2
CA10
PA2
BA10
BA18
DQ1
CA1
CA9
PA1
BA9
BA17
DQ0
CA02
CA8
PA0
BA84
BA16
Notes:
1. CAx = column address, PAx = page address, BAx = block address, LAx = LUN address; the
page address, block address, and LUN address are collectively called the row address.
2. When using the synchronous interface, CA0 is forced to 0 internally; one data cycle al-
ways returns one even byte and one odd byte.
3. Column addresses 8640 (21C0h) through 16,383 (3FFFh) are invalid, out of bounds, do
not exist in the device, and cannot be addressed.
4. BA[8] is the plane-select bit:
Plane 0: BA[8] = 0
Plane 1: BA[8] = 1
5. LA0 is the LUN-select bit. It is present only when two LUNs are shared on the target;
otherwise, it should be held LOW.
LUN 0: LA0 = 0
LUN 1: LA0 = 1
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Bus Operation – Asynchronous Interface
Bus Operation – Asynchronous Interface
The asynchronous interface is active when the NAND Flash device powers on. The I/O
bus, DQ[7:0], is multiplexed sharing data I/O, addresses, and commands. The DQS sig-
nal, if present, is tri-stated when the asynchronous interface is active.
Asynchronous interface bus modes are summarized below.
Table 3: Asynchronous Interface Mode Selection
Mode
Standby
Bus idle
Command input
CE#
CLE
ALE WE# RE#
DQS
DQx
WP#
Notes
H
X
X
X
X
X
X 0V/VCCQ2
2
L XXHHXXX
LHL
H X input H
Address input
L LH
H X input H
Data input
LLL
H X input H
Data output
L L LH
X output X
Write protect
XXXXXXX L
Notes:
1. DQS is tri-stated when the asynchronous interface is active.
2. WP# should be biased to CMOS LOW or HIGH for standby.
3. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
Asynchronous Enable/Standby
A chip enable (CE#) signal is used to enable or disable a target. When CE# is driven
LOW, all of the signals for that target are enabled. With CE# LOW, the target can accept
commands, addresses, and data I/O. There may be more than one target in a NAND
Flash package. Each target is controlled by its own chip enable; the first target (Target 0)
is controlled by CE#; the second target (if present) is controlled by CE2#, etc.
A target is disabled when CE# is driven HIGH, even when the target is busy. When disa-
bled, all of the target's signals are disabled except CE#, WP#, and R/B#. This functionali-
ty is also known as CE# "Don't Care". While the target is disabled, other devices can
utilize the disabled NAND signals that are shared with the NAND Flash.
A target enters low-power standby when it is disabled and is not busy. If the target is
busy when it is disabled, the target enters standby after all of the die (LUNs) complete
their operations. Standby helps reduce power consumption.
Asynchronous Bus Idle
A target's bus is idle when CE# is LOW, WE# is HIGH, and RE# is HIGH.
During bus idle, all of the signals are enabled except DQS, which is not used when the
asynchronous interface is active. No commands, addresses, and data are latched into
the target; no data is output.
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Bus Operation – Asynchronous Interface
Asynchronous Commands
An asynchronous command is written from DQ[7:0] to the command register on the
rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are
accepted by die (LUNs) even when they are busy.
Figure 19: Asynchronous Command Latch Cycle
CLE
CE#
WE#
ALE
DQx
tCLS
tCS
tCLH
tCH
tWP
tALS tALH
tDS tDH
COMMAND
Don’t Care
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Bus Operation – Asynchronous Interface
Asynchronous Addresses
An asynchronous address is written from DQ[7:0] to the address register on the rising
edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organiza-
tion). The number of cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements (see Command Definitions).
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses are accepted by die (LUNs) even when they are busy; for example, address
cycles that follow the READ STATUS ENHANCED (78h) command.
Figure 20: Asynchronous Address Latch Cycle
CLE
tCLS
tCS
CE#
tWC
tWP tWH
WE#
tALS
tALH
ALE
tDS tDH
DQx
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
Don’t Care
Undefined
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MT29F128G08CEAAA (Micron)
NAND Flash Memory

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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Bus Operation – Asynchronous Interface
Asynchronous Data Input
Data is written from DQ[7:0] to the cache register of the selected die (LUN) on the rising
edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.
Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0).
Figure 21: Asynchronous Data Input Cycles
CLE
CE#
ALE
WE#
DQx
tCLH
tALS
tWC
tWP
tWP
tWH
tDS tDH
DIN M
tDS tDH
DIN M+1
tCH
tWP
tDS tDH
DIN N
Don’t Care
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