MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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EVALUATION KIT AVAILABLE
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
General Description
The MAX5813/MAX5814/MAX5815 4-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal reference
that is selectable to be 2.048V, 2.500V, or 4.096V. The
MAX5813/MAX5814/MAX5815 accept a wide supply
voltage range of 2.7V to 5.5V with extremely low power
(3mW) consumption to accommodate most low-voltage
applications. A precision external reference input allows
rail-to-rail operation and presents a 100kI (typ) load to
an external reference.
The MAX5813/MAX5814/MAX5815 have an I2C-compatible,
2-wire interface that operates at clock rates up to
400kHz. The DAC output is buffered and has a low sup-
ply current of less than 250FA per channel and a low
offset error of Q0.5mV (typ). On power-up, the MAX5813/
MAX5814/MAX5815 reset the DAC outputs to zero, pro-
viding additional safety for applications that drive valves
or other transducers which need to be off on power-up.
The internal reference is initially powered down to allow
use of an external reference. The MAX5813/MAX5814/
MAX5815 allow simultaneous output updates using soft-
ware LOAD commands or the hardware load DAC logic
input (LDAC).
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
sets the DAC outputs to zero. The MAX5813/MAX5814/
MAX5815 are available in a 14-pin TSSOP and an ultra-
small, 12-bump WLP package and are specified over the
-40NC to +125NC temperature range.
Applications
Programmable Voltage and Current Sources
Gain and Offset Adjustment
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
Data Acquisition
Ordering Information appears at end of data sheet.
Benefits and Features
S Four High-Accuracy DAC Channels
12-Bit Accuracy Without Adjustment
±1 LSB INL Buffered Voltage Output
Guaranteed Monotonic Over All Operating
Conditions
Independent Mode Settings for Each DAC
S Three Precision Selectable Internal References
2.048V, 2.500V, or 4.096V
S Internal Output Buffer
Rail-to-Rail Operation with External Reference
4.5µs Settling Time
Outputs Directly Drive 2kI Loads
S Small 5mm x 4.4mm 14-Pin TSSOP or Ultra-Small
1.6mm x 2.2mm 12-Bump WLP Package
S Wide 2.7V to 5.5V Supply Range
S Separate 1.8V to 5.5V VDDIO Power-Supply Input
S Fast 400kHz I2C-Compatible, 2-Wire Serial
Interface
S Power-On-Reset to Zero-Scale DAC Output
S LDAC and CLR For Asynchronous Control
S Three Software-Selectable Power-Down Output
Impedances
1kI, 100kI, or High Impedance
Functional Diagram
VDDIO
VDD REF
SCL
SDA
ADDR0
(ADDR1)
CLR
(LDAC)
I2C SERIAL
INTERFACE
POR
INTERNAL REFERENCE/
EXTERNAL BUFFER
CODE
REGISTER
DAC
LATCH
8 -/10-/12-BIT
DAC
CODE
CLEAR /
RESET
LOAD
CLEAR /
RESET
DAC CONTROL LOGIC
POWER-DOWN
GND
( ) TSSOP PACKAGE ONLY
MAX5813
MAX5814
MAX5815
1 OF 4 DAC CHANNELS
BUFFER
100kI 1kI
OUTA
OUTB
OUTC
OUTD
For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX5813.related
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6167; Rev 3; 1/13


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Absolute Maximum Ratings
VDD, VDDIO to GND................................................. -0.3V to +6V
OUT_, REF to GND....0.3V to the lower of (VDD + 0.3V) and +6V
SCL, SDA, LDAC, CLR to GND............................... -0.3V to +6V
ADDR_ to GND.............................................-0.3V to the lower of
(VDDIO + 0.3V) and +6V
Continuous Power Dissipation (TA = +70NC)
TSSOP (derate at 10mW/NC above 70NC)....................797mW
WLP (derate at 16.1mW/NC above 70NC)...................1288mW
Maximum Continuous Current into Any Pin..................... Q50mA
Operating Temperature Range......................... -40NC to +125NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (TSSOP only)(soldering, 10s)............+300NC
Soldering Temperature (reflow)..................................... +260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 1)
TSSOP
WLP
Junction-to-Ambient Thermal Resistance (θJA) ........100NC/W
Junction-to-Case Thermal Resistance (θJC) ...............30NC/W
Junction-to-Ambient Thermal Resistance (θJA)
(Note 2).........................................................................62NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Note 2: Visit www.maximintegrated.com/app-notes/index.mvp/id/1891 for information about the thermal performance of WLP packaging.
Electrical Characteristics
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
DC PERFORMANCE (Note 4)
Resolution and Monotonicity
Integral Nonlinearity (Note 5)
Differential Nonlinearity (Note 5)
Offset Error (Note 6)
Offset Error Drift
Gain Error (Note 6)
SYMBOL
N
INL
DNL
OE
MAX5813
MAX5814
MAX5815
MAX5813
MAX5814
MAX5815
MAX5813
MAX5814
MAX5815
GE
CONDITIONS
Gain Temperature Coefficient
Zero-Scale Error
Full-Scale Error
With respect to VREF
With respect to VREF
MIN TYP MAX UNITS
8
10
12
-0.25
-0.5
-1
-0.25
-0.5
-1
-5
-1.0
0
-0.5
Q0.05
Q0.25
Q0.5
Q0.05
Q0.1
Q0.2
Q0.5
Q10
Q0.1
Q3.0
+0.25
+0.5
+1
+0.25
+0.5
+1
+5
+1.0
10
+0.5
Bits
LSB
LSB
mV
FV/NC
%FS
ppm of
FS/NC
mV
%FS
Maxim Integrated
  2


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
DAC OUTPUT CHARACTERISTICS
CONDITIONS
MIN TYP MAX UNITS
Output Voltage Range (Note 7)
No load
2kI load to GND
0 VDD
0
VDD -
0.2
V
Load Regulation
DC Output Impedance
Maximum Capacitive Load
Handling
Resistive Load Handling
Short-Circuit Output Current
DC Power-Supply Rejection
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
DAC Glitch Impulse
Channel-to-Channel
Feedthrough (Note 8)
Digital Feedthrough
Power-Up Time
2kI load to VDD
VOUT = VFS/2
VOUT = VFS/2
VDD = 3V Q10%,
|IOUT| P 5mA
VDD = 5V Q10%,
|IOUT| P 10mA
VDD = 3V Q10%,
|IOUT| P 5mA
VDD = 5V Q10%,
|IOUT| P 10mA
CL
RL
VDD = 5.5V
Sourcing (output
shorted to GND)
Sinking (output
shorted to VDD)
VDD = 3V Q10% or 5V Q10%
0.2 VDD
300
FV/mA
300
0.3
I
0.3
500
2
30
50
100
pF
kI
mA
FV/V
SR Positive and negative
¼ scale to ¾ scale, to P 1 LSB, MAX5813
¼ scale to ¾ scale, to P 1 LSB, MAX5814
¼ scale to ¾ scale, to P 1 LSB, MAX5815
Major code transition
External reference
Internal reference
Code = 0, all digital inputs from 0V to
VDDIO
Startup calibration time (Note 9)
From power-down
1.0
2.2
2.6
4.5
7
3.5
3.3
0.2
200
50
V/Fs
Fs
nV*s
nV*s
nV*s
Fs
Fs
Maxim Integrated
  3


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Voltage-Noise Density
(DAC Output at Midscale)
Integrated Output Noise
(DAC Output at Midscale)
Output Voltage-Noise Density
(DAC Output at Full Scale)
Integrated Output Noise
(DAC Output at Full Scale)
External reference
2.048V internal
reference
2.5V internal
reference
4.096V internal
reference
External reference
2.048V internal
reference
2.5V internal
reference
4.096V internal
reference
External reference
2.048V internal
reference
2.5V internal
reference
4.096V internal
reference
External reference
2.048V internal
reference
2.5V internal
reference
4.096V internal
reference
f = 1kHz
f = 10kHz
f = 1kHz
f = 10kHz
f = 1kHz
f = 10kHz
f = 1kHz
f = 10kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 1kHz
f = 10kHz
f = 1kHz
f = 10kHz
f = 1kHz
f = 10kHz
f = 1kHz
f = 10kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
90
82
112
102
125
nV/Hz
110
160
145
12
76
385
14
91
450
15
FVP-P
99
470
16
124
490
114
99
175
153
200
nV/Hz
174
295
255
13
94
540
19
143
685
21
FVP-P
159
705
26
213
750
Maxim Integrated
  4


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
REFERENCE INPUT
Reference Input Range
Reference Input Current
Reference Input Impedance
REFERENCE OUPUT
VREF
IREF
RREF
VREF = VDD = 5.5V
Reference Output Voltage
Reference Temperature
Coefficient (Note 10)
Reference Drive Capacity
VREF
VREF = 2.048V, TA = +25NC
VREF = 2.5V, TA = +25NC
VREF = 4.096V, TA = +25NC
MAX5815A
MAX5813/MAX5814/MAX5815B
External load
Reference Capacitive Load
Reference Load Regulation
Reference Line Regulation
ISOURCE = 0 to 500FA
POWER REQUIREMENTS
Supply Voltage
VDD
VREF = 4.096V
All other options
I/O Supply Voltage
Supply Current (Note 11)
Interface Supply Current
(Note 11)
VDDIO
IDD
IDDIO
Internal reference
External reference
VREF = 2.048V
VREF = 2.5V
VREF = 4.096V
VREF = 3V
VREF = 5V
All DACs off, internal reference ON
Power-Down Mode Supply
Current
All DACs off, internal reference OFF,
IPD TA = -40NC to +85NC
All DACs off, internal reference OFF,
TA = +125NC
DIGITAL INPUT CHARACTERISTICS (SCL, SDA, ADDR0, ADDR1, LDAC, CLR)
Input High Voltage (Note 11)
2.2V < VDDIO < 5.5V
VIH
1.8V < VDDIO < 2.2V
MIN TYP MAX UNITS
1.24
VDD
55 74
75 100
V
FA
kI
2.043
2.494
4.086
2.048
2.500
4.096
Q3.7
Q10
25
200
2
0.05
2.053
2.506
4.106
Q10
Q25
V
ppm/NC
kI
pF
mV/mA
mV/V
4.5 5.5
2.7 5.5
1.8 5.5
0.93 1.25
0.98 1.30
1.16 1.50
0.85 1.15
1.10 1.40
1
140
0.5 1
1.2 2.5
V
V
mA
FA
FA
0.7 x
VDDIO
0.8 x
VDDIO
V
V
Maxim Integrated
  5


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
Input Low Voltage (Note 11)
2.2V < VDDIO < 5.5V
VIL
1.8V < VDDIO < 2.2V
Hysteresis Voltage
Input Leakage Current
VH
IIN VIN = 0V or VDDIO (Note 11)
Input Capacitance (Note 10)
CIN
ADDR_ Pullup/Pulldown Strength RPU, RPD (Note 12)
DIGITAL OUTPUT (SDA)
Output Low Voltage
VOL ISINK = 3mA
I2C TIMING CHARACTERISTICS (SCL, SDA, LDAC, CLR)
SCL Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
Hold Time Repeated for a
START Condition
SCL Pulse Width Low
SCL Pulse Width High
Setup Time for Repeated START
Condition
Data Hold Time
Data Setup Time
SDA and SCL Receiving
Rise Time
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
SDA and SCL Receiving
Fall Time
tf
SDA Transmitting Fall Time
Setup Time for STOP Condition
Bus Capacitance Allowed
Pulse Width of Suppressed Spike
CLR Removal Time Prior to a
Recognized START
CLR Pulse Width Low
LDAC Pulse Width Low
SCLK Rise to LDAC Fall to Hold
tf
tSU;STO
CB
tsp
tCLRSTA
tCLPW
tLDPW
tLDH
VDD = 2.7V to 5.5V
Applies to execution edge
MIN TYP MAX UNITS
0.15
0.3 x
VDDIO
0.2 x
VDDIO
V
V
Q0.1
Q1
FA
10 pF
30 50 90 kI
0.2 V
400 kHz
1.3 Fs
0.6 Fs
1.3 Fs
0.6 Fs
0.6 Fs
0 900 ns
100 ns
20 +
CB/10
300 ns
20 +
CB/10
300 ns
20 +
CB/10
0.6
10
250 ns
Fs
400 pF
50 ns
100 ns
20 ns
20 ns
400 ns
Maxim Integrated
  6


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
Note 3: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range
are guaranteed by design and characterization. Typical specifications are at TA = +25°C and are not guaranteed.
Note 4: DC Performance is tested without load.
Note 5: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.
Note 6: Offset and gain errors are calculated from measurements made with VREF = VDD at code 30 and 4065 for MAX5815,
code 8 and 1016 for MAX5814, and code 2 and 254 for MAX5813.
Note 7: Subject to zero and full-scale error limits and VREF settings.
Note 8: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.
Note 9: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 10: Guaranteed by design.
Note 11: All channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDDIO.
Note 12: An unconnected condition on the ADDR_ pins is sensed via a resistive pullup and pulldown operation; for proper
operation, ADDR_ pins should be tied to VDDIO, GND, or left unconnected with minimal capacitance.
SDA
tf
SCL
tCLPW
S
tLOW
tHD;STA
tr tSU;DAT
tf
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
tSP tr
tBUF
tSU;STO
P
S
CLR
LDAC
tCLRSTA
tLDH tLDPW
Figure 1. I2C Serial Interface Timing Diagram
Typical Operating Characteristics
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
INL vs. CODE
1.0
0.8
VDD = VREF = 3V
NO LOAD
0.6
INL vs. CODE
1.0
0.8
VDD = VREF = 5V
NO LOAD
0.6
0.4 0.4
0.2 0.2
00
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
DNL vs. CODE
1.0
0.8
VDD = VREF = 3V
NO LOAD
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
Maxim Integrated
  7


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
DNL vs. CODE
1.0
0.8
VDD = VREF = 5V
NO LOAD
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
1.0
0.8
VREF = 2.5V (EXTERNAL)
NO LOAD
0.6 ZERO-SCALE ERROR
0.4
0.2
0
-0.2
-0.4 OFFSET ERROR
-0.6
-0.8
-1.0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
0.10
VREF = 2.5V (EXTERNAL)
NO LOAD
0.05
GAIN ERROR (VDD = 5V)
0
FULL-SCALE ERROR
GAIN ERROR (VDD = 3V)
-0.05
-0.10
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
INL AND DNL vs. SUPPLY VOLTAGE
1.0
0.8 VREF = 2.7V
0.6 MAX INL
0.4 MAX DNL
0.2
0
-0.2
-0.4 MIN DNL
-0.6 MIN INL
-0.8
-1.0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
1.0
0.8
VREF = 2.5V (EXTERNAL)
NO LOAD
0.6 ZERO-SCALE ERROR
0.4
0.2 OFFSET ERROR (VDD = 5V)
0
-0.2
-0.4 OFFSET ERROR (VDD = 3V)
-0.6
-0.8
-1.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
INL AND DNL vs. TEMPERATURE
1.0
0.8 VDD = VREF = 3V
0.6
0.4 MAX INL MAX DNL
0.2
0
-0.2
-0.4
MIN DNL
-0.6 MIN INL
-0.8
-1.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FULL-SCALE ERROR AND GAIN ERROR
vs. SUPPLY VOLTAGE
0.020
0.016
0.012
0.008
GAIN ERROR
0.004
0
-0.004
-0.008
FULL-SCALE ERROR
-0.012
-0.016
VREF = 2.5V (EXTERNAL)
NO LOAD
-0.020
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
1.4
OUT_ = FULL SCALE
NO LOAD
1.2
VREF (INTERNAL) = 4.096V,
VDD = 5V
VREF (INTERNAL) = 2.5V, VDD = 5V
1.0 VREF (INTERNAL) = 2.048V, VDD = 5V
0.8
VREF (EXTERNAL) = VDD = 5V
0.6
VREF (EXTERNAL) = VDD = 3V
0.4
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
1.2
1.1
VREF (INTERNAL) = 4.096V
1.0 VREF (INTERNAL) = 2.5V
0.9
0.8
0.7
0.6 VREF (EXTERNAL) = 2.5V
0.5
0.4 VREF (INTERNAL) = 2.048V
0.3
0.2
0.1
0
NO LOAD
TA = +25°C
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VDD (V)
Maxim Integrated
  8


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
POWER-DOWN MODE SUPPLY CURRENT
vs. TEMPERATURE
1.6
POWER-DOWN MODE
ALL DACs
1.2
TA = +125°C
0.8
TA = +85°C
TA = +25°C
0.4
TA = -40°C
0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
IREF (EXTERNAL) vs. CODE
60
VDD = VREF
NO LOAD
50
40 VREF = 5V
SUPPLY CURRENT vs. CODE
1.2
1.1
1.0
VDD = 5V, VREF
(INTERNAL) = 4.096V
VDD = 5V, VREF
(EXTERNAL) = 5V
0.9
0.8
0.7
0.6
0.5
0.4
VDD = 5V, VREF
(INTERNAL) = 2.048V
VDD = 3V, VREF
(EXTERNAL) = 3V
0.3
0.2
0.1
0
0
VDD = 5V, VREF
(INTERNAL) = 2.5V
NO LOAD
TA = +25°C
500 1000 1500 2000 2500 3000 3500 4000 4500
CODE (LSB)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
VOUT
0.5V/div
1/4 SCALE TO 3/4 SCALE
30
20 VREF = 3V
10
0
0 512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
TRIGGER PULSE
5V/div
3.75µs
ZOOMED VOUT
1 LSB/div
4µs/div
MAJOR CODE TRANSITION
GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
VOUT
0.5V/div
TRIGGER PULSE
5V/div
3/4 SCALE TO 1/4 SCALE
4.3µs
ZOOMED VOUT
1 LSB/div
4µs/div
ZOOMED VOUT
3.3mV/div
TRIGGER PULSE
5V/div
1 LSB CHANGE
(MIDCODE TRANSITION
0x7FF TO 0x800)
GLITCH ENERGY = 6.7nV•s
2µs/div
Maxim Integrated
  9


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
MAJOR CODE TRANSITION
GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
1 LSB CHANGE
(MIDCODE TRANSITION
0x800 TO 0x7FF)
GLITCH ENERGY = 6nV•s
VOUT vs. TIME TRANSIENT
EXITING POWER-DOWN
MAX5813 toc20
VSCL
0V 5V/div
36TH EDGE
DAC OUTPUT
500mV/div
ZOOMED VOUT
3.3mV/div
TRIGGER PULSE
5V/div
2µs/div
POWER-ON RESET TO 0V
MAX5813 toc21
0V
VDD = 5V, VREF = 2.5V
EXTERNAL
10µs /div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC,
RL = 2kI, CL = 200pF)
MAX5813 toc22
VDD = VREF = 5V
10kI LOAD TO VDD
VDD
2V/div
0V
VOUT
2V/div
0V
RL = 2kI
NO LOAD
TRANSITIONING
DAC
1V/div
STATIC DAC
1.25mV/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.5nV*s
TRIGGER PULSE
10V/div
20µs /div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC, NO LOAD)
MAX5813 toc23
NO LOAD
NO LOAD
TRANSITIONING
DAC
1V/div
STATIC DAC
1.25mV/div
4µs /div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V (INTERNAL),
TA = +25NC, RL = 2kI, CL = 200pF)
MAX5813 toc24
RL = 2kI
NO LOAD
TRANSITIONING
DAC
1V/div
STATIC DAC
1.25mV/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.8nV*s
TRIGGER PULSE
10V/div
5µs /div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.3nV*s
TRIGGER PULSE
10V/div
5µs /div
Maxim Integrated
  10


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V (INTERNAL),
TA = +25NC, NO LOAD) MAX5813 toc25
NO LOAD
NO LOAD
TRANSITIONING DAC
1V/div
STATIC DAC
1.25mV/div
DIGITAL FEEDTHROUGH
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5813 toc26
VDD = 5V
VREF = 5V (EXTERNAL)
DACS AT MIDSCALE
VOUT
1.65mV/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.1nV*S
4µs/div
TRIGGER PULSE
10V/div
OUTPUT LOAD REGULATION
10
8 VDD = VREF
6
4 VDD = 5V
2
0 VDD = 3V
-2
-4
-6
-8
-10
-30 -20 -10 0 10 20 30 40 50
IOUT (mA)
60
HEADROOM AT RAILS
vs. OUTPUT CURRENT (VDD = VREF)
5.00
4.50 DAC = FULL SCALE
4.00 VDD = 5V, SOURCING
3.50
3.00
2.50
2.00 VDD = 3V, SOURCING
1.50
1.00
0.50
DAC = ZERO SCALE
0
01234
VDD = 3V AND 5V
SINKING
56789
IOUT (mA)
10
Maxim Integrated
DIGITAL FEEDTHROUGH = 0.1nV·s·
40ns/div
OUTPUT CURRENT LIMITING
500
400 VDD = VREF
300
200
100 VDD = 5V
0
-100 VDD = 3V
-200
-300
-400
-500
-30 -20 -10 0 10 20 30 40 50 60 70
IOUT (mA)
NOISE-VOLTAGE DENSITY
VS. FREQUENCY (DAC AT MIDSCALE)
350
300
VDD = 5V, VREF = 4.096V
(INTERNAL)
250 VDD = 5V, VREF = 2.5V
(INTERNAL)
200 VDD = 5V, VREF = 2.048V
(INTERNAL)
150
100
50 VDD = 5V, VREF = 4.5V
(EXTERNAL)
0
100 1k 10k
FREQUENCY (Hz)
100k
  11


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
REFERENCE (VDD = 5V, VREF = 4.5V)
MAX5813 toc31
MIDSCALE UNLOADED
VP-P = 12µV
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.048V)
MAX5813 toc32
MIDSCALE UNLOADED
VP-P = 13µV
2µV/div
2µV/div
4s/div
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.5V)
MAX5813 toc33
MIDSCALE UNLOADED
VP-P = 15µV
2µV/div
4s/div
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 4.096V)
MAX5813 toc34
MIDSCALE UNLOADED
VP-P = 16µV
2µV/div
4s/div
VREF DRIFT vs. TEMPERATURE
25 VDD = 2.7V,
INTERNAL VREF = 2.5V
20 BOX METHOD
15
10
5
0
2.8 2.9 3.0 3.2 3.3 3.4 3.6 3.7 3.9 4.0 4.1 4.3 4.4
TEMPERATURE DRIFT (ppm/°C)
Maxim Integrated
REFERENCE LOAD REGULATION
0
VDD = 5V
INTERNAL REFERENCE
-0.2
-0.4
-0.6
VREF = 2.048V, 2.5V, AND 4.096V
-0.8
-1.0
0 50 100 150 200 250 300 350 400 450 500
REFERENCE OUTPUT CURRENT (µA)
4s/div
SUPPLY CURRENT vs. INPUT LOGIC VOLTAGE
2000
1800
1600
1400
1200 VDDIO = 5V
1000
800
600 VDDIO = 3V
400
200
0
0
VDDIO = 1.8V
1234
INPUT LOGIC VOLTAGE (V)
5
  12


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Pin/Bump Configurations
TOP VIEW
REF
OUTA
OUTB
GND
OUTC
OUTD
VDD
1
2
3
4
5
6
7
+
MAX5813
MAX5814
MAX5815
TSSOP
14 LDAC
13 VDDIO
12 CLR
11 SDA
10 SCL
9 ADDR0
8 ADDR1
TOP VIEW
MAX5813/MAX5814/MAX5815
1 2 34
+ OUTA
OUTB
OUTC
OUTD
A
REF
B
GND VDDIO VDD
CLR SDA SCL ADDR0
C
WLP
PIN
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BUMP
WLP
B1
A1
A2
B2
A3
A4
B4
C4
C3
C2
C1
B3
NAME
REF
OUTA
OUTB
GND
OUTC
OUTD
VDD
ADDR1
ADDR0
SCL
SDA
CLR
VDDIO
LDAC
Pin/Bump Description
FUNCTION
Reference Voltage Input/Output
Buffered Channel A DAC Output
Buffered Channel B DAC Output
Ground
Buffered Channel C DAC Output
Buffered Channel D DAC Output
Supply Voltage Input. Bypass VDD with a 0.1FF capacitor to GND.
I2C Interface Address Selection Bit 1
I2C Interface Address Selection Bit 0
I2C Interface Clock Input
I2C Bidirectional Serial Data
Active-Low Clear Input
Digital Interface Power-Supply Input
Load DAC. Active-low hardware load DAC input.
Maxim Integrated
  13


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Detailed Description
The MAX5813/MAX5814/MAX5815 are 4-channel, low-
power, 8-/10-/12-bit buffered voltage-output DACs. The
2.7V to 5.5V wide supply voltage range and low-power
consumption accommodates most low-power and low-
voltage applications. The devices present a 100kI load
to the external reference. The internal output buffers
allow rail-to-rail operation. An internal voltage reference
is available with software selectable options of 2.048V,
2.5V, or 4.096V. The devices feature a fast 400kHz I2C-
compatible interface. The MAX5813/MAX5814/MAX5815
include a serial-in/parallel-out shift register, internal
CODE and DAC registers, a power-on-reset (POR) cir-
cuit to initialize the DAC outputs to code zero, and con-
trol logic. CLR is available to asynchronously clear the
device independent of the serial interface.
DAC Outputs (OUT_)
The MAX5813/MAX5814/MAX5815 include internal buf-
fers on all DAC outputs. The internal output buffers
provide improved load regulation for the DAC outputs.
The output buffers slew at 1V/Fs (typ) and drive up to
2kI in parallel with 500pF. The analog supply voltage
(VDD) determines the maximum output voltage range
of the devices as VDD powers the output buffer. Under
no-load conditions, the output buffers drive from GND to
VDD, subject to offset and gain errors. With a 2kω load to
GND, the output buffers drive from GND to within 200mV
of VDD. With a 2kω load to VDD, the output buffers drive
from VDD to within 200mV of GND.
The DAC ideal output voltage is defined by:
V=OUT
VREF
×
D
2N
where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution.
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
Functional Diagram). The contents of the CODE register
hold pending DAC output settings which can later be
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user com-
mands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands or the LDAC
hardware pin.
The contents of both CODE and DAC registers are main-
tained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register
contents. SW_CLEAR and SW_RESET commands reset
the contents of all CODE and DAC registers to their zero-
scale defaults.
Internal Reference
The MAX5813/MAX5814/MAX5815 include an internal
precision voltage reference that is software selectable
to be 2.048V, 2.500V, or 4.096V. When an internal refer-
ence is selected, that voltage is available on the REF pin
for other external circuitry (see Figure 9) and can drive
a 25kI load.
External Reference
The external reference input has a typical input
impedance of 100kI and accepts an input voltage
from +1.24V to VDD. Connect an external voltage
supply between REF and GND to apply an exter-
nal reference. The MAX5813/MAX5814/MAX5815
power up and reset to external reference mode. Visit
www.maximintegrated.com/products/references for a
list of available external voltage-reference devices.
Load DAC (LDAC) Input
The MAX5813/MAX5814/MAX5815 feature an active-
low LDAC logic input that allows the outputs to update
asynchronously. Connect LDAC to VDDIO or keep LDAC
high during normal operation when the device is con-
trolled only through the serial interface. Drive LDAC low
to simultaneously update the DAC outputs with data
from the CODE registers. Holding LDAC low causes the
DAC registers to become transparent and CODE data is
passed through to the DAC registers immediately updat-
ing the DAC outputs. A software CONFIG command can
be used to configure the LDAC operation of each DAC
independently.
Maxim Integrated
  14


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Clear Input (CLR)
The MAX5813/MAX5814/MAX5815 feature an asynchro-
nous active-low CLR logic input that simultaneously sets
all four DAC outputs to zero. Driving CLR low clears the
contents of both the CODE and DAC registers and also
aborts the on-going I2C command. To allow a new I2C
command, drive CLR high, satisfying the tCLRSTA timing
requirement.
Figure 2
S
SCL
SDA
Sr P
Interface Power Supply (VDDIO)
The MAX5813/MAX5814/MAX5815 feature a separate
supply pin (VDDIO) for the digital interface (1.8V to 5.5V).
Connect VDDIO to the I/O supply of the host processor.
I2C Serial Interface
The MAX5813/MAX5814/MAX5815 feature an I2C-/
SMBusK-compatible, 2-wire serial interface consisting of
a serial data line (SDA) and a serial clock line (SCL). SDA
and SCL enable communication between the MAX5813/
MAX5814/MAX5815 and the master at clock rates up
to 400kHz. Figure 1 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
MAX5813/MAX5814/MAX5815 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5813/
MAX5814/MAX5815 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX5813/MAX5814/MAX5815 must transmit the
proper slave address followed by a series of nine SCL
pulses for each byte of data requested. The MAX5813/
MAX5814/MAX5815 transmit data on SDA in sync with
the master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START or Repeated START condition, a
not acknowledge, and a STOP condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically 4.7kI is required on SDA. SCL oper-
ates only as an input. A pullup resistor, typically 4.7kI, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5813/
MAX5814/MAX5815 from high voltage spikes on the bus
lines and minimize crosstalk and undershoot of the bus
VALID START, REPEATED START, AND STOP PULSES
PS
SP
PSP
INVALID START/STOP PULSE PAIRINGS -ALL WILL BE RECOGNIZED AS STARTS
Figure 2. I2C START, Repeated START, and STOP Conditions
signals. The MAX5813/MAX5814/MAX5815 can accom-
modate bus voltages higher than VDDIO up to a limit of
5.5V; bus voltages lower than VDDIO are not recommend-
ed and may result in significantly increased interface cur-
rents. The MAX5813/MAX5814/MAX5815 digital inputs
are double buffered. Depending on the command issued
through the serial interface, the CODE register(s) can
be loaded without affecting the DAC register(s) using
the write command. To update the DAC registers, either
drive the LDAC input low to asynchronously update all
DAC outputs, or use the software LOAD command.
I2C START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
SMBus is a trademark of Intel Corp.
Maxim Integrated
  15


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
to the MAX5813/MAX5814/MAX5815. The master termi-
nates transmission and frees the bus, by issuing a STOP
condition. The bus remains active if a Repeated START
condition is generated instead of a STOP condition.
START
CONDITION
CLOCK PULSE
FOR
ACKNOWLEDGMENT
I2C Early STOP and
Repeated START Conditions
The MAX5813/MAX5814/MAX5815 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse as
a START condition. Transmissions ending in an early
STOP condition will not impact the internal device set-
tings. If the STOP occurs during a readback byte, the
transmission is terminated and a later read mode request
will begin transfer of the requested register data from
the beginning (this applies to combined format I2C read
mode transfers only, interface verification mode transfers
will be corrupted). See Figure 2.
I2C Slave Address
The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the R/W bit. See
Figure 4. For the TSSOP packages, the three most signifi-
cant bits are 001 with the 4 LSBs determined by ADDR1
and ADDR0 as shown in Table 1. For the WLP package,
the five most significant bits are 00011 with the 2 LSBs
determined by ADDR0 as shown in Table 2. Setting
the R/W bit to 1 configures the MAX5813/MAX5814/
MAX5815 for read mode. Setting the R/W bit to 0 config-
ures the MAX5813/MAX5814/MAX5815 for write mode.
The slave address is the first byte of information sent
to the MAX5813/MAX5814/MAX5815 after the START
condition.
The MAX5813/MAX5814/MAX5815 have the ability to
detect an unconnected state on the ADDR input for
additional address flexibility; if leaving the ADDR input
unconnected, be certain to minimize all loading on the
pin (i.e. provide a landing for the pin, but do not allow
any board traces).
I2C Broadcast Address
A broadcast address is provided for the purpose of
updating or configuring all MAX5813/MAX5814/MAX5815
devices on a given I2C bus. All MAX5813/MAX5814/
MAX5815 devices acknowledge and respond to the
broadcast device address 00010000. The devices will
respond to the broadcast address, regardless of the
state of the address pins. The broadcast mode is intend-
ed for use in write mode only (as indicated by R/W = 0 in
the address given).
SCL 1 2
SDA
Figure 3. I2C Acknowledge
9
NOT ACKNOWLEDGE
ACKNOWLEDGE
Table 1. I2C Slave Address LSBs for
TSSOP Package
ADDR1
VDDIO
VDDIO
VDDIO
N.C.
N.C.
N.C.
GND
GND
GND
TSSOP PACKAGE (A[6:4] = 001)
ADDR0
A3
A2
A1
VDDIO
0
0
0
N.C.
0
0
1
GND
0
0
1
VDDIO
1
0
0
N.C.
1
0
1
GND
1
0
1
VDDIO
1
1
0
N.C.
1
1
1
GND
1
1
1
A0
0
0
1
0
0
1
0
0
1
Table 2. I2C Slave Address LSBs for WLP
Package
WLP PACKAGE (A[6:2] = 00011)
ADDR0
A1
VDDIO
N.C.
0
1
GND
1
A0
0
0
1
Maxim Integrated
  16


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
I2C Acknowledge
In write mode, the acknowledge bit (ACK) is a clocked 9th
bit that the MAX5813/MAX5814/MAX5815 use to hand-
shake receipt of each byte of data as shown in Figure 3.
The MAX5813/MAX5814/MAX5815 pull down SDA during
the entire master-generated 9th clock pulse if the previous
byte is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccess-
ful data transfer, the bus master will retry communication.
In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5813/MAX5814/MAX5815. An acknowledge is sent
by the master after each read byte to allow data transfer
to continue. A not-acknowledge is sent when the master
reads the final byte of data from the MAX5813/MAX5814/
MAX5815, followed by a STOP condition.
I2C Command Byte and Data Bytes
A command byte follows the slave address. A command
byte is typically followed by two data bytes unless it is
the last byte in the transmission. If data bytes follow the
command byte, the command byte indicates the address
of the register that is to receive the following two data
bytes. The data bytes are stored in a temporary register
and then transferred to the appropriate register during
the ACK periods between bytes. This avoids any glitch-
ing or digital feedthrough to the DACs while the interface
is active.
I2C Write Operations
A master device communicates with the MAX5813/
MAX5814/MAX5815 by transmitting the proper slave
address followed by command and data words. Each
transmit sequence is framed by a START or Repeated
START condition and a STOP condition as described
above. Each word is 8 bits long and is always followed
by an acknowledge clock (ACK) pulse as shown in the
Figure 4 and Figure 5. The first byte contains the address
of the MAX5813/MAX5814/MAX5815 with R/W = 0 to
indicate a write. The second byte contains the register
(or command) to be written and the third and fourth bytes
contain the data to be written. By repeating the register
address plus data pairs (Byte #2 through Byte #4 in
Figure 4 and Figure 5), the user can perform multiple
register writes using a single I2C command sequence.
There is no limit as to how many registers the user can
write with a single command. The MAX5813/MAX5814/
MAX5815 support this capability for all user-accessible
write mode commands.
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
START
SDA
SCL
0 0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
STOP
A ACK. GENERATED BY MAX5813/MAX5814/MAX5815
COMMAND EXECUTED
*I2C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 4. I2C Single Register Write Sequence
Maxim Integrated
  17


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
START
SDA
SCL
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
WRITE COMMAND1
BYTE #2: COMMAND1 BYTE
(B[23:16])
WRITE DATA1
BYTE #3: DATA1 HIGH BYTE
(B[15:8])
WRITE DATA1
BYTE #4: DATA1 LOW BYTE
(B[7:0])
0 0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
ADDITIONAL COMMAND AND
DATA PAIRS (3 BYTE BLOCKS)
COMMAND1
EXECUTED
BYTE #5: COMMANDn BYTE
(B[23:16])
BYTE #6: DATAn HIGH BYTE
(B[15:8])
BYTE #7: DATAn LOW BYTE
(B[7:0])
23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
STOP
A ACK. GENERATED BY MAX5813/MAX5814/MAX5815
*I2C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 5. Multiple Register Write Sequence (Standard I2C Protocol)
COMMANDn
EXECUTED
START
SDA
SCL
WRITE ADDRESS
BYTE #1: I2C SLAVE
ADDRESS*
WRITE COMMAND 1
BYTE #2: COMMAND 1
BYTE
READ ADDRESS
REPEATED BYTE #3: I2C SLAVE
START
ADDRESS*
READ DATA
BYTE #4: DATA 1 HIGH
BYTE (B[15:8])
READ DATA
BYTE #5: DATA 1 LOW
BYTE (B[7:0])
STOP
0 0 1 A3 A2 A1 A0 W A 0 0 N N N N N N A
0 0 1 A3 A2 A1 A0 R A D D D D D D D D A D D D D D D D D ~A
A ACK. GENERATED BY MAX5813/MAX5814/ MAX5815
*I2C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 6. Standard I2C Register Read Sequence
A ACK. GENERATED BY I2C MASTER
Combined Format I2C Readback Operations
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in Figure 6. The first byte contains
the address of the MAX5813/MAX5814/MAX5815 with
R/W = 0 to indicate a write. The second byte contains
the register that is to be read back. There is a Repeated
START condition, followed by the device address with
R/W = 1 to indicate a read and an acknowledge clock.
The master has control of the SCL line but the MAX5813/
MAX5814/MAX5815 take over the SDA line. The final two
bytes in the frame contain the register data readback
followed by a STOP condition. If additional bytes beyond
those required to readback the requested data are pro-
vided, the MAX5813/MAX5814/MAX5815 will continue to
readback ones.
Readback of individual CODE registers is supported for
the CODE command (B[23:20] = 0000). For this com-
mand, which supports a DAC address, the requested
channel CODE register content will be returned; if all
DACs are selected, CODEA content will be returned.
Readback of individual DAC registers is supported for
all LOAD commands (B[23:20] = 0001, 0010, or 0011).
For these commands, which support a DAC address, the
requested DAC register content will be returned. If all
DACs are selected, DACA content will be returned.
Modified readback of the POWER register is supported
for the POWER command (B[23:20] = 0100). The power
status of each DAC is reported in locations B[3:0], with a
1 indicating the DAC is powered down and a 0 indicating
the DAC is operational (see Table 3).
Maxim Integrated
  18


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s reference status and the device ID and revi-
sion information in the format as shown in Table 3.
Interface Verification I2C
Readback Operations
While the MAX5813/MAX5814/MAX5815 support stan-
dard I2C readback of selected registers, it is also
capable of functioning in an interface verification mode.
This mode is accessed any time a readback operation
follows an executed write mode command. In this mode,
the last executed three-byte command is read back in its
entirety. This behavior allows verification of the interface.
Sample command sequences are shown in Figure 7.
The first command transfer is given in write mode with
R/W = 0 and must be run to completion to qualify for
interface verification readback. There is now a STOP/
START pair or Repeated START condition required, fol-
lowed by the readback transfer with R/W = 1 to indicate
a read and an acknowledge clock from the MAX5813/
MAX5814/MAX5815. The master still has control of the
SCL line but the MAX5813/MAX5814/MAX5815 take over
the SDA line. The final three bytes in the frame contain
the command and register data written in the first transfer
presented for readback, followed by a STOP condition. If
additional bytes beyond those required to read back the
requested data are provided, the MAX5813/MAX5814/
MAX5815 will continue to read back ones.
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I2C transfers involv-
ing other devices do not impact the MAX5813/MAX5814/
MAX5815 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I2C readback operation
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands writ-
ten using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
one time; partial and/or multiple attempts to readback
executed in succession will not yield usable data.
Table 3. Standard I2C User Readback Data
COMMAND BYTE (REQUEST)
READBACK DATA HIGH BYTE
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8
0000
DAC selection
CODEn[11:4]
0001
DAC selection
DACn[11:4]
0010
DAC selection
DACn[11:4]
0011
DAC selection
DACn[11:4]
0 1 0 0 0 0XX0 0 0 0 0 0 0 0
10000000
CODEA[11:4]
10000001
DACA[11:4]
10100010
DACA[11:4]
10110011
DACA[11:4]
Any other command (TSSOP)
1111 1000
Any other command (WLP)
1001 1000
READBACK DATA LOW BYTE
B7 B6 B5 B4 B3 B2 B1 B0
CODEn[3:0]
0000
DACn[3:0]
0000
DACn[3:0]
0000
DACn[3:0]
0000
0 0 0 0 PWD PWC PWB PWA
CODEA[3:0]
0000
DACA[3:0]
0000
DACA[3:0]
0000
DACA[3:0]
0000
000 REV_ID[2:0] REF MODE
000
(010)
RF[1:0]
Table 4. Format DAC Data Bit Positions
PART
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
MAX5813 D7 D6 D5 D4 D3 D2 D1 D0 x x x x x x x x
MAX5814 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x x x x x
MAX5815 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x x x
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MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
SDA 0 0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
SCL
STOP
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
0 0 1 A3 A2 A1 A0 R A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 ~A
STOP
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
REPEATED
START
SDA 0 0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
0 0 1 A3 A2 A1 A0 R A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 ~A
STOP
A ACK. GENERATED BY MAX5813/MAX5814/MAX5815
*I2C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
A ACK. GENERATED BY I2C MASTER
Figure 7. Interface Verification I2C Register Read Sequences
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MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
µC
SDA SCL
MAX5813
MAX5814
MAX5815
SCL
SDA
ADDR0
(ADDR1)
+5V
( ) TSSOP PACKAGE ONLY
MAX5813
MAX5814
MAX5815
SCL
SDA
ADDR0
(ADDR1)
Figure 8. Typical I2C Application Circuit
I2C Compatibility
The MAX5813/MAX5814/MAX5815 are fully compatible
with existing I2C systems. SCL and SDA are high-imped-
ance inputs; SDA has an open drain which pulls the data
line low to transmit data or ACK pulses. Figure 8 shows a
typical I2C application.
I2C User-Command Register Map
This section lists the user accessible commands and
registers for the MAX5813/MAX5814/MAX5815.
Table 5 provides detailed information about the Command
Registers.
CODEn Command
The CODEn command (B[23:20] = 0000) updates the
CODE register contents for the selected DAC(s). Changes
to the CODE register content based on this command will
not affect DAC outputs directly unless the LDAC is in a
low state or the DAC latch has been configured to be
transparent. Issuing the CODEn command with DAC
SELECTION = ALL DACs is equivalent to CODE_ALL
(B[23:16] = 10000000). See Table 5 and Table 6.
LOADn Command
The LOADn command (B[23:20] = 0001) updates the
DAC register content for the selected DAC(s) by upload-
ing the current contents of the CODE register. The
LOADn command can be used with DAC SELECTION =
ALL DACs to issue a software load for all DACs, which
is equivalent to the LOAD_ALL (B[23:16] = 10000001)
command. See Table 5 and Table 6.
CODEn_LOAD_ALL Command
The CODEn_LOAD_ALL command (B[23:20] = 0010)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of all DACs.
Channels for which the CODE register content has not
been modified since the last load to DAC register or LDAC
operation will not be updated to reduce digital crosstalk.
Issuing this command with DAC_ADDRESS = ALL is
equivalent to the CODE_ALL_LOAD_ALL command. The
CODEn_LOAD_ALL command by definition will modify at
least one CODE register. To avoid this, use the LOADn
command with DAC SELECTION = ALL DACs or use the
LOAD_ALL command. See Table 5 and Table 6.
CODEn_LOADn Command
The CODEn_LOADn command (B[23:20] = 0011) updates
the CODE register contents for the selected DAC(s) as
well as the DAC register content of the selected DAC(s).
Channels for which the CODE register content has not
been modified since the last load to DAC register or
LDAC operation will not be updated to reduce digital
crosstalk. Issuing this command with DAC SELECTION
= ALL DACs is equivalent to the CODE_ALL_LOAD_ALL
command. See Table 5 and Table 6.
CODE_ALL Command
The CODE_ALL command (B[23:16] = 10000000)
updates the CODE register contents for all DACs. See
Table 5.
LOAD_ALL Command
The LOAD_ALL command (B[23:16] = 10000001) updates
the DAC register content for all DACs by uploading the
current contents of the CODE registers. See Table 5.
CODE_ALL_LOAD_ALL Command
The CODE_ALL_LOAD_ALL command (B[23:16] =
1000001x) updates the CODE register contents for all
DACs as well as the DAC register content of all DACs.
See Table 5.
Maxim Integrated
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Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
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Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
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Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Table 6. DAC Selection
B19 B18 B17 B16
DAC SELECTED
0 0 0 0 DAC A
0 0 0 1 DAC B
0 0 1 0 DAC C
0 0 1 1 DAC D
X 1 X X ALL DACs
1 X X X ALL DACs
POWER Command
The MAX5813/MAX5814/MAX5815 feature a software-
controlled power-mode (POWER) command (B[23:20] =
0100). The POWER command updates the power-mode
settings of the selected DACs while the power settings of
the rest of the DACs remain unchanged. The new power
setting is determined by bits B[17:16] while the affected
DAC(s) are selected by bits B[11:8]. If all DACs are pow-
ered down, the device enters a STANDBY mode.
In power-down, the DAC output is disconnected from the
buffer and is grounded with either one of the two select-
able internal resistors or set to high impedance. See Table
8 for the selectable internal resistor values in power-down
mode. In power-down mode, the DAC register retains its
value so that the output is restored when the device pow-
ers up. The serial interface remains active in power-down
mode.
In STANDBY mode, the internal reference can be pow-
ered down or it can be set to remain powered-on for
external use. Also, in STANDBY mode, devices using the
external reference do not load the REF pin. See Table 7.
SW_RESET and SW_CLEAR Command
The SW_RESET (B[23:16] = 01010001) and SW_CLEAR
(B[23:16] = 01010000) commands provide a means of
issuing a software reset or software clear operation. Use
SW_CLEAR to issue a software clear operation to return
all CODE and DAC registers to the zero-scale value. Use
SW_RESET to reset all CODE, DAC, and configuration
registers to their default values.
Table 7. POWER (100) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8
0 1 0 0 0 0 PD1 PD0 X X X X D C B A
POWER Command
Power
Mode:
00 =
Normal
01 = 1kI
10 =
100kI
11 = Hi-Z
Don’t Care
DAC Select:
1 = DAC Selected
0 = DAC Not
Selected
Default Values (all DACs) 0 0 X X X X 1 1 1 1
B7 B6 B5 B4 B3 B2 B1 B0
XXXXXXXX
Don’t Care
XXXXXXXX
Table 8. Selectable DAC Output Impedance in Power-Down Mode
PD1 (B17)
PD0 (B16)
OPERATING MODE
0 0 Normal operation
0 1 Power-down with internal 1kI pulldown resistor to GND.
1 0 Power-down with internal 100kI pulldown resistor to GND.
1 1 Power-down with high-impedance output.
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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
CONFIG Command
The CONFIG command (B[23:20] = 0110) updates the
LDAC and LOAD functions of selected DACs. Issue the
command with B16 = 0 to allow the DAC latches to oper-
ate normally or with B16 = 1 to disable the DAC latches,
making them perpetually transparent. Mode settings of
the selected DACs are updated while the mode settings
of the rest of the DACs remain unchanged; DAC(s) are
selected by bits B[11:8]. See Table 9.
REF Command
The REF command updates the global reference setting
used for all DAC channels. Set B[17:16] = 00 to use an
external reference for the DACs or set B[17:16] to 01, 10,
or 11 to select either the 2.5V, 2.048V, or 4.096V internal
reference, respectively.
If RF2 (B18) is set to zero (default) in the REF command,
the reference will be powered down any time all DAC
channels are powered down (in STANDBY mode). If RF2
(B18 = 1) is set to one, the reference will remain powered
even if all DAC channels are powered down, allowing
continued operation of external circuitry. In this mode,
the 1FA shutdown state is not available. See Table 10.
Table 9. CONFIG Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 1 1 0 All 0 0 LDB X X X X D C B A X X X X X X X X
CONFIG Command
CONFIG
Command
Don’t Care
DAC Select:
1 = DAC Selected
0 = DAC Not
Selected
Don’t Care
Default Values (All DACs)
0 X XXX1 11 1 XXXXXXXX
Table 10. REF Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 1 1 1 0 RF2 RF1 RF0 X X X X X X X X X X X X X X X X
REF Command
REF Mode:
00 = EXT
01 = 2.5V
10 = 2.0V
11 = 4.0V
Don’t Care
Don’t Care
Default Values
0 0 0 X XXXXXX X XXXXXXXX
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  25


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Applications Information
Power-On Reset (POR)
When power is applied to VDD and VDDIO, the DAC out-
put is set to zero scale. To optimize DAC linearity, wait
until the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Power Supplies and
Bypassing Considerations
Bypass VDD and VDDIO with high-quality ceramic capac-
itors to a low-impedance ground as close as possible to
the device. Minimize lead lengths to reduce lead induc-
tance. Connect the GND to the analog ground plane.
Layout Considerations
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with a
low-inductance ground plane, or star connect all ground
return paths back to the MAX5813/MAX5814/MAX5815
GND. Carefully layout the traces between channels to
reduce AC cross-coupling. Do not use wire-wrapped
boards and sockets. Use shielding to minimize noise immu-
nity. Do not run analog and digital signals parallel to one
another, especially clock signals. Avoid routing digital lines
underneath the MAX5813/MAX5814/MAX5815 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R 1 LSB, the DAC
output may still be monotonic.
Offset Error
Offset error indicates how well the actual transfer function
matches the ideal transfer function. The offset error is
calculated from two measurements near zero code and
near maximum code.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Zero-Scale Error
Zero-scale error is the difference between the DAC
output voltage when set to code zero and ground. This
includes offset and other die level nonidealities.
Full-Scale Error
Full-scale error is the difference between the DAC output
voltage when set to full scale and the reference voltage.
This includes offset, gain error, and other die level noni-
dealities.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
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Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Detailed Functional Diagram
REF
100kI RIN
INTERNAL / EXTERNAL REFERENCE (USER OPTION)
VDD
CODE
REGISTER
A
DAC
LATCH
A
8-/10-/12-BIT
DAC A
MAX5813
MAX5814
MAX5815
BUFFER A
OUTA
VDDIO
SCL
SDA
ADDR0
(ADDR1)
CLR
(LDAC)
I2C SERIAL
INTERFACE
POR
CODE
CLEAR /
RESET
LOAD
CLEAR /
RESET
DAC CONTROL LOGIC
POWER-DOWN
100kI 1kI
CODE
REGISTER
B
DAC
LATCH
B
8-/10-/12-BIT
DAC B
BUFFER B
OUTB
CODE
CLEAR /
RESET
LOAD
CLEAR /
RESET
DAC CONTROL LOGIC
POWER-DOWN
100kI 1kI
CODE
REGISTER
C
DAC
LATCH
C
8-/10-/12-BIT
DAC C
BUFFER C
OUTC
CODE
CLEAR /
RESET
LOAD
CLEAR /
RESET
DAC CONTROL LOGIC
POWER-DOWN
100kI 1kI
CODE
REGISTER
D
DAC
LATCH
D
8-/10-/12-BIT
DAC D
BUFFER D
OUTD
() TSSOP PACKAGE ONLY
Maxim Integrated
CODE
CLEAR /
RESET
LOAD
CLEAR /
RESET
DAC CONTROL LOGIC
POWER-DOWN
GND
100kI 1kI
  27


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Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
100nF
MICRO-
CONTROLLER
RPU =
5kI
RPU =
5kI
VDDIO
VDD
4.7µF
VDDIO
VDD
(LDAC)
SDA
DAC
SCL
ADDR0
(ADDR1)
MAX5813
MAX5814
MAX5815
CLR
GND
OUT
REF
100µF
R1 R2
R1 = R2
( ) TSSOP PACKAGE ONLY
NOTE: ONE CHANNEL SHOWN
Figure 9. Bipolar Operating Circuit
Typical Operating Circuit
100nF
RPU =
5kI
RPU =
5kI
MICRO-
CONTROLLER
( ) TSSOP PACKAGE ONLY
NOTE: UNIPOLAR OPERATION (ONE CHANNEL SHOWN)
Maxim Integrated
VDDIO
VDD
4.7µF
VDDIO
VDD
(LDAC)
SDA
DAC
SCL
ADDR0
(ADDR1)
MAX5813
MAX5814
MAX5815
CLR
GND
OUT_
REF
100µF
  28


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Ordering Information
PART
PIN-PACKAGE
RESOLUTION (BIT)
MAX5813AUD+T*
14 TSSOP
8
MAX5814AUD+T*
14 TSSOP
10
MAX5815AAUD+T
14 TSSOP
12
MAX5815BAUD+T*
14 TSSOP
12
MAX5815AWC+T
12 WLP
12
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Future product—Contact factory for availability.
INTERNAL REFERENCE TEMPCO (ppm/NC)
10 (typ)
10 (typ)
3 (typ),10 (max)
10 (typ)
3 (typ),10 (max)
PROCESS: BiCMOS
Chip Information
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
14 TSSOP
12 WLP
PACKAGE
CODE
U14+1
W121B2+1
OUTLINE
NO.
LAND
PATTERN NO.
21-0066
90-0113
21-0009
Refer to
Application Note 1891
Maxim Integrated
  29


MAX5815 (Maxim Integrated Products)
Ultra-Small Quad-Channel 8-/10-/12-Bit Buffered Output DACs

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MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Revision History
REVISION
NUMBER
0
1
2
3
REVISION
DATE
DESCRIPTION
2/12
6/12
Initial release
Revised the Electrical Characteristics and Typical Operating Characteristics.
11/12
Revised the Electrical Characteristics, Typical Operating Characteristics, Ordering
Information, Figure 9, and Typical Operating Circuit.
1/13
Updated the Electrical Characteristics and the Ordering Information.
PAGES
CHANGED
3, 5, 9, 12
7, 8, 9, 11, 12,
25, 26, 28, 29
7, 29
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
30
©  2013 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.




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