MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Features
NAND Flash and Mobile LPDRAM
152-Ball Package-on-Package (PoP)
Combination Memory (TI OMAP™)
MT29C Family
Current production part numbers: See Table 1 on page 3
Features
• Micron® NAND Flash and Mobile LPDRAM
components
• RoHS-compliant, “green” package
• Separate NAND Flash and Mobile LPDRAM
interfaces
• Space-saving package-on-package combination
• Low-voltage operation (1.70–1.95V)
• Industrial temperature range: –40°C to +85°C
NAND Flash-Specific Features
• Organization
Page size
x8: 2112 bytes (2048 + 64 bytes)
x16: 1056 words (1024 + 32 words)
Block size: 64 pages (128K + 4K bytes)
Mobile LPDRAM-Specific Features
• No external voltage reference required
• No minimum clock rate requirement
• 1.8V LVCMOS-compatible inputs
• Programmable burst lengths
• Partial-array self refresh (PASR)
• Deep power-down (DPD) mode
• Selectable output drive strength
• STATUS REGISTER READ (SRR) supported1
Figure 1: PoP Block Diagram
NAND Flash
Power
NAND Flash
Device
NAND Flash
Interface
LP-DRAM Power
www.DataSheet.net/
LP-DRAM
Device
LP-DRAM Interface
Options
• LP-DRAM
166 MHz CL32
133 MHz CL3
Marking
-6
-75
Notes: 1. Contact factory for remapped SRR output.
2. CL = CAS (READ) latency.
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Datasheet pdf - http://www.DataSheet4U.co.kr/


MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Part Numbering Information – 152-Ball PoP
Part Numbering Information – 152-Ball PoP
Micron NAND Flash and LPDRAM devices are available in different configurations and
densities.
Figure 2: 152-Ball Part Number Chart
Micron Technology
Product Family
29C = NAND + LPDRAM MCP
NAND Density
1G = 1Gb
2G = 2Gb
4G = 4Gb
LPDRAM Density
12M = 512Mb
24M = 1024Mb
48M = 2048Mb
Operating Voltage Range
A = 1.8V (1.70–1.95V)
NAND Flash Configuration
Width Density Generation
C x8
1Gb First
D x16 1Gb First
J x8
2Gb Second
K x16 2Gb Second
N x8
4Gb First
P x16 4Gb First
U x8
1Gb Second
V x16 1Gb Second
MT 29C 1G 24M A C J A CG – x
www.DataSheet.net/
LPDRAM Configuration
Type Width Density Generation
J DDR x16 1Gb First
L DDR x32 1Gb First
N DDR x16 512Mb Second
R DDR x32 512Mb Second
IT ES
Production Status
Blank = Production
ES = Engineering sample
MS = Mechanical sample
Operating Temperature Range
IT = Industrial (–40° to +85°C)
LPDRAM Self Refresh Current
Blank = Standard
LPDRAM Access Time
–6 166 MHz CL3
–75 133 MHz CL3
Package Codes
CA = 152-ball PoP VFBGA (14 x 14 x 0.9mm)
CG = 152-ball PoP VFBGA (14 x 14 x 1.0mm)
JQ = 152-ball PoP TFBGA (14 x 14 x 1.1mm)
Chip Count
CE#, CS# Chip Count
A 1, 1 1 NAND, 1 DRAM
B 1, 1 2 NAND, 1 DRAM
C 1, 2 1 NAND, 2 DRAM
D 1, 2 2 NAND, 2 DRAM
Note: Not all possible combinations are available. Contact factory for availability.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
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©2008 Micron Technology, Inc. All rights reserved.
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Device Marking
Table 1: Production Part Numbers
Part Number
MT29C4G48MAPLCCA-6 IT
MT29C4G48MAPLCCA-75 IT
MT29C4G48MAPLCJQ-6 IT
MT29C4G48MAPLCJQ-75 IT
MT29C1G12MADRACG-6 IT
MT29C1G12MADRACG-75 IT
MT29C2G24MAKLACG-6 IT
MT29C2G24MAKLACG-75 IT
MT29C1G12MAURACA-6 IT
MT29C1G12MAURACA-75 IT
MT29C1G12MAVRACA-6 IT
MT29C1G12MAVRACA-75 IT
NAND Product
MT46H32M32LFJG-6 IT
MT46H32M32LFJG-6 IT
MT46H32M32LFJG-6 IT
MT46H32M32LFJG-6 IT
MT46H16M32LFCM-6 IT
MT46H16M32LFCM-6 IT
MT46H32M32LFJG-6 IT
MT46H32M32LFJG-6 IT
MT46H16M32LFCM-6 IT
MT46H16M32LFCM-6 IT
MT46H16M32LFCM-6 IT
MT46H16M32LFCM-6 IT
LPDDR Product
MT29F4G16ABCWC-ET
MT29F4G16ABCWC-ET
MT29F4G16ABCWC-ET
MT29F4G16ABCWC-ET
MT29F1G16ABBHC-ET
MT29F1G16ABBHC-ET
MT29F2G16ABDHC-ET
MT29F2G16ABDHC-ET
MT29F1G08ABCHC-ET
MT29F1G08ABCHC-ET
MT29F1G16ABCHC-ET
MT29F1G16ABCHC-ET
Physical Part
Marking
JW399
JW400
JW297
JW296
JW226
JW227
JW188
JW189
JW385
JW384
JW375
JW374
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the
top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanu-
meric code is used. The abbreviated device marks are cross-referenced to the Micron
part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To
view the location of the abbreviated mark on the device, refer to customer service note
CSN-11, “Product Mark/Label,” at www.micron.com/csn.
www.DataSheet.net/
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.co.kr/


MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
General Description
General Description
Micron package-on-package (PoP) products combine NAND Flash and Mobile LPDRAM
devices in a single MCP. These products target mobile applications with low-power,
high-performance, and minimal package-footprint design requirements. The NAND
Flash and Mobile LPDRAM devices are also members of the Micron discrete memory
products portfolio.
The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces (no
shared address, control, data, or power balls). This bus architecture supports an opti-
mized interface to processors with separate NAND Flash and Mobile LPDRAM buses.
The NAND Flash and Mobile LPDRAM devices have separate core power connections
and share a common ground (i.e., VSS is tied together on the two devices).
The bus architecture of this device also supports separate NAND Flash and Mobile
LPDRAM functionality without concern for device interaction. Operational characteris-
tics for the NAND Flash and Mobile LPDRAM devices are found in the standard Micron
data sheets for each of the discrete devices.
For device specifications and complete Micron NAND Flash features documentation,
please refer to the component data sheet at www.micron.com/products/nand, or con-
tact your local Micron sales office.
For device specifications and complete Mobile LPDRAM features documentation,
please refer to the component data sheet at www.micron.com/products/mobiledram, or
contact your local Micron sales office.
www.DataSheet.net/
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
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©2008 Micron Technology, Inc. All rights reserved.
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 3: 152-Ball VFBGA Ball Assignments (NAND x8; LPDDR x16)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
A NC NC VDDQ LDM DQ5 DQ7 VSSQ DQ2 DQ4 DQ8 DQ11 CK VSS UDM VDDQ DQ13 DQ12 NC NC NC NC A
B NC NC NC NC VDDQ DQ1 DQ6 LDQS DQ3 DQ0 DQ9 DQ10 CK# VSSQ UDQS VDD DQ15 DQ14 NC NC NC B
C VSSQ NC
NC NC
C
D NC NC
NC NC
D
E NC NC
NC NC
E
F VSSQ VDDQ
VSSQ VDDQ
F
G NC NC
A0 NC
G
H NC VSS
VSS VDD
H
J VDD NC
A2 A3
J
K WE# NC
A1 A9
K
L NC RE#
M NC VSS
www.DataSheet.net/
VDDQ VSSQ
L
A7 A6
M
N NC VCC
A8 A11 N
P NC NC
VSS VDD
P
R NC VSS
A5 A12
R
T NC VCC
CS1# CS0# T
U I/O1 I/O0
CAS# A4
U
V I/O3 I/O2
BA1 RAS# V
W CE1# LOCK
VSSQ VDDQ
W
Y NC NC I/O6 I/O7 WP# VSS VCC NC NC R/B# VSS A14 CKE1 VDD CKE0 A10 VSS WE# VSSQ NC NC Y
AA NC NC I/O4 I/O5 NC VCC VSS CE0# ALE CLE VDD TQ VSS VDDQ A13 VSSQ VDD BA0 VDDQ NC NC AA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Top View – Ball Down
NAND
LPDDR
Supply
Ground
Note: Contact factory for availability of x16 LPDDR configuration.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
Figure 4: 152-Ball VFBGA Ball Assignments (NAND x16; LPDDR x32)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
A NC NC VDDQ DM1 DQ13 DQ15 VSSQ DQ10 DQ12 DQ16 DQ19 CK VSS DM2 VDDQ DQ21 DQ20 DM3 DQS3 NC NC A
B NC NC DQ6 DQ7 VDDQ DQ9 DQ14 DQS1 DQ11 DQ8 DQ17 DQ18 CK# VSSQ DQS2 VDD DQ23 DQ22 DQ28 NC NC B
C VSSQ DQS0
DQ24 DQ26 C
D DQ3 DQ5
DQ25 DQ29 D
E DQ0 DQ1
DQ27 DQ31 E
F VSSQ VDDQ
VSSQ VDDQ
F
G DQ4 DQ2
A0 DQ30 G
H DM0 VSS
VSS VDD
H
J VDD I/O14
A2 A3
J
K WE# I/O15
A1 A9
K
L NC RE#
VDDQ VSSQ
L
M I/O13 VSS
N I/O10 VCC
www.DataSheet.net/
A7 A6
M
A8 A11 N
P I/O12 I/O11
VSS VDD
P
R I/O8 VSS
A5 A12
R
T I/O9 VCC
CS1# CS0# T
U I/O1 I/O0
CAS# A4
U
V I/O3 I/O2
BA1 RAS# V
W CE1# LOCK
VSSQ VDDQ
W
Y NC NC I/O6 I/O7 WP# VSS VCC NC NC R/B# VSS RFU CKE1 VDD CKE0 A10 VSS WE# VSSQ NC NC Y
AA NC NC I/O4 I/O5 NC VCC VSS CE0# ALE CLE VDD TQ VSS VDDQ A13 VSSQ VDD BA0 VDDQ NC NC AA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Top View
(Ball Down)
NAND
LP-DRAM
Supply
Ground
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
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©2008 Micron Technology, Inc. All rights reserved.
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
Table 2: x8/x16 NAND Ball Descriptions
Symbol
ALE
CE1#, CE0#
CLE
LOCK
RE#
WE#
WP#
I/O[7:0]
(x8)
I/O[15:0]
(x16)
R/B#
VCC
Type
Input
Input
Input
Input
Input
Input
Input
Input/
output
Description
Address latch enable: When ALE is HIGH, addresses can be transferred to the on-chip address
register.
Chip enable: Gates transfers between the host system and the NAND Flash device.
Command latch enable: When CLE is HIGH, commands can be transferred to the on-chip
command register.
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK
LOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pull-down).
Read enable: Gates information from the NAND device to the host system.
Write enable: Gates information from the host system to the NAND device.
Write protect: Driving WP# LOW blocks ERASE and PROGRAM operations.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information.
Data is output only during READ operations; at other times the I/Os are inputs.
I/O[15:8] are RFU1 for NAND x8 devices.
Output Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in
progress.
Supply VCC: NAND power supply.
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Contact the factory for details.
www.DataSheet.net/
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
Table 3: x16/x32 LPDDR Ball Descriptions
Symbol
A[14:0]
BA1, BA0
CAS#
CK, CK#
CKE0, CKE1
CS1#, CS0#
LDM, UDM
(x16)
Type
Input
Input
Input
Input
Input
Input
Input
Description
Address inputs: Specifies the row or column address. Also used to load the mode registers. The
maximum LPDDR address is determined by density and configuration. Consult the LPDDR
product data sheet for the maximum address for a given density and configuration. Unused
address pins become RFU.
Bank address inputs: Specifies one of the 4 banks.
Column select: Specifies the command to execute.
CK is the system clock. CK and CK# are differential clock inputs. All address and control signals
are sampled and referenced on the crossing of the rising edge of CK with the falling edge of
CK#.
Clock enable:
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products.
Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs.
Data mask: Determines which bytes are written during WRITE operations.
For x16 LPDDR, unused DM balls become RFU.
DM[3:0]
(x32)
RAS#
WE#
DQ[15:0]
(x16)
Input
Input
Input/
output
Row select: Specifies the command to execute.
Write enable: Specifies the command to execute.
Data bus: Data inputs/outputs.
DQ[31:16] are RFU for x16 LPDDR devices.www.DataSheet.net/
DQ[31:0]
(x32)
LDQS, UDQS
(x16)
Input/
output
Data strobe: Coordinates READ/WRITE transfers of data; one DQS per DQ byte.
For x16 LPDDR, unused DQS balls become RFU.
DQS[3:0]
(x32)
TQ
VDD
VDDQ
VSSQ
Output
Supply
Supply
Supply
Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C.
VDD: LPDDR power supply.
VDDQ: LPDDR I/O power supply.
VSSQ: LPDDR I/O ground.
Table 4:
Symbol
VSS
NC
RFU1
Non-Device-Specific Ball Descriptions
Type
Supply
VSS: Shared ground.
No connect: Not internally connected.
Reserved for future use.
Description
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Contact the factory for details.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Electrical Specifications
Electrical Specifications
Table 5: Absolute Maximum Ratings
Parameters/Conditions
VCC, VDD, VDDQ Supply voltage
relative to VSS
Voltage on any pin
relative to VSS
Storage temperature range
Symbol
VCC, VDD,
VDDQ
VIN
Min
–1.0
–0.5
–55
Max
2.4
2.4 or (supply voltage1 +
0.3V), whichever is less
+150
Unit
V
V
°C
Notes: 1. Supply voltage references either VCC,VDD, or VDDQ.
Stresses greater than those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Table 6: Recommended Operating Conditions
Parameters
Supply voltage
I/O supply voltage
Operating temperature range
Symbol
VCC, VDD
VDDQ
Min
1.70
1.70
–40
Typ
1.80
1.80
Max
1.95
1.95
+85
Unit
V
V
°C
www.DataSheet.net/
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
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©2008 Micron Technology, Inc. All rights reserved.
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Device Diagrams
Device Diagrams
Figure 5: 152-Ball Functional Block Diagram (Single LPDDR)
CE0#
CLE
ALE
RE#
WE#
WP#
LOCK
NAND Flash
VCC
I/O
R/B#
VSS
CS0#
CK
CK#
CKE0
RAS#
CAS#
WE#
Address,
BA0, BA1
LPDDR
www.DataSheet.net/
VDD
VDDQ
DM
DQ
DQS
TQ
VSSQ
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Device Diagrams
Figure 6: 152-Ball Functional Block Diagram (Dual LPDDR)
CE0#
CLE
ALE
RE#
WE#
WP#
NAND Flash
VCC
I/O
R/B#
VSS
CS0#, CS1#
CK
CKE0, CKE1
RAS#
CAS#
WE#
Address,
BA0, BA1
LPDDR
(Die 0 and 1)
www.DataSheet.net/
VDD
VDDQ
DQM
DQ
TQ
VSS
VSSQ
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Package Dimensions
Package Dimensions
Figure 7: 152-Ball VFBGA (Package Code: CA)
0.46 ±0.1
Seating
plane
A
0.12 A
152X Ø0.45
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
14 ±0.1
Ball A1 ID
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
14 ±0.1
13
CTR
0.65 TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
www.DataSheet.net/
V
W
Y
AA
0.65 TYP
13 CTR
Note: All dimensions are in millimeters.
0.9 MAX
0.35 MIN
Ball A1 ID
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Package Dimensions
Figure 8: 152-Ball VFBGA (Package Code: CG)
Seating
plane
0.1 A
A
0.6 ±0.1
152X Ø0.46
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
13 CTR
0.65 TYP
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Ball A1 ID
A
B
C
D
E
F
G
H
J
K
L 14 ±0.1
M
N
P
R
T
U
www.DataSheet.net/
V
W
Y
AA
0.65 TYP
13 CTR
14 ±0.1
Note: All dimensions are in millimeters.
Ball A1 ID
1.0 MAX
0.35 MIN
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MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Package Dimensions
Figure 9: 152-Ball TFBGA (Package Code: JQ)
Seating
plane
0.12 A
A
0.75 ±0.1
152X Ø0.45
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
13 CTR
0.65 TYP
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Ball A1 ID
A
B
C
D
E
F
G
H
J
K
L 14 ±0.1
M
N
P
Q
R
T
U
www.DataSheet.net/
V
W
X
0.65 TYP
13 CTR
14 ±0.1
Notes: 1. All dimensions are in millimeters.
Ball A1 ID
1.1 MAX
0.35 MIN
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production
devices.
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.co.kr/


MT29C1G12MAURACA-6IT (Micron Technology)
NAND Flash and Mobile LPDRAM

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Preliminary
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Revision History
Revision History
Rev. E, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/09
• “NAND Flash-Specific Features” on page 1: Deleted device size bullet.
• Figure 2: “152-Ball Part Number Chart,” on page 2: Added U and V options under
NAND Flash configurations; deleted low-power option under LPDRAM self refresh
current; added dimensions to package codes; added CS# to first column under chip
count; changed CE# from 2 to 1 for B and D under chip count.
• Table 1, “Production Part Numbers,” on page 3: Replaced former table 1.
• Figure 3: “152-Ball VFBGA Ball Assignments (NAND x8; LPDDR x16),” on page 5:
Updated figure.
• Figure 4: “152-Ball VFBGA Ball Assignments (NAND x16; LPDDR x32),” on page 6:
Updated figure.
• Table 2, “x8/x16 NAND Ball Descriptions,” on page 7: Updated table.
• Table 3, “x16/x32 LPDDR Ball Descriptions,” on page 8: Updated table.
• Table 4, “Non-Device-Specific Ball Descriptions,” on page 8: Updated table.
• Table 5, “Absolute Maximum Ratings,” on page 9: Updated table.
• Table 6, “Recommended Operating Conditions,” on page 9: Updated table.
• Figure 5: “152-Ball Functional Block Diagram (Single LPDDR),” on page 10: Updated
figure title; updated figure.
• Figure 6: “152-Ball Functional Block Diagram (Dual LPDDR),” on page 11: Added fig-
ure.
Rev. D, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/08
• Updated template; ready for external publication.
www.DataSheet.net/
Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/08
• Added part number for JQ package code, page 1.
• Figure 2, Marketing Part Number Example, on page 2: added JQ package code.
• Added JQ package diagram, Figure 9, 152-Ball TFBGA (Package Code: JQ), on page 14.
Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/08
• On page 1, added part number for CA package code.
• Figure 2: Marketing Part Number Example on page 2: Added CA package code.
• Removed former capacitance tables. See component data sheets for capacitance.
• Figure 7: 152-Ball VFBGA (Package Code: CA) on page 12, and Figure 8: 152-Ball
VFBGA (Package Code: CG) on page 13: Updated figures.
Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/08
• Initial release.
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Datasheet pdf - http://www.Da




Click to Download PDF File