AD9955 (Analog Devices)
85Mhz Direct Digital Synthesizer

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c;bSo (~1- <-
,. ANALOG s -<:-<- I17t:J700 '8' G v- H-V 9'&::sO
85 MHzDirect
W DEVICES
DigitaSl ynthesizer
FEATURES
100 MHz Typical/8S MHz Minimum Clock Rate
32-Bit Phase Accumulator
12-Bit Sine Output
>90 dB Spurious Free Dynamic Range
Continuous Frequency Update
On-Board Data Ready Signal
APPLICATIONS
Frequency Synthesizers
DDS Tuning
Digital Demodulation
FM Modulators
AD9955
I
GENERAL DESCRIPTION
The AD99SS is a 100 MHz direct digital synthesizer for fre-
quency synthesis applications. It comprises a 32-bit phase accu-
mulator and a IS-bit phase-to-12-bit sine amplitude converter.
The control logic is CMOS compatible, and the clock input is
TTL. CMOS outputs are latched on board, and a data ready
signal is provided.
Designed for applications in communications, instrumentation,
and military systems, the AD99SS can be combined with a clock
reference and a DAC such as the AD97l3B or AD9721 to form
a digitally-controlled analog frequency reference.
The AD99SS is available in an SO-leadplastic quad flatpack
(PQFP) for commercial (O°Cto + 70°C) temperature range appli-
cations. Contact the factory for information concerning the avail-
ability of a military temperature range device.
PSEl
BREN
F[O:31)
COUT
FUNCTIONAL BLOCK DIAGRAM
RSTO
TCMS
Z
0
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BRCLK
FCLD
Z-OWC~.J.J
ClK
SIN [O:11J
DATA
READY
REV.0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329.4700
Fax: 617/326-8703
--
--
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AD9955 (Analog Devices)
85Mhz Direct Digital Synthesizer

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AD9955- SPECIFICATIONS
ELECTRICALCHARACTERISTIC(+SVs = +5 V;fClK= 40MHzC; l = 20pF,unlessotherwisenoted)
irest AJ>9955
Parameter (Conditions)
iremperature
Level Min iryp Max
CMOS INPUTS 1
Logic "I" Voltage
Logic "0" Voltage
Logic "I" Current
Logic "0" Current
InpUt Capacitance
Full
Full
Full
Full
+ 25°C
II 3.5
II 1.5
II 1.0
II -1.0
V 10
CMOS OUTPUTS
Logic "1" Voltage (VIH)
Logic "0" Voltage (VIL)
Logic "1" Current
Logic "0" Current
OutpUt Capacitance
Full
Full
Full
Full
+25°C
II 4.5
II 0.4
II 12
II 12
V3
TTL INPUTS2
Logic "1" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
Input Capacitance
POWER SUPPLIES
+Vs Current3
CLK = 50 MHz
CLK = 100 MHz
Nominal Power Dissipation
CLK = 50 MHz
CLK = 100 MHz
Relative to Frequency
Full
Full
Full
Full
+ 25°C
Full
+ 25°C
+25°C
+ 25°C
+25°C
IV 2.0
II 0.8
II 1.0
II -1.0
V4
IV 120 160
V 240
V 600
V 1.2
V 11.5
AC SPECIFICA TIONS4
Clock Update Rate (CLK)5
Frequency Update Rate (BRCLK)6
Clock Pulse Width
CLK Digital "1"
CLK Digital "0"
Frequency Update Pulse Width
BRCLK Digital "1"
BRCLK Digital "0"
Input Rise/Fall Times
CLK Rise Time
CLK Fall Time
BRCLK Rise Time
BRCLK Fall Time
BRCLK Input Timing
Setup Time (tcs, tEsf
Hold Time (tcH, tEHf
CLK Input Timing
Setup Time (tLS)8
Hold Time (tLH)8
RESET 0 Timing
Setup Time (tRS)9
Hold Time (tRH)9
Output Timing Characteristics
Data Output Delay (tOD)lO
DRDY Output Delay (tDR)lO
Output Data Setup Time (tos)ll
Carry Output Delay12
Spurious-Free Dynamic Range (SFDR)
Worst Case Spur13
Latency of Initial Data14
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
+25°C
+ 25°C
+ 25°C
IV 85 100
II 40
IV 7.9 5.7
IV 3.8 2.2
II 10
II 10
IV
IV
IV
IV
2
2
5
5
II 5 2
IV 5 1.8
IV 2.0 0.7
IV 2.0 0.7
IV 6
IV 6
IV 3.4 6.1 8.7
IV 4.7 7.5 10
IV 0.8 1.9
V 7.7
V >90
V 14
Units
V
V
fJ.A
fJ.A
pF
V
V
mA
mA
pF
V
V
fJ.A
fJ.A
pF
mA
mA
mW
W
mW/MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
dBc
Clock Cycles
-2-
~~ --- ---
REV. 0
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AD9955 (Analog Devices)
85Mhz Direct Digital Synthesizer

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AD9955
NOTES
'Includes F[0:31], PSEL, BREN, FCLD, CIN, TGLE, BRCLK, TCMS, and RSTO.
'Only the clock (CLK) is TTL compatible.
'focT = 1/2 fCLK' See performance curves.
.Nominal conditions (V'H = 3.4 V; V'L = 0.4 V).
'Based on minimum clock pulse width duty cycle (68% HIGH @ 85 MHz).
6This specification defines the maximum rate at which the output frequency tUning word (F[0:3I]) can be updated.
7Referenced to 2.5 V point of rising edge of BRCLK, specified for F[0:31], BREN.
"Referred to rising edge of CLK, specified for FCLD. CIN setup time is typically 1.2 ns, specified for FCLD, CIN.
"Referred to 1.6 V point of the rising edge of CLK. See Timing Diagram.
IOReferenced to 1.6 V point of the rising edge of CLK for 1.6 V point of the rising/falling edge of SIN [0:11]; or the falling edge of DRDY. Load is shown
below.
"Referenced from 1.6 V point of the rising/falling edge of SIN[O:II] to 1.6 V point of the falling edge of DATA READY. Specified driving AD9713B; no addi-
tional capacitive load.
"Referenced from 1.6 V point of rising edge of CLK to 1.6 V point of the rising/falling edge of COUTo
"Based on proprietary phase-to-sine algorithm, TGLE HIGH.
'.Referred to CLK for FCLD high. See Timing Diagram.
EXPLANATION OF TEST LEVELS
Test Level
I - 100% production tested.
II - 100% production tested at +25°e; parameter is
guaranteed by design and characterization at temp-
erature extremes.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
Parameters based on characterization testing have limits based on 6 sigma of
a normal distribution; typical values are the mean of the distribution.
ABSOLUTE MAXIMUM RATINGSI
Supply Voltage (+Vs)
-0.5 V to +7 V
Input Voltage. . . . . . . . . . . . . . . . . -0.5 V to +Vs +0.5 V
Output Voltage Swing. . . . . . . . . . . -0.5 V to +Vs +0.5 V
Operating Temperature Range (Ambient)
ooe to + 70oe
Maximum Junction Temperature2
+ 150oe
Storage Temperature Range. . . . . . . . . . . -65°e to + 150oe
Lead Temperature (soldering, 10 seconds) . . . . . . . . . + 250oe
ORDERING GUIDE
Model
AD9955KS-66t
AD9955KS-62
AD9955/PeB
Temperature
Range
ooe to + 70oe
ooe to + 70oe
N/A
Package
80-Terminal Plastic
Quad Flatpack
80-Terminal Plastic
Quad Flatpack
DDS Evaluation Board
NOTES
'Model AD9955KS-66 units are shipped in a standard JEDEC tray; mini-
mum order quantity is 66 units (I full tray).
'AD9955KS-6 units are shipped in a nonstandard tray; minimum order
quantity is 6 units (I full tray). Three nonstandard trays will fit in a stan-
dard JEDEC tray outline, allowing use with standard assembly equipment.
Contact factory for details.
NOTE: All units are dry packed to inhibit moistUre absorption. Units which
are exposed to air for more than 48 hours should be baked for 24 hours at
+ 125°C prior to assembly.
+5V AD97138
NOTES
'Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
'Typical thermal impedance; part soldered in place:
alA = 62°CIW
alC = 7°CIW.
1OkQ
AD9955 Load Circuit
REV.0
-3-
-- -~
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AD9955 (Analog Devices)
85Mhz Direct Digital Synthesizer

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AD9955
AD9955 PIN DESCRIPTIONS
Name
Description
GND
Ground Reference Voltage Connection.
+Vs
BRCLK
CLK
Positive voltage power connection, nominally + 5 V.
Buffer Register Clock. Data inputs are loaded into
the Frequency Control Word Buffer Register on the
rising edge of BRCLK when register is enabled
(BREN input at Logic "1").
System Clock. Continuous TTL signal for
synchronizing all internal operations, except loading
of Frequency Control Word Buffer Register; rising
edge initiates synchronization.
F[0:31] 32 parallel data inputs for loading frequency tuning
word.
BREN
Buffer Load Enable Signal. Enables loading of data
into the Frequency Control Word Buffer Register.
If BREN is logic "0," register retains its contents. If
BREN is Logic "1," theFrequency Control Word
Buffer Register either (1) parallel loads the data
present at F[0:31] inputs (PSEL = HIGH) or (2)
serially shifts data present at F[31] input (PSEL =
LOW).
FCLD Frequency Control Load Enable Signal. FCLD =
HIGH enables loading of data from Frequency
Control Word Buffer Register into Frequency
Control Register. Loading takes place on next rising
edge of CLK signal. FCLD = LOW disables
DRDY
loading of data.
Data Ready Signal. Output data (SIN [0: 11]) is
valid on the rising edge of DRDY, which tracks
propagation delay variations of the output data vs.
temperature. The duty cycle of DRDY is dependent
on the duty cycle of the CLK input. The DRDY
signal should be used only for applications which
have a very high clock rate (85 Msps) and require
operation over a wide temperature range. Normally
allowed to float.
CIN Carry-In signal is provided as the carry input to the
least significant bit (LSB) of the 32-bit adder in the
phase accumulator. This signal is used as the carry
TGLE
input only if the TGLE signal is a logic zero; carry
has 1 LSB weight, and is used for stacking units for
64-bit DDS. Normally tied to ground.
Carry Toggle Enable. When HIGH, the CIN signal
is disabled, and the Carry-In toggles internally
between HIGH and LOW on each clock (CLK)
cycle to reduce the worst case spurious response of
the digital output signal by 3.92 dB. Normally tied
to ground.
TCMS
Twos Complement/Magnitude Mode Select. Selects
binary output format of data on SIN[O:11] outputs.
If TCMS is a Logic "1," format of output data at
SIN[O:11] is in twos complement format. If TCMS
is a Logic "0," data is binary unsigned magnitude
format. Normally tied to ground.
SIN[O:11] 12 parallel data bits comprising the sine data output.
Frequency of the sine data outputs is defined by the
Name
RSTO
COUT
PSEL
Description
Frequency Control Register (~ phase) as
( )~ PhaSe
louT = !eLK ~
Binary data format of 12-bit samples is either twos
complement or unsigned magnitude, determined by
TCMS signal.
Reset Phase to Zero Signal. Activates synchronous
reset of the Phase Accumulation Register to a
binary value of "0," or zero radians. Reset is
enabled when RSTO is a Logic "1" and takes place
on rising edge of system clock (CLK). Normally
low.
Carry-Out signal output of the 32-bit adder in the
phase accumulator; used for stacking two AD9955
units for 64-bit DDS. Normally allowed to float.
ParalleUSerial Frequency Control Word Buffer
Input Selector. Selects mode for loading the Buffer
Register. If a load is enabled (BREN = "1"), and
PSEL is a Logic "1," data is parallel loaded into the
Frequency Control Word Buffer Register from the
FO:31] inputs on the next rising edge of BRCLK. If
a load is enabled and PSEL is a Logic "0," data is
serially shifted into the Frequency Control Word
Buffer Register from the F[31] input on rising edge of
BRCLK.
PIN DESIGNATIONS
9ofaf:i.i.izJzQzzQ»Q».QJ0>~00~0~'~+,",~0'
iill~II~II~II~II~II~
GND I'
,FO(MSB) I
AD9955
TOP VIEW
(NOIIO Scala)
F'6124
41 I TGlE
:;Jl.!JLEJ~~~l3JL£;Il1!JL.:Il1!JL.:IL.:JL.IDL.IDl.!
~ [ ~ ~ E ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~ ~
M..
-4- REV.0
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AD9955 (Analog Devices)
85Mhz Direct Digital Synthesizer

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DIE INFORMATION
Die Dimensions. . . . . . . . . . . . .215 x 199 x 20.7 (:!: 1) mils
PadDimensions
4x4mils
Metalization
Aluminum
Backing
SubstratePotential
None
Ground
Passivation
Oxynitride
Die Attach
Bond Wire
Epoxy
Gold
AD9955
><znooo':3"i'5zuzzjOz»O»OO<n<n<n<n"'<nO~
.0"-"'0.0000"++0+00:
~>z'"
~::-,~~WlJJ1
ri
00Z0. 0z> <n
I1
65 63
~
1
L
~
~
AD9955 Chip Layout
FIXED
FREQUENCY
REFERENCE
GENERATES SAMPLES
OF A SINE WAVE
IJ
I - - - - D-;-GITc;AcLuli - - - -I
CONVERTS SINE
SAMPLES INTO
ANALOG SIGNAL
I
II PHASE
N
PHASE
ACCUMULATOR
\ ---------------
SPECIFIES OUTPUT
FREQUENCY AS
FRACTION OF CLOCK
FREQUENCY
.,,1111111111111111
SINE
AMPLITUDE
CONVERTER
~
DIGITAL.
TO.
ANALOG
CONVERTER
rv
fo
rv
Figure 1. Block Diagram of DDS Generator
DDS
Direct digital synthesis (DDS) is a method of deriving a wide-
band, digitally controlled frequency (sine wave) synthesizer from
a single reference frequency (system clock).
The circuit has three major components:
1. Phase accumulator
2. Phase-to-amplitude converter
3. Digital-to-analog converter
These major stages and their relationships to one another are
illustrated in the block diagram shown above.
The phase accumulator is a digital device which generates the
phase increment of the output waveform. Its input is a digital
word which (with the reference oscillator) determines the fre-
quency of the output waveform. The output of the phase accu-
mulator stage represents the current phase of the generated
waveform. In effect, the accumulator serves as a variable-
frequency oscillator generating a digital ramp. The frequency of
the signal is defined by .lphase as
.lphase
.lphase
four = .A..phaseMAXfCLOCK= --yr- !cLOCK
Translating phase information from the phase accumulator into
amplitude data takes place in the phase-to-amplitude converter.
This is most commonly accomplished by means of a look-up
table (LUT) stored in memory, but may be calculated instead
using a digital algorithm to minimize circuit complexity and/or
increase the update rate.
In the final step of frequency synthesis, amplitude data is con-
verted into an analog signal. This is done by a digital-to-analog
(D/ A) converter which must have good linearity; low glitch
impulse; and fast, symmetrical rise and fall times. When it does,
the frequency synthesizer is able to produce a spectrally pure
waveform.
REV. 0
-5-
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85Mhz Direct Digital Synthesizer

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AD9955
==xF[0:31]
ALL ZEROS
c~
BRCLK
/
-1BREN
\
5$
\
~,
CLK
~,
5$
5$
~,
FCLD
,
RSTO
SIN[0:11)~
~,
x ~~ x ~~
X ECORNEDSIETTION RESET
IRSRESET SETUP TIME
IRHRESET HOLD TIME
Figure 2. Reset Timing
AD9955 DIRECT DIGITAL SYNTHESIZER
The AD9955 is a digital device which integrates a 32-bit phase
accumulator and IS-bit phase to 12-bit sine amplitude converter
(see block diagram). The circuit is fabricated in a CMOS pro-
cess technology, and designed to minimize the number of exter-
nal devices necessary to implement a high speed DDS system.
PhaseAccumulator Architecture
The phase accumulator is comprised of 8 pipelined, 4-bit adder
cells to achieve the typical 100 MHz operation. The pipelined
accumulator requires the use of input data alignment registers
between the frequency control register and the accumulator to
maintain the phase-coherent switching characteristics of the
DDS. The alignment registers on the 16 least significant bits of
the accumulator were eliminated to save power and reduce the
number of pipeline delays; this results in a maximum phase dis-
continuity of 0.005°.
240
220
:(
!. 200
.zw.. 180
aa::
B 160
>
~ 140
11.
::>
IJ) 120
aw:
;!: 100
0
11.
80
.60
1
..!...
2'
..!... ..!... ..!... ...L
24 2' 2' 210
OUTPUT FREQUENCY
...L ...L ...L
2" 214 2"
( )~
'CLOCK
...L
2"
Figure 3. Power Supply Current vs. Output Frequency
The accumulator incorporates carry input and output pins (CIN
and COUT) to enable stacking of devices to achieve greater than
32-bit resolution. In normal operation, CIN will be connected to
ground, and COUT allowed to float.
An additional feature of the AD9955 accumulator is controlled
by the TGLE pin. With this pin tied HIGH, the CIN pin is
disabled and the carry input is internally toggled on successive
clock cycles. The toggling of the carry input has two major ben-
efits. The theoretical worst case spur is reduced by 3.92 dB,
making the worst case spurious free dynamic range of the
SIN[O:l1] outputs 90.3 dBc. In addition, the DDS spur
performance is made more consistent versus frequency due to
the randomizing of the errors introduced by possible DAC
nonlinearities.
Resetting the AD9955
The synchronous reset function (RSTO) resets the output of the
phase accumulator to zero radians, allowing the user to initialize
the AD9955 from a known state. A reminder: the RSTO signal
does not affect the contents of the alignment registers on either
side of the adders. To properly reset the AD9955 to zero radians
(SIN[O:11] = 1000 0000 0000), perform the following steps in
the order listed:
1. Frequency input should be preloaded to zero (F[O:31] = 0;
see loading the AD9955).
2. Four clock cycles must pass to clear the prealignment
registers.
3. The RSTO signal should go HIGH for at least 12 ns, and
meet required setup (tRS)and hold (tRH) times.
4. Nine additional clock cycles must pass to clear the post-
alignment registers and allow the new tUning word (0 radi-
ans) to propagate through the phase to sine amplitUde
conversion circuitry.
Critical timing and pipeline delays required for resetting the
AD9955 are illustrated in the reset timing diagram. After the
RSTO signal is returned to LOW, a new frequency can be
-6- REV.0
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85Mhz Direct Digital Synthesizer

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==¥F[O:31]
--J Ics
BRCLK
tES-1~
BRE--N1
CLK
FCLD
DRDY
FREQUENCY 2
x
55
5S
/ \ 55
\/
\ 55
AD9955
Ics FREQUENCY CONTROL WORD SETUP TIME
IcH FREQUENCY CONTROL WORD HOLD TIME
rEs BUFFER REGISTER ENABLE SETUP TIME
tEH BUFFER REGISTER ENABLE HOLD TIME
tlS FREQUENCY CONTROL WORD LOAD SETUP TIME
tlH FREQUENCY CONTROL WORD LOAD HOLD TIME
Figure 4. ParallelMode Timing
tOR DATA READY DELAY
too OUTPUT DATA DELAY
tos OUTPUT DATA SETUP TIME
loaded into the frequency control register; the SIN[O:11] outputs
will remain at the midscale value for 14 clock cycles while the
new tuning word propagates through the AD9955.
Loading the Frequency Control Word
For convenience, the frequency control register is double buff-
ered at the inputs to allow asynchronous loading of a new fre-
quency control word. The frequency control word buffer
register can be loaded in either parallel (PSEL = HIGH) or
serial (PSEL = LOW) mode. The data is clocked on the rising
edge of the BRCLK signal when the BREN pin is held HIGH.
In serial mode, the data is fed through the LSB (F[31]) and
requires multiple clock edges to shift in data.
Once new frequency data is loaded into the frequency control
word buffer, it is passed into the frequency control register on
the next rising edge of the CLK signal following a HIGH signal
on the FCLD pin. The new frequency control word is then used
as the input to the phase accumulator and it begins to accumu-
late at the new rate. The Parallel Mode Timing diagram illus-
trates the critical timing relationships for loading new frequency
data into the AD9955 from the reset condition; these relation-
ships remain the same for any arbitrary condition.
Phase to Sine Architecture
The phase to sine amplitude converter calculates the sine ampli-
tude using a proprietary algorithm for the first 90° of the sine
cycle, and takes advantage of the symmetry of the waveform to
calculate the remaining quadrants. Only the 15 most significant
bits of the phase accumulator output are needed to achieve the
12-bit accuracy of the SIN[O:11] outputs.
In normal operation (TGLE = LOW), the frequency tuning
word may take on both odd and even values. Odd frequency
input words will result in a spurious free dynamic range (SFDR)
of 90.3 dBc, while even frequency words may have spurious fre-
quency content as high as 86.4 dBc. The carry toggle feature
discussed above guarantees a worst case SFDR of the frequency
tuning words of 90.3 dBc.
The architecture and implementation of the phase to sine algo-
rithm uses several compression techniques to reduce the amount
of internal memory required, and to guarantee a minimum
throughput rate of 85 MHz, a new benchmark for CMOS DDS
circuits. Accordingly, the CLK input is TTL logic compatible,
and buffered internally to minimize input capacitance. Although
most devices will operate with a 50% duty cycle on CLK input,
guaranteed operation at 85 MHz will require adjustment of
clock duty cycle (see specification table). All other inputs and
outputs are CMOS logic compatible.
SIN Outputs
The SIN[O:11] outputs of the phase to sine conversion circuitry
are latched at the output to minimize data skew. The TCMS
control signal specifies the format of the output data as either
binary unsigned magnitude or tWo's complement format. The
output data is valid on the rising edge of the data ready signal
(DRDY), and is designed to track the temperature variation of
the output data. The DRDY signal is not recommended for
clocking the DAC because of phase uncertainty (jitter). The par-
allel mode timing diagram also illustrates the timing relation-
ships relevant to capturing the output data, and also the pipeline
delays associated with loading a new frequency word. The
curves below show the typical propagation delays of SIN[O:11]
and DRDY vs. temperature.
REV.0
-7-
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85Mhz Direct Digital Synthesizer

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AD9955
8.2
7.8
<II
C
>I -
:ws 7.4
0
>0-
«
~ 7.0
0~
6.6
6.2
0
10 20 30 40 50 60 70
AMBIENT TEMPERATURE -"C
Figure 5. Data Ready Delay vs. Ambient Temperature
7.0
~ 6.5
I -
...J 6.0
w
0
~
~
.~.. 5.5
~
0
;:, 5.0
eo
z
Ui 4.5
CL = 20pF
7
CL = OpF
4.0
0
10 20 30 40 50
AMBIENT TEMPERATURE -"c
60
70
Figure 6. Output Delay vs. Ambient Temperature
Applications Information
The AD99SS can be used in digital demodulation applications to
provide a digital frequency reference, or combined with a DAC
to provide an analog frequency reference. In the latter applica-
tion, a DAC with exceptional ac performance is required. The
diagram below gives a recommended hookup for a complete
direct digital synthesizer employing the AD99SS and the
AD9721, a lO-bit 100 Msps DAc.
As in all high speed applications, proper layout is critical; it is
particularly important when both analog and digital signals are
involved. Analog signal paths should be kept as short as possi-
ble, and properly terminated to avoid reflections.
Digital signal paths should also be kept short, and run lengths
matched to avoid propagation delay mismatch. In the diagram,
series resistors (130 ohms) are inserted in the connections
between the SIN[0:9] outputs of the AD99SS and the data
inputs of the AD9721 (DcDIO) to reduce data feedthrough
effects and to insure that the setup and hold times of the
AD972I's input register are met over the commercial tempera-
ture range (O°Cto + 70°C).
Layout of the ground circuit is a critical factor. A single, low
impedance ground plane will reduce noise on the circuit ground.
Power supplies should be capacitively coupled to the ground
plane to reduce noise in the circuit. Multilayer boards allow
designers to layout signal traces without interrupting the
ground plane, and provide low impedance power planes.
Evaluation Board
An evaluation board is available which combines the AD99SS
and either the AD9713B, an 80 Msps 12-bit DAC, or the
AD9721, a 10- bit 100 Msps DAC, both of which are supplied
with the board. This simplifies the task of evaluating and char-
acterizing the DDS synthesizer. The block diagram shown in
Figure 9 illustrates its operation. For more information, please
consult the AD99SS/PCB data sheet.
ClK DRDY----------
F(O)-F(31)
COUT
I
~P +5V +Vs CLOCK
RSTO
BREN
130
BRClK
SIN 0-9
Dx AD9721
FClD
TGLE
PSEl
AD9955
-5.2V
,-Vs RSET
'OUT
50
+Vs GND CIN TCMS
'INDICATES ANALOG RETURN,
INVERT, AND GROUND
+5V
Figure 7. AD9955/AD9721 DDS Synthesizer
-8-
-~
REV.0
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AD9955 (Analog Devices)
85Mhz Direct Digital Synthesizer

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r
AD9955
-20
~ -40
"C
I
W
g -60
~
z"
«:;: -80
-100
-120
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
-NORMALIZEDFREQUENCY tOUT/tClK
0.5
Figure 8. AD9955 Output Spectrum
TTl CLOCK
REFERENCE
GENERATOR
SOFTWARE
PROVIDED
=l
INTERFACE
lOGIC
AD9955
100MHz
CMOS DDS
AD9955 DDS EVALUATION BOARD
IBM-COMPATIBLE PC
+5V
-5.2V
EXTERNAL
POWER
SUPPLY
50Q
CABLE
D
OCCC
CCC
CCC
SPECTRUM ANALYZER
Figure 9. AD9955 DDS Evaluation Board Setup
REV. 0
-9-
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85Mhz Direct Digital Synthesizer

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AD9955
AD9955/AD9721 20 MSPS 2.10 MHz
10dB/
I
JR f----
2.114MHz
-69.10 dB I--
REF-2.6 dam
AD9955/AD9721 50 MSPS 5.10 MHz
10dB/
,
II
MKR
5.11 MHz
-68.10 dB
REF-2.6 dam
-
-
J
START 200 kHz
..
STOP 10.000 MHz
Figure 10. AD9955/AD9721 Output Spectrum
AD9955/AD9721 20 MSPS 5.10 MHz
1OdB/
II I
MKR
-
-400 kHz
-72.35 dB
REF-2.6 dam
-
7
START 200 kHz
STOP 25.00 MHz
Figure 13. AD9955/AD9721 Output Spectrum
AD9955!AD9721 50 MSPS 12.55 MHz
10dB/
II
MKR
-196 kHz
-73.15 dB
REF-2.6 dam
-
-
y
START 200 kHz
STOP 10.000 MHz
Figure 11. AD9955/AD9721 Output Spectrum
AD9955/AD9721 20 MSPS 6.60 MHz
1OdB!
II
MKR
196 kHz
-70.90 dB
REF-2.6 dam
-
r--
CENTER 12.500 MHz
y
SPAN 2.50 MHz
Figure 14. AD9955/AD9721 Output Spectrum
AD9955!AD9721 50 MSPS 16.60 MHz
10dB!
or
II
MKR
196 kHz
2.97 dB
REF-2.6 dam
-
-
L
CENTER 6.500 MHz
y
SPAN 2.50 MHz
Figure 12. AD9955/AD9721 Output Spectrum
y
!I
CENTER 16.670 MHz
SPAN 2.50 MHz
Figure 15. AD9955/AD97212 Output Spectrum
-10-
REV.0
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85Mhz Direct Digital Synthesizer

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AD9955/AD9721 80 MSPS 8.10 MHz
10dB/
,
II
<lMKR
-
16.21MHz
-67.95dB -
REF -2.6 dam
AD9955/AD9721 100 MSPS 10.10 MHz
10dB/
..
AD9955
II
6MKR
-
30.10MHz
-66.85dB
REF-2.6 dam
-
i7
START 200 kHz
STOP 40.00 MHz
Figure 16. AD9955/AD9721 Output Spectrum
AD9955/AD9721 80 MSPS 20.10 MHz
10dB/
II
6MKR
-396 kHz
-68.50dB
REF-2.6 dam
-
-
START 200 kHz
I
STOP 50.00 MHz
Figure 19. AD9955/AD9721 Output Spectrum
AD9955/AD9721 100 MSPS 25.10 MHz
10dB/
II
6MKR
-400 kHz
-63.42 dB
REF-2.6 dam
-
-
I 'I
CENTER 20.00 MHz
SPAN 2.50 MHz
Figure 17. AD9955/AD9721 Output Spectrum
AD9955/AD9721 80 MSPS 26.60 MHz
1OdB/
II
6MKR
204 kHz
-60.97 dB
REF-2.6 dam
-
-
L
CENTER 25.00 MHz
.,.
,"
SPAN 2.50 MHz
Figure 20. AD9955/AD9721 Output Spectrum
AD99551AD9721 100 MSPS 33.30 MHz
10dBI
II
6MKR
200kHz
-66.80dB
REF-2.6 dam
e--
I--
7
". II ".L
CENTER 26.500 MHz
I
'.", . I
SPAN 2.50 MHz
Figure 18. AD9955/AD9721 Output Spectrum
.
CENTER 33.00 MHz
"
nilI I 1.1
I1
SPAN 2.50 MHz
Figure 21. AD9955/AD9721 Output Spectrum
REV. 0
-11-
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AD9955
Table I. Recommended Operation
Parameter
+Vs
CLK
BRCLK, PSEL, BREN,
FCLD, CIN, TGLE,
TCMS, RSTO, F[0:31]
Input Voitage
Min Nominal Max
4.75 500
0 TTL
0 CMOS
5025
+Vs
+Vs
.
.
0.555f(14.1)
0.5472 (13.9)
T
0.4724
T
MECHANICAL INFORMATION
Dimensions in inches and (mm)
0.9507 (24.15)
0.9311 (23.65)
0.7913 (20.10)
0.7834 (19.90)
..
..
l~
--II.-
-.J
001338(3.40) MAX
0.0141(0.36)
0.0039(0.10)
-1 0.0374 (0.95)
T 0.0255 (0.65)
-12-
REVoO
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