LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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Ordering number : ENA1035
LC87F5N62B
CMOS IC
FROM 66K byte, RAM 2048 byte on-chip
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F5N62B is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time
of 83.3ns, integrate on a single chip a number of hardware features such as 66K-byte flash ROM (onboard rewritable),
2048byte RAM, Onchip debugging function, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a
16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base
timer serving as a time-of-day clock, a high-speed clock counter, two synchronous SIO ports (with automatic block
transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full duplex), four 12-bit
PWM channels, an 8-bit 15-channel AD converter, a system clock frequency divider, and a 29-source 10-vector interrupt
feature.
Features
„Flash ROM
Capable of on-board-programing with wide range, 2.7 to 5.5V, of voltage source
Block-erase in 128-byte units
67584 × 8 bits ( Address: 00000H to 0FFFFH, 1F800H to 1FFFFH)
„RAM
2048 × 9 bits
„Minimum Bus Cycle Time
83.3ns (12MHz)
125ns (8MHz)
500ns (2MHz)
VDD=2.8 to 5.5V
VDD=2.5 to 5.5V
VDD=2.2 to 5.5V
Note: Bus cycle time indicates the speed to read ROM.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
Ver.1.00
31908HKIM 20080117-S00006 No. A1035-1/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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„Minimum Instruction Cycle Time (tCYC)
250ns (12MHz)
375ns (8MHz)
1.5μs (2MHz)
VDD=2.8 to 5.5V
VDD=2.5 to 5.5V
VDD=2.2 to 5.5V
LC87F5N62B
„Ports
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 2-bit units
Ports whose I/O direction can be designated in 4-bit units
Normal withstand voltage input port
Dedicated oscillator ports
Reset pins
Power pins
64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn,
S2Pn, PWM0, PWM1, XT2)
16 (PEn, PFn)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
8 (VSS1 to VSS4, VDD1 to VDD4)
„Timers
Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture registers) ×2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture registers)
+ 8-bit counter (with an 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with 16-bit capture registers)
Mode 3: 16-bit counter (with 16-bit capture registers)
Timer 1: 16-bit timer/counter that support PWM/toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
Timer 4: 8-bit timer with a 6-bit prescaler
Timer 5: 8-bit timer with a 6-bit prescaler
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes.
„High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz).
2) Can generate output real-time.
„SIO
SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of
data transmission possible in 1-byte units)
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 32 bytes)
No.A1035-2/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
„UART: 2 channels
Full duplex
7/8/9 bit data bits selectable
1 stop bit (2 bit in continuous transmission mode)
Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
„AD Converter: 8 bits × 15 channels
„PWM: Multifrequency 12-bit PWM × 4 channels
„Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
„Watchdog Timer
External RC watchdog timer
Interrupt and reset signals selectable
„Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
„Interrupts
29 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt
requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No. Vector Address
Level
Interrupt Source
1 00003H
X or L
INT0
2 0000BH
X or L
INT1
3 00013H
H or L
INT2/T0L/INT4
4 0001BH
H or L
INT3/INT5/base timer0/base timer1
5 00023H
H or L
T0H/INT6
6 0002BH
H or L
T1L/T1H/INT7
7 00033H
H or L
SIO0/UART1 receive/UART2 receive
8 0003BH
H or L
SIO/SIO2/UART1 transmit/UART2 transmit
9 00043H
H or L
ADC/T6/T7/PWM4, PWM5
10 0004BH
H or L
Port 0/T4/T5/PWM0, PWM1
Priority levels X > H > L
Of interrupts of the same level, the one with the smallest vector address takes precedence.
„Subroutine Stack Levels: 1024 levels maximum (the stack is allocated in RAM)
„High-speed Multiplication/Division Instructions
16-bits × 8-bits (5 tCYC execution time)
24-bits × 16-bits (12 tCYC execution time)
16-bits ÷ 8-bits (8 tCYC execution time)
24-bits ÷ 16-bits (12 tCYC execution time)
„Oscillation Circuits
RC oscillation circuit (internal)
: For system clock
CF oscillation circuit
: For system clock, with internal Rf
Crystal oscillation circuit
: For low-speed system clock
Multifrequency RC oscillation circuit (internal) : For system clock
No.A1035-3/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
„System Clock Divider Function
Can run on low current.
The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and
64.0μs (at a main clock rate of 12MHz).
„Standby Function
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of interrupt.
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
„On-chip Debugger Function
Permits software debugging with the test device installed on the target board.
„Package Form
QIP100E (14 × 20) : “Lead-free type”
„Development Tools
Evaluation (EVA) chip
Emulator
On-chip-debugger
: LC87EV690
: EVA62S + ECB876600D + SUB875C00 + POD100QFP
ICE-B877300 + SUB875C00 + POD100QFP
: TCB87-TypeB + LC87F5NC8A or LC87F5N62B
„Programming Boards
Package
QIP100E (14 × 20)
Programming boards
W87F52256Q
„Flash ROM Programmer
Maker
Model
Flash Support
Group, Inc.
(Single)
AF9708/09/09B
(including product of Ando Electric Co.,Ltd)
Flash Support
Group, Inc.(Gang)
AF9723(Main body)
(including product of Ando Electric Co.,Ltd)
AF9833(Unit)
(including product of Ando Electric Co.,Ltd)
SANYO
SKK/SKK Type-B/SKK DBG Type-B
(SANYO FWS)
Support version(Note)
Revision : After Rev.02.73
Revision : After Rev.02.29
Revision : After Rev.01.88
Application Version:
After 1.04
Chip Data Version:
After2.14
Device
LC87F76C8A
LC87F5NC8A
LC87F5NC8A
No.A1035-4/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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Package Dimensions
unit : mm (typ)
3151A
LC87F5N62B
23.2
20.0
80 51
81 50
100
1
(0.58)
0.65
31
30
0.3
0.15
SANYO : QIP100E(14X20)
No.A1035-5/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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Pin Assignment
LC87F5N62B
PB6
PB5
PB4
PB3
PB2
PB1
PB0
VSS3
VDD3
PC7/DBGP2
PC6/DBGP1
PC5/DBGP0
PC4
PC3
PC2
PC1
PC0
PA0
PA1
PA2
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90 LC87F5N62B
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SI2P1/SI2/SB2
SI2P0/SO2
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
VDD4
VSS4
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Top view
SANYO: QIP100E(14×20) “Lead-free Type”
No.A1035-6/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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System Block Diagram
LC87F5N62B
Interrupt control
SIO0
SIO1
SIO2
Timer 0
Timer 1
Timer 4
Timer 5
PWM0/1
PWM4/5
Base timer
Timer 6
Timer 7
UART1
UART2
Standby control
CF
RC
X’tal
MRC
Bus Interface
Port 0
Port 1
Port 3
Port 7
Port 8
ADC
INT0 to 7
Noise rejection filter
Port 2
Port A
Port B
Port C
Port E
Port F
IR PLA
Flash ROM
PC
ACC
B register
C register
ALU
PSW
RAR
RAM
Stack Pointer
Watchdog Timer
On-chip debugger
No.A1035-7/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
Pin Description
Pin Name
VSS1, VSS2
VSS3, VSS4
VDD1, VDD2
VDD3, VDD4
Port 0
I/O
-
-
I/O
P00 to P07
Port 1
P10 to P17
I/O
Port 2
P20 to P27
I/O
- Power supply pin
Description
+ Power supply pin
• 8-bit I/O port
• I/O specifiable in 4-bit units
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Pin functions
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
• 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input, bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input, bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output, Beeper output
• 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Rising
Falling
Rising/
Falling
H level
L level
INT4
enable
enable
enable
disable
disable
INT5
enable
enable
enable
disable
disable
INT6
enable
enable
enable
disable
disable
INT7
enable
enable
enable
disable
disable
Option
No
No
Yes
Yes
Yes
Port 3
P30 to P36
I/O • 7-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P30: PWM4 output
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Yes
Continued on next page.
No.A1035-8/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
Continued from preceding page.
Pin Name
I/O
Description
Port 7
P70 to P73
I/O • 4-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer
P71: INT1 input/HOLD release input/Timer 0H capture input
P72: INT2 input/HOLD release input/Timer 0 event input/Timer 0L capture input
P73: INT3 input with noise filter/Timer 0 event input/Timer 0H capture input
• Interrupt acknowledge type
Rising
Falling
Rising/
Falling
H level
L level
INT0
enable
enable
disable
enable
enable
INT1
enable
enable
disable
enable
enable
INT2
enable
enable
enable
disable
disable
INT3
enable
enable
enable
disable
disable
• AD converter input port: AN8 (P70), AN9 (P71)
Port 8
I/O • 8-bit I/O port
P80 to P87
• I/O specifiable in 1-bit units
• Other functions
P80 to P87: AD converter input port
Port A
I/O • 6-bit I/O port
PA0 to PA5
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
Port B
I/O • 8-bit I/O port
PB0 to PB7
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
Port C
I/O • 8-bit I/O port
PC0 to PC7
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
DBGP0 to DBGP2 (PC5 to PC7): On-chip Debugger
Port E
I/O • 8-bit I/O port
PE0 to PE7
• I/O specifiable in 2-bit units
• Pull-up resistor can be turned on and off in 1-bit units
Port F
I/O • 8-bit I/O port
PF0 to PF7
• I/O specifiable in 2-bit units
• Pull-up resistor can be turned on and off in 1-bit units
SIO2 Port
I/O • 4-bit I/O port
SI2P0 to SI2P3
• I/O specifiable in 1-bit units
• Shared functions:
SI2P0: SIO2 data output
SI2P1: SIO2 data input, bus input/output
SI2P2: SIO2 clock input/output
SI2P3: SIO2 clock output
PWM0, PWM1
O • PWM0, PWM1 output port
• General-purpose I/O available
RES
I Reset pin
XT1 I • Input terminal for 32.768kHz X'tal oscillation
• Shared functions:
AN10: AD converter input port
General-purpose input port
Must be connected to VDD1 if not to be used.
XT2 I/O • Output terminal for 32.768kHz X'tal oscillation
• Shared functions:
AN11: AD converter input port
General-purpose I/O port
Must be set for oscillation and kept open if not to be used.
CF1 I Ceramic resonator input pin
CF2 O Ceramic resonator output pin
Option
No
No
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No.A1035-9/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port
P00 to P07
Options Selected
in Units of
1 bit
Option Type
1
CMOS
Output Type
Pull-up Resistor
Programmable (Note 1)
2 N-channel open drain
No
P10 to P17 1 bit 1 CMOS
Programmable
2 N-channel open drain
Programmable
P20 to P27 1 bit 1 CMOS
Programmable
2 N-channel open drain
Programmable
P30 to P36 1 bit 1 CMOS
Programmable
2 N-channel open drain
Programmable
P70 - No N-channel open drain
Programmable
P71 to P73 - No CMOS
Programmable
P80 to P87
- No N-channel open drain
No
PA0 to PA5 1 bit 1 CMOS
Programmable
2 N-channel open drain
Programmable
PB0 to PB7 1 bit 1 CMOS
Programmable
2 N-channel open drain
Programmable
PC0 to PC7
1 bit
1 CMOS
Programmable
2 N-channel open drain
Programmable
PE0 to PE7
- No CMOS
Programmable
PF0 to PF7
- No CMOS
Programmable
SI2P0, SI2P2
SI2P3
SI2P1
PWM0, PWM1
-
-
-
No CMOS
No
No CMOS (when selected as ordinary port)
No
N-channel open drain (When SIO2 data is selected)
No CMOS
No
XT1 - No Input only
No
XT2
- No Output for 32.768kHz quartz oscillator
No
N-channel open drain (when in general-purpose No
output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time.
Be sure to electrically short the VSS1, VSS2, VSS3 and VSS4 pins.
(Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the
backup capacitors.
Power
Supply
Back-up
capacitor
LSI
VDD1
VDD2
VDD3
VDD4
VSS1 VSS2 VSS3 VSS4
No.A1035-10/25
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8-bit 1-chip Microcontroller

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LC87F5N62B
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Power
Supply
Back-up
capacitor
LSI
VDD1
VDD2
VDD3
VDD4
VSS1 VSS2 VSS3 VSS4
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Maximum Supply
voltage
Symbol
VDD max
Pins/Remarks
VDD1, VDD2,
VDD3, VDD4
Conditions
VDD1=VDD2=VDD3=VDD4
VDD[V]
min
-0.3
Specification
typ max
+6.5
unit
Input voltage
Input/Output
Voltage
VI(1)
VIO(1)
XT1, CF1
Ports 0, 1, 2
Ports 3, 7, 8
-0.3 VDD+0.3
V
Ports A, B, C, E, F
SI2P0 to SI2P3
-0.3 VDD+0.3
PWM0, PWM1, XT2
Peak output
IOPH(1)
Ports 0, 1, 2, 3
CMOS output select per 1
current
Ports A, B, C, E, F
application pin
-10
SI2P0 to SI2P3
IOPH(2)
PWM0, PWM1
Per 1 application pin.
-20
IOPH(3)
P71 to P73
Per 1 application pin.
-5
Average output IOMH(1)
Ports 0, 1, 2, 3
CMOS output select per 1
current
Ports A, B, C, E, F
application pin
-7.5
(Note1-1)
SI2P0 to SI2P3
IOMH(2)
PWM0, PWM1
Per 1 application pin.
-10
IOMH(3)
P71 to P73
Per 1 application pin.
-3
Total output
current
ΣIOAH(1)
ΣIOAH(2)
P71 to P73
PWM0, PWM1
SI2P0 to SI2P3
Total of all applicable pins
Total of all applicable pins
-10
-25
mA
ΣIOAH(3) Port 0
Total of all applicable pins
-25
ΣIOAH(4) Port 0
Total of all applicable pins
PWM0, PWM1
-45
SI2P0 to SI2P3
ΣIOAH(5) Ports 2, 3, B
Total of all applicable pins
-25
ΣIOAH(6) Ports A, C
Total of all applicable pins
-25
ΣIOAH(7) Ports 2, 3, A, B, C
Total of all applicable pins
-45
ΣIOAH(8) Port F
Total of all applicable pins
-25
ΣIOAH(9) Ports 1, E
Total of all applicable pins
-25
ΣIOAH(10) Ports 1, E, F
Total of all applicable pins
-45
Note 1-1: Average output current is average of current in 100ms interval.
Continued on next page.
No.A1035-11/25
Datasheet pdf - http://www.DataSheet4U.net/


LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
Continued from preceding page.
Parameter
Symbol
Pins/Remarks
Conditions
Peak output
current
IOPL(1)
IOPL(2)
P02 to P07
Ports 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1
P00, P01
Per 1 application pin.
Per 1 application pin.
IOPL(3)
Ports 7, 8, XT2
Per 1 application pin.
Average output
current
(Note1-1)
IOML(1)
IOML(2)
P02 to P07
Ports 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1
P00, P01
Per 1 application pin.
Per 1 application pin.
IOML(3)
Ports 7, 8, XT2
Per 1 application pin.
Total output
current
ΣIOAL(1)
ΣIOAL(2)
Port 7, XT2
Port 8
Total of all applicable pins
Total of all applicable pins
ΣIOAL(3) Ports 7, 8, XT2
Total of all applicable pins
ΣIOAL(4)
ΣIOAL(5)
PWM0, PWM1
SI2P0 to SI2P3
Port 0
Total of all applicable pins
Total of all applicable pins
ΣIOAL(6)
ΣIOAL(7)
Port 0
PWM0, PWM1
SI2P0 to SI2P3
Ports 2, 3, B
Total of all applicable pins
Total of all applicable pins
ΣIOAL(8) Ports A, C
Total of all applicable pins
ΣIOAL(9) Ports 2, 3, A, B, C
Total of all applicable pins
ΣIOAL(10) Port F
Total of all applicable pins
ΣIOAL(11) Ports 1, E
Total of all applicable pins
ΣIOAL(12) Ports 1, E, F
Total of all applicable pins
Maximum power
Pd max
QIP100E(14×20)
Ta=-40 to +85°C
dissipation
Operating ambient
Topr
temperature
Storage ambient
Tstg
temperature
Note 1-1: Average output current is average of current in 100ms interval.
VDD[V]
Specification
min typ max unit
20
30
10
15
20
7.5
15
mA
15
20
45
45
80
45
45
80
45
45
80
320 mW
-40 +85
°C
-55 +125
No.A1035-12/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
Recommended Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Operating
supply voltage
(Note2-1)
Symbol
VDD(1)
Pins/Remarks
VDD1=VDD2
=VDD3=VDD4
Conditions
0.245μstCYC200μs
0.367μstCYC200μs
1.470μstCYC200μs
VDD[V]
min
2.8
2.5
2.2
Specification
typ max
5.5
5.5
5.5
unit
Memory
sustaining
supply voltage
VHD
VDD1=VDD2
=VDD3=VDD4
RAM and register contents in
HOLD mode.
2.0 5.5
High level input
voltage
VIH(1)
Ports 1, 2, 3
SI2P0 to SI2P3
P71 to P73
P70 port input/
interrupt side
2.2 to 5.5
0.3VDD
+0.7
VDD
VIH(2)
Ports 0, 8
Ports A, B, C, E, F
PWM0, PWM1
2.2 to 5.5
0.3VDD
+0.7
VDD
VIH(3)
P70 Watchdog timer
side
2.2 to 5.5
0.9VDD
VDD
V
VIH(4)
XT1, XT2, CF1,
RES
2.2 to 5.5 0.75VDD
VDD
Low level input
voltage
VIL(1)
Ports 1, 2, 3
SI2P0 to SI2P3
P71 to P73
P70 port input/
interrupt
4.0 to 5.5
2.2 to 4.0
VSS
VSS
0.1VDD
+0.4
0.2VDD
VIL(2)
Ports 0, 8
Ports A, B, C, E, F
PWM0, PWM1
2.5 to 5.5
2.2 to 5.5
VSS
VSS
0.15VDD
+0.4
0.2VDD
VIL(5)
Port 70 Watchdog
Timer
2.5 to 5.5
VSS
0.8VDD
-1.0
VIL(6)
XT1, XT2, CF1,
RES
2.5 to 5.5
VSS
0.25VDD
Instruction cycle tCYC
time (Note2-2)
2.8 to 5.5
2.5 to 5.5
0.245
0.367
200
200 μs
2.2 to 5.5
1.470
200
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
• System clock frequency
division rate=1/1
• External system clock
duty=50±5%
2.8 to 5.5
2.5 to 5.5
2.2 to 5.5
0.1
0.1
0.1
12
8
2 MHz
• CF2 pin open
• System clock frequency
division rate=1/2
2.8 to 5.5
2.5 to 5.5
2.2 to 5.5
0.2
0.2
0.2
24.4
16
4
Oscillation
frequency
Range
(Note2-3)
FmCF(1) CF1, CF2
FmCF(2) CF1, CF2
12MHz ceramic oscillation
See Fig. 1.
8MHz ceramic oscillation
See Fig. 1.
2.8 to 5.5
2.5 to 5.5
12
8
FmCF(3) CF1, CF2
4MHz ceramic oscillation
See Fig. 1.
2.2 to 5.5
4 MHz
FmRC
Internal RC oscillation
2.2 to 5.5
0.3 1.0
2.0
FmMRC
Frequency variable RC
oscillation source oscillation
2.2 to 5.5
16
FsX’tal
XT1, XT2
32.768kHz crystal oscillation.
See Fig. 2.
2.2 to 5.5
32.768
kHz
Note 2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A1035-13/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
High level input
current
Symbol
Pins/Remarks
IIH(1)
Ports 0, 1, 2
Ports 3, 7, 8
Conditions
Output disable
Pull-up resistor OFF
VDD[V]
min
Specification
typ max
Ports A, B, C
SI2P0 to SI2P3
RES
VIN=VDD
(including the off-leak current of
the output Tr.)
2.2 to 5.5
1
PWM0, PWM1
IIH(2)
XT1, XT2
Using as an input port
VIN=VDD
2.2 to 5.5
1
IIH(3)
CF1
VIN=VDD
2.2 to 5.5
15
Low level input
current
IIL(1)
Ports 0, 1, 2
Ports 3, 7, 8
Output disable
Pull-up resistor OFF
Ports A, B, C, E, F
SI2P0 to SI2P3
RES
VIN=VSS
(including the off-leak current of
the output Tr.)
2.2 to 5.5
-1
PWM0, PWM1
IIL(2)
XT1, XT2
Using as an input port
VIN=VSS
2.2 to 5.5
-1
IIL(3)
CF1
VIN=VSS
2.2 to 5.5
-15
High level output
voltage
Low level output
voltage
VOH(1)
VOH(2)
VOH(3)
VOH(4)
VOH(5)
VOH(6)
VOH(7)
VOH(8)
VOL(1)
VOL(2)
VOL(3)
Ports 0, 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
Ports 71, 72, 73
PWM0, PWM1
P30, P31(PWM4, 5
output mode)
Ports 0, 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1,
IOH=-1.0mA
IOH=-0.4mA
IOH=-0.2mA
IOH=-0.4mA
IOH=-0.2mA
IOH=-10mA
IOH=-1.6mA
IOH=-1.0mA
IOL=10mA
IOL=1.6mA
IOL=1.0mA
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
VDD-1
VDD-0.4
VDD-0.4
VDD-0.4
VDD-0.4
VDD-1.5
VDD-0.4
VDD-0.4
1.5
0.4
0.4
VOL(4)
P00, P01
IOL=30mA
4.5 to 5.5
1.5
VOL(5)
IOL=5.0mA
3.0 to 5.5
0.4
VOL(6)
IOL=2.5mA
2.2 to 5.5
0.4
VOL(7)
Ports 7, 8, XT2
IOL=1.6mA
3.0 to 5.5
0.4
VOL(8)
IOL=1.0mA
2.2 to 5.5
0.4
Pull-up resistation
Rpu(1)
Rpu(2)
Ports 0, 1, 2, 3
Port 7
Ports A, B, C, E, F
VOH=0.9VDD
4.5 to 5.5 15 35 80
2.2 to 5.5 15 35 120
Hysteresis voltage VHYS
RES
Ports 1, 2, 7
SI2P0 to SI2P3
2.2to 5.5
0.1VDD
Pin capacitance
CP
All pins
• For pins other than that under
test: VIN=VSS
• f=1MHz
2.2 to 5.5
10
• Ta=25°C
unit
μA
V
kΩ
V
pF
No.A1035-14/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Frequency
Symbol
tSCK(1)
Pins
/Remarks
SCK0(P12)
Conditions
• See Fig. 6.
VDD[V]
Specification
min typ max
2
unit
Low level
pulse width
High level
pulse width
Frequency
Low level
pulse width
High level
pulse width
Data setup time
Data hold time
tSCKL(1)
tSCKH(1)
tSCKHA(1a)
tSCKHA(1b)
tSCK(2)
tSCKL(2)
SCK0(P12)
• Continuous data
transmission/reception mode
• SIO2 is not in use simultaneous.
• See Fig. 6.
• (Note 4-1-2)
• Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
• See Fig. 6.
• (Note 4-1-2)
• CMOS output selected.
• See Fig. 6.
tSCKH(2)
tSCKHA(2a)
tSCKHA(2b)
tsDI(1)
thDI(1)
SI0(P11),
SB0(P11)
• Continuous data
transmission/reception mode
• SIO2 is not in use simultaneous.
• CMOS output selected.
• See Fig. 6.
• Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
• CMOS output selected.
• See Fig. 6.
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
2.2 to 5.5
1
1
4
tCYC
6
4/3
1/2
1/2
tSCK
2.2 to 5.5
tSCKH(2)
+2tCYC
tSCKH(2)
+2tCYC
tSCKH(2)
+(10/3)
tCYC
tCYC
tSCKH(2)
+(16/3)
tCYC
2.2 to 5.5
0.03
0.03
Output
delay time
tdD0(1)
tdD0(2)
tdD0(3)
SO0(P10),
SB0(P11),
• Continuous data
transmission/reception mode
• (Note 4-1-3)
• Synchronous 8-bit mode.
• (Note 4-1-3)
• (Note 4-1-3)
2.2 to 5.5
(1/3)tCYC
+0.05
1tCYC
+0.05
μs
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A1035-15/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter
Frequency
Symbol
tSCK(3)
Pins/
Remarks
SCK1(P15)
Conditions
• See Fig. 6.
Low level
pulse width
High level
pulse width
Frequency
tSCKL(3)
tSCKH(3)
tSCK(4)
Low level
pulse width
High level
pulse width
Data setup time
tSCKL(4)
tSCKH(4)
tsDI(2)
Data hold time
thDI(2)
SCK1(P15)
• CMOS output selected.
• See Fig. 6.
SI1(P14),
SB1(P14)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
VDD[V]
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
min
2
1
1
2
0.03
0.03
Output delay
tdD0(4)
SO1(P13), • Must be specified with respect to
time
SB1(P14)
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
2.2 to 5.5
change in open drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Specification
typ max
1/2
1/2
(1/3)tCYC
+0.05
unit
tCYC
tSCK
μs
No.A1035-16/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
3. SIO2 Serial I/O Characteristics (Note 4-3-1)
Parameter
Frequency
Low level
pulse width
High level
pulse width
Frequency
Low level
pulse width
High level
pulse width
Data setup time
Data hold Time
Symbol
tSCK(5)
tSCKL(5)
tSCKH(5)
tSCKHA(5a)
tSCKHA(5b)
tSCK(6)
tSCKL(6)
tSCKH(6)
tSCKHA(6a)
tSCKHA(6b)
tsDI(3)
thDI(3)
Pins/
Remarks
SCK2
(SI2P2)
SCK2
(SI2P2),
SCK2O
(SI2P3)
SI2(SI2P1),
SB2(SI2P1)
Conditions
• See Fig. 6.
• Continuous data transmission/
reception mode of SIO0 is not in
use simultaneous.
• See Fig. 6.
• (Note 4-3-2)
• Continuous data transmission/
reception mode of SIO0 is in use
simultaneous.
• See Fig. 6.
• (Note 4-3-2)
• CMOS output selected.
• See Fig. 6.
• Continuous data transmission/
reception mode of SIO0 is not in
use simultaneous.
• CMOS output selected.
• See Fig. 6.
• Continuous data transmission/
reception mode of SIO0 is in use
simultaneous.
• CMOS output selected.
• See Fig. 6.
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
VDD[V]
Specification
min. typ max.
2
1
1
unit
2.2 to 5.5
4
tCYC
7
4/3
1/2
1/2
tSCK
2.2 to 5.5
tSCKH(6)
+(5/3)tCYC
tSCKH(6)
+(5/3)tCYC
tSCKH(6)
+(10/3)tCYC
tCYC
tSCKH(6)
+(19/3)tCYC
2.2 to 5.5
0.03
0.03
Output delay
tdD0(5)
SO2
• Must be specified with respect to
μs
time
(SI2P0),
falling edge of SIOCLK
SB2(SI2P1)
• Must be specified as the time to
the beginning of output state
2.2 to 5.5
(1/3)tCYC
+0.05
change in open drain output mode.
• See Fig. 6.
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge
of the serial clock must be longer than tSCKHA.
No.A1035-17/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter Symbol
Pins/Remarks
Conditions
VDD[V]
Specification
min typ max
High/low level tPIH(1) INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1) INT1(P71),
• Event inputs for timer 0 or 1 are
INT2(P72)
enabled.
INT4(P20 to P23),
2.2 to 5.5
1
INT5(P24 to P27),
INT6(P20)
INT7(P24)
tPIH(2)
tPIL(2)
INT3(P73) when noise filter
time constant is 1/1.
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
2.2 to 5.5
2
tPIH(3)
tPIL(3)
INT3(P73)(The noise rejection • Interrupt source flag can be set.
clock is selected to 1/32.)
• Event inputs for timer 0 are enabled.
2.2 to 5.5
64
tPIH(4)
tPIL(4)
INT3(P73)(The noise rejection • Interrupt source flag can be set.
clock is selected to 1/128.)
• Event inputs for timer 0 are enabled.
2.2 to 5.5
256
tPIL(5) RES
Reset acceptable.
2.2 to 5.5 200
unit
tCYC
μs
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Symbol
Resolution
Absolute
accuracy
Conversion time
N
ET
TCAD
Pins/Remarks
AN0(P80) to
AN7(P87),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2),
AN12(PA3),
AN13(PA4),
AN14(PA5)
Conditions
(Note 6-1)
AD conversion time=32×tCYC
(when ADCR2=0) (Note 6-2)
AD conversion time=64×tCYC
VDD[V]
3.0 to 5.5
3.0 to 5.5
4.5 to 5.5
3.0 to 5.5
min
11.74
(tCYC=
0.367μs)
23.53
(tCYC=
0.735μs)
15.68
Specification
typ max
8
±1.5
97.92
(tCYC=
3.06μs)
97.92
(tCYC=
3.06μs)
97.92
unit
bit
LSB
μs
(when ADCR2=1) (Note 6-2)
4.5 to 5.5
(tCYC=
0.245μs)
(tCYC=
1.53μs)
23.49
97.92
3.0 to 5.5
(tCYC=
(tCYC=
0.367μs)
1.53μs)
Analog input
voltage range
VAIN
3.0 to 5.5
VSS
VDD
V
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
-1
Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value.
1
μA
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the complete digital value corresponding to the analog input value is loaded in the required register.
No.A1035-18/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Symbol
Normal mode
consumption
current
(Note 7-1)
IDDOP(1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
Pins/Remarks
Conditions
VDD1
=VDD2
=VDD3
=VDD4
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
VDD[V]
4.5 to 5.5
2.8 to 4.5
4.5 to 5.5
2.5 to 4.5
4.5 to 5.5
2.2 to 4.5
4.5 to 5.5
2.2 to 4.5
min
Specification
typ max
unit
9.3 20.5
5.4 14.8
6.9 15.5
3.9 11
2.75
1.45
6.6
mA
4.2
1 4.8
0.55
3.3
IDDOP(8)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
4.5 to 5.5
1.3 5.7
IDDOP(9)
• System clock set to 1MHz with frequency
variable RC oscillation
• Internal RC oscillation stopped
2.2 to 4.5
0.7 4.6
• 1/2 frequency division ratio.
IDDOP(10)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
4.5 to 5.5
40 120
IDDOP(11)
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
2.2 to 4.5
μA
20 77
• 1/2 frequency division ratio.
HALT mode
consumption
current
(Note 7-1)
IDDHALT(1)
VDD1
=VDD2
=VDD3
=VDD4
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 12MHz side
4.5 to 5.5
3.6 8.3
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
2.8 to 5.5
2.1 4.4
IDDHALT(2)
• 1/1 frequency division ratio.
• HALT mode
mA
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
4.5 to 5.5
2.7 5.8
mode
IDDHALT(3)
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
2.5 to 4.5
1.4 3.1
• 1/1 frequency division ratio.
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
Continued on next page.
No.A1035-19/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
Continued from preceding page.
Parameter
HALT mode
consumption
current
(Note 7-1)
Symbol
IDDHALT(4)
IDDHALT(5)
Pins/Remarks
Conditions
VDD1
=VDD2
=VDD3
=VDD4
• HALT mode
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
VDD[V]
min
4.5 to 5.5
2.2 to 4.5
Specification
typ max
unit
1.1 2.6
0.57
1.5
IDDHALT(6)
IDDHALT(7)
IDDHALT(8)
IDDHALT(9)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 1MHz with frequency
variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
4.5 to 5.5
2.2 to 4.5
4.5 to 5.5
2.2 to 4.5
0.38
0.19
1.0
mA
0.8
1.15
4.2
0.57
3.0
IDDHALT(10)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
4.5 to 5.5
20 77
mode.
IDDHALT(11)
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
2.2 to 4.5
6 70
• 1/2 frequency division ratio.
μA
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
VDD1
• HOLD mode
• CF1=VDD or open (External clock mode)
4.5 to 5.5
2.2 to 4.5
0.04
0.02
19
14
Timer HOLD
mode
consumption
current
IDDHOLD(3)
IDDHOLD(4)
• Timer HOLD mode
• CF1=VDD or open (External clock mode)
• FmX'tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5
2.2 to 4.5
17 70
4 55
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Onboard
programming
Symbol
IDDFW(1)
Pins/Remarks
Conditions
VDD1
• Without CPU current
VDD[V]
2.7 to 5.5
min
Specification
typ max
unit
5 10 mA
current
Programming
time
tFW(1)
tFW(2)
• Erasing
• programming
2.7 to 5.5
2.7 to 5.5
20 30 ms
40 60 μs
No.A1035-20/25
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LC87F5N62B
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V
Parameter
Transfer rate
Symbol
UBR, UBR2
Pins/Remarks
UTX1(P32),
Conditions
VDD[V]
min
Specification
typ max
unit
RTX1(P33),
UTX2(P33),
2.5 to 5.5
16/3
8192/3 tCYC
RTX2(P34)
Data length : 7/8/9 bits (LSB first)
Stop bits : 1-bit (2-bit in continuous data transmission)
Parity bits : None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H)
Start of
transmission
Start bit
Transmit data (LSB first)
Stop bit
End of
transmission
UBR
UBR2
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H)
Start bit
Start of
reception
Receive data (LSB first)
Stop bit
End of
reception
UBR
UBR2
VDD1, VSS1 Terminal Condition
It is necessary to place capacitors between VDD1 and VSS1 as describe below.
Place capacitors as close to VDD1 and VSS1 as possible.
Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
Capacitance of C2 must be more than 0.1μF.
Use thicker pattern for VDD1 and VSS1.
L2
L1
VSS1
C1 C2
L1’
L2’
VDD1
No.A1035-21/25
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8-bit 1-chip Microcontroller

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LC87F5N62B
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Frequency
Vendor
Name
Oscillator Name
Circuit Constant
C1 C2
[pF] [pF]
Rf1
[Ω]
Operating
Oscillation
Voltage Stabilization Time
Rd1 Range typ max
[Ω] [V] [ms] [ms]
Remarks
12MHz
CSTCE12M0G52-R0 (10)
(10)
Open
470 2.5 to 5.5
0.03
0.5
Internal C1,C2
10MHz
CSTCE10M0G52-R0 (10)
(10)
Open
680 2.4 to 5.5
0.03
0.5
Internal C1,C2
CSTLS10M0G53-B0 (15)
(15)
Open
680 2.5 to 5.5
0.03
0.5
Internal C1,C2
MURATA CSTCE8M00G52-R0 (10)
(10) Open 1k 2.3 to 5.5 0.03
0.5
Internal C1,C2
8MHz
CSTLS8M00G53-B0 (15)
(15) Open 1k 2.5 to 5.5 0.03
0.5
Internal C1,C2
4MHz
CSTCR4M00G53-R0 (15)
(15)
Open 1.5k 2.2 to 5.5
0.03
0.5
Internal C1,C2
CSTLS4M00G53-B0 (15)
(15)
Open 1.5k 2.2 to 5.5
0.03
0.5
Internal C1,C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Fig. 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Frequency
Vendor
Name
Oscillator Name
Circuit Constant
C3 C4 Rf2 Rd2
[pF] [pF]
[Ω]
[Ω]
Operating Voltage
Range
[V]
Oscillation
Stabilization Time
typ max
[s] [s]
Remarks
32.768kHz
EPSON
TOYOCOM
MC-306
18 18 Open 560k
2.2 to 5.5
Applicable
1.5 3.0
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure. 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
Rf1
C1 CF
CF2
Rd1
C2
Figure 1 Ceramic Oscillator Circuit
XT1
C3
Rf2
X’tal
XT2
Rd2
C4
Figure 2 Crystal Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1035-22/25
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8-bit 1-chip Microcontroller

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Power supply
RES
Internal RC
oscillation
CF1, CF2
XT1, XT2
LC87F5N62B
Reset time
tmsCF
tmsX’tal
VDD
VDD limit
GND
Operating mode
Unfixed
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset
signal absent
Internal RC
oscillation
CF1, CF2
XT1, XT2
HOLD reset signal valid
tmsCF
tmsX’tal
State
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A1035-23/25
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8-bit 1-chip Microcontroller

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LC87F5N62B
VDD
RRES
Note:
Select CRES and RRES value to assure that at least 200μs
RES reset time is generated after the VDD becomes higher than
the minimum operating voltage.
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DATAOUT:
SIOCLK:
DATAIN:
DATAOUT:
SIOCLK:
DATAIN:
DATAOUT:
DI0 DI1 DI2 DI3 DI4 DI5 DI6
DI7
DI8
DO0 DO1 DO2 DO3 DO4 DO5 DO6
tSCKL
tSCK
tSCKH
DO7
Data RAM
transfer period
(SIO0,2 only)
DO8
tsDI thDI
tdDO
tSCKLA
tdDO
tsDI
tSCKHA
Data RAM
transfer period
(SIO0,2 only)
thDI
Figure 6 Serial I/O Waveforms
tPIL tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1035-24/25
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LC87F5N62B (Sanyo Semicon Device)
8-bit 1-chip Microcontroller

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LC87F5N62B
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of December, 2007. Specifications and information herein are subject
to change without notice.
PS No.A1035-25/25
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