HT46801N-1 (Holtek Semiconductor)
(HT4xR01x-1) Small Package 8-Bit OTP MCU

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HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
Small Package 8-Bit OTP MCU
Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
CPU Features
· Operating voltage:
fSYS= 4MHz: 2.2V~5.5V
fSYS= 8MHz: 3.3V~5.5V
fSYS= 12MHz: 4.5V~5.5V
· Up to 0.33ms instruction cycle with 12MHz system
clock at VDD= 5V
· Sleep mode and wake-up functions to reduce
power consumption
· Oscillator types:
External high frequency Crystal -- HXT
External RC -- ERC
Internal RC -- HIRC
External low frequency crystal -- LXT
· Three operational modes: Normal, Slow, Sleep
· Fully integrated internal 4MHz, 8MHz and 12MHz
oscillator requires no external components
· Program Memory: 1K´15
· Data Memory: 96´8
· Watchdog Timer function
· LIRC oscillator function for watchdog timer
· 6-level subroutine nesting
· All instructions executed in one or two instruction
cycles
· Table read instructions
· 63 powerful instructions
· Bit manipulation instruction
· Low voltage reset function
· 10-pin MSOP, 16-pin NSOP package types
Peripheral Features
· Up to 10 bidirectional I/O lines
· 4 channel 12-bit ADC
· 1 channel 8-bit PWM
· External interrupt input shared with an I/O line
· Two 8-bit programmable Timer/Event
Counter with overflow interrupt and prescaler
· Time-Base function
· Programmable Frequency Divider - PFD
General Description
The Small Package MCUs are a series of 8-bit high per-
formance, RISC architecture microcontrollers specifi-
cally designed for a wide range of applications. The
usual Holtek microcontroller features of low power con-
sumption, I/O flexibility, timer functions, oscillator op-
tions, power down and wake-up functions, watchdog
timer and low voltage reset, combine to provide devices
with a huge range of functional options while still main-
taining a high level of cost effectiveness. The fully inte-
grated system oscillator HIRC, which requires no
external components and which has three frequency
selections, opens up a huge range of new application
possibilities for these devices, some of which may in-
clude industrial control, consumer products, household
appliances subsystem controllers, etc.
Rev.1.00
1 June 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/


HT46801N-1 (Holtek Semiconductor)
(HT4xR01x-1) Small Package 8-Bit OTP MCU

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HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
Selection Table
Part No.
Program Data
8-bit Time HIRC RTC
I/O
Memory Memory
Timer Base (MHz) (LXT)
A/D
PWM PFD Stack Package
HT46R01B-1 1K´15
96´8
8
2
1 4/8/12 Ö 12-bit´4 8-bit´1 Ö
6 10MSOP
HT46R01N-1 1K´15
96´8
10
2
1
Ö 12-bit´4 8-bit´1 Ö
6 16NSOP
HT48R01B-1 1K´15
96´8
8
2
1
Ö ¾ ¾ Ö 6 10MSOP
HT48R01N-1 1K´15
96´8
10
2
1
Ö ¾ ¾ Ö 6 16NSOP
Block Diagram
The following block diagram illustrates the main functional blocks.
Low
V o lta g e
R eset
W a tc h d o g
T im e r
PW M
D r iv e r
O TP
P ro g ra m
M e m o ry
RAM
D a ta
M e m o ry
PFD
D r iv e r
I/O
P o rts
8 - b it
R IS C
M CU
C o re
A /D
C o n v e rte r
8 - b it
T im e r s
T im e
B ase
In te rn a l
O s c illa to r s
R eset
C ir c u it
In te rru p t
C o n tr o lle r
E x te rn a l
C r y s ta l/R C
O s c illa to r s
Pin Assignment
P A 3 /IN T
P A 2 /T C 0
P A 1 /P F D
PA0
VSS
1 10
29
38
47
56
H T 4 8 R 0 1 B -1
1 0 M S O P -A
P A 4 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
VDD
P A 3 /IN T
P A 2 /T C 0
P A 1 /P F D
PA0
PB0
VSS
NC
NC
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
H T 4 8 R 0 1 N -1
1 6 N S O P -A
P A 4 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
PB1
VDD
NC
NC
P A 3 /IN T /A N 3
P A 2 /T C 0 /A N 2
P A 1 /P F D /A N 1
P A 0 /A N 0
VSS
1 10
29
38
47
56
H T 4 6 R 0 1 B -1
1 0 M S O P -A
P A 4 /T C 1 /P W
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
VDD
M
P A 3 /IN T /A N 3
P A 2 /T C 0 /A N 2
P A 1 /P F D /A N 1
P A 0 /A N 0
PB0
VSS
NC
NC
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
H T 4 6 R 0 1 N -1
1 6 N S O P -A
P A 4 /T C 1 /P W
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
PB1
VDD
NC
NC
M
Rev.1.00
2 June 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/


HT46801N-1 (Holtek Semiconductor)
(HT4xR01x-1) Small Package 8-Bit OTP MCU

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HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
Pin Description
The function of each pin is listed in the following tables, however the details behind how each pin is configured is con-
tained in the other individual peripheral function sections.
HT46R01B-1
Pin Name Function OPT I/T O/T
Description
PA0/AN0
PA0
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
AN0 ADCR OPAI ¾ Analog to Digital Converter channel input 0
PA1/PFD/AN1
PA1
PFD
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CTRL0 ¾ CMOS PFD output
AN1 ADCR ¾ OPAO Analog to Digital Converter channel input 1
PA2/TC0/AN2
PA2
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC0 TMR0C ST
¾ External Timer 0 clock input
AN2 ADCR ¾ OPAO Analog to Digital Converter channel input 2
PA3
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PA3/INT/AN3
INT
INTC0
CTRL1
ST
¾ External interrupt input
AN3 ADCR OPAI ¾ Analog to Digital Converter channel input 3
PA4/TC1/PWM
PA4
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC1 TMR1C ST
¾ External Timer 1 clock input
PWM CTRL0 ¾ CMOS PWM output
PA5/OSC2
PA5
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC2 CO ¾ OSC Oscillator pin
PA6/OSC1
PA6
OSC1
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CO OSC ¾ Oscillator pin
PA7/RES
PA7
RES
PAWK ST NMOS General purpose I/O. Register enabled wake-up.
CO ST
¾ Reset input
VDD
VDD
¾ PWR ¾ Power supply
VSS
VSS
¾ PWR ¾ Ground
Note:
OPT: Optional by configuration option (CO) or register option
I/T: Input type
O/T: Output type
CO: Configuration option
ST: Schmitt Trigger input
AN: analog input;
CMOS: CMOS output
NMOS: NMOS output
OSC: Oscillator pin
PWR: Power
*: AVDD is the ADC power supply and is bonded together internally with VDD while AVSS is the ADC ground
pin and is bonded together internally with VSS.
Rev.1.00
3 June 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/


HT46801N-1 (Holtek Semiconductor)
(HT4xR01x-1) Small Package 8-Bit OTP MCU

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HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
HT46R01N-1
Pin Name Function OPT I/T O/T
Description
PA0/AN0
PA0
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
AN0 ADCR OPAI ¾ Analog to Digital Converter channel input 0
PA1/PFD/AN1
PA1
PFD
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CTRL0 ¾ CMOS PFD output
AN1 ADCR ¾ OPAO Analog to Digital Converter channel input 1
PA2/TC0/AN2
PA2
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC0 TMR0C ST
¾ External Timer 0 clock input
AN2 ADCR ¾ OPAO Analog to Digital Converter channel input 2
PA3
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PA3/INT/AN3
INT
INTC0
CTRL1
ST
¾ External interrupt input
AN3 ADCR OPAI ¾ Analog to Digital Converter channel input 3
PA4/TC1/PWM
PA4
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC1 TMR1C ST
¾ External Timer 1 clock input
PWM CTRL0 ¾ CMOS PWM output
PA5/OSC2
PA5
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC2 CO ¾ OSC Oscillator pin
PA6/OSC1
PA6
OSC1
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CO OSC ¾ Oscillator pin
PA7/RES
PA7
RES
PAWK ST NMOS General purpose I/O. Register enabled wake-up.
CO ST
¾ Reset input
PB0 PB0 PBPU ST CMOS General purpose I/O. Register enabled.
PB1 PB1 PBPU ST CMOS General purpose I/O. Register enabled.
VDD
VDD
¾ PWR ¾ Power supply
VSS
VSS
¾ PWR ¾ Ground
Note:
OPT: Optional by configuration option (CO) or register option
I/T: Input type
O/T: Output type
CO: Configuration option
ST: Schmitt Trigger input
AN: analog input
CMOS: CMOS output
NMOS: NMOS output
OSC: Oscillator pin
PWR: Power
*: AVDD is the ADC power supply and is bonded together internally with VDD while AVSS is the ADC ground
pin and is bonded together internally with VSS.
Rev.1.00
4 June 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/


HT46801N-1 (Holtek Semiconductor)
(HT4xR01x-1) Small Package 8-Bit OTP MCU

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HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
HT48R01B-1
Pin Name
PA0
PA1/PFD
PA2/TC0
PA3/INT
PA4/TC1
PA5/OSC2
PA6/OSC1
PA7/RES
VDD
VSS
Function OPT I/T
PA0
PAPU
PAWK
ST
PA1
PAPU
PAWK
ST
PFD CTRL0 ¾
PA2
PAPU
PAWK
ST
TC0 TMR0C ST
PA3
PAPU
PAWK
ST
INT
INTC0
CTRL1
ST
PA4
PAPU
PAWK
ST
TC1 TMR1C ST
PA5
PAPU
PAWK
ST
OSC2 CO ¾
PA6
PAPU
PAWK
ST
OSC1
CO OSC
PA7 PAWK ST
RES
CO ST
VDD
¾ PWR
VSS
¾ PWR
O/T Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS PFD output
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾ External Timer 0 clock input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾ External interrupt input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾ External Timer 1 clock input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC Oscillator pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾ Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
¾ Reset input
¾ Power supply
¾ Ground
Note:
OPT: Optional by configuration option (CO) or register option
I/T: Input type
O/T: Output type
CO: Configuration option
ST: Schmitt Trigger input
AN: analog input
CMOS: CMOS output
NMOS: NMOS output
OSC: Oscillator pin
PWR: Power
Rev.1.00
5 June 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/


HT46801N-1 (Holtek Semiconductor)
(HT4xR01x-1) Small Package 8-Bit OTP MCU

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HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
HT48R01N-1
Pin Name
PA0
PA1/PFD
PA2/TC0
PA3/INT
PA4/TC1
PA5/OSC2
PA6/OSC1
PA7/RES
PB0
PB1
VDD
VSS
Function OPT I/T
PA0
PAPU
PAWK
ST
PA1
PAPU
PAWK
ST
PFD CTRL0 ¾
PA2
PAPU
PAWK
ST
TC0 TMR0C ST
PA3
PAPU
PAWK
ST
INT
INTC0
CTRL1
ST
PA4
PAPU
PAWK
ST
TC1 TMR1C ST
PA5
PAPU
PAWK
ST
OSC2 CO ¾
PA6
PAPU
PAWK
ST
OSC1
CO OSC
PA7 PAWK ST
RES
CO ST
PB0 PBPU ST
PB1 PBPU ST
VDD
¾ PWR
VSS
¾ PWR
O/T Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS PFD output
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾ External Timer 0 clock input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾ External interrupt input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾ External Timer 1 clock input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC Oscillator pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾ Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
¾ Reset input
CMOS General purpose I/O. Register enabled.
CMOS General purpose I/O. Register enabled.
¾ Power supply
¾ Ground
Note:
OPT: Optional by configuration option (CO) or register option
I/T: Input type
O/T: Output type
CO: Configuration option
ST: Schmitt Trigger input
AN: analog input
CMOS: CMOS output
NMOS: NMOS output
OSC: Oscillator pin
PWR: Power
Rev.1.00
6 June 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/


HT46801N-1 (Holtek Semiconductor)
(HT4xR01x-1) Small Package 8-Bit OTP MCU

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HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................100mA
Total Power Dissipation .....................................500mW
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
VDD Operating Voltage
IDD1
Operating Current
(HXT, HIRC, ERC)
IDD2
Operating Current
(HXT, HIRC, ERC)
IDD3
Operating Current
(HXT, HIRC, ERC)
IDD4
Operating Current
(HIRC + LXT, Slow Mode)
ISTB1
Standby Current
(LIRC On, LXT Off)
ISTB2
Standby Current
(LIRC Off, LXT Off)
ISTB3
Standby Current
(LIRC Off, LXT On, LXTLP=1)
VIL1
Input Low Voltage for PA, PB
TCn and INT
VIH1
VIL2
VIH2
VLVR1
VLVR2
VLVR3
Input High Voltage for PA, PB
TCn and INT
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset 1
Low Voltage Reset 2
Low Voltage Reset 3
Test Conditions
VDD Conditions
fSYS=4MHz
¾ fSYS=8MHz
fSYS=12MHz
3V
No load, fSYS=4MHz
5V
3V
No load, fSYS=8MHz
5V
Ta=25°C
Min. Typ. Max. Unit
2.2 ¾ 5.5 V
3.3 ¾ 5.5 V
4.5 ¾ 5.5 V
¾ 0.8 1.2 mA
¾ 1.5 2.25 mA
¾ 1.4 2.1 mA
¾ 2.8 4.2 mA
5V No load, fSYS=12MHz
¾4
6 mA
3V No load, fSYS=32768Hz
5V (LVR disabled, LXTLP=1)
3V
No load, system HALT
5V
3V
No load, system HALT
5V
3V
No load, system HALT
5V
5V ¾
¾¾
5V ¾
¾¾
¾¾
¾¾
¾ VLVR = 4.2V
¾ VLVR = 3.15V
¾ VLVR = 2.1V
¾
¾
¾
¾
¾
¾
¾
¾
0
0
3.5
0.8VDD
0
0.9VDD
3.98
2.98
1.98
5
12
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
4.2
3.15
2.1
10
24
5
10
1
2
5
10
1.5
0.2VDD
5.0
VDD
0.4VDD
VDD
4.42
3.32
2.22
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
Rev.1.00
7 June 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/


HT46801N-1 (Holtek Semiconductor)
(HT4xR01x-1) Small Package 8-Bit OTP MCU

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HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
Ta=25°C
Symbol
Parameter
IOL1 I/O Port Sink Current
Test Conditions
VDD Conditions
3V
VOL=0.1VDD
5V
Min. Typ. Max. Unit
4 8 ¾ mA
10 20 ¾ mA
IOH I/O Port Source Current
3V
VOH=0.9VDD
5V
-2 -4 ¾ mA
-5 -10 ¾ mA
IOL2 PA7 Sink Current
3V
VOL=0.1VDD
5V
0.8 1.2 ¾ mA
2.0 3.0 ¾ mA
RPH Pull-high Resistance
3V ¾
5V ¾
20 60 100 kW
10 30 50 kW
Note: The standby current (ISTB1~ISTB3) and IDD4 are measured with all I/O pins in input mode and tied to VDD.
A.C. Characteristics
Symbol
Parameter
fSYS System Clock
fHIRC
System Clock
(HIRC)
Test Conditions
VDD Conditions
2.2V~5.5V
¾ 3.3V~5.5V
4.5V~5.5V
3V/5V Ta=25°C
3V/5V Ta=25°C
5V Ta=25°C
3V/5V Ta=0~70°C
3V/5V Ta=0~70°C
5V Ta=0~70°C
2.2V~
3.6V
Ta=0~70°C
3.0V~
5.5V
Ta=0~70°C
3.0V~
5.5V
Ta=0~70°C
4.5V~
5.5V
Ta=0~70°C
2.2V~
3.6V
Ta= -40°C~85°C
3.0V~
5.5V
Ta= -40°C~85°C
3.0V~
5.5V
Ta= -40°C~85°C
4.5V~
5.5V
Ta= -40°C~85°C
Ta=25°C
Min. Typ. Max. Unit
32
32
32
-2%
-2%
-2%
-5%
-5%
-5%
-8%
¾ 4000 kHz
¾ 8000 kHz
¾ 12000 kHz
4 +2% MHz
8 +2% MHz
12 +2% MHz
4 +5% MHz
8 +5% MHz
12 +5% MHz
4 +8% MHz
-8% 4 +8% MHz
-8% 8 +8% MHz
-8% 12 +8% MHz
-12% 4 +12% MHz
-12% 4 +12% MHz
-12% 8 +12% MHz
-12% 12 +12% MHz
Rev.1.00
8 June 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/


HT46801N-1 (Holtek Semiconductor)
(HT4xR01x-1) Small Package 8-Bit OTP MCU

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HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
Ta=25°C
Symbol
Parameter
Test Conditions
VDD Conditions
Min. Typ. Max. Unit
5V Ta=25°C, R=120kW *
-2% 4 +2% MHz
fERC
System Clock
(ERC)
5V Ta=0~70°C, R=120kW *
5V Ta= -40°C~85°C,
R=120kW *
-5% 4 +5% MHz
-7% 4 +7% MHz
2.2V~ Ta= -40°C~85°C,
5.5V R=120kW *
-11% 4 +11% MHz
fLXT System Clock (LXT)
¾
¾
¾ 32768 ¾
Hz
fTIMER
Timer Input Frequency
(TCn)
2.2V~5.5V
¾ 3.3V~5.5V
4.5V~5.5V
0 ¾ 4000 kHz
0 ¾ 8000 kHz
0 ¾ 12000 kHz
tLIRC
LIRC Oscillator
3V ¾ 45 90 180 ms
5V ¾ 32 65 130 ms
tRES External Reset Low Pulse Width ¾
¾
1 ¾ ¾ ms
tSST System Start-up time Period
For HXT/LXT
¾
For ERC/IRC
¾ 128 ¾ tSYS
¾ 2 ¾ tSYS
tINT Interrupt Pulse Width ¾ ¾
1 ¾ ¾ ms
tLVR Low Voltage Width to Reset
¾
¾
0.25 1
2 ms
tRSTD Reset Delay Time
¾ ¾ ¾ 100 ¾ ms
Note: 1. tSYS=1/fSYS
2. *For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
Rev.1.00
9 June 9, 2011
Datasheet pdf - http://www.DataSheet4U.net/


HT46801N-1 (Holtek Semiconductor)
(HT4xR01x-1) Small Package 8-Bit OTP MCU

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HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
A/D Converter Characteristics
Symbol
Parameter
AVDD Analog Operating Voltage
Test Conditions
VDD Conditions
¾¾
A/D Converter Input Voltage
¾¾
DNL Differential Non-Linearity
¾ tAD=0.5ms
INL Integral Non-Linearity
¾ tAD=0.5ms
IADC
Additional Power Consumption
if A/D Converter is Used
3V
5V
¾
tAD
A/D Converter Clock Period
2.7V~
5.5V
¾
tADC
A/D Converter Conversion Time 2.7V~
(including Sample and Hold Time) 5.5V
¾
tADCS
A/D Converter Sampling Time
2.7V~
5.5V
¾
tON2ST
A/D Converter On-to-Start Time
2.7V~
5.5V
¾
Ta=25°C
Min. Typ. Max. Unit
2.7 ¾ 5.5
V
0
¾ VREF
V
-2 ¾ 2 LSB
-4 ¾ 4 LSB
¾ 0.5 ¾
mA
¾ 0.6 ¾
mA
0.5 ¾ 10
ms
¾ 16 ¾ tAD
¾ 4 ¾ tAD
2 ¾ ¾ ms
Power-on Reset Characteristics
Symbol
Parameter
Test Conditions
VDD Conditions
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
RRVDD
VDD Rise Rate to Ensure
Power-on Reset
¾
¾
tPOR
Minimum Time for VDD to remain
at VPOR to Ensure Power-on Reset
¾
¾
Ta=25°C
Min. Typ. Max. Unit
¾¾
0.035 ¾
1¾
100 mV
¾ V/ms
¾ ms
V DD
tP O R R R V D D
V POR
T im e
Rev.1.00
10
June 9, 2011
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System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the inter-
nal system architecture. The range of devices take ad-
vantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It car-
ries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The inter-
nal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural fea-
tures ensure that a minimum of external components is
required to provide a functional I/O and A/D control sys-
tem with maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from either a Crys-
tal/Resonator or RC oscillator is subdivided into four in-
ternally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive in-
struction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two instruction cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m C o u n te r
PC
PC +1
PC +2
P ip e lin in g
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 M O V A ,[1 2 H ]
2 C A LL D E LA Y
3 C P L [1 2 H ]
4:
5:
6 D E LA Y : N O P
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
Instruction Fetching
Rev.1.00
11 June 9, 2011
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Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. Note that
the Program Counter width varies with the Program
Memory capacity depending upon which device is se-
lected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For condi-
tional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is dis-
carded and a dummy cycle takes its place while the cor-
rect instruction is obtained.
Device
All devices
Program Counter
High Byte
High Byte
(PCL Register)
PC9~PC8
PCL7~PCL0
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable regis-
ter. By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be in-
serted.
The lower byte of the Program Counter is fully accessi-
ble under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is neither part of the Data or Program Memory
space, and is neither readable nor writeable. The acti-
vated level is indexed by the Stack Pointer, SP, and is
neither readable nor writeable. At a subroutine call or in-
terrupt acknowledge signal, the contents of the Program
Counter are pushed onto the stack. At the end of a sub-
routine or an interrupt routine, signaled by a return in-
struction, RET or RETI, the Program Counter is restored
to its previous value from the stack. After a device reset,
the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the ac-
knowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine in-
struction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
P ro g ra m C o u n te r
T o p o f S ta c k
S ta c k
P o in te r
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k L e v e l 3
P ro g ra m
M e m o ry
B o tto m o f S ta c k
S ta c k L e v e l 6
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic op-
erations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related in-
struction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or oper-
ations may result in carry, borrow or other status
changes, the status register will be correspondingly up-
dated to reflect these changes. The ALU supports the
following functions:
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Rev.1.00
12 June 9, 2011
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Program Memory
The Program Memory is the location where the user
code or program is stored. The device is supplied with
One-Time Programmable, OTP, memory where users
can program their application code into the device. By
using the appropriate programming tools, OTP devices
offer users the flexibility to freely develop their applica-
tions which may be useful during debug or for products
requiring frequent upgrades or program changes.
Structure
The Program Memory has a capacity of 1K´15. The
Program Memory is addressed by the Program Counter
and also contains data, table information and interrupt
entries. Table data, which can be setup in any location
within the Program Memory, is addressed by separate
table pointer registers.
Special Vectors
Within the Program Memory, certain locations are re-
served for special usage such as reset and interrupts.
· Reset Vector
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
· External interrupt vector
This vector is used by the external interrupt. If the ex-
ternal interrupt pin on the device receives an edge
transition, the program will jump to this location and
begin execution if the external interrupt is enabled and
the stack is not full. The external interrupt active edge
transition type, whether high to low, low to high or both
is specified in the CTRL1 register.
· Timer/Event 0/1 counter interrupt vector
This internal vector is used by the Timer/Event Coun-
ters. If a Timer/Event Counter overflow occurs, the
program will jump to its respective location and begin
execution if the associated Timer/Event Counter inter-
rupt is enabled and the stack is not full.
· A/D interrupt vector
This internal vector is used by the A/D converter. If
A/D conversion complete , the program will jump to
this location and begin execution if the A/D interrupt is
enabled and the stack is not full.
· Time base interrupt vector
This internal vector is used by the internal Time Base.
If a Time Base overflow occurs, the program will jump
to this location and begin execution if the Time Base
counter interrupt is enabled and the stack is not full.
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the table pointer register,
TBLP. This register defines the lower 8-bit address of
the look-up table.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these in-
structions are executed, the lower order table byte from
the Program Memory will be transferred to the user de-
fined Data Memory register [m] as specified in the in-
struction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
H T 4 6 R 0 1 B -1
H T 4 6 R 0 1 N -1
000H R eset
004H
E x te rn a l
In te rru p t
008H
T im e r 0
In te rru p t
00C H
T im e r 1
In te rru p t
010H
A /D
In te rru p t
014H
T im e B a s e
In te rru p t
018H
H T 4 8 R 0 1 B -1
H T 4 8 R 0 1 N -1
000H R eset
004H
E x te rn a l
In te rru p t
008H
T im e r 0
In te rru p t
00C H
T im e r 1
In te rru p t
010H
014H
T im e B a s e
In te rru p t
018H
3 F F H 1 5 b its
3 F F H 1 5 b its
Program Memory Structure
Rev.1.00
13 June 9, 2011
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The following diagram illustrates the addressing/data
flow of the look-up table:
Lastpage or
p re s e n t p a g e
P C 9~P C 8
P C H ig h B y te
T B L P R e g is te r
P ro g ra m M e m o ry
D a ta
1 5 b its
R e g is te r T B L H
H ig h B y te
U s e r S e le c te d
R e g is te r
L o w B y te
Table Program Example
The accompanying example shows how the table
pointer and table data is defined and retrieved from the
device. This example uses raw table data located in the
last page which is stored there using the ORG state-
ment. The value at this ORG statement is ²300H² which
refers to the start address of the last page within the 1K
Program Memory of the device. The table pointer is
setup here to have an initial value of ²06H². This will en-
sure that the first data read from the data table will be at
the Program Memory address ²306H² or 6 locations af-
ter the start of the last page. Note that the value for the
table pointer is referenced to the first address of the
present page if the ²TABRDC [m]² instruction is being
used. The high byte of the table data which in this case
is equal to zero will be transferred to the TBLH register
automatically when the ²TABRDL [m]² instruction is ex-
ecuted.
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use the table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of TBLH and subsequently cause er-
rors if used again by the main routine. As a rule it is rec-
ommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the inter-
rupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
Table Location Bits
Instruction
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TABRDC [m]
PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m]
1 1 @7 @6 @5 @4 @3 @2 @1 @0
Note:
Table Location
PC9~PC8: Current program Counter bits
@7~@0: Table Pointer TBLP bits
· Table Read Program Example - 1K ROM size
tempreg1 db ?
tempreg2 db ?
:
:
; temporary register #1
; temporary register #2
mov a,06h
; initialise table pointer - note that this address is referenced
mov tblp,a
:
:
; to the last page or present page
tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempregl
; data at prog. memory address ²306H² transferred to tempreg1 and TBLH
dec tblp
; reduce value of table pointer by one
tabrdl
:
:
tempreg2
; transfers value in table referenced by table pointer to tempreg2
; data at prog.memory address ²305H² transferred to tempreg2 and TBLH
; in this example the data ²1AH² is transferred to
; tempreg1 and data ²0FH² to register tempreg2
; the value ²00H² will be transferred to the high byte register TBLH
org 300h
; sets initial address of last page
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev.1.00
14 June 9, 2011
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Data Memory
The Data Memory is a volatile area of 8-bit wide RAM
internal memory and is the location where temporary in-
formation is stored.
Structure
Divided into two sections, the first of these is an area of
RAM where special function registers are located. These
registers have fixed locations and are necessary for cor-
rect operation of the device. Many of these registers can
be read from and written to directly under program con-
trol, however, some remain protected from user manipu-
lation. The second area of Data Memory is reserved for
general purpose use. All locations within this area are
read and write accessible under program control.
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at con-
secutive locations. All are implemented in RAM and are 8
bits wide but the length of each memory section is dic-
tated by the type of microcontroller chosen. The start ad-
dress of the Data Memory for all devices is the address
²00H².
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user pro-
gram for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
0 0 H IA R 0
01H M P 0
0 2 H IA R 1
03H M P 1
S p e c ia l
P u rp o s e
R e g is te r s
3FH
40H
9 6 b y te s
G e n e ra l
P u rp o s e
R e g is te r s
9FH
Data Memory Structure
Note:
Most of the Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits.
The Data Memory can also be accessed
through the memory pointer registers.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writeable but some are protected and are readable only,
the details of which are located under the relevant Spe-
cial Function Register section. Note that for locations
H T 4 6 R 0 1 B -1
H T 4 6 R 0 1 N -1
0 0 H IA R 0
01H M P 0
0 2 H IA R 1
03H M P 1
04H
05H A C C
06H P C L
07H TB LP
08H TB LH
09H W D TS
0A H S TA TU S
0 B H IN T C 0
0C H TM R 0
0D H TM R 0C
0E H TM R 1
0FH TM R 1C
10H P A
11H P A C
12H P A P U
13H P A W K
14H P B
15H P B C
16H P B P U
17H
18H
19H
1A H C TR L0
1B H C TR L1
1C H
1D H
1 E H IN T C 1
1FH P W M 0
20H A D R L
21H A D R H
22H A D C R
23H A C S R
24H
25H
H T 4 8 R 0 1 B -1
H T 4 8 R 0 1 N -1
IA R 0
M P0
IA R 1
M P1
ACC
PCL
TB LP
TB LH
W D TS
STATU S
IN T C 0
TM R 0
TM R 0C
TM R 1
TM R 1C
PA
PAC
PAPU
PAW K
PB
PBC
PBPU
C TR L0
C TR L1
IN T C 1
3FH
: U n u s e d , re a d a s "0 0 "
Special Purpose Data Memory
that are unused, any read instruction to these addresses
will return the value ²00H².
Rev.1.00
15 June 9, 2011
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Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control. The
location of these registers within the Data Memory be-
gins at the address ²00H² and are mapped into Bank 0.
Any unused Data Memory locations between these spe-
cial function registers and the point where the General
Purpose Memory begins is reserved and attempting to
read data from these locations will return a value of
²00H².
Indirect Addressing Registers - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, al-
though having their locations in normal RAM register
space, do not actually physically exist as normal regis-
ters. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory ad-
dressing, where the actual memory address is speci-
fied. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corre-
sponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 with MP0 and IAR1 with MP1 can together ac-
cess data from the Data Memory. As the Indirect Ad-
dressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H² and writing to the registers indi-
rectly will result in no operation.
Memory Pointers - MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are pro-
vided. These Memory Pointers are physically imple-
mented in the Data Memory and can be manipulated in
the same way as normal registers providing a conve-
nient way with which to indirectly address and track
data. When any operation to the relevant Indirect Ad-
dressing Registers is carried out, the actual address that
the microcontroller is directed to, is the address speci-
fied by the related Memory Pointer. The following exam-
ple shows how to clear a section of four Data Memory
locations already defined as locations adres1 to adres4.
Accumulator - ACC
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
· Indirect Addressing Program Example
data .section ¢data¢
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 code
org 00h
start:
mov a,04h
mov block,a
mov a,offset adres1
mov mp0,a
; setup size of block
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
loop:
clr IAR0
inc mp0
sdz block
jmp loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific Data Memory
addresses.
Rev.1.00
16 June 9, 2011
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Program Counter Low Register - PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to pro-
grammers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily imple-
mented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory lo-
cation, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are per-
mitted. When such operations are used, note that a
dummy cycle will be inserted.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system manage-
ment flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, opera-
tions related to the status register may give different re-
sults due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² in-
struction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the interrupt rou-
tine can change the status register, precautions must be
taken to correctly save it. Note that bits 0~3 of the
STATUS register are both readable and writeable bits.
· STATUS Register
Bit
Name
R/W
POR
Bit 7, 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
76543210
¾ ¾ TO PDF OV Z AC C
¾¾
R
R
R/W
R/W
R/W
R/W
¾¾ 0 0 x x x x
²x² unknown
Unimplemented, read as ²0²
TO: Watchdog Time-Out flag
0: After power up or executing the ²CLR WDT² or ²HALT² instruction
1: A watchdog time-out occurred.
PDF: Power down flag
0: After power up or executing the ²CLR WDT² instruction
1: By executing the ²HALT² instruction
OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow from the
high nibble into the low nibble in subtraction
C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not take place
during a subtraction operation
C is also affected by a rotate through carry instruction.
Rev.1.00
17 June 9, 2011
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Input/Output Ports and Control Registers
Within the area of Special Function Registers, the port
PA, PB, etc data I/O registers and their associated con-
trol register PAC, PBC, etc play a prominent role. These
registers are mapped to specific addresses within the
Data Memory as shown in the Data Memory table. The
data I/O registers, are used to transfer the appropriate
output or input data on the port. The control registers
specifies which pins of the port are set as inputs and
which are set as outputs. To setup a pin as an input, the
corresponding bit of the control register must be set
high, for an output it must be set low. During program in-
itialisation, it is important to first setup the control regis-
ters to specify which pins are outputs and which are
inputs before reading data from or writing data to the I/O
ports. One flexible feature of these registers is the ability
to directly program single bits using the ²SET [m].i² and
²CLR [m].i² instructions. The ability to change I/O pins
from output to input and vice versa by manipulating spe-
cific bits of the I/O control registers during normal pro-
gram operation is a useful feature of these devices.
System Control Registers - CTRL0, CTRL1
These registers are used to provide control over various
internal functions. Some of these include the PFD con-
trol, PWM control, certain system clock options, the LXT
Oscillator low power control, external Interrupt edge trig-
ger type, Watchdog Timer enable function, Time Base
function division ratio, and the LXT oscillator enable
control.
Wake-up Function Register - PAWK
When the microcontroller enters the Sleep Mode, vari-
ous methods exist to wake the device up and continue
with normal operation. One method is to allow a falling
edge on the I/O pins to have a wake-up function. This
register is used to select which Port A I/O pins are used
to have this wake-up function.
Pull-high Registers - PAPU, PBPU
The I/O pins, if configured as inputs, can have internal
pull-high resistors connected, which eliminates the need
for external pull-high resistors. This register selects which
I/O pins are connected to internal pull-high resistors.
· CTRL0 Register - HT46R01B-1/HT46R01N-1
Bit
Name
R/W
POR
765
¾ PFDCS PWMSEL
¾
R/W
R/W
¾0
0
4
¾
¾
¾
3
PWMC
R/W
0
2
PFDC
R/W
0
1
LXTLP
R/W
0
0
CLKMOD
R/W
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note:
unimplemented, read as ²0²
PFDCS: PFD clock source selection
0: Timer 0
1: Timer 1
PWMSEL: PWM type selection
0: 6+2 type
1: 7+1 type
unimplemented, read as ²0²
PWMC: I/O or PWM selection
0: I/O or other pin-shared functions
1: PWM
PFDC: I/O or PFD selection
0: I/O
1: PFD
LXTLP: LXT oscillator low power control function
0: LXT oscillator quick start-up mode
1: LXT oscillator low power mode
CLKMOD: system clock mode selection
0: High speed - HIRC oscillator used as system clock
1: Low speed - LXT oscillator used as system clock, HIRC oscillator stopped.
If the PWMn output is selected by the PWMCn bit, the PWM clock source fTP always comes
from the system clock source fSYS. The fTP clock is the clock source for timer0, timer 1, time
base and PWM.
Rev.1.00
18 June 9, 2011
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· CTRL0 Register - HT48R01B-1/HT48R01N-1
Bit
Name
R/W
POR
765
¾ PFDCS ¾
¾ R/W ¾
¾0¾
4
¾
¾
¾
3210
¾
PFDC
LXTLP CLKMOD
¾
R/W
R/W
R/W
¾0 0 0
Bit 7
Bit 6
Bit 5~3
Bit 2
Bit 1
Bit 0
unimplemented, read as ²0²
PFDCS: PFD clock source selection
0: Timer 0
1: Timer 1
unimplemented, read as ²0²
PFDC: I/O or PFD selection
0: I/O
1: PFD
LXTLP: LXT oscillator low power control function
0: LXT oscillator quick start-up mode
1: LXT oscillator low power mode
CLKMOD: system clock mode selection
0: High speed - HIRC oscillator used as system clock
1: Low speed - LXT oscillator used as system clock, HIRC oscillator stopped.
· CTRL1 Register
Bit
Name
R/W
POR
7
INTEG1
R/W
1
6
INTEG0
R/W
0
5
TBSEL1
R/W
0
4
TBSEL0
R/W
0
3
WDTEN3
R/W
1
2
WDTEN2
R/W
0
1
WDTEN1
R/W
1
0
WDTEN0
R/W
0
Bit 7, 6
Bit 5, 4
Bit 3~0
Note:
INTEG1, INTEG0: External interrupt edge type
00: disable
01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
TBSEL1, TBSEL0: Time base period selection
00: 210 ´ (1/fTP)
01: 211 ´ (1/fTP)
10: 212 ´ (1/fTP)
11: 213 ´ (1/fTP)
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
1010: WDT disabled
Other values: WDT enabled - Recommended value is 0101
If the ²watchdog timer enable² configuration option is selected, then the watchdog timer will
always be enabled and the WDTEN3~WDTEN0 control bits will have no effect.
The WDT is only disabled when both the WDT configuration option is disabled and when bits
WDTEN3~WDTEN0=1010.
The WDT is enabled when either the WDT configuration option is enabled or when bits
WDTEN3~WDTEN0¹1010.
Rev.1.00
19
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Oscillator
Various oscillator options offer the user a wide range of
functions according to their various application require-
ments. The flexible features of the oscillator functions
ensure that the best optimisation can be achieved in
terms of speed and power saving. Oscillator selections
and operation are selected through a combination of
configuration options and registers.
System Oscillator Overview
In addition to being the source of the main system clock
the oscillators also provide clock sources for the Watch-
dog Timer and Time Base functions. External oscillators
requiring some external components as well as a two
fully integrated internal oscillators, requiring no external
components, are provided to form a wide range of both
fast and slow system oscillators.
Type
Name Freq. Pins
External Crystal
HXT
400kHz~
12MHz
OSC1
OSC2
External RC
ERC
400kHz~
12MHz
OSC1
Internal High Speed RC HIRC
4, 8 or
12MHz
¾
External Low Speed
Crystal
LXT
32768Hz
OSC1
OSC2
Internal Low Speed RC LIRC 13kHz
¾
Oscillator Types
System Clock Configurations
There are four system oscillators implemented in this
device, three high speed oscillators and one low speed
oscillator. The high speed oscillators are the external
crystal/ceramic oscillator -- HXT, the external RC oscil-
lator -- ERC and the internal RC oscillator -- HIRC. The
low speed oscillator is the external 32.768 kHz crystal
oscillator -- LXT. The LXT oscillator can be used as the
system oscillator only when the HIRC oscillator is se-
lected as the high speed system oscillator for the de-
vices. Also there is an internal 15kHz RC oscillator
named LIRC oscillator used as the clock source for the
C1
O SC1
In te r n a l
O s c illa to r
C ir c u it
Rp Rf
T o in te r n a l
C2
O SC2
c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator - HXT
WDT function. More details are described in the accom-
panying sections.
External Crystal/Resonator Oscillator - HXT
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feed-
back for oscillation. However, for some crystals and
most resonator types, to ensure oscillation and accurate
frequency generation, it is necessary to add two small
value external capacitors, C1 and C2. The exact values
of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer¢s specification.
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
8pF 10pF
8MHz
8pF 10pF
4MHz
8pF 10pF
1MHz
100pF
100pF
Note: C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
External RC Oscillator - ERC
Using the ERC oscillator only requires that a resistor,
with a value between 24kW and 1.5MW, is connected
between OSC1 and VDD, and a capacitor is connected
between OSC and ground, providing a low cost oscilla-
tor configuration. It is only the external resistor that de-
termines the oscillation frequency; the external
capacitor has no influence over the frequency and is
connected for stability purposes only. Device trimming
during the manufacturing process and the inclusion of
internal frequency compensation circuits are used to en-
sure that the influence of the power supply voltage, tem-
perature and process variations on the oscillation
frequency are minimised. Refer to the A.C. Characteris-
tics for more frequency accuracy details. Here only the
OSC1 pin is used, which is shared with I/O pin PA6,
leaving pin PA5 free for use as a normal I/O pin.
V DD
R O SC
470pF
P A 6 /O S C 1
P A 5 /O S C 2
External RC Oscillator - ERC
Rev.1.00
20 June 9, 2011
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Internal RC Oscillator - HIRC
The internal RC oscillator is a fully integrated system os-
cillator requiring no external components. The internal
RC oscillator has three fixed frequencies of either
4MHz, 8MHz or 12MHz. Device trimming during the
manufacturing process and the inclusion of internal fre-
quency compensation circuits are used to ensure that
the influence of the power supply voltage, temperature
and process variations on the oscillation frequency are
minimised. Refer to the A.C. Characteristics for more
frequency accuracy details. Note that if this internal sys-
tem clock option is selected, as it requires no external
pins for its operation, I/O pins PA5 and PA6 are free for
use as normal I/O pins or the LXT oscillator pins de-
pending upon the corresponding system oscillator con-
figuration option.
External 32768Hz Crystal Oscillator - LXT
When the microcontroller enters the Sleep Mode, the
system clock is switched off to stop microcontroller ac-
tivity and to conserve power. However, in many
microcontroller applications it may be necessary to keep
the internal timers operational even when the
microcontroller is in the Power-down Mode. To do this,
another clock, independent of the system clock, must be
provided. To do this a configuration option exists to allow
a high speed oscillator to be used in conjunction with a a
low speed oscillator, known as the LXT oscillator. The
LXT oscillator is implemented using a 32768Hz crystal
connected to pins OSC1/OSC2. However, for some
crystals, to ensure oscillation and accurate frequency
generation, it is necessary to add two small value exter-
nal capacitors, C1 and C2. The exact values of C1 and
C2 should be selected in consultation with the crystal or
resonator manufacturer¢s specification. The external
parallel feedback resistor, RP, is required. For the device
the LXT oscillator must be used together with the HIRC
oscillator.
C1
32768H z
Rp
C2
In te r n a l
O s c illa to r
C ir c u it
In te rn a l R C
O s c illa to r
T o in te r n a l
c ir c u its
N o te : 1 . R p , C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n p in s h a v e a
p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
External LXT Oscillator
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
32768Hz
8pF 10pF
Note: 1. C1 and C2 values are for guidance only.
2. RP=5M~10MW is recommended.
32768Hz Crystal Recommended Capacitor Values
LXT Oscillator Low Power Function
The LXT oscillator can function in one of two modes, the
Quick Start Mode and the Low Power Mode. The mode
selection is executed using the LXTLP bit in the CTRL0
register.
LXTLP Bit
0
1
LXT Mode
Quick Start
Low-power
After power on the LXTLP bit will be automatically
cleared to zero ensuring that the LXT oscillator is in the
Quick Start operating mode. In the Quick Start Mode the
LXT oscillator will power up and stabilise quickly. How-
ever, after the LXT oscillator has fully powered up it can
be placed into the Low-power mode by setting the
LXTLP bit high. The oscillator will continue to run but
with reduced current consumption, as the higher current
consumption is only required during the LXT oscillator
start-up. In power sensitive applications, such as battery
applications, where power consumption must be kept to
a minimum, it is therefore recommended that the appli-
cation program sets the LXTLP bit high about 2 seconds
after power-on.
It should be noted that, no matter what condition the
LXTLP bit is set to, the LXT oscillator will always func-
tion normally, the only difference is that it will take more
time to start up if in the Low-power mode.
Internal Low Speed Oscillator - LIRC
The LIRC is a fully self-contained free running on-chip
RC oscillator with a typical frequency of 15kHz at 5V re-
quiring no external components. When the device en-
ters the Sleep Mode, the system clock will stop running
but the LIRC oscillator continues to free-run and to keep
the watchdog active. However, to preserve power in cer-
tain applications the LIRC can be disabled via a configu-
ration option.
Rev.1.00
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Operating Modes
By using the LXT low frequency oscillator in combina-
tion with a high frequency oscillator, the system can be
selected to operate in a number of different modes.
These Modes are Normal, Slow and Sleep.
Mode Types and Selection
The higher frequency oscillators provide higher perfor-
mance but carry with it the disadvantage of higher
power requirements, while the opposite is of course true
for the lower frequency oscillators. With the capability of
dynamically switching between fast and slow oscillators,
the device has the flexibility to optimise the perfor-
mance/power ratio, a feature especially important in
power sensitive portable applications.
If the LXT oscillator is used then the internal RC oscilla-
tor, HIRC, must be used as the high frequency oscillator.
If the HXT or the ERC oscillator is chosen as the high
frequency system clock then the LXT oscillator cannot
be used for sharing the same pins. The CLKMOD bit in
the CTRL0 register can be used to switch the system
clock from the high speed HIRC oscillator to the low
speed LXT oscillator. When the HALT instruction is exe-
cuted and the device enters the Sleep Mode the LXT os-
cillator will always continue to run. For the device the
LXT crystal is connected to the OSC1/OSC2 pins and
LXT will always run.
Note that CLKMOD is only valid in HIRC+LXT oscillator
configuration.
When the system enters the Sleep Mode, the high fre-
quency system clock will always stop running. The ac-
companying tables shows the relationship between the
CLKMOD bit, the HALT instruction and the high/low fre-
quency oscillators. The CLMOD bit can change normal
or Slow Mode.
Operating
Mode
OSC1/OSC2 Configuration
HXT
HIRC + LXT
ERC HIRC
HIRC LXT
Normal
Run Run Run Run Run
Slow
¾ ¾ ¾ Stop Run
Sleep
Stop Stop Stop Stop Run
²¾² unimplemented
Operating Mode Control
Mode Switching
The devices are switched between one mode and an-
other using a combination of the CLKMOD bit in the
CTRL0 register and the HALT instruction. The CLKMOD
bit chooses whether the system runs in either the Nor-
mal or Slow Mode by selecting the system clock to be
sourced from either a high or low frequency oscillator.
The HALT instruction forces the system into either the
Sleep Mode, depending upon whether the LXT oscilla-
tor is running or not. The HALT instruction operates in-
dependently of the CLKMOD bit condition.
When a HALT instruction is executed and the LXT oscil-
lator is not running, the system enters the Sleep mode
the following conditions exist:
· The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the LIRC
or LXT oscillator. The WDT will stop if its clock source
originates from the system clock.
H X T fH X T
E R C fE R C
H IR C
f H IR C
L X T fL X T
C o n fig u r a tio n o p tio n
C LK M O D
( D e te r m in e N o r m a l/
S lo w M o d e )
( N o r m a l)
M UX
M UX
fS Y S
C o n fig u r a tio n o p tio n
(S L O W )
L IR C
f L IR C
fS Y S /4
M U X T o w a tc h d o g tim e r
System Clock Configurations
Rev.1.00
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· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Standby Current Considerations
As the main reason for entering the Sleep Mode is to
keep the current consumption of the MCU to as low a
value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimised.
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be con-
nected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. Care must also be
taken with the loads, which are connected to I/O pins,
which are setup as outputs. These should be placed in a
condition in which minimum current is drawn or con-
nected only to external circuits that do not draw current,
such as other CMOS inputs.
If the configuration options have enabled the LIRC oscil-
lator, then this will continue to run when in the Idle/Sleep
Mode and will thus consume some power. For power
sensitive applications it may be therefore preferable to
use the system clock source for the Watchdog Timer.
The LXT, if configured for use, will also consume a lim-
ited amount of power, as it continues to run when the de-
vice enters the Sleep Mode. To keep the LXT power
consumption to a minimum level the LXTLP bit in the
CTRL0 register, which controls the low power function,
should be set high.
Wake-up
After the system enters the Sleep Mode, it can be woken
up from one of various sources listed as follows:
· An external reset
· An external falling edge on PA0 to PA7
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the de-
vice will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the ac-
tual source of the wake-up can be determined by exam-
ining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the
²HALT² instruction. The TO flag is set if a WDT time-out
occurs, and causes a wake-up that only resets the Pro-
gram Counter and Stack Pointer, the other flags remain
in their original status.
Pins PA0 to PA7 can be setup via the PAWK register to
permit a negative transition on the pin to wake-up the
system. When a PA0 to PA7 pin wake-up occurs, the pro-
gram will resume execution at the instruction following
the ²HALT² instruction.
If the system is woken up by an interrupt, then two possi-
ble situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume exe-
cution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be ser-
viced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² be-
fore entering the Sleep Mode, then any future interrupt
requests will not generate a wake-up function of the re-
lated interrupt will be ignored.
No matter what the source of the wake-up event is, once
a wake-up event occurs, there will be a time delay be-
fore normal program execution resumes. Consult the ta-
ble for the related time.
Wake-up
Source
External RES
PA Port
Interrupt
WDT Overflow
Oscillator Type
ERC, IRC
Crystal
tRSTD + tSST1
tRSTD + tSST2
tSST1
tSST2
Note:
1. tRSTD (reset delay time), tSYS (system clock)
2. tRSTD is power-on delay, typical time=100ms
3. tSST1= 2 or 128 tSYS
4. tSST2= 128 tSYS
Wake-up Delay Time
Rev.1.00
23
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Watchdog Timer
The Watchdog Timer, also known as the WDT, is pro-
vided to inhibit program malfunctions caused by the pro-
gram jumping to unknown locations due to certain
uncontrollable external events such as electrical noise.
Watchdog Timer Operation
It operates by providing a device reset when the Watch-
dog Timer counter overflows. Note that if the Watchdog
Timer function is not enabled, then any instructions re-
lated to the Watchdog Timer will result in no operation.
Setting up the various Watchdog Timer options are con-
trolled via the configuration options and two internal reg-
isters WDTS and CTRL1. Enabling the Watchdog Timer
can be controlled by both a configuration option and the
WDTEN bits in the CTRL1 internal register in the Data
Memory.
Configuration
Option
Disable
Disable
Enable
CTRL1
Register
Disable
Enable
x
WDT
Function
OFF
ON
ON
Watchdog Timer On/Off Control
The Watchdog Timer will be disabled if bits
WDTEN3~WDTEN0 in the CTRL1 register are written
with the binary value 1010B and WDT configuration op-
tion is disable. This will be the condition when the device
is powered up. Although any other data written to
WDTEN3~WDTEN0 will ensure that the Watchdog
Timer is enabled, for maximum protection it is recom-
mended that the value 0101B is written to these bits.
The Watchdog Timer clock can emanate from three dif-
ferent sources, selected by configuration option. These
are LXT, fSYS/4, or LIRC. It is important to note that when
the system enters the Sleep Mode the instruction clock is
stopped, therefore if the configuration options have se-
lected fSYS/4 as the Watchdog Timer clock source, the
Watchdog Timer will cease to function. For systems that
operate in noisy environments, using the LIRC or the
LXT as the clock source is therefore the recommended
choice. The division ratio of the prescaler is determined
by bits 0, 1 and 2 of the WDTS register, known as WS0,
WS1 and WS2. If the Watchdog Timer internal clock
source is selected and with the WS0, WS1 and WS2 bits
of the WDTS register all set high, the prescaler division
ratio will be 1:128, which will give a maximum time-out
period.
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status bit
TO. However, if the system is in the Sleep Mode, when a
Watchdog Timer time-out occurs, the device will be
woken up, the TO bit in the status register will be set and
only the Program Counter and Stack Pointer will be re-
set. Three methods can be adopted to clear the con-
tents of the Watchdog Timer. The first is an external
hardware reset, which means a low level on the external
reset pin, the second is using the Clear Watchdog Timer
software instructions and the third is when a HALT in-
struction is executed. There are two methods of using
software instructions to clear the Watchdog Timer, one
of which must be chosen by configuration option. The
first option is to use the single ²CLR WDT² instruction
while the second is to use the two commands ²CLR
WDT1² and ²CLR WDT2². For the first option, a simple
execution of ²CLR WDT² will clear the Watchdog Timer
while for the second option, both ²CLR WDT1² and
²CLR WDT2² must both be executed to successfully
clear the Watchdog Timer. Note that for this second op-
tion, if ²CLR WDT1² is used to clear the Watchdog
Timer, successive executions of this instruction will have
no effect, only the execution of a ²CLR WDT2² instruc-
tion will clear the Watchdog Timer. Similarly after the
²CLR WDT2² instruction has been executed, only a suc-
cessive ²CLR WDT1² instruction can clear the Watch-
dog Timer.
C L R W D T 1 F la g
C L R W D T 2 F la g
1 o r 2 In s tr u c tio n s
fS Y S /4
LX T
L IR C
W D T C lo c k S o u r c e S e le c tio n
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
C o n fig .
O p tio n
S e le c t
fW D T C K
C LR
1 5 s ta g e c o u n te r
W S 2~W S 0
Watchdog Timer
W D T T im e - o u t
Rev.1.00
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HT48R01B-1/HT48R01N-1
· WDTS Register
Bit 7 6 5 4 3
Name
¾
¾
¾
¾
¾
R/W
¾
¾
¾
¾
¾
POR
¾
¾
¾
¾
¾
Bit 7~3 :
Bit 2~0
unimplemented, read as ²0²
WS2, WS1, WS0: WDT time-out period selection
000: 28 tWDTCK
001: 29 tWDTCK
010: 210 tWDTCK
011: 211 tWDTCK
100: 212 tWDTCK
101: 213 tWDTCK
110: 214 tWDTCK
111: 215 tWDTCK
2
WS2
R/W
1
1
WS1
R/W
1
0
WS0
R/W
1
Reset and Initialisation
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, af-
ter a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program com-
mences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is force-
fully pulled low. In such a case, known as a normal oper-
ation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of re-
set operations result in different register conditions be-
ing setup.
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is imple-
mented in situations where the power supply voltage
falls below a certain threshold.
Reset Functions
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and ex-
ternally:
· Power-on Reset
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory ad-
dress, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recom-
mended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
VDD
RES
In te rn a l R e s e t
0 .9 V D D
t RR SS TT DD ++ t SS SS TT
Note: tRSTD is power-on delay, typical time=100ms
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected be-
tween VSS and the RES pin will provide a suitable ex-
ternal reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
Rev.1.00
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For applications that operate within an environment
where more noise is present the reset circuit shown is
recommended.
V DD
0 .0 1 m F * *
VDD
1N 4148*
10kW ~
100kW
0 .1 ~ 1 m F
300W *
R E S /P A 7
VSS
Note:
²*² It is recommended that this component is
added for added ESD protection
²**² It is recommended that this component is
added in environments where power line noise
is significant
External RES Circuit
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
· RES Pin Reset
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initi-
ated from this point.
R E S 0 .4 V D D
0 .9 V D D
tR S T D + tS S T
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=100ms
RES Reset Timing Chart
· Low Voltage Reset - LVR
The microcontroller contains a low voltage reset cir-
cuit in order to monitor the supply voltage of the de-
vice. The LVR function is selected via a configuration
option. If the supply voltage of the device drops to
within a range of 0.9V~VLVR such as might occur when
changing the battery, the LVR will automatically reset
the device internally. For a valid LVR signal, a low sup-
ply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that spec-
ified by tLVR in the A.C. characteristics. If the low sup-
ply voltage state does not exceed this value, the LVR
LV R
tR S T D + tS S T
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=100ms
Low Voltage Reset Timing Chart
will ignore the low supply voltage and will not perform
a reset function. The actual VLVR value can be se-
lected via configuration options.
· Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal opera-
tion is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
In te rn a l R e s e t
tR S T D + tS S T
Note: tRSTD is power-on delay, typical time=100ms
WDT Time-out Reset during Normal Operation
Timing Chart
· Watchdog Time-out Reset during Sleep mode
The Watchdog time-out Reset during Sleep mode is a
little different from other kinds of reset. Most of the
conditions remain unchanged except that the Pro-
gram Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
W D T T im e - o u t
tS S T
In te rn a l R e s e t
WDT Time-out Reset during Sleep
Timing Chart
Note:
The tSST can be chosen to be either 128 or 2
clock cycles via configuration option if the sys-
tem clock source is provided by ERC or HIRC.
The SST is 128 for HXT or LXT.
Reset Initial Conditions
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the Sleep
function or Watchdog Timer. The reset flags are shown
in the table:
TO PDF
RESET Conditions
0 0 Power-on reset
u
u
RES or LVR reset during Normal or Slow
Mode operation
1
u
WDT time-out reset during Normal or
Slow Mode operation
1
1
WDT time-out reset during Sleep Mode
operation
Note: ²u² stands for unchanged
Rev.1.00
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HT48R01B-1/HT48R01N-1
The following table indicates the way in which the various components of the microcontroller are affected after a
power-on reset occurs.
Item
Program Counter
Interrupts
WDT
Timer/Event Counter
Prescaler
Input/Output Ports
Stack Pointer
Condition After RESET
Reset to zero
All interrupts will be disabled
Clear after reset, WDT begins counting
Timer Counter will be turned off
The Timer Counter Prescaler will be cleared
I/O ports will be setup as inputs
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers.
HT46R01B-1/HT46R01N-1
Register
PCL
MP0
MP1
ACC
TBLP
Power-on
Reset
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TBLH
WDTS
STATUS
-xxx xxxx
---- -111
--00 xxxx
INTC0
-000 0000
INTC1
TMR0
TMR0C
TMR1
--00 --00
xxxx xxxx
0000 1000
xxxx xxxx
TMR1C
PA
PAC
PAWK
0000 1---
1111 1111
1111 1111
0000 0000
PAPU
-000 0000
PB - - - - - - 1 1
PBC
---- --00
PBPU
CTRL0
CTRL1
PWM
---- --00
-00- 0000
1000 1010
xxxx xxxx
RES or LVR
Reset
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- -111
--uu uuuu
-000 0000
--00 --00
xxxx xxxx
0000 1000
xxxx xxxx
0000 1---
1111 1111
1111 1111
0000 0000
-000 0000
---- --11
---- --00
---- --00
-00- 0000
1000 1010
xxxx xxxx
WDT Time-out
(Normal Operation)
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- -111
--1u uuuu
-000 0000
--00 --00
xxxx xxxx
0000 1000
xxxx xxxx
0000 1---
1111 1111
1111 1111
0000 0000
-000 0000
---- --11
---- --00
---- --00
-00- 0000
1000 1010
xxxx xxxx
WDT Time-out
(HALT)
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- -uuu
--11 uuuu
-uuu uuuu
--uu --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u---
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- --uu
---- --uu
---- --uu
-uu- uuuu
uuuu uuuu
uuuu uuuu
Rev.1.00
27 June 9, 2011
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Register
ADRL
ADRH
ADCR
ACSR
Power-on
Reset
xxxx ----
xxxx xxxx
0100 0000
10-- -000
Note:
²-² not implemented
²u² means ²unchanged²
²x² means ²unknown²
HT48R01B-1/HT48R01N-1
Register
PCL
MP0
MP1
ACC
TBLP
Power-on
Reset
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
TBLH
-xxx xxxx
WDTS
STATUS
INTC0
---- -111
--00 xxxx
-000 0000
INTC1
TMR0
TMR0C
TMR1
--00 --00
xxxx xxxx
0000 1000
xxxx xxxx
TMR1C
PA
PAC
PAWK
0000 1---
1111 1111
1111 1111
0000 0000
PAPU
-000 0000
PB - - - - - - 1 1
PBC
---- --00
PBPU
---- --00
CTRL0
CTRL1
-0-- -000
1000 1010
Note:
²-² not implemented
²u² means ²unchanged²
²x² means ²unknown²
HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
RES or LVR
Reset
xxxx ----
xxxx xxxx
0100 0000
10-- -000
WDT Time-out
(Normal Operation)
xxxx ----
xxxx xxxx
0100 0000
10-- -000
WDT Time-out
(HALT)
uuuu ----
uuuu uuuu
uuuu uuuu
uu-- -uuu
RES or LVR
Reset
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- -111
--uu uuuu
-000 0000
--00 --00
xxxx xxxx
0000 1000
xxxx xxxx
0000 1---
1111 1111
1111 1111
0000 0000
-000 0000
---- --11
---- --00
---- --00
-0-- -000
1000 1010
WDT Time-out
(Normal Operation)
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- -111
--1u uuuu
-000 0000
--00 --00
xxxx xxxx
0000 1000
xxxx xxxx
0000 1---
1111 1111
1111 1111
0000 0000
-000 0000
---- --11
---- --00
---- --00
-0-- -000
1000 1010
WDT Time-out
(HALT)
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- -uuu
--11 uuuu
-uuu uuuu
--uu --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u---
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- --uu
---- --uu
---- --uu
-u-- -uuu
uuuu uuuu
Rev.1.00
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HT48R01B-1/HT48R01N-1
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. Most pins can have either an input or out-
put designation under user program control. Addi-
tionally, as there are pull-high resistors and wake-up
software configurations, the user is provided with an I/O
structure to meet the needs of a wide range of applica-
tion possibilities.
For input operation, these ports are non-latching, which
means the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]², where m denotes the port ad-
dress. For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external
resistor. To eliminate the need for these external resis-
tors, when configured as an input have the capability of
being connected to an internal pull-high resistor. These
pull-high resistors are selectable via a register known as
PAPU located in the Data Memory. The pull-high resis-
tors are implemented using weak PMOS transistors.
Note that pin PA7 does not have a pull-high resistor se-
lection.
Port A Wake-up
If the HALT instruction is executed, the device will enter
the Sleep Mode, where the system clock will stop result-
ing in power being conserved, a feature that is important
for battery and other low-power applications. Various
methods exist to wake-up the microcontroller, one of
which is to change the logic condition on one of the
PA0~PA7 pins from high to low. After a HALT instruction
forces the microcontroller into entering the Sleep Mode,
the processor will remain in a low-power state until the
logic condition of the selected wake-up pin on Port A
changes from high to low. This function is especially suit-
able for applications that can be woken up via external
switches. Note that pins PA0 to PA7 can be selected indi-
vidually to have this wake-up feature using an internal
register known as PAWK, located in the Data Memory.
· I/O Port Register Lists
Register
Name
PAWK
PAC
PAPU
PBC
PBPU
POR
00H
FFH
00H
0FH
00H
7
PAWK7
PAC7
¾
¾
¾
6
PAWK6
PAC6
PAPU6
¾
¾
5
PAWK5
PAC5
PAPU5
¾
¾
Bit
43
PAWK4 PAWK3
PAC4 PAC3
PAPU4 PAPU3
¾¾
¾¾
2
PAWK2
PAC2
PAPU2
¾
¾
1
PAWK1
PAC1
PAPU1
PBC1
PBPU1
0
PAWK0
PAC0
PAPU0
PBC0
PBPU0
²¾² Unimplemented, read as ²0²
PAWKn: PA wake-up function enable
0: disable
1: enable
PACn/PBCn: I/O type selection
0: output
1: input
PAPUn/PBPUn: Pull-high function enable
0: disable
1: enable
Rev.1.00
29
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I/O Port Control Registers
Each Port has its own control register, known as PAC,
PBC, which controls the input/output configuration. With
this control register, each I/O pin with or without
pull-high resistors can be reconfigured dynamically un-
der software control. For the I/O pin to function as an in-
put, the corresponding bit of the control register must be
written as a ²1². This will then allow the logic state of the
input pin to be directly read by instructions. When the
corresponding bit of the control register is written as a
²0², the I/O pin will be setup as a CMOS output. If the pin
is currently setup as an output, instructions can still be
used to read the output register. However, it should be
noted that the program will in fact only read the status of
the output data latch and not the actual logic status of
the output pin.
Pin-shared Functions
The flexibility of the microcontroller range is greatly en-
hanced by the use of pins that have more than one func-
tion. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be over-
come. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application pro-
gram control.
· External Interrupt Input
The external interrupt pin, INT, is pin-shared with an
I/O pin. To use the pin as an external interrupt input
the correct bits in the INTC0 register must be pro-
grammed. The pin must also be setup as an input by
setting the PAC3 bit in the Port Control Register. A
pull-high resistor can also be selected via the appro-
priate port pull-high resistor register. Note that even if
the pin is setup as an external interrupt input the I/O
function still remains.
· External Timer/Event Counter Input
The Timer/Event Counter pins, TC0 and TC1 are
pin-shared with I/O pins. For these shared pins to be
used as Timer/Event Counter inputs, the Timer/Event
Counter must be configured to be in the Event Coun-
ter or Pulse Width Capture Mode. This is achieved by
setting the appropriate bits in the Timer/Event Counter
Control Register. The pins must also be setup as in-
puts by setting the appropriate bit in the Port Control
Register. Pull-high resistor options can also be se-
lected using the port pull-high resistor registers. Note
that even if the pin is setup as an external timer input
the I/O function still remains.
· PFD Output
The PFD function output is pin-shared with an I/O pin.
The output function of this pin is chosen using the
CTRL0 register. Note that the corresponding bit of the
port control register, must setup the pin as an output
to enable the PFD output. If the port control register
has setup the pin as an input, then the pin will function
as a normal logic input with the usual pull-high selec-
tion, even if the PFD function has been selected.
· PWM Outputs
For the HT46R01B-1 and HT46R01N-1 devices the
PWM function is included. The PWM function whose
outputs are pin-shared with I/O pins. The PWM output
functions are chosen using the CTRL0 register. Note
that the corresponding bit of the port control registers,
for the output pin, must setup the pin as an output to
enable the PWM output. If the pins are setup as in-
puts, then the pin will function as a normal logic input
with the usual pull-high selections, even if the PWM
registers have enabled the PWM function.
· A/D Inputs
The HT46R01B-1 and HT46R01N-1 devices have
four inputs to the A/D converter. All of these analog in-
puts are pin-shared with I/O pins. If these pins are to
be used as A/D inputs and not as I/O pins, then the
corresponding PCRn bits in the A/D converter control
register, PCR or ANCSR, must be properly setup.
There are no configuration options associated with
the A/D converter. If chosen as I/O pins, then full
pull-high resistor control remains, however if used as
A/D inputs then any pull-high resistor control associ-
ated with these pins will be automatically discon-
nected.
Rev.1.00
30
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