DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
© 2011 Microchip Technology Inc.
DS70292E


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-820-7
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70292E-page 2
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, AND
dsPIC33FJ128GPX02/X04
High-Performance, 16-Bit Digital Signal Controllers
Operating Range:
• Up to 40 MIPS operation (at 3.0-3.6V):
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
• Up to 20 MIPS operation (at 3.0-3.6V):
- High temperature range (-40°C to +150°C)
High-Performance DSC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
• 24-bit wide instructions
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 83 base instructions: mostly 1 word/1 cycle
• Two 40-bit accumulators with rounding and
saturation options
• Flexible and powerful addressing modes:
- Indirect
- Modulo
- Bit-Reversed
• Software stack
• 16 x 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
• Up to ±16-bit shifts for up to 40-bit data
Direct Memory Access (DMA):
• 8-channel hardware DMA
• Up to 2 Kbytes dual ported DMA buffer area (DMA
RAM) to store data transferred via DMA:
- Allows data transfer between RAM and a
peripheral while CPU is executing code (no
cycle stealing)
• Most peripherals support DMA
Timers/Capture/Compare/PWM:
• Timer/Counters, up to five 16-bit timers:
- Can pair up to make two 32-bit timers
- One timer runs as a Real-Time Clock with an
external 32.768 kHz oscillator
- Programmable prescaler
• Input Capture (up to four channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to four channels):
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM mode
• Hardware Real-Time Clock/Calendar (RTCC):
- Provides clock, calendar and alarm functions
Interrupt Controller:
• 5-cycle latency
• Up to 49 available interrupt sources
• Up to three external interrupts
• Seven programmable priority levels
• Five processor exceptions
Digital I/O:
• Peripheral pin Select functionality
• Up to 35 programmable digital I/O pins
• Wake-up/Interrupt-on-Change for up to 31 pins
• Output pins can drive from 3.0V to 3.6V
• Up to 5.5V output with open drain configuration on
5V tolerant pins with external pull-up
• 4 mA sink on all I/O pins
On-Chip Flash and SRAM:
• Flash program memory (up to 128 Kbytes)
• Data SRAM (up to 16 Kbytes)
• Boot, Secure and General Security for program
Flash
© 2011 Microchip Technology Inc.
DS70292E-page 3


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep, and Doze modes with fast wake-up
Analog-to-Digital Converters (ADCs):
• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:
- Two and four simultaneous samples (10-bit ADC)
- Up to 13 input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
Audio Digital-to-Analog Converter (DAC):
• 16-bit Dual Channel DAC module
• 100 ksps maximum sampling rate
• Second-Order Digital Delta-Sigma Modulator
Data Converter Interface (DCI) module:
• Codec interface
• Supports I2S and AC’97 protocols
• Up to 16-bit data words, up to 16 words per frame
• 4-word deep TX and RX buffers
Comparator Module:
• Two analog comparators with programmable
input/output configuration
CMOS Flash Technology:
• Low-power, high-speed Flash technology
• Fully static design
• 3.3V (±10%) operating voltage
• Industrial and Extended temperature
• Low power consumption
Communication Modules:
• 4-wire SPI (up to two modules):
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
• I2C™:
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
• UART (up to two modules):
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN 2.0 bus support
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
• Enhanced CAN (ECAN™ module) 2.0B active:
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and three masks
- Loopback, Listen Only and Listen All
- Messages modes for diagnostics and bus
monitoring
- Wake-up on CAN message
- Automatic processing of Remote
Transmission Requests
- FIFO mode using DMA
- DeviceNet™ addressing support
• Parallel Master Slave Port (PMP/EPSP):
- Supports 8-bit or 16-bit data
- Supports 16 address lines
• Programmable Cyclic Redundancy Check (CRC):
- Programmable bit length for the CRC
generator polynomial (up to 16-bit length)
- 8-deep, 16-bit or 16-deep, 8-bit FIFO for data
input
Packaging:
• 28-pin SDIP/SOIC/QFN-S
• 44-pin TQFP/QFN
Note: See the device variant tables for exact
peripheral features per device.
DS70292E-page 4
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, AND
dsPIC33FJ128GPX02/X04 PRODUCT
FAMILIES
The device names, pin counts, memory sizes, and
peripheral availability of each device are listed below.
The following pages show their pinout diagrams.
TABLE 1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
CONTROLLER FAMILIES
Remappable Peripheral
Device
dsPIC33FJ128GP804 44 128 16 26 5 4 4
1 2 2 1 3 1 1 1 13 6 1/1 11 35 QFN
TQFP
dsPIC33FJ128GP802 28 128 16 16 5 4 4
1 2 2 1 3 1 1 1 10 4 1/0
2 21 SDIP
SOIC
QFN-S
dsPIC33FJ128GP204 44 128 8 26 5 4 4
1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN
TQFP
dsPIC33FJ128GP202 28 128 8 16 5 4 4
1 2 2 0 3 1 1 1 10 0 1/0
2 21 SDIP
SOIC
QFN-S
dsPIC33FJ64GP804 44 64 16 26 5 4 4
1 2 2 1 3 1 1 1 13 6 1/1 11 35 QFN
TQFP
dsPIC33FJ64GP802 28 64 16 16 5 4 4
1 2 2 1 3 1 1 1 10 4 1/0
2 21 SDIP
SOIC
QFN-S
dsPIC33FJ64GP204 44 64 8 26 5 4 4
1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN
TQFP
dsPIC33FJ64GP202 28 64 8 16 5 4 4
1 2 2 0 3 1 1 1 10 0 1/0
2 21 SDIP
SOIC
QFN-S
dsPIC33FJ32GP304 44 32 4 26 5 4 4
1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN
TQFP
dsPIC33FJ32GP302 28 32 4 16 5 4 4
1 2 2 0 3 1 1 1 10 0 1/0
2 21 SDIP
SOIC
QFN-S
Note 1:
2:
3:
RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except dsPIC33FJ32GP302/304, which include 1 Kbyte of DMA RAM.
Only four out of five timers are remappable.
Only two out of three interrupts are remappable.
© 2011 Microchip Technology Inc.
DS70292E-page 5


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagrams
28-Pin SDIP, SOIC
= Pins are up to 5V tolerant
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/PMA0/RA3
SOSCI/RP4(1)/CN1/PMBE/RB4
SOSCO/T1CK/CN0/PMA1/RA4
VDD
PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 AVDD
27 AVSS
26 AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15
25 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14
24 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
23 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
22 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11
21 PGED2/TDI/RP10(1)/CN16/PMD2/RB10
20 VCAP
19 VSS
18 TDO/SDA1/RP9(1)/CN21/PMD3/RB9
17 TCK/SCL1/RP8(1)/CN22/PMD4/RB8
16 INT0/RP7(1)/CN23/PMD5/RB7
15 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6
28-Pin SDIP, SOIC
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/PMA0/RA3
SOSCI/RP4(1)/CN1/PMBE/RB4
SOSCO/T1CK/CN0/PMA1/RA4
VDD
PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
= Pins are up to 5V tolerant
28 AVDD
27 AVSS
26 AN9/RP15(1)/CN11/PMCS1/RB15
25 AN10/RTCC/RP14(1)/CN12/PMWR/RB14
24 AN11/RP13(1)/CN13/PMRD/RB13
23 AN12/RP12(1)/CN14/PMD0/RB12
22 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11
21 PGED2/TDI/RP10(1)/CN16/PMD2/RB10
20 VCAP
19 VSS
18 TDO/SDA1/RP9(1)/CN21/PMD3/RB9
17 TCK/SCL1/RP8(1)/CN22/PMD4/RB8
16 INT0/RP7(1)/CN23/PMD5/RB7
15 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6
Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals.
DS70292E-page 6
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagrams (Continued)
28-Pin QFN-S(2)
= Pins are up to 5V tolerant
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/PMA0/RA3
1 21
2 20
3 dsPIC33FJ64GP802 19
4 dsPIC33FJ128GP802 18
5 17
6 16
7 15
AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
PGEC2/TMS/RP11(1)/CN15/PMD1/RB11
PGED2/TDI/RP10(1)/CN16/PMD2/RB10
VCAP
VSS
TDO/SDA1/RP9(1)/CN21/PMD3/RB9
Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
© 2011 Microchip Technology Inc.
DS70292E-page 7


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagrams (Continued)
28-Pin QFN-S(2)
= Pins are up to 5V tolerant
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/PMA0/RA3
1 21
2 20
3 dsPIC33FJ32GP302 19
4 dsPIC33FJ64GP202 18
5 dsPIC33FJ128GP202 17
6 16
7 15
AN11/RP13(1)/CN13/PMRD/RB13
AN12/RP12(1)/CN14/PMD0/RB12
PGEC2/TMS/RP11(1)/CN15/PMD1/RB11
PGED2/TDI/RP10(1)/CN16/PMD2/RB10
VCAP
VSS
TDO/SDA1/RP9(1)/CN21/PMD3/RB9
Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS70292E-page 8
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagrams (Continued)
44-Pin QFN(2)
= Pins are up to 5V tolerant
AN4/C1IN-/RP2(1)/CN6/RB2 23
11 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
AN5/C1IN+/RP3(1)/CN7/RB3 24
10 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
AN6/DAC1RM/RP16(1)/CN8/RC0 25
9 PGEC2/RP11(1)/CN15/PMD1/RB11
AN7/DAC1LM/RP17(1)/CN9/RC1 26
8 PGED2/RP10(1)/CN16/PMD2/RB10
AN8/CVREF/RP18(1)/PMA2/CN10/RC2
VDD
27
28
dsPIC33FJ64GP804
7 VCAP
6 VSS
VSS 29 dsPIC33FJ128GP804 5 RP25(1)/CN19/PMA6/RC9
OSC1/CLKI/CN30/RA2 30
4 RP24(1)/CN20/PMA5/RC8
OSC2/CLKO/CN29/RA3 31
3 RP23(1)/CN17/PMA0/RC7
TDO/PMA8/RA8 32
2 RP22(1)/CN18/PMA1/RC6
SOSCI/RP4(1)/CN1/RB4 33
1 SDA1/RP9(1)/CN21/PMD3/RB9
Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
© 2011 Microchip Technology Inc.
DS70292E-page 9


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagrams (Continued)
44-Pin QFN(2)
= Pins are up to 5V tolerant
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
AN6/RP16(1)/CN8/RC0
AN7/RP17(1)/CN9/RC1
AN8/CVREF/RP18(1)/PMA2/CN10/RC2
23
24
25
26
27
11 AN11/RP13(1)/CN13/PMRD/RB13
10 AN12/RP12(1)/CN14/PMD0/RB12
9 PGEC2/RP11(1)/CN15/PMD1/RB11
8 PGED2/RP10(1)/CN16/PMD2/RB10
dsPIC33FJ32GP304 7 VCAP
VDD 28 dsPIC33FJ64GP204 6 VSS
VSS 29 dsPIC33FJ128GP204 5 RP25(1)/CN19/PMA6/RC9
OSC1/CLKI/CN30/RA2 30
4 RP24(1)/CN20/PMA5/RC8
OSC2/CLKO/CN29/RA3 31
3 RP23(1)/CN17/PMA0/RC7
TDO/PMA8/RA8 32
2 RP22(1)/CN18/PMA1/RC6
SOSCI/RP4(1)/CN1/RB4 33
1 SDA1/RP9(1)/CN21/PMD3/RB9
Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS70292E-page 10
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagram
44-Pin TQFP
= Pins are up to 5V tolerant
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
AN6/DAC1RM/RP16(1)/CN8/RC0
AN7/DAC1LM/RP17/(1)/CN9/RC1
AN8/CVREF/RP18(1)/PMA2/CN10/RC2
VDD
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
TDO/PMA8/RA8
SOSCI/RP4(1)/CN1/RB4
23 11
24 10
25 9
26 8
27 dsPIC33FJ64GP804 7
28
29
dsPIC33FJ128GP804
6
5
30 4
31 3
32 2
33 1
AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
PGEC2/RP11(1)/CN15/PMD1/RB11
PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10
VCAP
VSS
RP25(1)/CN19/PMA6/RC9
RP24(1)/CN20/PMA5/RC8
RP23(1)/CN17/PMA0/RC7
RP22(1)/CN18/PMA1/RC6
SDA1/RP9(1)/CN21/PMD3/RB9
Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals.
© 2011 Microchip Technology Inc.
DS70292E-page 11


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagram
44-Pin TQFP
= Pins are up to 5V tolerant
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
AN6/RP16(1)/CN8/RC0
AN7/RP17(1)/CN9/RC1
AN8/CVREF/RP18(1)/PMA2/CN10/RC2
VDD
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
TDO/PMA8/RA8
SOSCI/RP4(1)/CN1/RB4
23 11
24 10
25 9
26 8
27 dsPIC33FJ32GP304 7
28 dsPIC33FJ64GP204 6
29
30
dsPIC33FJ128GP204
5
4
31 3
32 2
33 1
AN11/RP13(1)/CN13/PMRD/RB13
AN12/RP12(1)/CN14/PMD0/RB12
PGEC2/RP11(1)/CN15/PMD1/RB11
PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10
VCAP
VSS
RP25(1)/CN19/PMA6/RC9
RP24(1)/CN20/PMA5/RC8
RP23(1)/CN17/PMA0/RC7
RP22(1)/CN18/PMA1/RC6
SDA1/RP9(1)/CN21/PMD3/RB9
Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals.
DS70292E-page 12
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Table of Contents
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Product Families............................................. 5
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 21
3.0 CPU............................................................................................................................................................................................ 25
4.0 Memory Organization ................................................................................................................................................................. 37
5.0 Flash Program Memory.............................................................................................................................................................. 73
6.0 Resets ....................................................................................................................................................................................... 79
7.0 Interrupt Controller ..................................................................................................................................................................... 87
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 129
9.0 Oscillator Configuration ............................................................................................................................................................ 141
10.0 Power-Saving Features............................................................................................................................................................ 153
11.0 I/O Ports ................................................................................................................................................................................... 159
12.0 Timer1 ...................................................................................................................................................................................... 187
13.0 Timer2/3 and Timer4/5 Feature ............................................................................................................................................... 189
14.0 Input Capture............................................................................................................................................................................ 195
15.0 Output Compare....................................................................................................................................................................... 197
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 201
17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 207
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 215
19.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 221
20.0 Data Converter Interface (DCI) Module.................................................................................................................................... 247
21.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 253
22.0 Audio Digital-to-Analog Converter (DAC)................................................................................................................................. 265
23.0 Comparator Module.................................................................................................................................................................. 271
24.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 277
25.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 287
26.0 Parallel Master Port (PMP)....................................................................................................................................................... 291
27.0 Special Features ...................................................................................................................................................................... 299
28.0 Instruction Set Summary .......................................................................................................................................................... 309
29.0 Development Support............................................................................................................................................................... 317
30.0 Electrical Characteristics .......................................................................................................................................................... 321
31.0 High Temperature Electrical Characteristics ............................................................................................................................ 375
32.0 Packaging Information.............................................................................................................................................................. 385
Appendix A: Revision History............................................................................................................................................................. 395
Index .................................................................................................................................................................................................. 403
The Microchip Web Site ..................................................................................................................................................................... 409
Customer Change Notification Service .............................................................................................................................................. 409
Customer Support .............................................................................................................................................................................. 409
Reader Response .............................................................................................................................................................................. 410
Product Identification System ............................................................................................................................................................ 411
© 2011 Microchip Technology Inc.
DS70292E-page 13


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS70292E-page 14
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
1.0 DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04,
and
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to the “dsPIC33F/PIC24H Family
Reference Manual”. Please see the
Microchip web site (www.microchip.com)
for the latest dsPIC33F/PIC24H Family
Reference Manual sections.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
This document contains device specific information for
the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 Digital Signal
Controller (DSC) Devices. The dsPIC33F devices
contain extensive Digital Signal Processor (DSP)
functionality with a high performance 16-bit
microcontroller (MCU) architecture.
Figure 1-1 shows a general block diagram of the
core and peripheral modules in the
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 families of devices.
Table 1-1 lists the functions of the various pins
shown in the pinout diagrams.
© 2011 Microchip Technology Inc.
DS70292E-page 15


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 1-1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Interrupt
Controller
23
23
23
8 16
PCU PCH PCL
Program Counter
Stack
Control
Logic
Loop
Control
Logic
Y Data Bus
X Data Bus
16
16
Data Latch
16
Data Latch
X RAM
Address
Latch
Y RAM
Address
Latch
16 16
DMA
RAM
PORTA
PORTB
DMA
Controller
16
PORTC
Address Latch
Address Generator Units
Program Memory
Data Latch
24
ROM Latch
EA MUX
16 16
Remappable
Pins
Instruction
Decode and
Control
Control Signals
to Various Blocks
OSC2/CLKO Timing
OSC1/CLKI Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Instruction Reg
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-bit ALU
16
VCAP
VDD, VSS MCLR
PMP/
EPSP
Comparator
2 Ch.
ECAN1
Timers
1-5
UART1, 2
ADC1
OC/
PWM1-4
RTCC
DAC1
SPI1, 2 IC1, 2, 7, 8
CNx
I2C1
DCI
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features pres-
ent on each device.
DS70292E-page 16
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Type
Buffer
Type
PPS
Description
AN0-AN12
CLKI
CLKO
OSC1
OSC2
SOSCI
SOSCO
CN0-CN30
IC1-IC2
IC7-IC8
OCFA
OC1-OC4
I Analog
Analog input channels.
I ST/CMOS No External clock source input. Always associated with OSC1 pin
function.
O — No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
I ST/CMOS No Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
I/O — No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
I ST/CMOS No 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
O — No 32.768 kHz low-power oscillator crystal output.
I ST No Change notification inputs.
No Can be software programmed for internal weak pull-ups on all inputs.
I ST Yes Capture inputs 1/2.
I ST Yes Capture inputs 7/8.
I ST Yes Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
O — Yes Compare outputs 1 through 4.
INT0
INT1
INT2
I ST No External interrupt 0.
I ST Yes External interrupt 1.
I ST Yes External interrupt 2.
RA0-RA4
RA7-RA10
RB0-RB15
RC0-RC9
T1CK
T2CK
T3CK
T4CK
T5CK
I/O ST No PORTA is a bidirectional I/O port.
I/O ST No PORTA is a bidirectional I/O port.
I/O ST No PORTB is a bidirectional I/O port.
I/O ST No PORTC is a bidirectional I/O port.
I ST No Timer1 external clock input.
I ST Yes Timer2 external clock input.
I ST Yes Timer3 external clock input.
I ST Yes Timer4 external clock input.
I ST Yes Timer5 external clock input.
U1CTS
U1RTS
U1RX
U1TX
I ST Yes UART1 clear to send.
O — Yes UART1 ready to send.
I ST Yes UART1 receive.
O — Yes UART1 transmit.
U2CTS
U2RTS
U2RX
U2TX
I ST Yes UART2 clear to send.
O — Yes UART2 ready to send.
I ST Yes UART2 receive.
O — Yes UART2 transmit.
SCK1
SDI1
SDO1
SS1
I/O ST Yes Synchronous serial clock input/output for SPI1.
I ST Yes SPI1 data in.
O — Yes SPI1 data out.
I/O ST Yes SPI1 slave synchronization or frame pulse I/O.
SCK2
SDI2
SDO2
SS2
I/O ST Yes Synchronous serial clock input/output for SPI2.
I ST Yes SPI2 data in.
O — Yes SPI2 data out.
I/O ST Yes SPI2 slave synchronization or frame pulse I/O.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
© 2011 Microchip Technology Inc.
DS70292E-page 17


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS
Description
SCL1
SDA1
ASCL1
ASDA1
I/O ST No Synchronous serial clock input/output for I2C1.
I/O ST No Synchronous serial data input/output for I2C1.
I/O ST No Alternate synchronous serial clock input/output for I2C1.
I/O ST No Alternate synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
C1RX
C1TX
I ST No JTAG Test mode select pin.
I ST No JTAG test clock input pin.
I ST No JTAG test data input pin.
O — No JTAG test data output pin.
I ST Yes ECAN1 bus receive pin.
O — Yes ECAN1 bus transmit pin.
RTCC
O — No Real-Time Clock Alarm Output.
CVREF
O
ANA
No Comparator Voltage Reference Output.
C1IN-
C1IN+
C1OUT
I
ANA
No Comparator 1 Negative Input.
I
ANA
No Comparator 1 Positive Input.
O — Yes Comparator 1 Output.
C2IN-
C2IN+
C2OUT
I
ANA
No Comparator 2 Negative Input.
I
ANA
No Comparator 2 Positive Input.
O — Yes Comparator 2 Output.
PMA0
I/O
PMA1
I/O
PMA2 -PMPA10
PMBE
PMCS1
PMD0-PMPD7
O
O
O
I/O
PMRD
PMWR
O
O
TTL/ST
TTL/ST
TTL/ST
No Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and
Output (Master modes).
No Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and
Output (Master modes).
No Parallel Master Port Address (Demultiplexed Master Modes).
No Parallel Master Port Byte Enable Strobe.
No Parallel Master Port Chip Select 1 Strobe.
No Parallel Master Port Data (Demultiplexed Master mode) or Address/
Data (Multiplexed Master modes).
No Parallel Master Port Read Strobe.
No Parallel Master Port Write Strobe.
DAC1RN
DAC1RP
DAC1RM
O — No DAC1 Right Channel Negative Output.
O — No DAC1 Right Channel Positive Output.
O — No DAC1 Right Channel Middle Point Value (typically 1.65V).
DAC1LN
DAC1LP
DAC1LM
O — No DAC1 Left Channel Negative Output.
O — No DAC1 Left Channel Positive Output.
O — No DAC1 Left Channel Middle Point Value (typically 1.65V).
COFS
I/O ST Yes Data Converter Interface frame synchronization pin.
CSCK
CSDI
I/O ST Yes Data Converter Interface serial clock input/output pin.
I ST Yes Data Converter Interface serial data input pin
CSDO
O — Yes Data Converter Interface serial data output pin.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O ST No Data I/O pin for programming/debugging communication channel 1.
I ST No Clock input pin for programming/debugging communication channel 1.
I/O ST No Data I/O pin for programming/debugging communication channel 2.
I ST No Clock input pin for programming/debugging communication channel 2.
I/O ST No Data I/O pin for programming/debugging communication channel 3.
I ST No Clock input pin for programming/debugging communication channel 3.
MCLR
I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD
P P No Positive supply for analog modules. This pin must be connected at all
times.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
DS70292E-page 18
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS
Description
AVSS
VDD
VCAP
P P No Ground reference for analog modules.
P — No Positive supply for peripheral logic and I/O pins.
P — No CPU logic filter capacitor connection.
Vss P — No Ground reference for logic and I/O pins.
VREF+
I Analog No Analog voltage reference (high) input.
VREF-
I Analog No Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input P = Power
O = Output
I = Input
PPS = Peripheral Pin Select
© 2011 Microchip Technology Inc.
DS70292E-page 19


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292E-page 20
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
2.0 GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04,
and
dsPIC33FJ128GPX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
2.1 Basic Connection Requirements
Getting started with the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 family of 16-bit Digital Signal Controllers (DSCs)
requires attention to a minimal set of device pin
connections before proceeding with development. The
following is a list of pin names, which must always be
connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
2.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
© 2011 Microchip Technology Inc.
DS70292E-page 21


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
VDD
10 µF
Tantalum
R
R1
MCLR
C
0.1 µF
Ceramic
VSS
VDD
dsPIC33F
10 Ω
0.1 µF
Ceramic
0.1 µF
Ceramic
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
2.2.1 TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device, and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3 CPU Logic Filter Capacitor
Connection (VCAP)
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a capacitor between
4.7 µF and 10 µF, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 30.0
“Electrical Characteristics” for additional
information.
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 27.2
“On-Chip Voltage Regulator” for details.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R
R1
MCLR
JP dsPIC33F
C
Note 1:
2:
R 10 kΩ is recommended. A suggested
starting value is 10 kΩ. Ensure that the
MCLR pin VIH and VIL specifications are met.
R1 470Ω will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
DS70292E-page 22
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™.
For more information on ICD 2, ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip website.
“MPLAB® ICD 2 In-Circuit Debugger User’s
Guide” DS51331
“Using MPLAB® ICD 2” (poster) DS51265
“MPLAB® ICD 2 Design Advisory” DS51566
“Using MPLAB® ICD 3 In-Circuit Debugger”
(poster) DS51765
“MPLAB® ICD 3 Design Advisory” DS51764
“MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
“Using MPLAB® REAL ICE™” (poster) DS51749
2.6 External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
Guard Ring
Guard Trace
Secondary
Oscillator
13
14
15
16
17
18
19
20
© 2011 Microchip Technology Inc.
DS70292E-page 23


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
2.7 Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 8 MHz for start-up with the PLL enabled to comply
with device PLL start-up conditions. This means that if
the external oscillator frequency is outside this range,
the application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8 Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the A/D input
pins (ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3 or REAL
ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the AD1PCFGL register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic ‘0’, which may affect user application
functionality.
2.9 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor between VSS
and the unused pin.
DS70292E-page 24
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
3.0 CPU
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04,
and
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 2. CPU” (DS70204) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
3.1 Overview
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any time.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The 16th
working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1, and
the programmer’s model for the dsPIC33FJ32GP302/
304, dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04 is shown in Figure 3-2.
3.2 Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
3.3 DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal real-
time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
© 2011 Microchip Technology Inc.
DS70292E-page 25


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
3.4 Special MCU Features
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 features a 17-bit
by 17-bit single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can per-
form signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 supports 16/16
and 32/16 divide operations, both fractional and inte-
ger. All divide instructions are iterative operations. They
must be executed within a REPEAT loop, resulting in a
total execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Interrupt
Controller
23
23
23
Address Latch
8 16
PCU PCH PCL
Program Counter
Stack
Control
Logic
Loop
Control
Logic
Y Data Bus
X Data Bus
16 16 16
Data Latch Data Latch
X RAM
Address
Latch
Y RAM
Address
Latch
16 16
Address Generator Units
DMA
RAM
DMA
Controller
Program Memory
Data Latch
24
Instruction
Decode and
Control
Control Signals
to Various Blocks
ROM Latch
EA MUX
16 16
Instruction Reg
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
16
16-bit ALU
16
To Peripheral Modules
DS70292E-page 26
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 3-2:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 PROGRAMMER’S MODEL
DSP Operand
Registers
DSP Address
Registers
D15 D0
W0/WREG
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
PUSH.S Shadow
DO Shadow
Legend
Working Registers
SPLIM
Stack Pointer Limit Register
DSP
Accumulators
PC22
AD39
ACCA
ACCB
AD31
70
TBLPAG
Data Table Page Address
AD15
AD0
PC0
0 Program Counter
70
PSVPAG
Program Space Visibility Page Address
15
RCOUNT
0
REPEAT Loop Counter
15
DCOUNT
0
DO Loop Counter
22
DOSTART
0
DO Loop Start Address
22
DOEND
DO Loop End Address
15
CORCON
0
Core Configuration Register
OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register
SRH
SRL
© 2011 Microchip Technology Inc.
DS70292E-page 27


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
3.5 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER
R-0
OA
bit 15
R-0
R/C-0
R/C-0
OB
SA(1)
SB(1)
R/W-0(3)
bit 7
R/W-0(3)
IPL<2:0>(2)
R/W-0(3)
R-0
RA
R-0
OAB
R/W-0
N
R/C-0
SAB(4)
R/W-0
OV
R -0
DA
R/W-0
Z
R/W-0
DC
bit 8
R/W-0
C
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
SAB: SA || SB Combined Accumulator (Sticky) Status bit(4)
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1:
2:
3:
4:
This bit can be read or cleared (not set).
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15>) = 1.
This bit can be read or cleared (not set). Clearing this bit clears SA and SB.
DS70292E-page 28
© 2011 Microchip Technology Inc.


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
3:
4:
This bit can be read or cleared (not set).
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15>) = 1.
This bit can be read or cleared (not set). Clearing this bit clears SA and SB.
© 2011 Microchip Technology Inc.
DS70292E-page 29


DSPIC33FJ64GPX02 (Microchip)
16-bit Digital Signal Controllers

No Preview Available !

Click to Download PDF File for PC

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 3-2: CORCON: CORE CONTROL REGISTER
U-0
bit 15
U-0
U-0
R/W-0
R/W-0
— — US EDT(1)
R-0 R-0
DL<2:0>
R-0
bit 8
R/W-0
SATA
bit 7
R/W-0
SATB
R/W-1
SATDW
R/W-0
ACCSAT
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
Legend:
R = Readable bit
0’ = Bit is cleared
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15-13
bit 12
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops active
001 = 1 DO loop active
000 = 0 DO loops active
SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
DS70292E-page 30
© 2011 Microchip Technology Inc.




DSPIC33FJ64GPX02.pdf
Click to Download PDF File