MC56F8247 (Freescale Semiconductor)
(MC56F824x / MC56F825x) Digital Signal Controller Battery chargers and management

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Freescale Semiconductor
Technical Data
Document Number: MC56F825X
Rev. 3, 04/2011
MC56F825x/MC56F824x
MC56F825x/MC56F824x
Digital Signal Controller
44-pin LQFP
Case:
10 x 10 mm2
64-pin LQFP
Case:
10 x 10 mm2
48-pin LQFP
Case:
7 x 7 mm2
The MC56F825x/MC56F824x is a member of the 56800E
core-based family of digital signal controllers (DSCs). It
combines, on a single chip, the processing power of a DSP
and the functionality of a microcontroller with a flexible set of
peripherals to create a cost-effective solution. Because of its
lwowwwc.oDsatta,Schoeentf4iUg.unertation flexibility, and compact program
code, it is well-suited for many applications. The
MC56F825x/MC56F824x includes many peripherals that are
especially useful for cost-sensitive applications, including:
• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Solar inverters
• Battery chargers and management
• Switched-mode power supplies and power management
• Power metering
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical devices/equipment
• Instrumentation
• Lighting ballast
The 56800E core is based on a modified Harvard-style
architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction
cycle. The MCU-style programming model and optimized
instruction set allow straightforward generation of efficient,
compact DSP and control code. The instruction set is also
highly efficient for C compilers to enable rapid development
of optimized control applications.
The MC56F825x/MC56F824x supports program execution
from internal memories. Two data operands per instruction
cycle can be accessed from the on-chip data RAM. A full set
of programmable peripherals supports various applications.
Each peripheral can be independently shut down to save
power. Any pin, except Power pins and the Reset pin, can also
be configured as General Purpose Input/Outputs (GPIOs).
On-chip features include:
• 60 MHz operation frequency
• DSP and MCU functionality in a unified, C-efficient
architecture
• On-chip memory
– 56F8245/46: 48 KB (24K x 16) flash memory; 6 KB
(3K x 16) unified data/program RAM
– 56F8247: 48 KB (24K x 16) flash memory; 8 KB
(4K x 16) unified data/program RAM
– 56F8255/56/57: 64 KB (32K x 16) flash memory; 8 KB
(4K x 16) unified data/program RAM
• eFlexPWM with up to 9 channels, including 6 channels
with high (520 ps) resolution NanoEdge placement
• Two 8-channel, 12-bit analog-to-digital converters (ADCs)
with dynamic x2 and x4 programmable amplifier,
conversion time as short as 600 ns, and input
current-injection protection
• Three analog comparators with integrated 5-bit DAC
references
• Cyclic Redundancy Check (CRC) Generator
• Two high-speed queued serial communication interface
(QSCI) modules with LIN slave functionality
• Queued serial peripheral interface (QSPI) module
• Two SMBus-compatible inter-integrated circuit (I2C) ports
• Freescale’s scalable controller area network (MSCAN) 2.0
A/B module
• Two 16-bit quad timers (2 x 4 16-bit timers)
• Computer operating properly (COP) watchdog module
• On-chip relaxation oscillator: 8 MHz (400 kHz at standby
mode)
• Crystal/resonator oscillator
• Integrated power-on reset (POR) and low-voltage interrupt
(LVI) and brown-out reset module
• Inter-module crossbar connection
• Up to 54 GPIOs
• 44-pin LQFP, 48-pin LQFP, and 64-pin LQFP packages
• Single supply: 3.0 V to 3.6 V
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009-2011. All rights reserved.


MC56F8247 (Freescale Semiconductor)
(MC56F824x / MC56F825x) Digital Signal Controller Battery chargers and management

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Table of Contents
1 MC56F825x/MC56F824x Family Configuration . . . . . . . . . . . .3
2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 MC56F825x/MC56F824x Features. . . . . . . . . . . . . . . . .4
2.2 Award-Winning Development Environment. . . . . . . . . . .8
2.3 Architecture Block Diagram. . . . . . . . . . . . . . . . . . . . . . .8
2.4 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . .11
3 Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.3 MC56F825x/MC56F824x Signal Pins . . . . . . . . . . . . . .18
4 Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.2 Program Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.3 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.4 Interrupt Vector Table and Reset Vector . . . . . . . . . . . .33
4.5 Peripheral Memory-Mapped Registers . . . . . . . . . . . . .34
4.6 EOnCE Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .35
5 General System Control Information . . . . . . . . . . . . . . . . . . .36
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.2 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.3 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.4 On-chip Clock Synthesis . . . . . . . . . . . . . . . . . . . . . . . .37
5.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5.6 System Integration Module (SIM) . . . . . . . . . . . . . . . . .39
5.7 Inter-Module Connections. . . . . . . . . . . . . . . . . . . . . . .40
5.8 Joint Test Action Group (JTAG)/Enhanced On-Chip
Emulator (EOnCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.1 Operation with Security Enabled. . . . . . . . . . . . . . . . . .46
6.2 Flash Access Lock and Unlock Mechanisms . . . . . . . .47
6.3 Product Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
7 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
7.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . .48
7.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .49
7.3 ESD Protection and Latch-up Immunity . . . . . . . . . . . .50
7.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .50
7.5 Recommended Operating Conditions . . . . . . . . . . . . . .52
7.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 53
7.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . 55
7.8 Power-On Reset, Low Voltage Detection Specification 56
7.9 Voltage Regulator Specifications . . . . . . . . . . . . . . . . . 56
7.10 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 56
7.11 Enhanced Flex PWM Characteristics . . . . . . . . . . . . . 57
7.12 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . 57
7.13 External Clock Operation Timing. . . . . . . . . . . . . . . . . 57
7.14 Phase Locked Loop Timing . . . . . . . . . . . . . . . . . . . . . 58
7.15 External Crystal or Resonator Requirement . . . . . . . . 59
7.16 Relaxation Oscillator Timing . . . . . . . . . . . . . . . . . . . . 59
7.17 Reset, Stop, Wait, Mode Select, and Interrupt Timing. 60
7.18 Queued Serial Peripheral Interface (SPI) Timing . . . . 60
7.19 Queued Serial Communication Interface (SCI) Timing 64
7.20 Freescale’s Scalable Controller Area Network (MSCAN)65
7.21 Inter-Integrated Circuit Interface (I2C) Timing . . . . . . . 65
7.22 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.23 Quad Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.24 COP Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.25 Analog-to-Digital Converter (ADC) Parameters. . . . . . 68
7.26 Digital-to-Analog Converter (DAC) Parameters . . . . . . 70
7.27 5-Bit Digital-to-Analog Converter (DAC) Parameters. . 71
7.28 HSCMP Specifications . . . . . . . . . . . . . . . . . . . . . . . . 71
7.29 Optimize Power Consumption . . . . . . . . . . . . . . . . . . . 71
8 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . 72
8.2 Electrical Design Considerations. . . . . . . . . . . . . . . . . 73
9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10 Package Mechanical Outline Drawings . . . . . . . . . . . . . . . . . 76
10.1 44-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.2 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Appendix A
Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
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MC56F825x/MC56F824x Family Configuration
1 MC56F825x/MC56F824x Family Configuration
Table 1 compares the MC56F825x/MC56F824x devices.
Table 1. MC56F825x/MC56F824x Device Comparison
Feature
56F8245 56F8246 56F8247 56F8255 56F8256 56F8257
Operation Frequency (MHz)
60
High Speed Peripheral Clock (MHz)
120
Flash memory size (KB) with 1024 words per page
48 48 48 64 64 64
RAM size (KB)
668888
Enhanced
Flex PWM
(eFlexPWM)
High resolution NanoEdge PWM (520 ps res.)
Enhanced Flex PWM with Input Capture
PWM Fault Inputs (from Crossbar Input)
666666
003003
444444
12-bit ADC with x1, 2x, 4x Programmable Gain
2 x 4Ch 2 x 5Ch 2 x 8Ch 2 x 4Ch 2 x 5 Ch 2 x 8 Ch
Analog comparators (ACMP) each with integrated 5-bit DAC
3
12-bit DAC
1
Cyclic Redundancy Check (CRC)
Inter-Integrated Circuit (I2C) / SMBus
Yes
2
Queued Serial peripheral Interface (QSPI)
High speed Queued Serial Communications Interface (QSCI)1
1
2
Controller Area Network (MSCAN)
High Speed 16-bit multi-purpose timers (TMR)2
01
8
Computer operating properly (COP) watchdog timer
Yes
Integrated Power-On Reset and low voltage detection
Yes
Phase-locked loop (PLL)
Yes
8 MHz (400 kHz at standby mode) on-chip ROSC
Yes
Crystal/resonator oscillator
Yes
Crossbar Input pins
666666
Output pins
General purpose I/O (GPIO)3
226226
35 39 54 35 39 54
IEEE 1149.1 Joint Test Action Group (JTAG) interface
Yes
Enhanced on-chip emulator (EOnCE)
Yes
Operating temperature range
-40 °C to 105 °C
Package
1 Can be clocked by high speed peripheral clock up to 120 MHz
2 Can be clocked by high speed peripheral clock up to 120 MHz
3 Shared with other function pins
44LQFP 48LQFP 64LQFP 44LQFP 48LQFP 64LQFP
Freescale Semiconductor
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Overview
2 Overview
2.1 MC56F825x/MC56F824x Features
2.1.1 Core
• Efficient 56800E digital signal processor (DSP) engine with modified Harvard architecture
— Three internal address buses
— Four internal data buses
• As many as 60 million instructions per second (MIPS) at 60 MHz core frequency
• 155 basic instructions in conjunction with up to 20 address modes
• 32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition, subtraction, and logical
operation
• Single-cycle 16 × 16-bit parallel multiplier-accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Instruction set supports DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging
2.1.2 Operation Range
• 3.0 V to 3.6 V operation (power supplies and I/O)
• From power-on-reset: approximately 2.7 V to 3.6 V
• Ambient temperature operating range: –40 °C to +105 °C
2.1.3 Memory
• Dual Harvard architecture that permits as many as three simultaneous accesses to program and data memory
• 48 KB (24K x 16) to 64 KB (32K x 16) on-chip flash memory with 2048 bytes (1024 x 16) page size
• 6 KB (3K x 16) to 8 KB (4K x 16) on-chip RAM with byte addressable
• EEPROM emulation capability using flash
• Support for 60 MHz program execution from both internal flash and RAM memories
• Flash security and protection that prevent unauthorized users from gaining access to the internal flash
2.1.4 Interrupt Controller
• Five interrupt priority levels
— Three user programmable priority levels for each interrupt source: Level 0, 1, 2
— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, and
SWI3 instruction
— Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, and EOnCE trace buffer
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
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Overview
— Lowest-priority software interrupt: level LP
• Nested interrupts: higher priority level interrupt request can interrupt lower priority interrupt subroutine
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to system integration module (SIM) to restart clock out of wait and stop states
• Ability to relocate interrupt vector table
The masking of interrupt priority level is managed by the 56800E core.
2.1.5 Peripheral Highlights
• One Enhanced Flex Pulse Width Modulator (eFlexPWM) module
— Up to nine output channels
— 16-bit resolution for center aligned, edge aligned, and asymmetrical PWMs
— Each complementary pair can operate with its own PWM frequency based and deadtime values
– 4 Time base
– Independent top and bottom deadtime insertion
— PWM outputs can operate as complimentary pairs or independent channels
— Independent control of both edges of each PWM output
— 6-channel NanoEdge high resolution PWM
– Fractional delay for enhanced resolution of the PWM period and edge placement
– Arbitrary eFlexPWM edge placement - PWM phase shifting
– NanoEdge implementation: 520 ps PWM frequency resolution
— 3 Channel PWM with full Input Capture features
– Three PWM Channels - PWMA, PWMB, and PWMX
– Enhanced input capture functionality
— Support for synchronization to external hardware or other PWM
— Double buffered PWM registers
– Integral reload rates from 1 to 16
– Half cycle reload capability
— Multiple output trigger events can be generated per PWM cycle via hardware
— Support for double switching PWM outputs
— Up to four fault inputs can be assigned to control multiple PWM outputs
– Programmable filters for fault inputs
— Independently programmable PWM output polarity
— Individual software control for each PWM output
— All outputs can be programmed to change simultaneously via a FORCE_OUT event
— PWMX pin can optionally output a third PWM signal from each submodule
— Channels not used for PWM generation can be used for buffered output compare functions
— Channels not used for PWM generation can be used for input capture functions
— Enhanced dual edge capture functionality
— Option to supply the source for each complementary PWM signal pair from any of the following:
– Crossbar module outputs
– External ADC input, taking into account values set in ADC high and low limit registers
• Two independent 12-bit analog-to-digital converters (ADCs)
— 2 x 8 channel external inputs
— Built-in x1, x2, x4 programmable gain pre-amplifier
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Overview
— Maximum ADC clock frequency: up to 10 MHz
– Single conversion time of 8.5 ADC clock cycles (8.5 x 100 ns = 850 ns)
– Additional conversion time of 6-ADC clock cycles (6 x 100 ns = 600 ns)
— Sequential, parallel, and independent scan mode
— First 8 samples have Offset, Limit and Zero-crossing calculation supported
— ADC conversions can be synchronized by eFlexPWM and timer modules via internal crossbar module
— Support for simultaneous and software triggering conversions
— Support for multi-triggering mode with a programmable number of conversions on each trigger
• Inter-module Crossbar Switch (XBAR)
— Programmable internal module connections among the eFlexPWM, ADCs, Quad Timers, 12-bit DAC, HSCMPs,
and package pins
— User-defined input/output pins for PWM fault inputs, Timer input/output, ADC triggers, and Comparator outputs
• Three analog comparators (CMPs)
— Selectable input source includes external pins, internal DACs
— Programmable output polarity
— Output can drive timer input, eFlexPWM fault input, eFlexPWM source, external pin output, and trigger ADCs
— Output falling and rising edge detection able to generate interrupts
— 32-tap programmable voltage reference per comparator
• One 12-bit digital-to-analog converter (12-bit DAC)
— 12-bit resolution
— Power down mode
— Output can be routed to internal comparator, or off chip
• Two four-channel 16-bit multi-purpose timer (TMR) modules
— Four independent 16-bit counter/timers with cascading capability per module
— Up to 120 MHz operating clock
— Each timer has capture and compare and quadrature decoder capability
— Up to 12 operating modes
— Four external inputs and two external outputs
• Two queued serial communication interface (QSCI) modules with LIN slave functionality
— Up to 120 MHz operating clock
— Four-byte-deep FIFOs available on both transmit and receive buffers
— Full-duplex or single-wire operation
— Programmable 8- or 9-bit data format
— 13-bit integer and 3-bit fractional baud rate selection
— Two receiver wakeup methods:
– Idle line
– Address mark
— 1/16 bit-time noise detection
— Support LIN slave operation
• One queued serial peripheral interface (QSPI) module
— Full-duplex operation
— Four-word deep FIFOs available on both transmit and receive buffers
— Master and slave modes
— Programmable length transactions (2 to 16 bits)
— Programmable transmit and receive shift order (MSB as first or last bit transmitted)
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Overview
— Maximum slave module frequency = module clock frequency/2
— 13-bit baud rate divider for low speed communication
• Two inter-integrated circuit (I2C) ports
— Operation at up to 100 kbps
— Support for master and slave operation
— Support for 10-bit address mode and broadcasting mode
— Support for SMBus, Version 2
• One Freescale Scalable Controller Area Network (MSCAN) module
— Fully compliant with CAN protocol Version 2.0 A/B
— Support for standard and extended data frames
— Support for data rate up to 1 Mbit/s
— Five receive buffers and three transmit buffers
• Computer operating properly (COP) watchdog timer capable of selecting different clock sources
— Programmable prescaler and timeout period
— Programmable wait, stop, and partial powerdown mode operation
— Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected
— Choice of clock sources from four sources in support of EN60730 and IEC61508:
– On-chip relaxation oscillator
– External crystal oscillator/external clock source
– System clock (IP bus to 60 MHz)
• Power supervisor (PS)
— On-chip linear regulator for digital and analog circuitry to lower cost and reduce noise
— Integrated low voltage detection to generate warning interrupt if VDD is below low voltage detection (LVI)
threshold
— Integrated power-on reset (POR)
– Reliable reset process during power-on procedure
– POR is released after VDD passes low voltage detection (LVI) threshold
— Integrated brown-out reset
— Run, wait, and stop modes
• Phase lock loop (PLL) providing a high-speed clock to the core and peripherals
— 2x system clock provided to Quad Timers and SCIs
— Loss of lock interrupt
— Loss of reference clock interrupt
• Clock sources
— On-chip relaxation oscillator with two user selectable frequencies: 400 kHz for low speed mode, 8 MHz for
normal operation
— External clock: crystal oscillator, ceramic resonator, and external clock source
• Cyclic Redundancy Check (CRC) Generator
— Hardware CRC generator circuit using 16-bit shift register
— CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial
— Error detection for all single, double, odd, and most multi-bit errors
— Programmable initial seed value
— High-speed hardware CRC calculation
— Optional feature to transpose input data and CRC result via transpose register, required on applications where
bytes are in LSb (Least Significant bit) format.
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Overview
• Up to 54 general-purpose I/O (GPIO) pins
— 5 V tolerant I/O
— Individual control for each pin to be in peripheral or GPIO mode
— Individual input/output direction control for each pin in GPIO mode
— Individual control for each output pin to be in push-pull mode or open-drain mode
— Hysteresis and configurable pullup device on all input pins
— Ability to generate interrupt with programmable rising or falling edge and software interrupt
— Configurable drive strength: 4 mA / 8 mA sink/source current
• JTAG/EOnCE debug programming interface for real-time debugging
— IEEE 1149.1 Joint Test Action Group (JTAG) interface
— EOnCE interface for real-time debugging
2.1.6 Power Saving Features
• Low-speed run, wait, and stop modes: as low as 781 Hz clock provided by OCCS and internal ROSC
• Large regulator standby mode available for reducing power consumption at low-speed mode
• Less than 30 µs typical wakeup time from stop modes
• Each peripheral can be individually disabled to save power
2.2 Award-Winning Development Environment
Processor Expert (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software
application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment (IDE) is a sophisticated tool for code navigation, compiling, and
debugging. A complete set of evaluation modules (EVMs), demonstration board kit, and development system cards supports
concurrent engineering. Together, PE, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and
efficient development.
2.3 Architecture Block Diagram
The MC56F825x/MC56F824x’s architecture appears in Figure 1 and Figure 2. Figure 1 illustrates how the 56800E system
buses communicate with internal memories and the IP bus interface as well as the internal connections among the units of the
56800E core.
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
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Overview
DSP56800E Core
Program Control Unit
PC
LA
LA2
HWS0
HWS1
FIRA
OMR
SR
LC
LC2
FISR
Instruction
Decoder
Interrupt
Unit
Looping
Unit
Address
Generation
Unit
(AGU)
M01
N3
ALU1
ALU2
R0
R1
R2
R3
R4
R5
N
SP
XAB1
XAB2
PAB
PDB
CDBW
CDBR
XDB2
Program
Memory
Data/
Program
RAM
Bit-
Manipulation
Unit
Enhanced
OnCE™
JTAG TAP
A2
B2
C2
D2
Y
A1
B1
C1
D1
Y1
Y0
X0
A0
B0
C0
D0
Data
Arithmetic
Logic Unit
(ALU)
MAC and ALU Multi-Bit Shifter
IP Bus
Interface
Figure 1. 56800E Core Block Diagram
Figure 2 shows the peripherals and control blocks connected to the IP bus bridge. Refer to the system integration module (SIM)
section in the device’s reference manual for information about which signals are multiplexed with those of other peripherals.
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Overview
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MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
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Signal/Connection Descriptions
2.4 Product Documentation
The documents listed in Table 2 are required for a complete description and proper design with the MC56F825x/MC56F824x.
Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature
Distribution Centers, or online at http://www.freescale.com.
Table 2. MC56F825x/MC56F824x Device Documentation
Topic
Description
Order Number
DSP56800E Reference Manual
Detailed description of the 56800E family architecture, 16-bit digital DSP56800ERM
signal controller core processor, and the instruction set
MC56F825x Reference Manual
Detailed description of peripherals of the MC56F825x/MC56F824x MC56F825XRM
devices
MC56F824x/5x Serial Bootloader Detailed description of the Serial Bootloader in the 56F800x family of TBD
User Guide
devices
MC56F825x Technical Data Sheet Electrical and timing specifications, pin descriptions, and package MC56F825X
descriptions (this document)
MC56F825x Errata
Detailed description of any chip issues that might be present
MC56F825XE
3 Signal/Connection Descriptions
3.1 Introduction
The input and output signals of the MC56F825x/MC56F824x are organized into functional groups, as detailed in Table 3.
Table 3. Functional Group Pin Allocations
Functional Group
Number of Pins Number of Pins Number of Pins
in 44 LQFP
in 48 LQFP
in 64 LQFP
Power inputs (VDD, VDDA, VCAP)
556
Ground (VSS, VSSA)
Reset1
444
111
Enhanced Flex Pulse Width Modulator (eFlexPWM) ports1
669
Queued Serial Peripheral Interface (SPI) ports1
444
Queued Serial Communications Interface 0&1 (QSCI0 & QSCI1) ports1
6
6
9
Inter-Integrated Circuit Interface 0&1 (I2C0 & I2C0) ports1
446
Analog-to-Digital Converter (ADC) inputs1
8 10 16
High Speed Analog Comparator inputs/outputs1
11 12 15
12-bit Digital-to-Analog Converter (DAC_12B) output
Quad Timer Module (TMRA & TMRB) ports1
Freescale’s Scalable Controller-Area-Network (MSCAN)1, 2
Inter-Module Cross Bar package inputs/outputs1
Clock1
JTAG/Enhanced On-Chip Emulation (EOnCE)1
111
558
222
10 12 17
344
444
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Signal/Connection Descriptions
1 Pins may be shared with other peripherals. See Table 4.
2 Exclude MC56F824x.
Table 4 summarizes all device pins. Each table row describes the signal or signals present on a pin, sorted by pin number.
Peripheral pins in bold identify reset state.
Table 4. MC56F825x/MC56F824x Pins
Pin Number
44 48 64
LQFP LQFP LQFP
111
222
333
Pin Name
TCK/GPIOD2
RESET / GPIOD4
GPIOC0/XTAL/CLKIN
GPIO
I2C
SCI
SPI
MS
CAN1
GPIOD2
GPIOD4
GPIOC0
444
GPIOC1/EXTAL
GPIOC1
5 5 5 GPIOC2/TXD0/TB0/XB_IN2/ GPIOC2
CLKO
6
GPIOF8/RXD0/TB1
GPIOF8
6 6 7 GPIOC3/TA0/CMPA_O/RXD0 GPIOC3
TXD0
RXD0
RXD0
Peripherals
ADC
Cross Bar
COMP
Quad
Timer
eFlex
PWM
Power JTAG Misc.
XB_IN2
TB0
TCK
RESET
XTAL/
CLKIN
EXTAL
CLKO
TB1
CMPA_O TA0
778
9
10
11
8 12
8 9 13
GPIOC4/TA1/CMPB_O
GPIOA7/ANA7
GPIOA6/ANA6
GPIOA5/ANA5
GPIOA4/ANA4
GPIOA0/ANA0&
CMPA_P2/CMPC_O
GPIOC4
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA0
9 10 14
GPIOA1/
ANA1&CMPA_M0
GPIOA1
10 11 15 GPIOA2/ANA2&VREFHA& GPIOA2
CMPA_M1
11 12 16
GPIOA3/ANA3&VREFLA& GPIOA3
CMPA_M2
17 GPIOB7/ANB7&CMPB_M2 GPIOB7
12 13 18
GPIOC5/DACO/XB_IN7 GPIOC5
19 GPIOB6/ANB6&CMPB_M1 GPIOB6
20 GPIOB5/ANB5&CMPC_M2 GPIOB5
14 21 GPIOB4/ANB4&CMPC_M1 GPIOB4
13 15 22
14 16 23
15 17 24
VDDA
VSSA
GPIOB0/
ANB0&CMPB_P2
GPIOB0
16 18 25
GPIOB1/
ANB1&CMPB_M0
GPIOB1
17 19 26
VCAP
18 20 27
GPIOB2/
GPIOB2
ANB2&VREFHB&CMPC_P2
ANA7
ANA6
ANA5
ANA4
ANA0
ANA1
CMPB_O TA1
CMPA_P2/
CMPC_O
CMPA_M0
ANA2&
VREFHA
CMPA_M1
ANA3&
VREFLA
CMPA_M2
ANB7
CMPB_M2
XB_IN7
ANB6
CMPB_M1
ANB5
CMPC_M2
ANB4
CMPC_M1
ANB0
ANB1
ANB2&
VREFHB
CMPB_P2
CMPB_M0
CMPC_P2
DACO
VDDA
VSSA
VCAP
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
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Table 4. MC56F825x/MC56F824x Pins (continued)
Pin Number
44 48 64
LQFP LQFP LQFP
Pin Name
Peripherals
GPIO
I2C
SCI
SPI
MS
CAN1
ADC
Cross Bar
COMP
Quad
Timer
eFlex
PWM
Power JTAG Misc.
19 21 28
GPIOB3/
GPIOB3
ANB3&VREFLB&CMPC_M0
ANB3&
VREFLB
CMPC_M0
29
20 22 30
21 23 31
22 24 32
23 25 33
24 26 34
VDD
VSS
GPIOC6/TA2/XB_IN3/
CMP_REF
GPIOC7/SS/TXD0
GPIOC8/MISO/RXD0
GPIOC9/SCLK/XB_IN4
GPIOC6
GPIOC7
GPIOC8
GPIOC9
TXD0 SS
RXD0 MISO
SCLK
XB_IN3 CMP_REF TA2
VDD
VSS
XB_IN4
25 27 35 GPIOC10/MOSI/XB_IN5/MISO GPIOC10
MOSI/
MISO
28 36
GPIOF0/XB_IN6
GPIOF0
26 29 37 GPIOC11/CANTX/SCL1/TXD1 GPIOC11 SCL1 TXD1
CANTX
27 30 38 GPIOC12/CANRX/SDA1/RXD1 GPIOC12 SDA1 RXD1
CANRX
39 GPIOF2/SCL1/XB_OUT2 GPIOF2 SCL1
40 GPIOF3/SDA1/XB_OUT3 GPIOF3 SDA1
41 GPIOF4/TXD1/XB_OUT4 GPIOF4
TXD1
42 GPIOF5/RXD1/XB_OUT5 GPIOF5
RXD1
XB_IN5
XB_IN6
XB_OUT2
XB_OUT3
XB_OUT4
XB_OUT5
28 31 43
VSS
29 32 44
30 33 45
VDD
GPIOE0/PWM0B
GPIOE0
31 34 46
GPIOE1/PWM0A
GPIOE1
32 35 47
GPIOE2/PWM1B
GPIOE2
33 36 48
GPIOE3/PWM1A
GPIOE3
34 37 49
GPIOC13/TA3/XB_IN6 GPIOC13
38 50
GPIOF1/CLKO/XB_IN7 GPIOF1
35 39 51
GPIOE4/PWM2B/XB_IN2 GPIOE4
36 40 52
GPIOE5/PWM2A/XB_IN3 GPIOE5
53 GPIOE6/PWM3B/XB_IN4 GPIOE6
54 GPIOE7/PWM3A/XB_IN5 GPIOE7
37 41 55 GPIOC14/SDA0/XB_OUT0 GPIOC14 SDA0
38 42 56 GPIOC15/SCL0/XB_OUT1 GPIOC15 SCL0
XB_IN6
XB_IN7
XB_IN2
XB_IN3
XB_IN4
XB_IN5
XB_OUT0
XB_OUT1
VSS
VDD
PWM0B
PWM0A
PWM1B
PWM1A
TA3
PWM2B
PWM2A
PWM3B
PWM3A
CLKO
39 43 57
58
59
VCAP
GPIOF6/TB2/PWM3X
GPIOF7/TB3
GPIOF6
GPIOF7
VCAP
TB2 PWM3X
TB3
40 44 60
VDD
VDD
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Table 4. MC56F825x/MC56F824x Pins (continued)
Pin Number
44 48 64
LQFP LQFP LQFP
Pin Name
Peripherals
GPIO
I2C
SCI
SPI
MS
CAN1
ADC
Cross Bar
COMP
Quad
Timer
eFlex
PWM
Power JTAG Misc.
41 45 61
42 46 62
VSS
TDO/GPIOD1
GPIOD1
43 47 63
TMS/GPIOD3
GIPOD3
44 48 64
TDI/GPIOD0
GPIOD0
1 The MSCAN module is not available on the MC56F824x devices.
VSS
TDO
TMS
TDI
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
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Signal/Connection Descriptions
3.2 Pin Assignment
Figure 3 shows the pin assignments of the 56F8245 and 56F8255’s 44-pin low-profile quad flat pack (44LQFP). Figure 4 shows
the pin assignments of the 56F8246 and 56F8256’s 48-pin low-profile quad flat pack (48LQFP). Figure 5 shows the pin
assignments of the 56F8247 and 56F8257’s 64-pin low-profile quad flat pack (64LQFP).
NOTE
The CANRX and CANTX signals of the MSCAN module are not available on the
MC56F824x devices.
GPIOD2/TCK
GPIOD4/RESET
GPIOC0/XTAL/CLKIN
GPIOC1/EXTAL
GPIOC2/TXD0/TB0/XB_IN2/CLKO
GPIOC3/TA0/CMPA_O/RXD0
GPIOC4/TA1/CMPB_O
GPIOA0/ANA0/CMPA_P2/CMPC_O
GPIOA1/ANA1/CMPA_M0
GPIOA2/ANA2/VREFHA/CMPA_M1
GPIOA3/ANA3/VREFLA/CMPA_M2
1
2
3
4
5
6
7
8
9
10
11
33 GPIOE3/PWM1A
32 GPIOE2/PWM1B
31 GPIOE1/PWM0A
30 GPIOE0/PWM0B
29 VDD
28 VSS
27 GPIOC12/CANRX0/SDA1/RXD1
26 GPIOC11/CANTX0/SCL1/TXD1
25 GPIOC10/MOSI/XB_IN5/MISO
24 GPIOC9/SCLK/XB_IN4
23 GPIOC8/MISO/RXD0
Figure 3. Top View: 56F8245 and 56F8255 44-Pin LQFP Package
Freescale Semiconductor
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Signal/Connection Descriptions
GPIOD2/TCK
GPIOD4/RESET
GPIOC0/XTAL/CLKIN
GPIOC1/EXTAL
GPIOC2/TXD0/TB0/XB_IN2/CLKO
GPIOC3/TA0/CMPA_O/RXD0
GPIOC4/TA1/CMPB_O
GPIOA4/ANA4
GPIOA0/ANA0/CMPA_P2/CMPC_O
GPIOA1/ANA1/CMPA_M0
GPIOA2/ANA2/VREFHA/CMPA_M1
GPIOA3/ANA3/VREFLA/CMPA_M2
1
2
3
4
5
6
7
8
9
10
11
12
36 GPIOE3/PWM1A
35 GPIOE2/PWM1B
34 GPIOE1/PWM0A
33 GPIOE0/PWM0B
32 VDD
31 VSS
30 GPIOC12/CANRX0/SDA1/RXD1
29 GPIOC11/CANTX0/SCL1/TXD1
28 GPIOF0/XB_IN6
27 GPIOC10/MOSI/XB_IN5/MISO
26 GPIOC9/SCLK/XB_IN4
25 GPIOC8/MISO/RXD0
Figure 4. Top View: 56F8246 and 56F8256 48-Pin LQFP Package
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
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GPIOD2/TCK
GPIOD4/RESET
GPIOC0/XTAL/CLKIN
GPIOC1/EXTAL
GPIOC2/TXD0/TB0/XB_IN2/CLKO
GPIOF8/RXD0/TB1
GPIOC3/TA0/CMPA_O/RXD0
GPIOC4/TA1/CMPB_O
GPIOA7/ANA7
GPIOA6/ANA6
GPIOA5/ANA5
GPIOA4/ANA4
GPIOA0/ANA0/CMPA_P2/CMPC_O
GPIOA1/ANA1/CMPA_M0
GPIOA2/ANA2/VREFHA/CMPA_M1
GPIOA3/ANA3/VREFLA/CMPA_M2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Signal/Connection Descriptions
48 GPIOE3/PWM1A
47 GPIOE2/PWM1B
46 GPIOE1/PWM0A
45 GPIOE0/PWM0B
44 VDD
43 VSS
42 GPIOF5/RXD1/XB_OUT5
41 GPIOF4/TXD1/XB_OUT4
40 GPIOF3/SDA1/XB_OUT3
39 GPIOF2/SCL1/XB_OUT2
38 GPIOC12/CANRX/SDA1/RXD1
37 GPIOC11/CANTX/SCL1/TXD1
36 GPIOF0/XB_IN6
35 GPIOC10/MOSI/XB_IN5/MISO
34 GPIOC9/SCLK/XB_IN4
33 GPIOC8/MISO/RXD0
Figure 5. Top View: 56F8247 and 56F8257 64-Pin LQFP Package
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Signal/Connection Descriptions
3.3 MC56F825x/MC56F824x Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternative functionality, shown in parentheses and
as italic, must be programmed via the GPIO module’s peripheral enable registers (GPIO_x_PER) and the SIM module’s GPIO
peripheral select (GPSx) registers.
Table 5. MC56F825x/MC56F824x Signal and Package Information
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
VDD
VDD
VDD
VSS
VSS
VSS
VDDA
29
29 32 44
40 44 60
20 22 30
28 31 43
41 45 61
13 15 22
Supply
Supply
Supply
VSSA
14 16 23 Supply
VCAP
VCAP
17 19 26
39 43 57
Supply
TDI
44 48 64
Input
(GPIOD0)
Input/
Output
State
During
Reset
Signal Description
Supply I/O Power — This pin supplies 3.3 V power to the chip I/O interface.
Supply I/O Ground — These pins provide ground for chip I/O interface.
Supply Analog Power — This pin supplies 3.3 V power to the analog
modules. It must be connected to a clean analog power supply.
Supply Analog Ground — This pin supplies an analog ground to the analog
modules. It must be connected to a clean power supply.
Supply
VCAP — Connect a bypass capacitor of 2.2 µF or greater between
this pin and VSS to stabilize the core voltage regulator output
required for proper device operation. See Section 8.2, “Electrical
Design Considerations,” on page 73.
Input,
internal
pullup
enabled
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK
and has an on-chip pullup resistor.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
TDO
42 46 62 Output
(GPIOD1)
Input/
Output
Output
After reset, the default state is TDI.
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
TCK
111
Input
After reset, the default state is TDO.
Input,
internal
pullup
enabled
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pullup resistor. A
Schmitt-trigger input is used for noise immunity.
(GPIOD2)
Input/
Output
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TCK
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
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Signal/Connection Descriptions
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
TMS
43 47 63
input
(GPIOD3)
Input/
Output
State
During
Reset
Signal Description
Input,
internal
pullup
enabled
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pullup resistor.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TMS
RESET 2 2 2
Input
Note: Always tie the TMS pin to VDD through a 2.2K resistor if need
to keep on-board debug capability. Otherwise directly tie to VDD
Input,
internal
pullup
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed in
the reset state. A Schmitt-trigger input is used for noise immunity.
The internal reset signal is deasserted synchronous with the
internal clocks after a fixed number of internal clocks.
(GPIOD4)
Input/
Open-drain
Output
Port D GPIO — This GPIO pin can be individually programmed as
an input or open-drain output pin.If RESET functionality is disabled
in this mode and the chip can be reset only via POR, COP reset, or
software reset.
GPIOA0 8
(ANA0&
CMPA_P2)
(CMPC_O)
After reset, the default state is RESET.
9 13 Input/
Input, Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input
enabled ANA0 and CMPA_P2 — Analog input to channel 0 of ADCA and
positive input 2 of analog comparator A.
Output
CMPC_O— Analog comparator C output
When used as an analog input, the signal goes to the ANA0 and
CMPA_P2.
GPIOA1 9
(ANA1&
CMPA_M0)
10 14
Input/
Output
Input
After reset, the default state is GPIOA0.
Input,
internal
pullup
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANA1 and CMPA_M0 — Analog input to channel 1of ADCA and
negative input 0 of analog comparator A.
When used as an analog input, the signal goes to the ANA1 and
CMPA_M0.
After reset, the default state is GPIOA1.
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Signal/Connection Descriptions
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
GPIOA2 10 11 15
(ANA2&
VREFHA&
CMPA_M1)
Input/
Output
Input
State
During
Reset
Signal Description
Input,
internal
pullup
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANA2 and VREFHA and CMPA_M1 — Analog input to channel 2 of
ADCA and analog references high of ADCA and negative input 1 of
analog comparator A.
When used as an analog input, the signal goes to ANA2 and
VREFHA and CMPA_M1. ADC control register configures this input
as ANA2 or VREFHA.
GPIOA3 11 12 16
(ANA3&
VREFLA&
CMPA_M2)
Input/
Output
Input
After reset, the default state is GPIOA2.
Input,
internal
pullup
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANA3 and VREFLA and CMPA_M2 — Analog input to channel 3 of
ADCA and analog references low of ADCA and negative input 2 of
analog comparator A.
When used as an analog input, the signal goes to ANA3 and
VREFLA and CMPA_M2. ADC control register configures this input
as ANA3 or VREFLA.
GPIOA4
(ANA4)
After reset, the default state is GPIOA3.
8 12 Input/
Input, Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input
enabled ANA4 — Analog input to channel 4 of ADCA.
GPIOA5
(ANA5)
After reset, the default state is GPIOA4.
11 Input/
Input, Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input
enabled ANA5 — Analog input to channel 5 of ADCA.
GPIOA6
(ANA6)
After reset, the default state is GPIOA5.
10 Input/
Input, Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input
enabled ANA6 — Analog input to channel 5 of ADCA.
GPIOA7
(ANA7)
After reset, the default state is GPIOA6.
9 Input/
Input, Port A GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input
enabled ANA7 — Analog input to channel 7 of ADCA.
After reset, the default state is GPIOA7.
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
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Signal/Connection Descriptions
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
GPIOB0 15 17 24
(ANB0&
CMPB_P2)
Input/
Output
Input
State
During
Reset
Signal Description
Input,
internal
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANB0 and CMPB_P2 — Analog input to channel 0 of ADCB and
positive input 2 of analog comparator B.
When used as an analog input, the signal goes to ANB0 and
CMPB_P2.
GPIOB1 16 18 25
(ANB1&
CMPB_M0)
Input/
Output
Input
After reset, the default state is GPIOB0.
Input,
internal
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANB1 and CMPB_M0— Analog input to channel 1 of ADCB and
negative input 0 of analog comparator B.
When used as an analog input, the signal goes to ANB1 and
CMPB_M0.
GPIOB2 18 20 27
(ANB2&
VREFHB&
CMPC_P2)
Input/
Output
Input
After reset, the default state is GPIOB1.
Input,
internal
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANB2 and VREFHB and CMPC_P2 — Analog input to channel 2 of
ADCB and analog references high of ADCB and positive input 2 of
analog comparator C.
When used as an analog input, the signal goes to ANB2 and
VREFHB and CMPC_P2. ADC control register configures this input
as ANB2 or VREFHB.
GPIOB3 19 21 28
(ANB3&
VREFLB&
CMPC_M0)
Input/
Output
Input
After reset, the default state is GPIOB2.
Input,
internal
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANB3 and VREFLB and CMPC_M0 — Analog input to channel 3 of
ADCB and analog references low of ADCB and negative input 0 of
analog comparator C.
When used as an analog input, the signal goes to ANB3 and
VREFLB and MPC_M0. ADC control register configures this input
as ANB3 or VREFLB.
After reset, the default state is GPIOB3.
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Signal/Connection Descriptions
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
GPIOB4
(ANB4&
CMPC_M1)
14 21
Input/
Output
Input
State
During
Reset
Signal Description
Input,
internal
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANB4 and CMPC_M1 — Analog input to channel 4 of ADCB and
negative input 1 of analog comparator C.
GPIOB5
(ANB5&
CMPC_M2)
After reset, the default state is GPIOB4.
20 Input/
Input, Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input
enabled ANB5 and CMPC_M2 — Analog input to channel 5 of ADCB and
negative input 2 of analog comparator C.
GPIOB6
(ANB6&
CMPB_M1)
After reset, the default state is GPIOB5.
19 Input/
Input, Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input
enabled ANB6 and CMPB_M1 — Analog input to channel 6 of ADCB and
negative input 1 of analog comparator B.
GPIOB7
(ANB7&
CMPB_M2)
After reset, the default state is GPIOB6.
17 Input/
Input, Port B GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input
enabled ANB7 and CMPB_M2 — Analog input to channel 7 of ADCB and
negative input 2 of analog comparator B.
After reset, the default state is GPIOB7.
GPIOC0 3 3 3
Input/
Input, Port C GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
XTAL
Analog
pullup
enabled XTAL — External Crystal Oscillator Output. This output connects
Output
the internal crystal oscillator output to an external crystal or ceramic
resonator.
CLKIN
Input
CLKIN — This pin serves as an external clock input.1
After reset, the default state is GPIOC0.
GPIOC1 4 4 4
Input/
Input, Port C GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
(EXTAL)
Analog
pullup
enabled EXTAL — External Crystal Oscillator Input. This input connects the
Input
internal crystal oscillator input to an external crystal or ceramic
resonator.
After reset, the default state is GPIOC1.
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Signal/Connection Descriptions
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
GPIOC2 5 5 5
Input/
Output
(TXD0)
Output
(TB0)
(XB_IN2)
(CLKO)
Input/
Output
Input
Output
State
During
Reset
Signal Description
Input,
internal
pullup
enabled
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
TXD0 — The SCI0 transmit data output or transmit/receive in single
wire operation.
TB0 — Quad timer module B channel 0 input/output.
XB_IN2 — Crossbar module input 2
CLKO — This is a buffered clock output; the clock source is selected
by clockout select (CLKOSEL) bits in the clock output select register
(CLKOUT) of the SIM.
After reset, the default state is GPIOC2.
GPIOC3 6 6 7
Input/
Input, Port C GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
(TA0)
Input/
pullup
enabled TA0 — Quad timer module A channel 0 input/output.
Output
(CMPA_O)
Output
CMPA_O— Analog comparator A output
(RXD0)
Input
RXD0 — The SCI0 receive data input.
After reset, the default state is GPIOC3.
GPIOC4 7 7 8
Input/
Input, Port C GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
(TA1)
Input/
pullup
enabled TA1 — Quad timer module A channel 1input/output
Output
(CMPB_O)
Output
CMPB_O — Analog comparator B output
GPIOC5 12 13 18
(DACO)
(XB_IN7)
Input/
Output
Analog
Output
Input
After reset, the default state is GPIOC4.
Input,
internal
pullup
enabled
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
DACO — 12-bit Digital-to-Analog Controller output
XB_IN7 — Crossbar module input 7
After reset, the default state is GPIOC5.
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Signal/Connection Descriptions
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
GPIOC6 21 23 31
(TA2)
(XB_IN3)
(CMP_REF)
Input/
Output
Input/
Output
Input
Analog
Input
GPIOC7
(SS)
(TXD0)
22 24 32
Input/
Output
Input/
Output
Output
State
During
Reset
Signal Description
Input,
internal
pullup
enabled
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
TA2 — Quad timer module A channel 2 input/output
XB_IN3 — Crossbar module input 3
CMP_REF— Positive input 3 of analog comparator A and B and C
After reset, the default state is GPIOC6
Input,
internal
pullup
enabled
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
SS — SS is used in slave mode to indicate to the SPI module that
the current transfer is to be received.
TXD0 — SCI0 transmit data output or transmit/receive in single wire
operation
GPIOC8
(MISO)
(RXD0)
23 25 33
Input/
Output
Input/
Output
Input
After reset, the default state is GPIOC7.
Input,
internal
pullup
enabled
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
MISO — Master in/slave out. In master mode, this pin serves as the
data input. In slave mode, this pin serves as the data output. The
MISO line of a slave device is placed in the high-impedance state if
the slave device is not selected.
RXD0 — SCI0 receive data input
GPIOC9 24 26 34
(SCLK)
(XB_IN4)
Input/
Output
Input/
Output
Input
After reset, the default state is GPIOC8.
Input,
internal
pullup
enabled
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
SCLK — The SPI serial clock. In master mode, this pin serves as
an output, clocking slaved listeners. In slave mode, this pin serves
as the data clock input.
XB_IN4 — Crossbar module input 4
After reset, the default state is GPIOC9.
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Signal/Connection Descriptions
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
GPIOC10 25 27 35
(MOSI)
Input/
Output
Input/
Output
State
During
Reset
Signal Description
Input,
internal
pullup
enabled
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
MOSI — Master out/slave in. In master mode, this pin serves as the
data output. In slave mode, this pin serves as the data input.
(XB_IN5)
Input
XB_IN5 — Crossbar module input 5
(MISO)
Input/
Output
MISO — Master in/slave out. In master mode, this pin serves as the
data input. In slave mode, this pin serves as the data output. The
MISO line of a slave device is placed in the high-impedance state if
the slave device is not selected.
After reset, the default state is GPIOC10.
GPIOC11 26 29 37 Input/
Input, Port C GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
(CANTX)
pullup
Open-drain enabled CANTX — CAN transmit data output (not available on
Output
56F8245/46/47)
(SCL1)
Input/
Open-drain
Output
SCL1 — I2C1 serial clock
(TXD1)
Output
TXD1 — SCI1 transmit data output or transmit/receive in single wire
operation
GPIOC12 27 30 38
(CANRX)
Input/
Output
Input
After reset, the default state is GPIOC11.
Input,
internal
pullup
enabled
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
CANRX — CAN receive data input (not available on
56F8245/46/47)
(SDA1)
Input/
Open-drain
Output
SDA1 — I2C1 serial data line
(RXD1)
Input
RXD1 — SCI1 receive data input
GPIOC13 34 37 49
(TA3)
(XB_IN6)
Input/
Output
Input/
Output
Input
After reset, the default state is GPIOC12.
Input,
internal
pullup
enabled
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
TA3 — Quad timer module A channel 3input/output.
XB_IN6 — Crossbar module input 6
After reset, the default state is GPIOC13.
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Signal/Connection Descriptions
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
State
During
Reset
Signal Description
GPIOC14 37 41 55 Input/
Input, Port C GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
(SDA0)
Input/
pullup
enabled SDA0 — I2C0 serial data line
Open-drain
Output
(XB_OUT0)
Input
XB_OUT0 — Crossbar module output 0
After reset, the default state is GPIOC14.
GPIOC15 38 42 56 Input/
Input, Port C GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
(SCL0)
Input/
pullup
enabled SCL0 — I2C0 serial clock
Open-drain
Output
(XB_OUT1)
Input
XB_OUT1 — Crossbar module output 1
After reset, the default state is GPIOC15.
GPIOE0 30 33 45
Input/
Input, Port E GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
PWM0B
Input
enabled PWM0B — NanoEdge PWM submodule 0 output B
After reset, the default state is GPIOE0.
GPIOE1 31 34 46
Input/
Input, Port E GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
(PWM0A)
Output enabled PWM0A — NanoEdge PWM submodule 0 output B
After reset, the default state is GPIOE1.
GPIOE2 32 35 47
Input/
Input, Port E GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
(PWM1B)
Output enabled PWM1B — NanoEdge PWM submodule 1 output A
After reset, the default state is GPIOE2.
GPIOE3 33 36 48
Input/
Input, Port E GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
(PWM1A)
Output enabled PWM1A — NanoEdge PWM submodule 1 output A
After reset, the default state is GPIOE3.
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Signal/Connection Descriptions
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
GPIOE4 35 39 51
(PWM2B)
(XB_IN2)
Input/
Output
Output
Input
State
During
Reset
Signal Description
Input,
internal
pullup
enabled
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
PWM2B — NanoEdge PWM submodule 2 output B
XB_IN2 — Crossbar module input 2
GPIOE5 36 40 52
(PWM2A)
(XB_IN3)
Input/
Output
Output
Input
After reset, the default state is GPIOE4.
Input,
internal
pullup
enabled
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
PWM2A — NanoEdge PWM submodule 2 output A
XB_IN3 — Crossbar module input 3
GPIOE6
(PWM3B)
(XB_IN4)
After reset, the default state is GPIOE5.
53 Input/
Input, Port E GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input/ enabled PWM3B — Enhanced PWM submodule 3 output B or input capture
Output
B
Input
XB_IN4 — Crossbar module input 4
GPIOE7
(PWM3A)
(XB_IN5)
After reset, the default state is GPIOE6.
54 Input/
Input, Port E GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input/ enabled PWM3A — Enhanced PWM submodule 3 output A or input capture
Output
A
Input
XB_IN5 — Crossbar module input 5
GPIOF0
(XB_IN6)
28 36
Input/
Output
Input
After reset, the default state is GPIOE7.
Input,
internal
pullup
enabled
Port F GPIO — This GPIO pin can be individually programmed as
an input or output pin.
XB_IN6 — Crossbar module input 6
After reset, the default state is GPIOF0.
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Signal/Connection Descriptions
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
GPIOF1
(CLKO)
38 50
Input/
Output
Output
(XB_IN7)
Input
State
During
Reset
Signal Description
Input,
internal
pullup
enabled
Port F GPIO — This GPIO pin can be individually programmed as
an input or output pin.
CLKO — This is a buffered clock output; the clock source is selected
by clockout select (CLKOSEL) bits in the clock output select register
(CLKOUT) of the SIM.
XB_IN7 — Crossbar module input 7
GPIOF2
(SCL1)
(XB_OUT2)
After reset, the default state is GPIOF1.
39 Input/
Input, Port F GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
Input/
pullup
enabled SCL1 — The I2C1 serial clock.
Open-drain
Output
Output
XB_OUT2 — Crossbar module output 2
GPIOF3
(SDA1)
(XB_OUT3)
After reset, the default state is GPIOF2.
40 Input/
Input, Port F GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
Input/
pullup
enabled SDA1 — The I2C1 serial data line.
Open-drain
Output
Output
XB_OUT3 — Crossbar module output 3
GPIOF4
(TXD1)
(XB_OUT4)
After reset, the default state is GPIOF3.
41 Input/
Input, Port F GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Output enabled TXD1 — The SCI1 transmit data output or transmit/receive in single
wire operation.
Output
XB_OUT4 — Crossbar module output 4
GPIOF5
(RXD1)
(XB_OUT5)
After reset, the default state is GPIOF4.
42 Input/
Input, Port F GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Output enabled RXD1 — The SCI1 receive data input.
Output
XB_OUT5 — Crossbar module output 5
After reset, the default state is GPIOF5.
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Memory Maps
Table 5. MC56F825x/MC56F824x Signal and Package Information (continued)
Signal
Name
44 48 64
LQFP LQFP LQFP
Type
GPIOF6
(TB2)
(PWM3X)
58 Input/
Output
Input/
Output
Input/
Output
State
During
Reset
Signal Description
Input,
internal
pullup
enabled
Port F GPIO — This GPIO pin can be individually programmed as
an input or output pin.
TB2 — Quad timer module B channel 2 input/output.
PWM3X — Enhanced PWM submodule 3 output X or input capture
X
GPIOF7
(TB3)
GPIOF8
(RXD0)
After reset, the default state is GPIOF6.
59 Input/
Input, Port F GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input/ enabled TB3 — Quad timer module B channel 3 input/output.
Output
After reset, the default state is GPIOF7.
6 Input/
Input, Port F GPIO — This GPIO pin can be individually programmed as
Output internal an input or output pin.
pullup
Input
enabled RXD0 — The SCI0 receive data input.
(TB1)
Input/
Output
TB1 — Quad timer module B channel 1 input/output.
After reset, the default state is GPIOF8.
1 If CLKIN is selected as the device’s external clock input, both the GPS_C0 bit in GPS1 and the EXT_SEL bit in the OCCS
oscillator control register (OSCTL) must be set. In this case, it is also recommended to power down the crystal oscillator.
4 Memory Maps
4.1 Introduction
The MC56F825x/MC56F824x device is based on the 56800E core. It uses a dual Harvard-style architecture with two
independent memory spaces for data and program. On-chip RAM is shared by both data and program spaces; flash memory is
used only in program space.
This section provides memory maps for:
• Program address space, including the interrupt vector table
• Data address space, including the EOnCE memory and peripheral memory maps
On-chip memory sizes for the device are summarized in Table 6. Flash memories’ restrictions are identified in the “Use
Restrictions” column of Table 6.
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Memory Maps
Table 6. Chip Memory Configurations
On-Chip Memory
56F8245
56F8246
Program Flash
(PFLASH)
Unified RAM
(RAM)
24K x 16
or
48 KB
3K x 16
or
6 KB
56F8247
24K x 16
or
48 KB
4K x 16
or
8 KB
56F8255
56F8256
56F8357
Use Restrictions
32K x 16 Erase/program via flash interface unit and word writes to CDBW
or
64 KB
4K x 16
or
8 KB
Usable by the program and data memory spaces
4.2 Program Map
The MC56F825x/MC56F824x series provide up to 64 KB on-chip flash memory. It primarily accesses through the program
memory buses (PAB; PDB). PAB is used to select program memory addresses; instruction fetches are performed over PDB.
Data can be read from and written to the program memory space through the primary data memory buses: CDBW for data write
and CDBR for data read. Access time for accessing the program memory space over the data memory buses is longer than for
accessing data memory space. The special MOVE instructions are provided to support these accesses. The benefit is that
non-time-critical constants or tables can be stored and accessed in program memory.
The program memory map appears in Table 7, Table 8, and Table 9, depending on the device.
Table 7. Program Memory Map1 for 56F8255/56/57 at Reset
Begin/End Address
Memory Allocation
P: 0x1F FFFF
P: 0x00 8800
P: 0x00 8FFF
P: 0x00 8000
RESERVED
On-chip RAM2: 8 KB
P: 0x00 7FFF
P: 0x00 0000
• Internal program flash: 64 KB
• Interrupt vector table locates from 0x00 0000 to 0x00 0085
• COP reset address = 0x00 0002
• Boot location = 0x00 0000
1 All addresses are 16-bit word addresses.
2 This RAM is shared with data space starting at address X: 0x00 0000. See Figure 6.
Table 8. Program Memory Map1 for 56F82447 at Reset
Begin/End Address
P: 0x1F FFFF
P: 0x00 8800
P: 0x00 8FFF
P: 0x00 8000
P: 0x00 7FFF
P: 0x00 2000
P: 0x00 2000
P: 0x00 0000
RESERVED
On-chip RAM2: 8 KB
Memory Allocation
• Internal program flash: 48 KB
• Interrupt vector table locates from 0x00 2000 to 0x00 2085
• COP reset address = 0x00 2002
• Boot location = 0x00 2000
RESERVED
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