MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Features
NAND Flash Memory MLC
MT29F8G08MAAWC, MT29F8G08MAAWP,
MT29F16G08QAAWC,MT29F32G08TAAWC
Features
• Organization
Page size
x8: 2,112 bytes (2,048 + 64 bytes)
Block size: 128 pages (256K + 8K bytes)
Plane size: 2,048 blocks
Device size: 8Gb: 4,096 blocks; 16Gb: 8,192 blocks;
32Gb: 16,384 blocks
• READ performance
Random READ: 50µs
Sequential READ: 25ns
• WRITE performance
PROGRAM PAGE: 650µs (TYP)
BLOCK ERASE: 2ms (TYP)
• Endurance: 10,000 PROGRAM/ERASE cycles
(with ECC and invalid block mapping)
• First block (block address 00h) guaranteed to be
valid with ECC when shipped from factory
• Industry-standard basic NAND Flash command set
• New commands
PAGE READ CACHE MODE
TWO-PLANE/MULTIPLE-DIE READ STATUS
Two-plane commands for concurrent-plane oper-
ations
READ UNIQUE ID (contact factory)
READ ID2 (contact factory)
• Operation status byte provides a software method of
detecting:
PROGRAM/ERASE/READ operation completion
PROGRAM/ERASE pass/fail condition
Write-protect status
• Ready/busy# (R/B#) signal provides a hardware
method of detecting PROGRAM, READ, or ERASE
cycle completion
• WP# signal: Entire device hardware write protect
• Staggered power-up sequence: Issue RESET (FFh)
command
Figure 1: 48-Pin TSOP Type 1
Options
• Density1
8Gb (single-die stack)
16Gb (dual-die stack)
32Gb (quad-die stack)
• Device width: x8
• Configuration
# of die # of # of
I/O
CE# R/B#
11
1
Common
22
2
Common
42
2
Common
• VCC: 2.7–3.6V
• First-generation die
• Package
48-pin TSOP type I (lead-free plating)
48-pin TSOP type I OCPL2 (lead-free plating)
• Operating temperature
Commercial (0°C to 70°C)
Extended (–40°C to +85°C)3
Notes: 1. For part numbering and markings, see
Figure 2 on page 2.
2. OCPL = off-center parting line.
3. For ET devices.
MLC PDF: 09005aef828313aa / Source: 09005aef82831392
8gb_nand_l41b_mlc__1.fm - Rev. B 11/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
www.DataSheet.in


MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

No Preview Available !

Click to Download PDF File for PC

Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Part Numbering Information
Part Numbering Information
Micron NAND Flash devices are available in several different configurations and densi-
ties (see Figure 2).
Figure 2: Part Number Chart
MT 29F 8G 08 M A A WC
Micron Technology
Product Family
29F = Single-supply NAND Flash memory
Density
8G = 8Gb
16G = 16Gb
32G = 32Gb
Device Width
08 = 8 bits
Classification
# of die # of CE# # of R/B#
I/O
M1
1
1 Common
Q2
2
2 Common
T4
2
2 Common
Operating Voltage Range
A = 3.3V (2.70–3.60V)
Feature Set
A = First
B = Second
C = Third
ES :B
Design Revision
A = First generation
B = Second generation
Production Status
Blank = Production
ES = Engineering sample
MS = Mechanical sample
QS = Qualification sample
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
ET = Extended (–40°C to +85°C)
Reserved for Future Use
Blank
Flash Performance
Blank = Standard
Package Codes
WC = 48-pin TSOP 1 OCPL (lead-free)
WP = 48-pin TSOP 1 CPL (lead-free)
Valid Part Number Combinations
After building the part number from the part numbering chart, verify that the part
number is offered and valid by using the Micron Parametric Part Search Web site:
www.micron.com/products/parametric. If the device required is not on this list, contact
the factory.
MLC PDF: 09005aef828313aa / Source: 09005aef82831392
8gb_nand_l41b_mlc__1.fm - Rev. B 11/07 EN
www.DataSheet.in
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.


MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

No Preview Available !

Click to Download PDF File for PC

Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PAGE READ 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
RANDOM DATA READ 05h-E0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PAGE READ CACHE MODE Start 31h; PAGE READ CACHE MODE Start Last 3Fh . . . . . . . . . . . . . . . . . . . 24
READ ID 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
READ STATUS 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PROGRAM PAGE 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SERIAL DATA INPUT 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PROGRAM PAGE CACHE MODE 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Internal Data Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
READ FOR INTERNAL DATA MOVE 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PROGRAM for INTERNAL DATA MOVE 85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
BLOCK ERASE 60h-D0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Two-Plane Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Two-Plane Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TWO-PLANE PAGE READ 00h-00h-30h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TWO-PLANE RANDOM DATA READ 06h-E0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TWO-PLANE PROGRAM PAGE 80h-11h-80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TWO-PLANE RANDOM DATA INPUT 80h-85h-11h (or 80h-85h-10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TWO-PLANE PROGRAM PAGE CACHE MODE 80h-11h-80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TWO-PLANE INTERNAL DATA MOVE 00h-00h-35h/85h-11h-80h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TWO-PLANE READ for INTERNAL DATA MOVE 00h-00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TWO-PLANE PROGRAM for INTERNAL DATA MOVE 85h-11h-80h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TWO-PLANE BLOCK ERASE 60h-60h-D0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TWO PLANE/MULTIPLE-DIE READ STATUS 78h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interleaved Die Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interleaved PAGE READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interleaved TWO-PLANE PAGE READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interleaved PROGRAM PAGE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interleaved PROGRAM PAGE CACHE MODE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interleaved TWO-PLANE PROGRAM PAGE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interleaved BLOCK ERASE Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
MLC PDF: 09005aef828313aa / Source: 09005aef82831392
8gb_nand_l41b_mlcTOC.fm - Rev. B 11/07 EN
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
www.DataSheet.in


MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

No Preview Available !

Click to Download PDF File for PC

Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Table of Contents
Interleaved TWO-PLANE BLOCK ERASE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
WRITE PROTECT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
VCC Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MLC PDF: 09005aef828313aa / Source: 09005aef82831392
8gb_nand_l41b_mlcTOC.fm - Rev. B 11/07 EN
www.DataSheet.in
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.


MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

No Preview Available !

Click to Download PDF File for PC

Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
List of Figures
List of Figures
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48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
NAND Flash Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Assignment (Top View) 48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory Map x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Array Organization for MT29F8G08MAA and MT29F16G08QAA (x8). . . . . . . . . . . . . . . . . . . . . . . . 13
Array Organization for MT29F32G08TAA (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
tFall and tRise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PAGE READ CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PROGRAM PAGE CACHE MODE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TWO-PLANE PAGE READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TWO-PLANE PAGE READ with RANDOM DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TWO-PLANE PROGRAM PAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TWO-PLANE PROGRAM PAGE CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TWO-PLANE INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . 44
TWO-PLANE BLOCK ERASE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interleaved PAGE READ with R/B# Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interleaved PAGE READ with Status Register Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interleaved TWO-PLANE PAGE READ with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interleaved TWO-PLANE PAGE READ with Status Register Monitoring . . . . . . . . . . . . . . . . . . . . . 50
Interleaved PROGRAM PAGE with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interleaved PROGRAM PAGE with Status Register Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interleaved PROGRAM PAGE CACHE MODE with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . 52
Interleaved PROGRAM PAGE CACHE MODE with Status Register Monitoring . . . . . . . . . . . . . . . 52
Interleaved TWO-PLANE PROGRAM PAGE with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interleaved TWO-PLANE PROGRAM PAGE with Status Register Monitoring . . . . . . . . . . . . . . . . 54
Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE with R/B# Monitoring . . . . . . . . . . . 55
Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE with Status Register Monitoring . . 56
Interleaved BLOCK ERASE with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interleaved BLOCK ERASE with Status Register Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interleaved TWO-PLANE BLOCK ERASE with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interleaved TWO-PLANE BLOCK ERASE with Status Register Monitoring . . . . . . . . . . . . . . . . . . . 59
RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PROGRAM for INTERNAL DATA MOVE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PROGRAM for INTERNAL DATA MOVE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TWO-PLANE ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TWO-PLANE ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
MLC PDF: 09005aef828313aa / Source: 09005aef82831392
8gb_nand_l41b_mlcLOF.fm - Rev. B 11/07 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
www.DataSheet.in


MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
List of Figures
Figure 57:
Figure 58:
Figure 59:
Figure 60:
Figure 61:
Figure 62:
Figure 63:
Figure 64:
Figure 65:
Figure 66:
Figure 67:
Figure 68:
Figure 69:
Figure 70:
Figure 71:
Figure 72:
Figure 73:
Figure 74:
Figure 75:
Figure 76:
Figure 77:
Figure 78:
Figure 79:
Figure 80:
Figure 81:
Figure 82:
Figure 83:
Figure 84:
TWO-PLANE PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
TWO-PLANE PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
TWO-PLANE PROGRAM for INTERNAL DATA MOVE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
TWO-PLANE PROGRAM for INTERNAL DATA MOVE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
AC Waveforms During Power Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
INPUT DATA LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SERIAL ACCESS Cycle After READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
READ STATUS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
READ Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PAGE READ CACHE MODE Operation, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PAGE READ CACHE MODE Operation, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PAGE READ CACHE MODE Operation without R/B#, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PAGE READ CACHE MODE Operation without R/B#, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PROGRAM Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PROGRAM PAGE Operation with RANDOM DATA INPUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
INTERNAL DATA MOVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PROGRAM PAGE CACHE MODE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PROGRAM PAGE CACHE MODE Operation Ending on 15h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
48-Pin TSOP Type 1 OCPL (WC Package Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
48-Pin TSOP Type 1 CPL (WP Package Code). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
MLC PDF: 09005aef828313aa / Source: 09005aef82831392
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6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
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MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Signal/Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operational Example (8Gb x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Array Addressing: MT29F8G08MAA and MT29F16G08QAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Array Addressing: MT29F32G08TAA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Two-Plane Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device ID and Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Status Register Contents After RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Absolute Maximum Ratings by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
M29FxGxx Device DC and Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AC Characteristics – Command, Data, and Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AC Characteristics – Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
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MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
General Description
General Description
NAND Flash technology provides a cost-effective solution for applications requiring
high-density, solid-state storage. The MT29F8G08 is an 8Gb NAND Flash memory
device. The MT29F16G08 is a two-die stack that operates as two independent 8Gb
devices (MT29F8G08). The MT29F32G08 is a four-die stacked device that operates as
two independent 16Gb devices (MT29F16G08), providing a total storage capacity of
32Gb in a single, space-saving package. Micron® NAND Flash devices include standard
NAND Flash features as well as new features designed to enhance system-level perfor-
mance.
These NAND Flash devices utilize multilevel cell (MLC) technology. Each memory cell
stores 2 bits of information.
Micron NAND Flash devices use a highly multiplexed 8-bit bus (I/O[7:0]) to transfer
data, addresses, and instructions. The five command signals (CLE, ALE, CE#, RE#, WE#)
implement the NAND Flash command bus interface protocol. Two additional signals
control hardware write protection (WP#) and monitor device status (R/B#).
This hardware interface creates a low-pin-count device with a standard pinout that is
the same from one density to another, allowing future upgrades to higher densities with-
out board redesign.
The MT29FxG devices contain two planes per die. Each plane consists of 2,048 blocks.
Each block is subdivided into 128 programmable pages. Each page consists of 2,112
bytes (x8). The pages are further divided into a 2,048-byte data storage region with a sep-
arate 64-byte area on the x8 device. The 64-byte area is typically used for error manage-
ment functions.
The contents of each 2,112-byte page can be programmed in tPROG (TYP), and an entire
264K-byte block can be erased in tBERS (TYP). On-chip control logic automates PRO-
GRAM and ERASE operations to maximize cycle endurance. PROGRAM/ERASE endur-
ance is specified at 10,000 cycles when appropriate error correction code (ECC) and
error management are used.
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8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.


MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
General Description
Figure 3: NAND Flash Functional Block Diagram
VCC VSS
I/O [7:0]
I/O
Control
Address Register
Status Register
CE#
CLE
ALE
WE#
RE#
WP#
R/B#
Command Register
Control
Logic
Column Decode
Data Register
Cache Register
Figure 4: Pin Assignment (Top View) 48-Pin TSOP Type 1
x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
DNU
DNU
DNU
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
x8
48 DNU
47 NC
46 NC
45 NC
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 NC
39 NC
38 DNU
37 VCC
36 VSS
35 NC
34 NC
33 NC
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 NC
27 NC
26 DNU
25 DNU
Notes: 1. CE2# and R/B2# on 16Gb and 32Gb device only. These pins are NC for other configurations.
MLC PDF: 09005aef828313aa / Source: 09005aef82831392
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9 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.


MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
General Description
Table 1: Signal/Pin Descriptions
Symbol
ALE
CE#, CE2#
CLE
RE#
WE#
WP#
I/O[7:0]
MT29FxG08
R/B#, R/B2#
VCC
VSS
NC
DNU
Type
Input
Input
Input
Input
Input
Input
I/O
Output
Supply
Supply
Function
Address latch enable: During the time ALE is HIGH, address information is
transferred from I/O[7:0] into the on-chip address register on the rising edge of
WE#. When address information is not being loaded, ALE should be driven LOW.
Chip enable: CE# and CE2# are used to gate transfers between the host system
and the NAND Flash device. After the device starts a PROGRAM or ERASE
operation, chip enable(s) can be de-asserted. For the 16Gb configuration, CE#
controls the first 8Gb of memory, and CE2E controls the second 8Gb. For the 32Gb
configuration, CE# controls the first 16Gb of memory; CE2# controls the second
16Gb. See “Bus Operation” on page 15 for additional operational details.
Command latch enable: When CLE is HIGH, information is transferred from
I/O[7:0] to the on-chip command register on the rising edge of WE#. When
command information is not being loaded, CLE should be driven LOW.
Read enable: RE# is used to gate transfers from the NAND Flash device to the host
system.
Write enable: WE# is used to gate transfers from the host system to the NAND
Flash device.
Write protect: WP# protects against inadvertent PROGRAM and ERASE
operations. All PROGRAM and ERASE operations are disabled when the WP# is
LOW.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction
information. Data is output only during READ operations; at other times the I/Os
are inputs.
Ready/busy: This is an open-drain, active-LOW output that uses an external pull-
up resistor. R/B# and R/B2# are used to indicate when the chip is processing a
PROGRAM or ERASE operation. R/B# and R/B2# are also used during READ
operations to indicate when data is being transferred from the array into the
serial data register. After these operations have completed, the R/B# returns to
the high-impedance state. In the 16Gb configuration, R/B# is used for the 8Gb of
memory enabled by CE#, and R/B2# is used for the 8Gb of memory enabled by
CE2#. In the 32Gb configuration, R/B# used is for the 16Gb of memory enabled by
CE#, and R/B2# is used for the 16Gb of memory enabled by CE2#.
VCC: The VCC pin is the power supply pin.
VSS: The VSS pin is the ground connection.
No connect: NC pins are not internally connected. These pins can be driven or left
unconnected.
Do not use: These pins must be left disconnected.
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10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.


MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Architecture
Addressing
Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins. This provides a memory device with
a low pin count.
The internal memory array is accessed on a page basis. For reads, a page of data is cop-
ied from the memory array into the data register. After being copied to the data register,
data is output sequentially, byte by byte on x8 devices.
The memory array is programmed on a page basis. After the starting address is loaded
into the internal address register, data is sequentially written to the internal data register
up to the end of a page. After all of the page data has been loaded into the data register,
array programming is started.
In order to increase programming bandwidth, this device incorporates a cache register.
In the cache programming mode, data is first copied into the cache register and then
into the data register. After the data is copied into the data register, programming begins.
After the data register has been loaded and programming started, the cache register
becomes available for loading additional data. Loading of the next page of data into the
cache register takes place while page programming is in process.
The INTERNAL DATA MOVE command also uses the internal cache register. Normally,
moving data from one area of external memory to another requires a large number of
external memory cycles. When the internal cache register and data register are used,
array data can be copied from one page and then programmed into another without
requiring external memory cycles.
NAND Flash devices do not contain dedicated address pins. Addresses are loaded using
a 5-cycle sequence, as shown in Figures 6 and 7 on pages 13 and 14. Table 3 on page 13
presents address functions internal to the x8 device. See Figure 5 on page 12 for addi-
tional memory mapping and addressing details.
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MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Addressing
Figure 5: Memory Map x8
Blocks
8Gb, 16Gb: BA[18:7] 0 1
32Gb: BA[19:7]
2 • • • • • • • • • • • • 4,095
32Gb: 8,192 blocks per CE#
Pages
PA[6:0] 0 1 2 • • • 127
Bytes
CA[11:0] 0 1 2 • • • • • • • • • • • • • • • • • • • 2,047 • • • 2,111
Spare area
Table 2:
Block
0
0
0
...
4,095
4,095
Operational Example (8Gb x8)
Page
0
1
2
...
126
127
Min Address in Page
0x00000000
0x00010000
0x00020000
...
0x7FFFE0000
0x7FFFF0000
Max Address in Page
0x0000083F
0x0001083F
0x0002083F
...
0x7FFFE083F
0x7FFFF083F
Out-of-Bounds Addresses in Page
0x00000840-0x00000FFF
0x00010840-0x00010FFF
0x00020840-0x00020FFF
...
0x7FFFE0840-0x7FFFE0FFF
0x7FFFF0840-0x7FFFF0FFF
Notes: 1. As shown in Table 3 on page 13, the high nibble of address cycle 2 has no assigned address
bits; however, these 4 bits must be held LOW during the address cycle to ensure that the
address is interpreted correctly by the NAND Flash device. These extra bits are accounted
for in address cycle 2 even though they have no address bits assigned to them.
2. Block address concatenated with page address = row address.
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NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Addressing
Figure 6: Array Organization for MT29F8G08MAA and MT29F16G08QAA (x8)
Cache Register
Data Register
2,112 bytes
2,048
2,048
64
64
2,112 bytes
2,048
2,048
64
64
I/O7
I/O0
2,048 blocks
per plane
4,096 blocks
per device
1 block
1 block
1 page
1 block
= (2K + 64 bytes)
= (2K + 64) bytes x 128 pages
= (256K + 8K) bytes
1 plane = (256K + 8K) bytes x 2,048 blocks
= 4,224Mb
1 device = 4,224Mb x 2 planes
= 8,448Mb
Plane of
even-numbered blocks
(0, 2, 4, 6, ..., 4,092, 4,094)
Plane of
odd-numbered blocks
(1, 3, 5, 7, ..., 4,093, 4,095)
Table 3:
Cycle
First
Second
Third
Fourth
Fifth
Note:
For the 16Gb MT29F16G08QAA, the 8Gb array organization shown applies to each chip
enable (CE# and CE2#).
Array Addressing: MT29F8G08MAA and MT29F16G08QAA
I/O7
CA7
LOW
BA73
BA15
LOW
I/O6
CA6
LOW
PA6
BA14
LOW
I/O5
CA5
LOW
PA5
BA13
LOW
I/O4
CA4
LOW
PA4
BA12
LOW
I/O3
CA3
CA11
PA3
BA11
LOW
I/O2
CA2
CA10
PA2
BA10
BA18
I/O1
CA1
CA9
PA1
BA9
BA17
I/O0
CA0
CA8
PA0
BA8
BA16
Notes: 1. Block address concatenated with page address = actual page address. CAx = column
address; PAx = page address; BAx = block address.
2. If CA11 is “1,” then CA[10:6] must be “0.” This keeps a MAX limit of 2,112 bytes addressed
per page.
3. Plane select bit.
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NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Addressing
Figure 7:
Array Organization for MT29F32G08TAA (x8)
Die 0
Die 1
Cache Register
Data Register
2,112 bytes
2,112 bytes
2,048
2,048
64 2,048
64 2,048
64
64
2,112 bytes
2,048
2,048
64
64
2,112 bytes
2,048
2,048
64
64
4,096 blocks
per plane
8,192 blocks
per die
1 block
1 block
1 block
1 block
Plane 0: even-
numbered blocks
(0, 2, 4, 6, ...,
4,092, 4,094)1
Plane 1: odd-
numbered blocks
(1, 3, 5, 7, ...,
4,093, 4,095)2
Plane 0: even-
numbered blocks
(4,096, 4,098, ...,
8,188, 8,190)3
Plane 1: odd-
numbered blocks
(4,097,4,099, ...,
8,189, 8,191)4
I/O7
I/O0
1 page = (2K + 64 bytes)
1 block = (2K + 64) bytes x 128 pages
= (256K + 8K) bytes
1 plane = (256K + 8K) bytes x 2,048 blocks
= 4,224Mb
1 die = 4,224Mb x 2 planes
= 8,448Mb
1 device = 8,448Mb x 2 die
= 16,896Mb
Table 4:
Cycle
First
Second
Third
Fourth
Fifth
Notes: 1. Die 0, Plane 0: BA19 = 0; BA7 = 0
2. Die 0, Plane 1: BA19 = 0; BA7 = 1
3. Die 1, Plane 0: BA19 = 1; BA7 = 0
4. Die 1, Plane 1: BA19 = 1; BA7 = 1
5. For the 32Gb MT29F32G08TAA, the 16Gb array organization shown applies to each chip
enable (CE# and CE2#).
Array Addressing: MT29F32G08TAA
I/O7
CA7
LOW
BA74
BA15
LOW
I/O6
CA6
LOW
PA6
BA14
LOW
I/O5
CA5
LOW
PA5
BA13
LOW
I/O4
CA4
LOW
PA4
BA12
LOW
I/O3
CA3
CA11
PA3
BA11
BA193
I/O2
CA2
CA10
PA2
BA10
BA18
I/O1
CA1
CA9
PA1
BA9
BA17
I/O0
CA0
CA8
PA0
BA8
BA16
Notes: 1. CAx = column address; PAx = page address; BAx = block address.
2. If CA11 is “1,” then CA[10:6] must be “0.” This keeps a MAX limit of 2,112 bytes addressed
per page.
3. Die address boundary: 0 = 0–8Gb; 1 = 8Gb–16Gb.
4. Plane select bit.
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NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Bus Operation
Bus Operation
The bus on the MT29Fxxx devices is multiplexed. Data I/O, addresses, and commands
all share the same pins.
The command sequence normally consists of a COMMAND LATCH cycle, an address
LATCH cycle, and a DATA cycle—either READ or WRITE.
Control Signals
CE#, WE#, RE#, CLE, ALE, and WP# control Flash device READ and WRITE operations.
On the 16Gb MT29F16G devices, CE# and CE2# each control an independent 8Gb array.
On the 32Gb MT29F32G devices, CE# and CE2# each control independent 16Gb arrays.
CE2# functions the same as CE# for its own array; all operations described for CE# also
apply to CE2#.
CE# is used to enable a device. When CE# is LOW and the device is not in the busy state,
the Flash memory will accept command, data, and address information.
When the device is not performing an operation, CE# is typically driven HIGH and the
device enters standby mode. The memory will enter standby if CE# goes HIGH while
data is being transferred and the device is not busy. This helps reduce power consump-
tion. See Figure 68 on page 74 and Figure 75 on page 80 for examples of CE# “Don’t Care”
operations.
The CE# “Don’t Care” operation allows the NAND Flash to reside on the same asynchro-
nous memory bus as other Flash or SRAM devices. Other devices on the memory bus
can then be accessed while the NAND Flash is busy with internal operations. This capa-
bility is important for designs that require multiple NAND Flash devices on the same
bus. One device can be programmed while another is being read.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an address input cycle is occurring.
Commands
Commands are written to the command register on the rising edge of WE# when:
• CE# and ALE are LOW, and
• CLE is HIGH, and
• the device is not busy.
As exceptions, the device accepts the READ STATUS, TWO-PLANE/MULTIPLE-DIE
READ STATUS and RESET commands when busy. Commands are transferred to the
command register on the rising edge of WE# (see Figure 62 on page 71).
Address Input
Addresses are written to the address register on the rising edge of WE# when:
• CE# and CLE are LOW, and
• ALE is HIGH.
See Figure 63 on page 71 for additional address input details.
The number of address cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements. See Tables 6 and 7 on pages 20 and
21.
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NAND Flash Memory MLC

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Data Input
READ
Ready/Busy#
Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Bus Operation
Data is written to the data register on the rising edge of WE# when:
• CE#, CLE, and ALE are LOW, and
• the device is not busy.
See Figure 64 on page 72 for additional data input details.
After a READ command is issued, data is transferred from the memory array to the data
register from the rising edge of WE#. R/B# goes LOW for tR and transitions HIGH after
the transfer is complete. When data is available in the data register, it is clocked out of
the device by RE# going LOW. See Figure 67 on page 74 for detailed timing information.
The READ STATUS (70h) or TWO-PLANE/MULTIPLE-DIE READ STATUS (78h) com-
mand or the R/B# signal can be used to determine when the device is ready.
The R/B# output provides a hardware method of indicating the completion of PRO-
GRAM, ERASE, and READ operations. The signal requires a pull-up resistor for proper
operation. The signal is typically HIGH, and it transitions to LOW after the appropriate
command is written to the device. The signal’s open-drain driver enables multiple R/B#
outputs to be OR-tied. The READ STATUS command can be used in place of R/B#. Typi-
cally, R/B# would be connected to an interrupt pin on the system controller (see Figure 8
on page 17).
On 16Gb MT29F16G devices, R/B# indicates the 8Gb section enabled by CE#, and R/B2#
does the same for the 8Gb section enabled by CE2#. R/B# and R/B2# can be tied
together, or they can be used separately to provide independent indications for each
8Gb section.
On 32Gb MT29F32G devices, R/B# indicates the 16Gb section enabled by CE#, and
R/B2# does the same for the 16Gb section enabled by CE2#. R/B# and R/B2# can be tied
together, or they can be used separately to provide independent indications for each
16Gb section.
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# signal. The actual value used for Rp depends on system timing require-
ments. Large values of Rp cause R/B# to be delayed significantly. At the 10- to 90-percent
points on the R/B# waveform, rise time is approximately two time constants (TC).
TC = R × C
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# signal and the total load capacitance.
Figure 9 on page 17 and Figure 10 on page 18 depict approximate Rp values for a circuit
load of 100pF.
The minimum value for Rp is determined by the output drive capability of the R/B# sig-
nal, the output voltage swing, and VCC.
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MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Bus Operation
Rp
=
V----C----C----(--M-----A----X-----)---–-----V----O---L---(---M-----A----X----)-
IOL + ΣIL
=
--------3---.--2---V----------
8mA + ΣIL
Where ΣIL is the sum of the input currents of all devices tied to the R/B# pin.
Figure 8: READY/BUSY# Open Drain
Rp
VCC
R/B#
Open drain output
GND
IOL
Device
Figure 9: tFall and tRise
3.50
3.00
2.50
2.00
V
1.50
tFall tRise
1.00
0.50
0.00
-1 0 2 4 0 2 4 6
TC Vcc 3.3
Notes: 1. tFall and tRise are calculated at 10 percent–90 percent points.
2. tRise is dependent on external capacitance and resistive loading and output transistor
impedance.
3. tRise is primarily dependent on external pull-up resistor and external capacitive loading.
4. tFall 10ns at 3.3V.
5. See TC values in Figure 11 on page 18 for approximate Rp value and TC.
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NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Bus Operation
Figure 10: IOL vs. Rp
3.50mA
3.00mA
2.50mA
2.00mA
1.50mA
1.00mA
0.50mA
0.00mA
0
2,000
4,000
6,000 8,000 10,000 12,000
Rp
IOL at 3.60V (MAX)
Note:
Figure 11: TC vs. Rp
To calculate Rp value, see page 16.
1.20µs
1.00µs
800ns
T
600ns
400ns
200ns
0ns
0
2kΩ 4kΩ 6kΩ 8kΩ 10kΩ 12kΩ
Rp
IOL at 3.60V (MAX)
RC = TC
C = 100pF
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NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Bus Operation
Table 5:
CLE
H
L
H
L
L
L
X
X
X
X
X
Mode Selection
ALE CE#
LL
WE#
RE# WP#1 Mode
H X Read mode
Command input
HL
HX
Address input
LL
H H Write mode
Command input
HL
HH
Address input
LL
H H Data input
L LH
X Sequential read and data output
X X X H X During read (busy)
X X X X H During program (busy)
X X X X H During erase (busy)
X X X X L Write protect
X H X X 0V/VCC Standby
Notes: 1. WP# should be biased to CMOS HIGH or LOW for standby.
2. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW;
X = VIH or VIL.
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MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Command Definitions
Command Definitions
Table 6: Command Set
Operation
PAGE READ
PAGE READ CACHE MODE
PAGE READ CACHE MODE LAST
READ for INTERNAL DATA MOVE
RANDOM DATA READ
READ ID
READ STATUS
PROGRAM PAGE
PROGRAM PAGE CACHE MODE
PROGRAM for INTERNAL DATA MOVE
RANDOM DATA INPUT
BLOCK ERASE
RESET
Command
Cycle 1
00h
31h
3Fh
00h
05h
90h
70h
80h
80h
85h
85h
60h
FFh
Number of
Address
Cycles
5
5
2
1
5
5
5
2
3
Data
Cycles
Required1
No
No
No
No
No
No
No
Yes
Yes
Optional
Yes
No
No
Command
Cycle 2
30h
35h
E0h
10h
15h
10h
D0h
Valid
During
Busy
No
No
No
No
No
No
Yes
No
No
No
No
No
Yes
Notes
2
2
3
4
3
5
Notes: 1. Indicates required DATA cycles between COMMAND cycle 1 and COMMAND cycle 2.
2. Do not cross block address boundaries when using PAGE READ CACHE MODE operations.
See Table 4 on page 14 for die address boundary definitions.
3. Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE and
PROGRAM for INTERNAL DATA MOVE. See Table 4 on page 14 for die address boundary
definitions.
4. RANDOM DATA READ command is limited to use within a single page.
5. RANDOM DATA INPUT command is limited to use within a single page.
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NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Command Definitions
Table 7: Two-Plane Command Set
Operation
Number of
Number of
Valid
Command Address Command Address Command During
Cycle 1
Cycles
Cycle 2
Cycles
Cycle 3 Busy Notes
TWO-PLANE PAGE READ
TWO-PLANE READ for INTERNAL DATA
MOVE
TWO-PLANE RANDOM DATA READ
TWO-PLANE/MULTIPLE-DIE READ
STATUS
TWO-PLANE PROGRAM PAGE
TWO-PLANE PROGRAM PAGE CACHE
MODE
TWO-PLANE PROGRAM for INTERNAL
DATA MOVE
TWO-PLANE BLOCK ERASE
00h
00h
06h
78h
80h
80h
85h
60h
5 00h 5
5 00h 5
5 E0h –
3––
5 11h-80h 5
5 11h-80h 5
5 11h-80h 5
3 60h 3
30h No
35h No 1
– No 2
– Yes
10h No
15h No 3
10h No 1
D0h No
Notes: 1. Do not cross plane address boundaries when using TWO-PLANE READ for INTERNAL DATA
MOVE and TWO-PLANE PROGRAM for INTERNAL DATA MOVE. See Table 4 on page 14 for
die address boundary definitions.
2. TWO-PLANE RANDOM DATA READ command is limited to use within a single page.
3. Do not cross block address boundaries when using cache operations. See Table 4 on
page 14 for die address boundary definitions.
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NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Command Definitions
READ Operations
PAGE READ 00h-30h
To enter READ mode while the device is in operation, write the 00h command to the
command register, then write 5 address cycles, and conclude with the 30h command.
To determine the progress of the data transfer from the Flash array to the data register
(tR), monitor the R/B# signal, or, alternatively, issue a READ STATUS command. If the
READ STATUS command is used to monitor the data transfer, the user must re-issue the
READ (00h) command to receive data output from the data register (see Figure 72 on
page 78 and Figure 73 on page 79 for examples). After the READ command has been re-
issued, pulsing the RE# line will result in outputting data, starting from the initial col-
umn address.
A serial page read sequence outputs a complete page of data. After 30h is written, the
page data is transferred to the data register, and R/B# goes LOW during the transfer.
When the transfer to the data register is complete, R/B# returns HIGH. At this point, data
can be read from the device. Starting from the initial column address and going to the
end of the page, read the data by repeatedly pulsing RE# at the maximum tRC rate (see
Figure 12).
Figure 12: PAGE READ Operation
CLE
CE#
WE#
ALE
R/B#
tR
RE#
I/Ox 00h
Address (5 cycles)
30h
Data output (Serial access)
Don‘t Care
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NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Command Definitions
RANDOM DATA READ 05h-E0h
The RANDOM DATA READ command enables the user to specify a new column address
so the data at single or multiple addresses can be read. The random read mode is
enabled after a normal PAGE READ (00h-30h sequence).
Random data can be output after the initial page read by writing an 05h-E0h command
sequence along with the new column address (2 cycles).
The RANDOM DATA READ command can be issued without limit within the page.
Only data on the current page can be read. Pulsing RE# outputs data sequentially (see
Figure 13).
Figure 13: RANDOM DATA READ Operation
R/B#
tR
RE#
I/Ox
00h
Address
(5 cycles)
30h
Data output
05h
Address
(2 cycles)
E0h
Data output
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NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Command Definitions
PAGE READ CACHE MODE Start 31h; PAGE READ CACHE MODE Start Last 3Fh
Micron NAND Flash devices have a cache register that can be used to increase the READ
operation speed when accessing sequential pages in a block.
First, a normal PAGE READ (00h-30h) command sequence is issued (see Figure 14 on
page 25 for operation details). The R/B# signal goes LOW for tR during the time it takes
to transfer the first page of data from the memory to the data register. After R/B# returns
to HIGH, the PAGE READ CACHE MODE START (31h) command is latched into the com-
mand register. R/B# goes LOW for tDCBSYR1 while data is being transferred from the
data register to the cache register. After the data register contents are transferred to the
cache register, another PAGE READ is automatically started as part of the 31h command.
Data is transferred from the next sequential page of the memory array to the data regis-
ter during the same time data is being read serially (pulsing of RE#) from the cache regis-
ter. If the total time to output data exceeds tR, then the PAGE READ is hidden.
The second and subsequent pages of data are transferred to the cache register by issuing
additional 31h commands. R/B# will stay LOW up to tDCBSYR2. This time can vary,
depending on whether the previous memory-to-data-register transfer was completed
prior to issuance of the next 31h command (see Table 18 on page 69 for timing parame-
ters). If the data transfer from memory to the data register is not completed before the
31h command is issued, R/B# stays LOW until the transfer is complete.
It is not necessary to output a whole page of data before issuing another 31h command.
R/B# will stay LOW until the previous PAGE READ is complete and the data has been
transferred to the cache register.
To read out the last page of data, the PAGE READ CACHE MODE START LAST (3Fh) com-
mand is issued. This command transfers data from the data register to the cache register
without issuing another PAGE READ (see Figure 14 on page 25).
Random DATA READ commands are permitted during a PAGE READ CACHE MODE
operation.
PAGE READ CACHE MODE cannot be used to cross block boundaries.
If monitoring the progress of PAGE READ CACHE MODE via the read status register, use
only READ STATUS (70h) commands. TWO-PLANE/MULTIPLE-DIE READ STATUS
(78h) commands are not supported during a PAGE READ CACHE MODE operation.
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MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Figure 14: PAGE READ CACHE MODE
CLE
CE#
WE#
ALE
R/B#
tR tDCBSYR1
RE#
I/Ox 00h
Address (5 cycles) 30h
31h
Data output
(Serial access)
tDCBSYR2
31h
Data output
(Serial access)
tDCBSYR2
3Fh
Data output
(Serial access)
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MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Command Definitions
READ ID 90h
The READ ID command is used to read the 5 bytes of identifier codes programmed into
the devices. The READ ID command reads a 5-byte table that includes manufacturer’s
ID, device configuration, and part-specific information. See Table 8 on page 27, which
shows complete listings of all configuration details.
Writing 90h to the command register puts the device into the read ID mode. The com-
mand register stays in this mode until another valid command is issued (see Figure 15).
Figure 15: READ ID Operation
CLE
CE#
WE#
ALE
RE#
I/Ox
tAR
tWHR tREA
90h 00h
Address, 1 cycle
Byte 0
Byte 1
Byte 2
Note: See Table 8 on page 27 for byte definitions.
Byte 3
Byte 4
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MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Command Definitions
Table 8: Device ID and Configuration Codes
Options
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value1
Byte 0
Manufacturer
ID
Micron
0 0 1 0 1 1 0 0 2Ch
Byte 1
Device ID
MT29F8G08MAA
8Gb, x8, 3.3V
1
1
0
1
0
0
1
1 D3h
MT29F16G08QAA 16Gb, x8, 3.3V 1 1 0 1 0 0 1 1 D3h
MT29F32G08TAA
32Gb, x8, 3.3V
1
1
0
1
0
1
0
1 D5h
Byte 2
Number of die per CE
1
0 0 00b
2 0 1 01b
Cell type
MLC
01
00b
Number of
simultaneously
programmed pages
2
01
01b
Interleaved
operations between
multiple die
Not supported
Supported
0
1
0b
1b
Cache programming Supported
1
1b
Byte value
MT29F8Gxx
1
0
0
1
0
1
0
0
94h
MT29F16Gxx
1
0
0
1
0
1
0
0
94h
MT29F32Gxx
1
1
0
1
0
1
0
1 D5h
Byte 3
Page size
2KB
0 1 01b
Spare area size
(bytes)
64B
1 1b
Block size (w/o spare)
256KB
10
10b
Organization
x8
0
0b
Serial access (MIN)
50ns/30ns
0
0 0xxx0b
25ns
1
0 1xxx0b
Byte value
MT29FxG08
1
0
1
0
0
1
0
1 A5h
Byte 4
Reserved
0 0 00b
Planes per CE#
2
01
01b
4
10
10b
Plane size
4Gb 1 1 0
110b
Reserved
0
0b
Byte value
MT29F8Gxx
0
1
1
0
0
1
0
0
64h
MT29F16Gxx
0
1
1
0
0
1
0
0
64h
MT29F32Gxx
0
1
1
0
1
0
0
0
68h
Notes: 1. b = binary; h = hex.
2. The MT29F16Gxx device ID code reflects the configuration of each 8Gb section.
Notes
2
2
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MT29F8G08MAAWP (Micron)
NAND Flash Memory MLC

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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Command Definitions
READ STATUS 70h
These NAND Flash devices have an 8-bit status register that the software can read during
device operation. Table 9 describes the status register.
After a READ STATUS (70h) command, all READ cycles are from the status register until a
new command is given. Changes in the status register are seen on I/O[7:0] as long as
CE# and RE# are LOW; it is not necessary to start a new READ cycle to see these changes.
In devices that have more than one die sharing a common CE# connection, the READ
STATUS (70h) command reports the status of the die that was last addressed. If concur-
rent operations are started on both die, then the TWO-PLANE/MULTIPLE-DIE READ
STATUS (78h) command must be used to select the die that should report status. In this
situation, using the READ STATUS (70h) command will result in bus contention, as both
die will respond until the next operation is issued.
While monitoring the read status to determine when the transfer from the Flash array to
the data register (tR) is complete, the user must re-issue the READ (00h) command to
make the change from STATUS to DATA. After the READ command has been re-issued,
pulsing the RE# line will result in outputting data, starting from the initial column
address.
Table 9: Status Register Bit Definition
SR Program Program Page
Page Read
Bit
Page
Cache Mode Page Read Cache Mode Block Erase
Definition
01
Pass/fail
Pass/fail (N)
– Pass/fail 0 = Successful PROGRAM/ERASE
1 = Error in PROGRAM/ERASE
1 – Pass/fail (N -1) – – – 0 = Successful PROGRAM
1 = Error in PROGRAM
2 – – – – –0
3 – – – – –0
4 – – – – –0
5 Ready/busy Ready/busy2 Ready/busy Ready/busy2 Ready/busy 0 = Busy
1 = Ready
6 Ready/busy Ready/busy Ready/busy Ready/busy Ready/busy 0 = Busy
cache3
cache3
1 = Ready
7 Write protect Write protect Write protect Write protect Write protect 0 = Protected
1 = Not protected
Notes: 1. Status register bit 0 reports a “1” if a TWO-PLANE PROGRAM operation fails on one or
both planes. Status register bit 1 reports a “1” if a TWO-PLANE PROGRAM PAGE CACHE
MODE operation fails on one or both planes. Use TWO-PLANE/MULTIPLE-DIE READ STATUS
(78h) to determine the plane on which the operation failed.
2. Status register bit 5 is “0” during the actual programming operation. If cache mode is
used, this bit will be “1” when all internal operations are complete.
3. Status register bit 6 is “1” when the cache is ready to accept new data. R/B# follows bit 6
(see Figure 14 on page 25 and Figure 19 on page 31).
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NAND Flash Memory MLC

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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Command Definitions
Figure 16: Status Register Operation
CE#
CLE
tCLR
WE#
RE#
tREA
I/Ox 70h1
Status output
Notes: 1. Command can be 70h or 78h.
PROGRAM Operations
PROGRAM PAGE 80h-10h
Micron NAND Flash devices are inherently page-programmed devices. Within a block,
the pages must be programmed consecutively from the least significant page address to
the most significant page address. Random page address programming is prohibited.
These MLC NAND Flash devices do not support partial-page programming operations—
a page can only be programmed one time before requiring an ERASE operation.
If a RESET (FFh) command is issued during a PROGRAM PAGE operation while R/B# is
LOW, the data in the shared memory cells being programmed could become invalid.
Interrupting a programming operation on one page could corrupt the data in another
page within the block being programmed.
SERIAL DATA INPUT 80h
PROGRAM PAGE operations require loading the SERIAL DATA INPUT (80h) command
into the command register, followed by 5 address cycles, then the data. Serial data is
loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h)
command is written after the data input is complete. The control logic automatically
executes the proper algorithm and controls all the necessary timing to program and ver-
ify the operation. Write verification only detects “1s” that are not successfully written to
“0s.”
R/B# goes LOW for the duration of array programming time, tPROG. The READ STATUS
(70h, 78h) and the RESET (FFh) commands are the only commands valid during the pro-
gramming operation. Bit 5 of the status register will reflect the state of R/B#. When the
device reaches ready, read bit 0 of the status register to determine if the programming
operation passed or failed (see Figure 17). The command register stays in read status
register mode until another valid command is written to it.
RANDOM DATA INPUT 85h
After the initial data set is input, additional data can be written to a new column address
with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT com-
mand can be used any number of times in the same page prior to issuance of the PAGE
WRITE (10h) command. See Figure 18 for the proper command sequence.
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NAND Flash Memory MLC

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8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Command Definitions
Figure 17: PROGRAM and READ STATUS Operation
R/B#
I/Ox 80h Address (5 cycles) DIN 10h
tPROG
70h1
Status
I/O 0 = 0 PROGRAM successful
I/O 0 = 1 PROGRAM error
Notes: 1. Command can be 70h or 78h.
Figure 18: RANDOM DATA INPUT
R/B#
I/Ox 80h
Address
(5 cycles)
DIN 85h
Address
(2 cycles)
DIN 10h
tPROG
70h1
Status
Notes: 1. Command can be 70h or 78h.
PROGRAM PAGE CACHE MODE 80h-15h
Cache programming is actually a buffered programming mode of the standard PRO-
GRAM PAGE command. Programming is started by loading the SERIAL DATA INPUT
(80h) command to the command register, followed by 5 cycles of address, and a full or
partial page of data. The data is initially copied into the cache register, and the CACHE
WRITE (15h) command is then latched to the command register. Data is transferred
from the cache register to the data register on the rising edge of WE#. R/B# goes LOW
during this transfer time. After the data has been copied into the data register and R/B#
returns to HIGH, memory array programming begins.
When R/B# returns to HIGH, new data can be written to the cache register by issuing
another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be
controlled by the actual programming time. The first time through equals the time it
takes to transfer the cache register contents to the data register. On the second and sub-
sequent programming passes, transfer from the cache register to the data register is held
off until current data register content has been programmed into the array.
The PROGRAM PAGE CACHE MODE command can cross block boundaries; it cannot
cross die boundaries. RANDOM DATA INPUT commands are allowed during PROGRAM
PAGE CACHE MODE operations.
Bit 6 (Cache R/B#) of the status register can be read by issuing the READ STATUS (70h,
78h) commands to determine when the cache register is ready to accept new data. R/B#
always follows bit 6.
Bit 5 (R/B#) of the status register can be polled to determine when the actual program-
ming of the array is complete for the current programming cycle.
If just R/B# is used to determine programming completion, the last page of the program
sequence must use the PROGRAM PAGE (10h) command instead of the CACHE PRO-
GRAM (15h) command. If the CACHE PROGRAM (15h) command is used every time,
including the last page of the programming sequence, status register bit 5 must be used
to determine when programming is complete (see Figure 19 on page 31).
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