BLF7G20LS-200 (NXP)
Power LDMOS transistor

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BLF7G20L-200;
BLF7G20LS-200
Power LDMOS transistor
Rev. 01 — 3 June 2010
www.DataSheet4U.com
Objective data sheet
1. Product profile
1.1 General description
200 W LDMOS power transistor for base station applications at frequencies from
1805 MHz to 1990 MHz.
Table 1. Typical performance
Typical RF performance at Tcase = 25 °C in a common source class-AB production test circuit.
Mode of operation
f
IDq
VDS PL(AV) Gp
ηD ACPR
(MHz)
(mA) (V) (W)
(dB) (%) (dBc)
2-carrier W-CDMA
1805 to 1880
1620 28 55
18 33 29[1]
[1] Test signal: 3GPP; test model 1; 64 PDPCH; PAR = 8.4 dB at 0.01 % probability on CCDF.
1.2 Features and benefits
„ Excellent ruggedness
„ High efficiency
„ Low Rth providing excellent thermal stability
„ Designed for broadband operation (1805 MHz to 1990 MHz)
„ Lower output capacitance for improved performance in Doherty applications
„ Designed for low-memory effects providing excellent digital pre-distortion capability
„ Internally matched for ease of use
„ Integrated ESD protection
„ Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
„ RF power amplifiers for W-CDMA base stations and multi-carrier applications in the
1805 MHz to 1990 MHz frequency range


BLF7G20LS-200 (NXP)
Power LDMOS transistor

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BLF7G20L-200; BLF7G20LS-200
Power LDMOS transistor
2. Pinning information
Table 2. Pinning
Pin Description
BLF7G20L-200 (SOT502A)
1 drain
2 gate
3 source
BLF7G20LS-200 (SOT502B)
1 drain
2 gate
3 source
[1] Connected to flange
3. Ordering information
Simplified outline Graphic symbol
11
3
[1]
22
3
sym112
1
3
[1]
2
1
2
3
sym112
Table 3. Ordering information
Type number
Package
Name Description
BLF7G20L-200 -
flanged LDMOST ceramic package; 2 mounting holes;
2 leads
BLF7G20LS-200 -
earless flanged LDMOST ceramic package; 2 leads
Version
SOT502A
SOT502B
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS drain-source voltage
VGS gate-source voltage
Tstg storage temperature
Tj junction temperature
Min Max Unit
- 65 V
0.5 +13 V
65 +150 °C
- 225 °C
5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter
Rth(j-c) thermal resistance from junction to case
Conditions
Tcase = 80 °C; PL = 55 W;
VDS = 28 V; IDq = 1620 mA
Typ Unit
0.27 K/W
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
© NXP B.V. 2010. All rights reserved.
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Power LDMOS transistor

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Power LDMOS transistor
6. Characteristics
Table 6. Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
V(BR)DSS drain-source breakdown voltage VGS = 0 V; ID = 1.5 mA
VGS(th) gate-source threshold voltage VDS = 10 V; ID = 150 mA
IDSS drain leakage current
VGS = 0 V; VDS = 28 V
IDSX drain cut-off current
VGS = VGS(th) + 3.75 V;
VDS = 10 V
IGSS gate leakage current
VGS = 11 V; VDS = 0 V
gfs forward transconductance
VDS = 10 V; ID = 7.5 A
RDS(on) drain-source on-state resistance VGS = VGS(th) + 3.75 V;
ID = 5.25 A
65
1.5
-
42
-
-
-
--
1.9 2.3
- 4.2
50.6 -
V
V
μA
A
- <tbd> nA
18.6 -
S
0.093 -
Ω
7. Test information
Table 7. Functional test information
Mode of operation: 2-carrier W-CDMA; PAR = 8.4 dB at 0.01 % probability on the CCDF; 3GPP test
model 1; 64 PDPCH; f1 = 1807.5 MHz; f2 = 1812.5 MHz; f3 = 1872.5 MHz; f4 = 1877.5 MHz;
RF performance at VDS = 28 V; IDq = 1620 mA; Tcase = 25 °C; unless otherwise specified; in a
class-AB production test circuit.
Symbol Parameter
Conditions
Min Typ Max Unit
PL(AV)
Gp
RLin
ηD
ACPR
average output power
power gain
input return loss
drain efficiency
adjacent channel power ratio
PL(AV) = 55 W
PL(AV) = 55 W
PL(AV) = 55 W
PL(AV) = 55 W
- 55
17 18
--
30 33
- 29
-W
- dB
10 dB
-%
- dBc
7.1 Ruggedness in class-AB operation
The BLF7G20L-200 and BLF7G20LS-200 are capable of withstanding a load mismatch
corresponding to VSWR = 10 : 1 through all phases under the following conditions:
VDS = 30 V; IDq = 1620 mA; PL = 185 W (CW); f = 1805 MHz to 1990 MHz.
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
© NXP B.V. 2010. All rights reserved.
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BLF7G20LS-200 (NXP)
Power LDMOS transistor

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BLF7G20L-200; BLF7G20LS-200
Power LDMOS transistor
19.0
Gp
(dB)
18.5
18.0
17.5
7.2 1 Tone CW
014aab189
(3)
(2)
(1)
60
ηD
(%)
40
20
014aab190
(1)
(2)
(3)
17.0
0
40 80 120 160 200
PL(AV) (W)
VDS = 28 V; IDq = 1620 mA.
(1) f = 1805 MHz.
(2) f = 1845 MHz.
(3) f = 1880 MHz.
Fig 1. Power gain as a function of average output
power; typical values
0
0 40 80 120 160 200
PL(AV) (W)
VDS = 28 V; IDq = 1620 mA.
(1) f = 1805 MHz.
(2) f = 1845 MHz.
(3) f = 1880 MHz.
Fig 2. Drain efficiency as a function of average
output power; typical values
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
© NXP B.V. 2010. All rights reserved.
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BLF7G20LS-200 (NXP)
Power LDMOS transistor

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BLF7G20L-200; BLF7G20LS-200
Power LDMOS transistor
19
Gp
(dB)
18
17
16
7.3 1-carrier W-CDMA
014aab191 50
ηD
(%)
40
Gp
30
ηD
20
8
PAR
(dB)
6
4
014aab192
(3)
(2)
(1)
15
0
10
40 80 120 160
PL(AV) (W)
2
0 100 200 300 400
PL(M) (W)
Fig 3.
VDS = 28 V; IDq = 1620 mA; f = 1845 MHz; PAR = 7.2 dB
at 0.01 % probability on the CCDF.
Power gain and drain efficiency as functions
of average output power; typical values
VDS = 28 V; IDq = 1620 mA; PAR = 7.2 dB at 0.01 %
probability on the CCDF.
(1) f = 1805 MHz.
(2) f = 1845 MHz.
(3) f = 1880 MHz.
Fig 4. Peak-to-average power ratio as a function of
peak power; typical values
20
APCR5M
(dBc)
30
014aab193
40 (1)
(2)
(3)
50
60
0
40 80 120 160
PL(AV) (W)
VDS = 28 V; IDq = 1620 mA; PAR = 7.2 dB at 0.01 % probability on the CCDF.
(1) f = 1805 MHz.
(2) f = 1845 MHz.
(3) f = 1880 MHz.
Fig 5. Adjacent power channel ratio (5 MHz) as function of average output power; typical values
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
© NXP B.V. 2010. All rights reserved.
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Power LDMOS transistor

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BLF7G20L-200; BLF7G20LS-200
Power LDMOS transistor
7.4 2-carrier W-CDMA
19
Gp
(dB)
18
17
16
ηD
014aab194 50
ηD
(%)
40
Gp
30
20
19.0
Gp
(dB)
18.5
18.0
17.5
014aab195
(3)
(2)
(1)
15
0
10
30 60 90 120 150
PL(AV) (W)
VDS = 28 V; IDq = 1620 mA; channel spacing = 5 MHz;
PAR = 8.4 dB at 0.01 % probability on the CCDF.
Fig 6. Power gain and drain efficiency as functions
of average output power; typical values
17.0
0
30 60 90 120 150
PL(AV) (W)
VDS = 28 V; IDq = 1620 mA; channel spacing = 5 MHz;
PAR = 8.4 dB at 0.01 % probability on the CCDF.
(1) f = 1805 MHz.
(2) f = 1845 MHz.
(3) f = 1880 MHz.
Fig 7. Power gain as a function of average output
power; typical values
50
ηD
(%)
40
30
014aab196
(1)
(2)
(3)
10
APCR5M
(dBc)
20
30
40
(1)
(2)
(3)
014aab197
20
50
10
0
30 60 90 120 150
PL(AV) (W)
VDS = 28 V; IDq = 1620 mA; channel spacing = 5 MHz;
PAR = 8.4 dB at 0.01 % probability on the CCDF.
(1) f = 1805 MHz.
(2) f = 1845 MHz.
(3) f = 1880 MHz.
Fig 8. Drain efficiency as a function of average
output power; typical values
60
0
30 60 90 120 150
PL(AV) (W)
VDS = 28 V; IDq = 1620 mA; channel spacing = 5 MHz;
PAR = 8.4 dB at 0.01 % probability on the CCDF.
(1) f = 1805 MHz.
(2) f = 1845 MHz.
(3) f = 1880 MHz.
Fig 9.
Adjacent power channel ratio (5 MHz) as a
function of average output power;
typical values
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
© NXP B.V. 2010. All rights reserved.
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Power LDMOS transistor

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BLF7G20L-200; BLF7G20LS-200
Power LDMOS transistor
7.5 Test circuit
C2
50 mm
+ C1
R1
C4
50 mm
C10
C12
+
C11
C5 C13
C8
R2
+
C6
C9
See Table 8 for list of components. The drawing is not to scale.
Fig 10. Component layout
C14
C15
+
C16
014aab198
Table 8. List of components
See Figure 10 for component layout.
Component
Description
C1, C9, C11, C16 multilayer ceramic chip capacitor
C4, C6
multilayer ceramic chip capacitor
C5 multilayer ceramic chip capacitor
C12, C14
multilayer ceramic chip capacitor
C13 multilayer ceramic chip capacitor
C2, C8, C10, C15 electrolytic capacitor
R1, R2
chip resistor
Value
10 μF
68 pF
2.0 pF
100 pF
3.3 pF
470 μF; 63 V
10 Ω
Remarks
TDK
ATC800B
ATC800B
ATC800B
ATC800B
Philips 0603
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
© NXP B.V. 2010. All rights reserved.
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Power LDMOS transistor

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BLF7G20L-200; BLF7G20LS-200
Power LDMOS transistor
8. Package outline
Flanged LDMOST ceramic package; 2 mounting holes; 2 leads
SOT502A
D
A
F
3
D1
U1
q
1
B
C
L
c
H U2
A
2
b
p E1
w1 M A M B M
E
w2 M C M
Q
0 5 10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT A
b
c
D D1 E E1 F
H
L
p
Q q U1 U2 w1
mm
4.72 12.83 0.15 20.02 19.96 9.50
3.43 12.57 0.08 19.61 19.66 9.30
9.53
9.25
1.14 19.94 5.33
0.89 18.92 4.32
3.38
3.12
1.70
1.45
27.94 34.16
33.91
9.91
9.65
0.25
inches
0.186
0.135
0.505 0.006
0.495 0.003
0.788 0.786
0.772 0.774
0.374 0.375
0.366 0.364
0.045 0.785
0.035 0.745
0.210 0.133
0.170 0.123
0.067
0.057
1.100
1.345
1.335
0.390
0.380
0.01
w2
0.51
0.02
OUTLINE
VERSION
SOT502A
IEC
REFERENCES
JEDEC
JEITA
Fig 11. Package outline SOT502A
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
EUROPEAN
PROJECTION
ISSUE DATE
99-12-28
03-01-10
© NXP B.V. 2010. All rights reserved.
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Power LDMOS transistor

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Power LDMOS transistor
Earless flanged LDMOST ceramic package; 2 leads
SOT502B
D
A
F
3
D1 D
L
H U2
U1
1
c
E1 E
2
b
w2 M D M
Q
0 5 10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT A
b
c
D D1 E E1 F
H
L
Q U1 U2 w2
mm
4.72 12.83 0.15 20.02 19.96 9.50
3.43 12.57 0.08 19.61 19.66 9.30
9.53
9.25
1.14 19.94 5.33
0.89 18.92 4.32
1.70
1.45
20.70
20.45
9.91
9.65
0.25
inches
0.186
0.135
0.505
0.495
0.006
0.003
0.788 0.786
0.772 0.774
0.374
0.366
0.375
0.364
0.045
0.035
0.785
0.745
0.210
0.170
0.067
0.057
0.815
0.805
0.390 0.010
0.380
OUTLINE
VERSION
SOT502B
IEC
REFERENCES
JEDEC
JEITA
Fig 12. Package outline SOT502B
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
EUROPEAN
PROJECTION
ISSUE DATE
03-01-10
07-05-09
© NXP B.V. 2010. All rights reserved.
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Power LDMOS transistor

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Power LDMOS transistor
9. Abbreviations
Table 9. Abbreviations
Acronym
Description
3GPP
Third Generation Partnership Project
CCDF
Complementary Cumulative Distribution Function
CW Continuous Wave
DPCH
Dedicated Physical CHannel
ESD
ElectroStatic Discharge
LDMOS
Laterally Diffused Metal Oxide Semiconductor
LDMOST
Laterally Diffused Metal Oxide Semiconductor Transistor
PAR Peak-to-Average power Ratio
PDPCH
transmission Power of the Dedicated Physical CHannel
RF Radio Frequency
VSWR
Voltage Standing Wave Ratio
W-CDMA
Wideband Code Division Multiple Access
10. Revision history
Table 10. Revision history
Document ID
BLF7G20L-200_7G20LS-200 v.1
Release date Data sheet status
20100603
Objective data sheet
Change notice
-
Supersedes
-
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
© NXP B.V. 2010. All rights reserved.
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Power LDMOS transistor

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Power LDMOS transistor
11. Legal information
11.1 Data sheet status
Document status[1][2]
Objective [short] data sheet
Preliminary [short] data sheet
Product [short] data sheet
Product status[3]
Development
Qualification
Production
Definition
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
11.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
11.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
© NXP B.V. 2010. All rights reserved.
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Power LDMOS transistor
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
11.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
12. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
BLF7G20L-200_7G20LS-200
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 3 June 2010
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Power LDMOS transistor
13. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 2
6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 3
7.1 Ruggedness in class-AB operation . . . . . . . . . 3
7.2 1 Tone CW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.3 1-carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . . 5
7.4 2-carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . . 6
7.5 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
11.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
11.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
11.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
11.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12 Contact information. . . . . . . . . . . . . . . . . . . . . 12
13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 June 2010
Document identifier: BLF7G20L-200_7G20LS-200




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