SEN6A40 (Avant Electronics)
68-ROW driver

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DATA SHEET
www.DataSheet4U.com
SEN6A40
68-ROW driver for
dot-matrix STN LCD
To improve design and/or performance,
Avant Electronics may make changes to its
products. Please contact Avant Electronics
for the latest versions of its products
data sheet (v3)
2005 Oct 20


SEN6A40 (Avant Electronics)
68-ROW driver

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Avant Electronics
SEN6A40
68-ROW driver for dot-matrix STN LCD
1 GENERAL
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1.1 Description
The SEN6A40 is a 68-ROW (COMMON) driver for dot-matrix STN LCD. It is desinged to be paired with the SEN6A39
80-COLUMN (SEGMENT) driver.
1.2 Features
68-output ROW (COMMON) driver for dot-matrix STN LCD.
Display duty : up to 1/240.
Capability of being cascaded in application to expand common number.
Support 1-bit, bidirectional data shift.
Output data shift on the falling edge or rising edge of LP input.
Data shift directioin can be:
– O1 O68,
– O68 O1, or
– O1O34 and O68 O35.
External LCD bias voltage.
Operating voltage range (control logic): 2.7 ~ 5.5 volts.
Operating voltage range (LCD-bias high voltage, VDD-V5): 8~ 30 volts.
Operating temperature range: -20 to +75 °C.
Storage temperature range: -40 to +125 °C.
1.3 Ordering information
Table 1 Ordering information
TYPE NUMBER
SEN6A40-LQFPG
SEN6A40-QFPG
SEN6A40-LQFP
SEN6A40-QFP
DESCRIPTION
LQFP100 Green package.
QFP100 Green package.
LQFP100 package.
QFP100 package.
2005 Oct 20
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data sheet (v3)


SEN6A40 (Avant Electronics)
68-ROW driver

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SEN6A40
68-ROW driver for dot-matrix STN LCD
2 FUNCTIONAL BLOCK DIAGRAM AND DESCRIPTION
2.1 Funtional block diagram
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O1 O2 O3
O66 O68
V1
V4
V5
FR
DIO1
4-level LCD Driver Circuit
(68 bits)
68 High voltage area
HV logic and level shifter (68 bits)
68
68-bit bi-directional
I/O
shift register & control
I/O
DIO2
LP
DIR
DUAL
TSW
VDD
VSS
Fig.1 Functional Block Diagram
2005 Oct 20
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SEN6A40 (Avant Electronics)
68-ROW driver

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3 PINNING INFORMATION
3.1 Pinning diagram
SEN6A40
68-ROW driver for dot-matrix STN LCD
www.DataSheet4U.com
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
O46 76
50 O23
O47 77
49 O22
O48 78
48 O21
O49 79
47 O20
O50 80
46 O19
O51 81
45 O18
O52 82
44 O17
O53 83
43 O16
O54 84
42 O15
O55 85
41 O14
O56 86
NC 87
SEN6A40
40 O13
39 NC
NC 88
38 NC
NC 89
37 NC
O57 90
36 O12
O58 91
35 O11
O59 92
34 O10
O60 93
33 O9
O61 94
32 O8
O62 95
31 O7
O63 96
30 O6
O64 97
29 O5
O65 98
28 O4
O66 99
27 O3
O67 100
26 O2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Fig.2 Pin diagram of QFP100/LQFP100 package
2005 Oct 20
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SEN6A40 (Avant Electronics)
68-ROW driver

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Avant Electronics
SEN6A40
68-ROW driver for dot-matrix STN LCD
3.2 Signal description
Table 2 Pin signal description.
www.DataSheet4U.com
To avoid a latch-up effect at power-on: VSS 0.5 V < voltage at any pin at any time < VDD + 0.5 V .
Pin
number
SYMBOL
I/O
DESCRIPTION
1,
25~36,
40~61,
65~86,
90~100
O68,
O1~O12,
O13~O34,
O35~O56,
O57~O67
2, 19 DIO2, DIO1
3
4
5, 6, 10,
12, 14,
16,
20~24,
37~39,
62~64,
87~89
LP
FR
NC
COMMON driver output.
Output Please refer to Fig. 2 for pin assignment and Table 4 for output voltage level.
Input/output for COMMON scan data. COMMON scan data is sent out by the
I/O controller SAP1024B from its CDATA output. The COMMON scan data is for
horizontal scan line synchronization.
I Horizontal line pule, used as shift clock of the internal 68-bit shift register.
I Frame signal. This signal is used to generate alternating LCD bias voltage.
No Connection.
These pins should be left open in application.
Terminal switch.
7 TSW
I When this pin is connected to VDD, O1~O68 are output on the falling edge of LP.
8
9
11
13
15, 17,
18
VSS
DUAL
DIR
VDD
V4, V1, V5
I
Input
When this pin is connected to VSS, O1~O68 are output on the rising edge of LP.
Ground.
Select dual input mode or single input mode. Please refer to Table 5.
Select the shift direction of the scan data. Please refer to Table 5.
Power supply for control logic.
LCD bias voltage.
2005 Oct 20
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68-ROW driver

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4 PAD DIAGRAM AND COORDINATES
4.1 Pad diagram
SEN6A40
68-ROW driver for dot-matrix STN LCD
www.DataSheet4U.com
O45
O46
O47
O48
O49
O50
O51
O52
O53
O54
O55
O56
O57
O58
O59
O60
O61
O62
O63
O64
O65
O66
O67
O68
Note:
1. For chip_on_board (COB) bonding, chip carrier should be
connected to VDD or left open. Chip carrier is the metal
pad to which die is attached.
2. The chip size is : (X-axis, Y-axis)= 2432 µm x 2717µm.
3. The Chip ID is: 3007.
O23
O22
O21
O20
O19
O18
O17
O16
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
Fig.3 Pad locations.
2005 Oct 20
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data sheet (v3)


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68-ROW driver

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SEN6A40
68-ROW driver for dot-matrix STN LCD
4.2 Pad description
Table 3 Pad signal names and coordinates
The unit for coordinates is µm.
PAD
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
PAD
NAME
O68
O67
O66
O65
O64
O63
O62
O61
O60
O59
O58
O57
O56
O55
O54
O53
O52
O51
O50
O49
O48
O47
O46
O45
O44
O43
O42
O41
O40
O39
O38
O37
O36
O35
COORDINATES
XY
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
98.50
203.5
308.5
413.5
518.5
623.5
728.5
833.5
938.5
1043.5
1148.5
117.20
222.20
327.20
432.20
537.20
642.20
747.20
852.20
957.20
1062.20
1167.20
1272.20
1377.20
1482.20
1587.20
1692.20
1797.20
1902.20
2007.20
2112.20
2217.20
2322.20
2427.20
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
PAD
NO.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PAD
NAME
O34
O33
O32
O31
O30
O29
O28
O27
O26
O25
O24
O23
O22
O21
O20
O19
O18
O17
O16
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
www.DataSheet4U.com
COORDINATES
X
1253.5
1358.5
1463.5
1568.5
1673.5
1778.5
1883.5
1988.5
2093.5
2198.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
2303.5
Y
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2587.80
2427.2
2322.2
2217.2
2112.2
2007.2
1902.2
1797.2
1692.2
1587.2
1482.2
1377.2
1272.2
1167.2
1062.2
957.2
852.2
747.2
642.2
537.2
432.2
327.2
222.2
117.2
PAD
NO.
69
70
71
72
73
74
75
76
77
78
79
80
PAD
NAME
DIO1
V5
V1
V4
VDD
DIR
DUAL
VSS
TSW
FR
LP
DIO2
COORDINATES
X
1970.1
1802.6
1669.0
1527.5
1295.3
1168.2
1041.1
915.6
788.4
661.3
533.8
406.7
Y
117.3
117.3
117.3
117.3
117.3
117.3
117.3
117.3
117.3
117.3
117.3
117.3
2005 Oct 20
7 of 20
data sheet (v3)


SEN6A40 (Avant Electronics)
68-ROW driver

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SEN6A40
68-ROW driver for dot-matrix STN LCD
5 FUNCTIONAL DESCRIPTION
5.1 Row output drive (O1~O68)
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The output voltage level of outputs O1~O68 is determined by input data (row scan data) and FR (frame signal), as given
in Table 4.
Table 4 output voltage level of O1~O68
FR Data
LL
LH
HL
HH
SEN6A40 O1~O68
outpust
V1
V5
V4
VDD
SEN6A39 O1~O80
outputs
V2
VDD
V3
V5
5.2 Single/Dual Mode selection
The mode selection and scan data shift direction is given in the following table.
Table 5 Mode selection
Mode
Single mode, left-to-right
shift
Dual mode
Single mode, right-to-left
shift
DIR pin
VDD
VSS
DUAL pin
VSS
VDD
don’t care ( VDD or
VSS)
Data shift direction
O1 O68
O1 O34, O68 O35
O68 → Ο1
DIO1
IN
IN
OUT
DIO2
OUT
IN
IN
5.3 Cascading connection
5.3.1 SINGLE MODE, LEFT-TO-RIGHT SHIFT
First
Data input
O1
DIO1
O68
DIO2
O1
DIO1
O68
DIO2
O1
DIO1
Last
O68
DIO2
LP
VSS
VDD
FR
Fig.4 Single mode, left-to-right shift
2005 Oct 20
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68-ROW driver

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5.3.2 SINGLE MODE, RIGHT-TO-LEFT SHIFT
Last
O1
DIO1
O68
DIO2
O1
DIO1
SEN6A40
68-ROW driver for dot-matrix STN LCD
O68
DIO2
O1
DIO1
www.DataSheet4U.com
First
O68
DIO2
Data input
LP
VSS
FR
Note: in this application, DUAL can also be connected
to VDD.
5.3.3 DUAL MODE
Fig.5 Single mode, right-to-left Shift
First1
Data input1
O1
DIO1
O68
DIO2
Last1 Last2
O1
DIO1
O34 O35
O68
DIO2
O1
DIO1
First2
O68
DIO2
Data input2
LP
VSS
VDD
FR
Single mode
Dual mode
Single mode
Fig.6 Dual Mode
2005 Oct 20
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68-ROW driver

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SEN6A40
68-ROW driver for dot-matrix STN LCD
6 ABSOLUTE MAXIMUM RATING
Table 6 Absolute maximum rating
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VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = 25±2°C.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
VDD-V5
Vi(max)
Tamb
Tstg
Voltage on the VDD input.
LCD bias voltage (note 1).
Maximum input voltage to input pins (note 2).
Operating ambient temperature range.
Storage temperature range.
0.3 +7.0 V
0 30 V
-0.3 VDD + 0.3
-20 + 75 °C
40
+125
°C
Note:
1. The following conditions must always be met: VDD V1 > V4 > V5, VSS=0 V.
2. For the input pins: FR, LP, DIR, DUAL, TSW, DIO1, and DIO2.
2005 Oct 20
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data sheet (v3)


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68-ROW driver

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SEN6A40
68-ROW driver for dot-matrix STN LCD
7 DC CHARACTERISTICS
Table 7 DC Characteristics
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VDD = 5V ±10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = 25±2 °C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
VDD
Supply voltage for control logic
Please refer to Fig. 10 for
DC power-up sequence.
2.7
5.0
5.5 V
VDD-V5 LCD bias voltage
Note 1.
12 30
VIL
Input LOW voltage of input pins
DIO1, DIO2, LP, TSW, FR,
DUAL, DIR
0
0.2 VDD V
VIH
Input HIGH voltage of input pins
DIO1, DIO2, LP, TSW, FR,
DUAL, DIR
0.8 VDD
VDD
V
VOL
Output LOW voltage level of the
DIO1 and DIO2 pins
IOL=400µA
0.0 0.4 V
VOH
Output HIGH voltage level of the
DIO1 and DIO2 pins
IOH=-400µA
VDD − 0.4
VDD
V
ISTBY
Standby current
Note 2.
2 µA
ISS
IEE
RON1
RON2
Operating current
Operating current
Driver ON resistance at
VLCD= 30 V
Driver ON resistance at
VLCD= 20 V
Note 3.
Note 4.
Note 5.
Note 6.
80 µA
80 µA
1.0 ΚΩ
1.0 ΚΩ
Notes:
1. The following coditions: VDD V1 > V4 > V5 must always be met.
2. VDD-V5=30 V, LP=LOW, Output unloaded; measured at the VSS pin.
3. Condition for the measurement: VLCD=VDD-V5=30 V, VDD=5.5 V, LP=14 KHz, No load. This is the current flowing
from VDD to VSS, measured at the VSS pin.
4. Condition for the measurement: VLCD=VDD-V5=30 V, VDD=5.5 V, LP=14 KHz, No load. This is the current flowing
from VDD to V5, measured at the V5 pin.
5. Condition for the measurment: VDD-V5=30 V, |VDE-VO|=0.5 V, where VDE= one of V1, V4, or V5.
V1=VDD - (1/9) x (VDD-V5), V4=VDD - (8/9) x (VDD-V5). For the driver circuits (O1~O68), please refer to Section 12,
Pin Circuits.
6. Condition for the measurment: VDD-V5=20 V, |VDE-VO|=0.5 V, where VDE= one of V1, V4, or V5.
V1=VDD - (1/9) x (VDD-V5), V4=VDD - (8/9) x (VDD-V5). For the driver circuits (O1~O68), please refer to Section 12,
Pin Circuits.
2005 Oct 20
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data sheet (v3)


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68-ROW driver

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SEN6A40
68-ROW driver for dot-matrix STN LCD
8 AC CHARACTERISTICS
tR tCWH tF
tCWL
LP 0.1VDD 0.9VDD
0.1VDD
tDSU
tDHD
0.1VDD
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DIO1
(DIO2)
DIO2
(DIO1)
0.9VDD
0.1VDD
0.9VDD
0.1VDD
tPLH , tPHL
0.9VDD
0.1VDD
Fig.7 AC characteristics
Table 8 AC Characteristics
VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = 25 ±2 °C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
TCWH
TCWH
tR
tF
tDSU
tDHD
tPLH ,tPHL
High period of the LP clock
Low period of the LP clock
LP rise time
LP fall time
Input data setup time
Input data hold time.
Output delay time
For both DIO1 and DIO2
For both DIO1 and DIO2
LPDIO1, LPDIO2,
Load=10 pF.
30
1000
30
50
50
50
250
UNIT
ns
ns
ns
ns
ns
ns
ns
2005 Oct 20
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68-ROW driver

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9 LCD BIAS VOLTAGE
SEN6A40
68-ROW driver for dot-matrix STN LCD
www.DataSheet4U.com
VDD
VDD
VDD
VDD
R
V1 V1
SEN6A39
R
V2 V2
VLCD
5R
V3 V3
SEN6A40
R
V4 V4
R
V5 V5
V5 VR VSS
VEE
VLCD=VDD-V5
V1 = VDD - (1/9) VLCD
V2 = VDD - (2/9) VLCD
V3 = VDD - (7/9) VLCD
V4 = VDD - (8/9) VLCD
V5 = VDD - (9/9) VLCD
Fig.8 LCD bias voltage
2005 Oct 20
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68-ROW driver

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10 TIMING DIAGRAM
DIR=H,
DUAL=L,
FR
TSW=H
LP
272 1
2
3
VDD
O1 V1
V4
V5
VDD
O2
V1
V4
V5
VDD
O68
V1
V4
V5
VDD
O1
V1
V4
V5
VDD
O2
V1
V4
V5
VDD
O1
V1
V4
V5
VDD
O2
V1
V4
V5
VDD
O1
V1
V4
V5
VDD
O2
V1
V4
V5
67 68 69 70 71
135 136 137 138 139
203 204 205 206 207
271 272 1 2 3
67 68 69 70 71
135 136 137 138 139


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68-ROW driver

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11 APPLICATION EXAMPLES
11.1 EXAMPLE 1 (64X160)
SEN6A40
68-ROW driver for dot-matrix STN LCD
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D0~D7
8
Z80
IORQ
WR
RD
A0
A1~A7
Address
decoding
circuit
D0~D7
MDS
MD0 ad0~ad12
MD1
MD2
MD3
r/w
d0~d7
FS0
FS1 ce
SDSEL
SAP1024B
HALT
DUAL
WR
CDATA
RD LP
FR
C/D
ED
CE HSCP
RESET
XI
XO
Display Memory
13 A0~12
R/W
6264
I/O1~8
CE1
DIO1
SCP SEN6A40 O1
FR
O64
64 x 160 dots
LCD
EIO1
O1....O80
O1....O80
SEN6A39
SEN6A39
EIO2 EIO1
EIO2
RESET
VDD
VSS
Fig.9 64 X 160 dots application
2005 Oct 20
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68-ROW driver

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SEN6A40
68-ROW driver for dot-matrix STN LCD
12 PIN CIRCUITS
Table 9 MOS-level schematics of all input, output, and I/O pins.
SYMBOL
Input/
output
CIRCUIT
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NOTES
Output Enable
VDD
VDD
DIO1, DIO2 I/O
Data out
VSS VSS
FR, LP, DIR,
DUAL, TSW
Inputs
VDD
O1~O68,
Driver
outputs,
VDD, V1, V4, High
V5 voltage
inputs
V1
V4
V5
Data in
VDD
VDD
VSS VSS
VDD EN1
V5
VDD
EN2
V5
VDD
EN3
V5
VDD
EN4
V5
VDD
On
n= 1 ~ 68
V5
2005 Oct 20
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68-ROW driver

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SEN6A40
68-ROW driver for dot-matrix STN LCD
13 APPLICATION NOTES
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1. It is recommended that the following power-up sequence be followed to ensure reliable operation of your display
system. As the ICs are fabricated in CMOS and there is intrinsic latch-up problem associated with any CMOS devices,
proper power-up sequence can reduce the danger of triggering latch-up. When powering up the system, control logic
power must be powered on first. When powering down the system, control logic must be shut off later than or at the same
time with the LCD bias (V5).
VDD
Signal
V5
5V
0V 0~50 ms
1 second (minimum)
1 second (minimum)
0~50 ms
0 second
(minimum)
-30V
0 second
(minimum)
Fig.10 Recommended power up/down sequence
2005 Oct 20
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68-ROW driver

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14 PACKAGE OUTLINE INFORMATION
SEN6A40
LQFP100 Package Outline Drawing


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68-ROW driver

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Avant Electronics
SEN6A40
68-ROW driver for dot-matrix STN LCD
15 SOLDERING
15.1 Introduction
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There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and
surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for
surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often
used.
This text gives a very brief insight to a complex technology. For more in-depth account of soldering ICs, please refer to
dedicated reference materials.
15.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages.
The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight),
vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, please
contact Avant for drypack information.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the
printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between
50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
15.3 Wave soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following conditions must be observed:
A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering
technique should be used.
The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
15.4 Repairing soldered joints
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less
than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a
dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
2005 Oct 20
19 of 20
data sheet (v3)


SEN6A40 (Avant Electronics)
68-ROW driver

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Avant Electronics
SEN6A40
68-ROW driver for dot-matrix STN LCD
16 LIFE SUPPORT APPLICATIONS
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These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Avant customers using or selling these products for use
in such applications do so at their own risk and agree to fully indemnify Avant for any damages resulting from such
improper use or sale.
2005 Oct 20
20 of 20
data sheet (v3)




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