LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

Ordering number : EN5730A
CMOS IC
LC74787, 74787M, 74787JM
On-Screen Display Controller
Overview
The LC74787, LC74787M, and LC74787JM are on-
screen display controller CMOS ICs that display
characters and patterns on the TV screen under
microprocessor control. These ICs support 12 × 18 dot
characters and can display 12 lines by 24 characters of
text.
Features
• Display format: 24 characters by 12 rows (Up to 288
characters)
• Character format: 12 (horizontal) × 18 (vertical) dots
• Character sizes: Three sizes each in the horizontal and
vertical directions
• Characters in font: 256 (254 characters, one spacing
character, and one transparent spacing character)
• Initial display positions: 64 horizontal positions and 64
vertical positions
• Blinking: Specifiable in character units
• Blinking types: Two periods supported: About 1.0
second and about 0.5 second
• Blanking: Over the whole font (12 × 18 dots)
• Background color: 8 colors (internal synchronization
mode): 2fSC and 4fSC
• Line background color
— Can be set for 3 lines
— Line background color: 8 colors (internal
synchronization mode): 2fSC and 4fSC
• External control input: 8-bit serial input format
• On-chip sync separator circuit
• Video outputs: NTSC, PAL, PAL-N, PAL-M, NTSC
4.43, and PAL60 format composite video outputs
• Package
— 24-pin plastic DIP-24S (300 mil)
— 24-pin plastic MFP-24 (375 mil)
— 24-pin plastic MFP-24S (300 mil)
Package Dimensions
unit: mm
3067-DIP24S
[LC74787]
unit: mm
3045B-MFP24
[LC74787M]
unit: mm
3112-MFP24S
[LC74787JM]
SANYO: DIP24S
SANYO: MFP24
SANYO: MFP24S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
30698HA (OT) No. 5730-1/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

Pin Assignment
LC74787, 74787M, 74787JM
LC74787
LC74787M
LC74787JM
A08680
Pin Functions
Pin No.
1
2
Pin Name
VSS1
XtalIN
3
XtalOUT
(MUTE)
Function
Ground
Crystal oscillator
(MUTE input)
CTRL1 Crystal oscillator input switching
4 (CHABLK)
(CHABLK output)
5 HFTONOUT
6 OSCIN
7 OSCOUT
Background line output
LC oscillator
External synchronizing signal
8 SYNCJDG
judgment output
9 CS
10 SCLK
11 SIN
12 VDD2
Enable input
Clock input
Data input
Power supply
Notes
Ground connection (digital system ground)
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an external
clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to function as the
MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pull-
up resistor is built in and the input has hysteresis characteristics.)
Switches the mode between external clock input and crystal oscillator operation. A low level
selects crystal oscillator operation and a high level selects external clock input. As a mask
option, the CTRL1 input pin can be set to function as the CHABLK (character · frame) output.
This is a 3-value output.
Outputs the range signal specified by LNA*, LNB*, and LNC*. Outputs the crystal oscillator
clock when RST is low. (This signal is not output after a reset command is executed.)
Connections for the inductor and capacitor that form the character output dot clock generation
oscillator.
Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a
high level when synchronizing signals are present.
Outputs the dot clock (LC oscillator) when RST is low. (This signal is not output on command
resets.)
Serial data input circuit enable pin. Serial data input is enabled when a low level is input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
Serial data input circuit clock input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
Serial data input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
Composite video signal level adjustment power supply (analog system power supply)
Continued on next page.
No. 5730-2/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
Continued from preceding page.
Pin No. Pin Name
Function
Notes
13 CVOUT
14 VSS2
15 CVIN
16 VDD1
17 SYNIN
Video signal output
Ground
Video signal input
Power supply
Sync separator circuit input
Composite video signal output
Ground connection (analog system ground)
Composite video signal input
Power supply (+5 V: digital system power supply)
Video signal input to the internal sync separator circuit (Used as either the horizontal
synchronizing signal or the composite synchronizing signal input when the internal sync
separator circuit is not used.)
18 SEPC
Sync separator circuit bias
voltage
Internal sync separator circuit bias voltage monitor
19 SEPOUT
Composite synchronizing
signal output
Internal sync separator circuit composite synchronizing signal output. Can be switched to
function as a signal (high, low, or ST. pulse) output by the SEL0 and MOD0 setting.
Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output signal.
20
SEPIN
Vertical synchronizing signal input
An integration circuit must be connected to the SEPOUT pin. This pin must be tied to VDD1 if
unused. This pin can be switched to function as the frame signal input mode by setting SEL1
high. This is valid when CTL3 is set high. This input has hysteresis characteristics.
21 CTRL2
NTSC/PAL-M selection input
Pin settings take priority for switching between the NTSC, PAL, PAL-M, PAL-N, NTSC 4.43,
and PAL60 video formats. The NTSC format is selected when this pin is low after a reset.
The command video format (NTSC, PAL, PAL-M, PAL-N, NTSC 4.43, or PAL60) selection is
valid. The PAL-M format is selected when this pin is high.
22 CDLR
Background color phase
adjustment
Background color phase adjustment. Connect a resistor between this pin and ground.
23 RST
Reset input
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
24 VDD1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
Note: Both VDD1 pins must be connected to the power supply.
No. 5730-3/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
Specifications
Absolute Maximum Ratings
Parameter
Maximum supply voltage
Maximum input voltage
Maximum output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN max
VOUT max
Pd max
Topr
Tstg
Conditions
VDD1 and VDD2
All input pins
HFTONOUT, SYNCJDG, and SEPOUT
Ta = 25°C
Ratings
VSS–0.3 to VSS+6.5
VSS–0.3 to VDD+0.3
VSS–0.3 to VDD+0.3
350
–30 to +70
–40 to +125
Unit
V
V
V
mW
°C
°C
Allowable Operating Ranges
Parameter
Symbol
Conditions
min
Supply voltage
Input high-level voltage
Input low-level voltage
Pull-up resistance
VDD1
VDD2
VIH1
VIH2
VIL1
VIL2
RPU
VDD1
VDD2
RST, CS, SIN, SCLK, SEPIN, and MUTE
CTRL1 and CTRL2
RST, CS, SIN, SCLK, SEPIN, and MUTE
CTRL1 and CTRL2
RST, CS, SIN, SCLK, and MUTE
Applies to pins set up by options.
4.5
4.5
0.8 VDD1
0.7 VDD1
VSS – 0.3
VSS – 0.3
25
Composite video signal input voltage
Input voltage
Oscillator frequencies
VIN1
VIN2
VIN3
FOSC1
FOSC2
CVIN: VDD1 = 5 V
SYNIN: VDD1 = 5 V
XtalIN (when used for external clock input)
fIN = 2fsc or 4fsc ; VDD1 = 5 V
XtalIN and XtalOUT oscillator pins (2fsc: NTSC)
XtalIN and XtalOUT oscillator pins (4fsc: NTSC)
XtalIN and XtalOUT oscillator pins (2fsc: PAL)
XtalIN and XtalOUT oscillator pins (4fsc: PAL)
XtalIN and XtalOUT oscillator pins (2fsc: PAL-M)
XtalIN and XtalOUT oscillator pins (4fsc: PAL-M)
XtalIN and XtalOUT oscillator pins (2fsc: PAL-N)
XtalIN and XtalOUT oscillator pins (4fsc: PAL-N)
OSCIN and OSCOUT oscillator pins (LC oscillator)
0.10
5
Note: Applications must be especially cautious about noise when using the XtalIN input pin in clock input mode.
Ratings
typ max
5.0 5.5
5.0 1.27 VDD1
VDD1+0.3
VDD1+0.3
0.2 VDD1
0.3 VDD1
50 90
2.0
2.0 2.5
5.0
7.159
14.318
8.867
17.734
7.151
14.302
7.164
14.328
10
Unit
V
V
V
V
V
V
k
Vp-p
Vp-p
Vp-p
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
No. 5730-4/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
Electrical Characteristics at Ta = –30 to +70°C. VDD1 = 5 V unless otherwise specified.
Parameter
Symbol
Pin
Conditions
Input off leakage current
Output off leakage current
Output high-level voltage
Output low-level voltage
Ileak1
Ileak2
VOH1
VOL1
CVIN
CVOUT
HFTONOUT, SYNCJDG, and SEPOUT
HFTONOUT, SYNCJDG, and SEPOUT
VDD1 = 4.5 V,
IOH = –1.0 mA
VDD1 = 4.5 V,
IOL = –1.0 mA
H
Three-value output voltage
VO CHABLK
VDD1 = 5.0 V M
L
Input current
Operating mode current drain
RST, CS, SIN, SCLK, CTRL1,
IIH SEPIN, and MUTE
IIL CTRL1 and OSCIN
IDD1 VDD1
VIN = VDD1
VIN = VSS1
All outputs: open
Xtal:7.159 MHz
LC:8 MHz
IDD2 VDD2
VDD2 = 5 V
(1)
SYNC level
VSN
(2)
(3)
(1)
Pedestal level
VPD
(2)
(3)
(1)
Color burst low level
VCBL
(2)
(3)
(1)
Color burst high level
VCBH
(2)
(3)
(1)
Background color low level (other than blue)
VRSL0
(2)
(3)
(1)
Background color high level (other than blue)
Blue background 1 low level
VRSH0
VRSL1
CVOUT
(1): When the sync level = 0.8 V
(2): When the sync level = 1.0 V
(3): When the sync level = 1.3 V
(2)
VDD1 = 5.0 V (3)
VDD2 = 5.0 V (1)
(2)
(3)
(1)
Blue background 2 low level
VRSL2
(2)
(3)
(1)
Blue background 1 and 2 high level
VRSH1, 2
(2)
(3)
(1)
Frame level 0
VBK0
(2)
(3)
(1)
Frame level 1
VBK1
(2)
(3)
(1)
Character level
VCHA
(2)
(3)
Note: Blue background 1 or 2 are option settings.
Ratings
min typ max
1
1
3.5
1.0
3.3 5.0
1.8 2.3
0 0.8
1
–1
15
0.70
0.89
1.18
1.32
1.52
1.81
0.98
1.17
1.46
1.63
1.83
2.11
1.17
1.36
1.65
2.33
2.52
2.81
1.08
1.27
1.56
1.49
1.68
1.97
1.97
2.17
2.46
1.40
1.60
1.89
1.97
2.17
2.46
2.55
2.75
3.04
0.82
1.01
1.30
1.44
1.64
1.93
1.10
1.29
1.58
1.75
1.95
2.23
1.29
1.48
1.77
2.45
2.64
2.93
1.20
1.39
1.68
1.61
1.80
2.09
2.09
2.29
2.58
1.52
1.72
2.01
2.09
2.29
2.58
2.67
2.87
3.16
20
0.94
1.13
1.42
1.56
1.76
2.05
1.22
1.41
1.70
1.87
2.07
2.35
1.41
1.60
1.89
2.57
2.76
3.05
1.32
1.51
1.80
1.83
1.92
2.21
2.21
2.41
2.70
1.64
1.84
2.13
2.21
2.41
2.70
2.79
2.99
3.28
Unit
µA
µA
V
V
V
V
V
µA
µA
mA
mA
V
V
V
V
V
V
V
V
V
V
V
V
No. 5730-5/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V
Parameter
Minimum input pulse width
Data setup time
Data hold time
One word write time
Symbol
Conditions
tW(SCLK)
tW(CS)
tSU(CS)
tSU(SIN)
th(CS)
th(SIN)
tword
twt
SCLK
CS (The period when CS is high)
CS
SIN
CS
SIN
The time to write 8 bits of data
The RAM data write time
Serial Data Input Timing
min
200
1
200
200
2
200
4.2
1
Ratings
typ
max
Unit
ns
µs
ns
ns
µs
ns
µs
µs
First byte
Second byte
A08681
No. 5730-6/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

System Block Diagram
LC74787, 74787M, 74787JM
No. 5730-7/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
Display Control Commands
Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of
a command identification code in the first byte and command data in the following bytes. The following commands are
supported.
1 COMMAND0: Display memory (VRAM) write address setup command
2 COMMAND1: Display character data write command
3 COMMAND2: Vertical display start position and vertical character size setup command
4 COMMAND3: Horizontal display start position and horizontal character size setup command
5 COMMAND4: Display control setup command
6 COMMAND5: Display control setup command
7 COMMAND6: Synchronizing signal detection setup command
8 COMMAND7: Display control setup command
9 COMMAND8: Display control setup command
10 COMMAND9: Display control setup command
11 COMMAND10: Display control setup command
Display Control Command Table
Command
COMMAND0
Write address setup
COMMAND1
Character write
COMMAND2
Vertical character size and vertical
display start position
COMMAND3
Horizontal character size and
horizontal display start position
COMMAND4
Display control
COMMAND5
Display control
COMMAND6
Synchronizing signal detection
COMMAND7
Display control
COMMAND8
Display control
COMMAND9
Display control
COMMAND10
Display control
First byte
Second byte
Command identification code
Data
Data
7654321076543210
1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0
1 0 0 1 0 0 0 at c7 c6 c5 c4 c3 c2 c1 c0
1 0 1 0 VS VS VS VS 0 FS VP VP VP VP VP VP
21 20 11 10
543210
1 0 1 1 HS HS HS HS 0 LC HP HP HP HP HP HP
21 20 11 10
543210
1 1 0 0 TST RAM OSC SYS 0 BLK BLK BLK BK BK RV DSP
MOD ERS STP RST
21010
ON
1 1 0 1 NP NP NON INT 0 NP 0 BCL CB PH PH PH
10 2 210
1 1 1 0 SEL MOD DIS MUT 0 RN RN RN SN SN SN SN
0 0 LIN
2103210
1 1 1 1 0 0 SEL CTL 0 0 0 VNP VSP MSK MSK EGL
13
SEL SEL ERS SEL
1 1 1 1 0 1 VSY HSY 0 LNA LNA LNA LNA LPA LPA LPA
SEL SEL
3210210
1 1 1 1 1 0 LNB MOD 0 LNB LNB LNB LNB LPB LPB LPB
SEL 2
3210210
1 1 1 1 1 1 LNC MOD 0 LNC LNC LNC LNC LPC LPC LPC
SEL 3
3210210
Once written, a first byte command identification code is stored until the next first byte is written. However, when the
display character data write command (COMMAND1) is written, the LC74787/M/JM locks into the display character
data write mode, and another first byte cannot be written.
When the CS pin is set high, the LC74787/M/JM is set to the COMMAND0 (display memory write address setup mode)
state.
No. 5730-8/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND0 (Display memory write address setup command)
• First byte
DA
Register
0 to 7
7—
6—
5—
4—
3 V3
2 V2
1 V1
0 V0
Contents
State
Function
1
0 Command 0 identification code
0 Sets the display memory write address.
0
0
1
0
1
Display memory line address (0 to B hexadecimal)
0
1
0
1
• Second byte
DA
0 to 7
7
6
Register
Contents
State
Function
0 Second byte identification code
0
5 —0
0
4 H4
1
0
3 H3
1
0
2 H2
Display memory column address (0 to 17 hexadecimal)
1
0
1 H1
1
0
0 H0
1
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
Notes
Notes
No. 5730-9/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND1 (Display character data write setup command)
• First byte
DA
Register
0 to 7
7—
6—
5—
4—
3—
2—
1—
0 at
Contents
State
Function
1
0 Command 1 identification code.
0 Sets up display character data write mode.
1
0
0
0
0 Character attribute off
1 Character attribute on
Notes
When this command is input, the LC74787/M/JM
locks in the display character data write mode until
the CS pin goes high
• Second byte
DA
0 to 7
7
6
5
4
3
2
1
0
Register
c7
c6
c5
c4
c3
c2
c1
c0
Contents
State
Function
0
1
0
1
0
1 Character code (00 to FF hexadecimal)
0
1 (FE (hex): spacing character)
0 (FF (hex): transparent spacing character)
1
0
1
0
1
0
1
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
Notes
No. 5730-10/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND2: Vertical display start position and vertical character size setup command
• First byte
DA
Register
0 to 7
7—
6—
5—
4—
3 VS21
2 VS20
1 VS11
0 VS10
Contents
State
Function
1
0 Command 2 identification code.
1 Sets the vertical display start position and the vertical character size.
0
0
1 VS21
VS20
00
11
0
1H/dot
3H/dot
1
2H/dot
1H/dot
0
1 VS11
VS10
00
11
0
1H/dot
3H/dot
1
2H/dot
1H/dot
Notes
Second line vertical character size
First line vertical character size
• Second byte
DA
0 to 7
7
6
5
4
3
2
1
0
Register
FS
VP5
(MSB)
VP4
VP3
VP2
VP1
VP0
(LSB)
Contents
State
Function
0 Second byte identification bit
0 Crystal oscillator frequency: 2fsc
1 Crystal oscillator frequency: 4fsc
0 If VS is the vertical display start position then:
5
1 VS = α + H × (2Σ 2n VPn)
n=0
0 H: the horizontal synchronization pulse period
1 α = 20 H (in 525-line systems)
0 = 25 H (in 625-line systems)
1
0
1
0
1 Character
0 display area
1
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
Notes
The vertical display start position is set by the 6 bits
VP0 to VP5.
The weight of bit 1 is 2H.
No. 5730-11/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND3 (Horizontal display start position and horizontal size setup command)
• First byte
DA
Register
0 to 7
7—
6—
5—
4—
3 HS21
2 HS20
1 HS11
0 HS10
Contents
State
Function
1
0 Command 3 identification code.
1 Sets the horizontal display start position and the horizontal character size.
1
0
1 HS21
HS20
00
11
0
1 Tc/dot
3 Tc/dot
1
2 Tc/dot
1 Tc/dot
0
1 HS11
HS10
00
11
0
1 Tc/dot
3 Tc/dot
1
2 Tc/dot
1 Tc/dot
Notes
Second line horizontal character size
First line horizontal character size
• Second byte
DA
0 to 7
7
6
5
4
3
2
1
0
Register
LC
HP5
(MSB)
HP4
HP3
HP2
HP1
HP0
(LSB)
Contents
State
Function
0 Second byte identification bit
0 Use the LC oscillator for the dot clock
1 Use the crystal oscillator for the dot clock
0 If HS is the horizontal start position then:
5
1 HS =Tc × (2Σ 2n HPn)
n=0
0 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating
1 mode.
0
1
0
1
0
1
0
1
Notes
Selects the dot clock used for character display in the
horizontal direction
The horizontal display start position is set by the 6
bits HP0 to HP5.
The weight of bit 1 is 2Tc.
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
No. 5730-12/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND4 (Display control setup command)
• First byte
DA
Register
0 to 7
State
Contents
Function
7 —1
6 — 1 Command 4 identification code
5 — 0 Display character data write setup
4 —0
0 Normal operating mode
3 TSTMOD
1 Test mode
0
2 RAMERS
1 Erase display RAM. (The RAM data is set to FF hexadecimal.)
0 Do not stop the crystal and LC oscillators
1 OSCSTP
1 Stop the crystal and LC oscillators
0
0 SYSRST
1 Reset all registers and turn display off
Notes
This bit must be set to 0
Erasing RAM takes about 500 µs. (This operation
must be executed in the DSPOFF state.)
Valid in external synchronization mode when
character display is off
The registers are reset when the CS pin is low, and
the reset state is cleared when CS is set high
• Second byte
DA
0 to 7
7
6
5
4
3
2
1
0
Register
BLK2
BLK1
BLK0
BK1
BK0
RV
DSPON
Contents
State
Function
0 Second byte identification bit
0 Character display area
1 Video display area
0
1 BLK1
BLK0
00
11
0
Blanking off
Frame size
0 Blinking period: About 0.5 s
1 Blinking period: About 1.0 s
0 Blinking off
1 Blinking on
0 Reverse video off
1 Reverse video on
0 Character display off
1 Character display on
1
Character size
Complete fill in
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
Notes
Specifies the size for complete fill in
Changes the blanking size
Switches the blinking period
Blinking in reverse video mode switches the display between
normal character display and reverse video display
No. 5730-13/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND5 (Display control setup command)
• First byte
DA
Register
0 to 7
7—
6—
5—
4—
Contents
State
Function
1
1 Command 5 identification code.
0 Display control setup.
1
0
NP2
NP1
NP0
3 NP1
000
1
001
Format
NTSC
PAL-M
010
0011
PAL
PAL-N
2 NP0
1 0 0 NTSC4.43
1101
PAL60
0 Interlaced
1 NON
1 Noninterlaced
0 External synchronization
0 INT
1 Internal synchronization
Notes
Switches between the NTSC, PAL, PAL-N, PAL-M,
NTSC 4.43, and PAL60 formats
Switches between interlaced and noninterlaced video
Switches between external and internal
synchronization
• Second byte
DA
Register
0 to 7
7—
6 NP2
5—
4 BCL
3 CB
Contents
State
Function
0 Second byte identification bit
0
1
0
0 Background color on
1 No background color (Only the background level is set)
0 Color burst signal output
1 Color burst signal output stopped
2
PH2
0
PH2
PH1
PH0 Background color (phase)
1000
Cyan
001
Yellow
0010
1 PH1
011
1100
Red
Blue
Cyan blue
101
0110
Green
Orange
0 PH0
111
1
Magenta
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
Notes
Set with NP0 and NP1
Only valid in internal synchronization mode
Only valid when BCL is high
Background color specification
No. 5730-14/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND6 (Synchronizing signal detection setup command)
• First byte
DA
Register
0 to 7
7—
6—
5—
4—
Contents
State
Function
1
1 Command 6 identification code.
1 Sets up synchronizing signal control.
0
0
3 SEL0
1
0
2 MOD0
1
SEL0
0
0
1
1
MOD
0
1
0
1
SEPOUT output
Sync separator signal
Low-level output
High-level output
ST pulse signal
0 12 lines
1 DISLIN
1 10 lines
0 Normal output
0 MUT
1 CVIN is cut and CVOUT is held at the pedestal level
Notes
Switches the SEPOUT (pin 19) output
Switches the number of lines displayed
CVOUT switching
• Second byte
DA
0 to 7
7
6
5
4
3
2
1
0
Register
RN2
RN1
RN0
SN3
SN2
SN1
SN0
Contents
State
Function
0 Second byte identification bit
0
1
RN2
RN1
RN0 Number of times HSYNC detected
000
0
001
1
010
0
100
1
0 times
4 times
8 times
16 times
0
1 SN3 SN2 SN1 SN0 Number of times HSYNC detected
0 0000
Not detected
1 0001
32 times
0 0010
64 times
1 0100
128 times
0 1000
256 times
1
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
Notes
External synchronizing signal detection control
Signal absent signal present transition detection
Sets the sampling period in which SYNC can be
detected continuously in the horizontal synchronizing
signal period (1H).
External synchronizing signal detection control
Signal present signal absent transition detection
Sets the sampling period in which SYNC cannot be
detected continuously in the horizontal synchronizing
signal period (1H).
No. 5730-15/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND7 (Display control setup command)
• First byte
DA
Register
0 to 7
7—
6—
5—
4—
3—
2—
1 SEL1
0 CTL3
Contents
State
Function
1
1 Command 7 identification code.
1 Display control setup.
1
0
Extended command 0 identification code
0
0 Vertical synchronizing signal (external V separation) input
1 Frame signal input
0 Use internal V separation
1 Do not use internal V separation
Notes
Switches the SEPIN (pin 20) input.
Only valid when CTL3 is high.
Switches V separation.
• Second byte
DA
Register
0 to 7
State
Contents
Function
7 — 0 Second byte identification bit
6 —0
5 —0
0 V falling edge detection
4 VNPSEL
1 V rising edge detection
0 VSEP: about 8.9 µs (for NTSC)
3 VSPSEL
1 VSEP: about 17.8 µs (for NTSC)
0 Mask valid
2 MSKERS
1 Mask invalid
0 3H (for NTSC)
1 MSKSEL
1 20H (for NTSC)
0
EGL
0 Frame level 0 only (VBK0)
1 Two-stage frame level (VBK0 and VBK1)
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
Notes
Switches the V acquisition polarity in external mode
when internal V separation is used.
Switches the internal V separation period.
Clears the HSYNC and VSYNC masks.
Switches the VSYNC mask.
Switches the frame level.
(Only valid when BLK0 is 0 and BLK1 is 1.)
No. 5730-16/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND8 (Display control setup command)
• First byte
DA
Register
0 to 7
7—
6—
5—
4—
3—
2—
Contents
State
Function
1
1 Command 8 identification code.
1 Display control setup.
1
0
Extended command 1 identification code
1
0 Negative polarity
1 VSYSEL
1 Positive polarity
Notes
SEPIN input polarity switching.
Only valid when CTL3 is high.
0 Negative polarity
0 HSYSEL
1 Positive polarity
SYNIN (only valid when the sync separator circuit is
not used) and SEPOUT input and output polarity
switching
• Second byte
DA
Register
0 to 7
7—
Contents
State
Function
0 Second byte identification bit
Notes
0 LNA3 LNA2 LNA1 LNA0
Specified line
6 LNA1
0 0 0 0 Do not change the line background
1 0001
Line 1
0
5 LNA2
1
0
4 LNA1
1
0010
0011
0100
0101
0110
0111
1000
1001
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Specifies the line whose background is to be
changed.
(If the same line is specified to have different
background colors with LNA*, LNB*, and LNC*, then
the setting specified by the last command issued will
be valid. The previously specified registers (LN* and
LP*) will all be reset to 0.)
0
3 LNA0
1
1010
1011
1 1 ——
Line 10
Line 11
Line 12
0
2 LPA2
LPA2 LPA1 LPA0 Line background color (phase)
1000
Cyan
001
Yellow
0010
1 LPA1
011
1100
Red
Blue
Cyan blue
101
0110
0 LPA0
111
1
Green
Orange
Magenta
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
Specifies the background color.
No. 5730-17/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND9 (Display control setup command)
• First byte
DA
Register
0 to 7
7—
6—
5—
4—
3—
2—
1 LNBSEL
0 MOD2
State
Contents
Function
Notes
1
1 Command 9 identification code.
1 Display control setup.
1
1
Extended command 2 identification code
0
0 Normal line background color operation
Switches the RV mode background color for the line
RV characters have the background color specified by PH* or the RV specified by LNB* for characters specified for RV
1 character background color is white.
display.
0 The LNBSEL: 1 setting specifications
1
RV characters have the background color specified by PH*, characters Valid when LNBSEL is high
are white.
• Second byte
DA
Register
0 to 7
7—
Contents
State
Function
0 Second byte identification bit
Notes
0 LNB3 LNB2 LNB1 LNB0
Specified line
6 LNB3
0 0 0 0 Do not change the line background
1 0001
Line 1
0
5 LNB2
1
0
4 LNB1
1
0010
0011
0100
0101
0110
0111
1000
1001
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Specifies the line whose background is to be
changed.
(If the same line is specified to have different
background colors with LNA*, LNB*, and LNC*, then
the setting specified by the last command issued will
be valid. The previously specified registers (LN* and
LP*) will all be reset to 0.)
0
3 LNB0
1
1010
1011
1 1 ——
Line 10
Line 11
Line 12
0
2 LPB2
LPB2 LPB1 LPB0 Line background color (phase)
1000
Cyan
001
Yellow
0010
1 LPB1
011
1100
Red
Blue
Cyan blue
101
0110
0 LPB0
111
1
Green
Orange
Magenta
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
Specifies the background color.
No. 5730-18/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
COMMAND10 (Display control setup command)
• First byte
DA
Register
0 to 7
State
Contents
Function
Notes
7 —1
6 — 1 Command 10 identification code.
5 — 1 Display control setup.
4 —1
3 —1
Extended command 3 identification code
2 —1
0 Normal line background color operation
Switches the RV mode background color for the line
1 LNCSEL
RV characters have the background color specified by PH* or the RV specified by LNC* for characters specified for RV
1 character background color is white.
display.
0 The LNCSEL: 1 setting specifications
0
MOD3
1
RV characters have the background color specified by PH*, characters Valid when LNCSEL is high
are white.
• Second byte
DA
Register
0 to 7
7—
Contents
State
Function
0 Second byte identification bit
Notes
0 LNC3 LNC2 LNC1 LNC0
Specified line
6 LNC3
0 0 0 0 Do not change the line background
1 0001
Line 1
0
5 LNC2
1
0
4 LNC1
1
0010
0011
0100
0101
0110
0111
1000
1001
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Specifies the line whose background is to be
changed.
(If the same line is specified to have different
background colors with LNA*, LNB*, and LNC*, then
the setting specified by the last command issued will
be valid. The previously specified registers (LN* and
LP*) will all be reset to 0.)
0
3 LNC0
1
1010
1011
1 1 ——
Line 10
Line 11
Line 12
0
2 LPC2
LPC2 LPC1 LPC0 Line background color (phase)
1000
Cyan
001
Yellow
0010
1 LPC1
011
1100
Red
Blue
Cyan blue
101
0110
0 LPC0
111
1
Green
Orange
Magenta
Note: All registers are set to 0 when the LC74787/M/JM is reset by the RST pin.
Specifies the background color.
No. 5730-19/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
Display Screen Structure
The display consists of 12 lines of 24 characters.
Up to 288 characters can be displayed.
The number of characters that can be displayed is reduced when enlarged characters are displayed.
Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses.
Display Screen Structure (display memory addresses)
24 Characters
12 Rows
A08683
No. 5730-20/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
Composite Video Signal Output Levels (internally generated levels)
CVOUT output level waveform (VDD2 = 5.0 V)
Output level
VCHA : Character
VRH0 : Background color (other than blue) high
VRSH1, 2 : Blue background color 1 and 2 high
VBk1 : Frame 1
VCBH : Color burst high
VRSL2 : Blue background color 2 low
VBK0 : Frame 0
VPD : Pedestal
VRSL0 : Background color (other than blue) low
VRSL1 : Blue background color 1 low
VCBL : Color burst low
VSN : Sync
Output voltage (1) [V]
2.67
2.45
2.09
2.09
1.75
1.61
1.52
1.44
1.29
1.20
1.10
0.82
Output voltage (2) [V]
2.87
2.64
2.29
2.29
1.95
1.80
1.72
1.64
1.48
1.39
1.29
1.01
Output voltage (3) [V]
3.16
2.93
2.58
2.58
2.23
2.09
2.01
1.93
1.77
1.68
1.58
1.30
No. 5730-21/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
Sample Application Circuits (When the LC74787/M/JM is used in conjunction with a single-chip Y/C circuit.)
• Circuit Using an External System Clock Input
Micro-
controller
• Circuit Using a Crystal Oscillator
A08685
Micro-
controller
A08686
No. 5730-22/23


LC74787M (Sanyo Semicon Device)
On-Screen Display Controller

No Preview Available !

Click to Download PDF File for PC

LC74787, 74787M, 74787JM
• Circuit Using an External System Clock Input (when the pin 3 and 4 functions are modified by mask options)
Micro-
controller
A08687
Note: When a sync tip level of 1.3 V DC (CVIN input signal: sync tip = 1.3 V) is selected for the internal generated video signals by option settings, the
electrolytic capacitor connected to SYNIN must be connected with the correct polarity.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s Anyone purchasing any products described or contained herein for an above-mentioned use shall:
ΠAccept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of March, 1998. Specifications and information herein are subject to
change without notice.
PS No. 5730-23/23




LC74787M.pdf
Click to Download PDF File