LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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Ordering number : EN5159A
CMOS LSI
LC74772V
Camcorder On-Screen Display LSI
Overview
The LC74772V is a CMOS LSI that implements on-screen
display for camcorders. It displays characters and patterns
in a camcorder viewfinder under microprocessor control.
The LC74772V displays a 12 × 18 dot font with 256
characters.
Features
• Screen format: 12 lines ¥ 24 characters (up to 288
characters)
• Number of characters displayed: Up to 288 characters
• Character format: 12 (horizontal) × 18 (vertical) dots
• Number of characters in font: 256 characters
• Character sizes: Normal and double, specified in line
units
• Display start position
— Horizontal: 64 positions
— Vertical: 64 positions
• Character reverse video function: Individual characters
can be displayed in reverse video.
• Types of blinking: Two types with periods of 1.0 and
0.5 seconds, specifiable on a per character basis.
(Blinking has a 60% display on duty.)
(Four divisors: 1/25, 1/30, 1/50, 1/60)
• Outputs: R, G, B plus 2 output systems
Or: 4 output systems (character data and blanking data:
4 outputs each)
• External control input: 8-bit serial data input format
Package Dimensions
unit: mm
3175A-SSOP24
[LC74772V]
SANYO: SSOP24
Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD
VIN
VOUT
Pd max
Topr
Tstg
Conditions
VDD
All input pins
CKOUT, CHA4, BLK4, CHA3, BLK3, B, G, R, BLANK
Ta = 25°C
Ratings
VSS – 0.3 to VSS + 7.0
VSS – 0.3 to VDD + 0.3
VSS – 0.3 to VDD + 0.3
300
–30 to +70
–40 to +125
Unit
V
V
V
mW
°C
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
O3096HA(OT)/D3095HA (OT) No. 5159-1/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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LC74772V
Allowable Operating Ranges at Ta = –30 to +70°C
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
Oscillator frequency
Symbol
Conditions
VDD
VIH
VIL
FOSC
VDD
CTRL1, TESTIN, CS, SCLK, SIN, OUTMOD, HSYNC,
VSYNC, RST
CTRL1, TESTIN, CS, SCLK, SIN, OUTMOD, HSYNC,
VSYNC, RST
OSCIN, OSCOUT (LC oscillator)
min
2.7
0.8 VDD
VSS – 0.3
6
Ratings
typ
5.0
max
5.5
VDD + 0.3
Unit
V
V
0.2 VDD
V
(8) 10 MHz
Electrical Characteristics at Ta = –30 to +70°C, unless otherwise specified VDD = 5 V
Parameter
Output high-level voltage
Output low-level voltage
Input current
Operating current drain
Symbol
Conditions
CKOUT, CHA4, BLK4, CHA3, BLK3, B, G, R, BLANK:
VOH VDD = 5.5 to 4.5 V (VDD = 4.4 to 2.7 V), IOH = –1.0 mA
(–0.5 mA)
CKOUT, CHA4, BLK4, CHA3, BLK3, B, G, R, BLANK:
VOL VDD = 5.5 to 4.5 V (VDD = 4.4 to 2.7 V), IOL = 1.0 mA
(0.5 mA)
IIH
CTRL1, TESTIN, CS, SCLK, SIN, OUTMOD, HSYNC,
VSYNC: VIN = VDD
IIL CTRL1, TESTIN, HSYNC, VSYNC: VIN = VSS
IDD VDD pin; all outputs open, LC oscillator: 8 MHz
min
0.9 VDD
–1
Ratings
typ
Unit
max
V
0.1 VDD
V
1 µA
µA
10 mA
Timing Characteristics at Ta = –30 to +70°C, VDD = 5 ± 0.5 V
Parameter
Minimum input pulse width
Data setup time
Data hold time
One-word write time
Symbol
Conditions
tW (SCLK)
tW (CS)
tSU (CS)
tSU (SIN)
th (CS)
th (SIN)
tword
twt
SCLK
CS (the period that CS is high)
CS
SIN
CS
SIN
The time to write 8 bits of data
The RAM data write time
min
200
1
200
200
2
200
4.2
1
Ratings
typ
max
Unit
ns
µs
ns
ns
µs
ns
µs
µs
No. 5159-2/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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Serial Data Input Timing
LC74772V
Pin Assignment
The signal names in parentheses indicate the output pin functions when 4-system output mode is used.
No. 5159-3/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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LC74772V
Pin Functions
PinNo.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
VSS
OSCIN
OSCOUT
CTRL1
TESTIN
CS
SCLK
SIN
CKOUT
BLK4
CHA4
NC
NC
BLK3
CHA3
BLANK
R
G
B
OUTMOD
VSYNC
HSYNC
RST
VDD
Function
Ground
LC oscillator
Clock input control
Test control input
Enable input
Clock input
Data input
Clock output
Blanking signal output
Character data output
Unused
Unused
Blanking signal output
Character data output
Blanking signal output
Character data output
Character data output
Character data output
Output control input
Vertical synchronizing
signal input
Horizontal synchronizing
Reset input
Power supply
Ground connection
Description
Connections for the coil and capacitor that form the oscillator that generates the character
output horizontal dot clock.
Control input that switches between LC oscillator mode and clock input mode
Low: LC oscillator mode, high: clock input mode
Test mode control input (The IC operates in test mode when this input is high.)
Serial data input enable input
Low: active (This input has hysteresis characteristics.)
Serial data input clock input (This input has hysteresis characteristics.)
Serial data input (This input has hysteresis characteristics.)
LC oscillator clock monitor output
This signal is output when RST is low.
Blanking signal output (system 2)
Functions as the system 4 blanking data signal output in 4-system mode.
Character data signal output (system 2)
Functions as the system 4 character data signal output in 4-system mode.
Must be left open or tied to ground in normal operation.
Must be left open or tied to ground in normal operation.
Blanking signal output (system 1)
Functions as the system 3 blanking data signal output in 4-system mode.
Character data signal output (system 1)
Functions as the system 3 character data signal output in 4-system mode.
Blanking signal output (blanking signal for RGB output)
Functions as the system 2 blanking data signal output in 4-system mode.
Character data (R) signal output
Functions as the system 2 character data signal output in 4-system mode.
Character data (G) signal output
Functions as the system 1 blanking data signal output in 4-system mode.
Character data (B) signal output
Functions as the system 1 character data signal output in 4-system mode.
Control input that switches between RGB output and 4-system output
Low: RGB output, high 4-system output
Vertical synchronizing signal input (This input has hysteresis characteristics.)
Horizontal synchronizing signal input (This input has hysteresis characteristics.)
signal input
System reset signal input (This input has hysteresis characteristics.)
Power supply connection (+5 V)
Note: 1. Built-in pull-up resistors can be specified for inclusion in the CS (pin 6), SCLK (pin 7), SIN (pin 8), and RST (pin 23) pins as mask options.
2. In clock input mode (when CTRL1 is high), the function that holds the OSCIN (pin 2) pin high during an oscillator reset is stopped.
No. 5159-4/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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Block Diagram
LC74772V
No. 5159-5/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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LC74772V
Display Control Commands
The display control commands have an 8-bit serial input format. Data is input LSB first.
Display Control Command Table
Command
COMMAND 0
System setup 1
COMMAND 1
System setup 2
COMMAND 2
Input control setup
COMMAND 3
General-purpose port control
COMMAND 4
Display operation control:
reverse video and blinking
COMMAND 5
Display control: on/off settings
for each output
COMMAND 6
Output control: systems 3 and 4
COMMAND 8
Display control: border
COMMAND 9
Display start position
COMMAND 10
Display line control
COMMAND 11
RAM write address
COMMAND 14
Display RAM setup data
First byte
Second byte
Command code
Data
Data
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
RST RAM OSC TST
0 0 0 0 SYS CLR STP MOD — — — — — — — —
CSYN CLK CLK CLK
0 0 0 1 MOD POLT MOD1 MOD0 — — — — — — — —
VSYN HSYN DATA ART
0 0 1 0 POLT POLT FMT FMT — — — — — — — —
PORT OUT OUT OUT
0 0 1 1 SET P11 P10 P9 — — — — — — — —
0 1 0 0 RVS BLK BLK BLK — — — — — — — —
ON ON 1
0
0 1 0 1 DSP DSP DSP DSP — — — — — — — —
4321
DSPF DSP DSP DSP
0 1 1 0 SL34 RSG GSG BSG — — — — — — — —
BKC BKC BKC BKO4 BKO4 BKO3 BKO3 BKO2 BKO2 BKO1 BKO1
1 0 0 0 0 R G B F1 F0 F1 F0 F1 F0 F1 F0
1 0 0 1 VP5 VP4 VP3 VP2 VP1 VP0 HP5 HP4 HP3 HP2 HP1 HP0
LNF LNF LNF LN
LIN LIN LIN LIN LIN LIN
1 0 1 0 SZ OT4 OT3 SEL 0 0 126 115 104 93 82 71
VADR VADR VADR VADR
HADR HADR HADR HADR HADR
1011321000043210
1 1 1 BLK RV R G B C7 C6 C5 C4 C3 C2 C1 C0
xy
x Command code: (These 4 bits in the first byte identify the command.)
Command 14 is recognized by the upper 3 bits.
y Command data: (These bits specify the data for each command.)
• For commands 0 through 7, 8 bits of data are read in.
• For commands 8 through 14, 16 bits of data are read in.
• If the command 1 data-9 bit (DATAFMT) was set to 1, after the first byte of a command 14 is read
in, the system goes to continuous transfer mode for reading in a series of following bytes.
Note: 1. If the CS pin is set high, the command state is set to the command 0 (system control setup) state.
2. If a system reset is executed from the RST pin or by a command reset, the command register is set tot 0.
No. 5159-6/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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LC74772V
x COMMAND 0 (System control setup 1)
First byte
DA0 to DA7 Register name
State
Register content
Function
Note
7 —0
6 —0
Command 0 identification code
5 —0
4 —0
3
RST
SYS
0 Normal operation
1 System reset
If CS is low, the reset is executed, but if
CS is high this command will be excluded.
2
RAM
CLR
0 Normal operation
The VRAM clear operation is not
executed when the oscillator
1 Normal operation VRAM clear (All data is set to FE (hexadecimal)) is stopped.
1
OSC
STP
0 The LC oscillator operating state is maintained.
1 The LC oscillator is stopped.
Valid when the display is off. VRAM write
is not possible when the oscillator is
stopped.
0
TST
MOD
0 Normal operation
1 Test mode
Illegal setting.
This bit must always be set to 0.
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Notes on command settings
1. RSTSYS: A command reset is executed immediately after the data is read.
The reset is cleared by returning the CS pin to high to reset this register. The reset is also cleared if this command is
executed consecutively or if this register is set to 0.
2. RAMCLR: The RAM can only be erased when display is off. This operation is not executed during display. This
operation cannot be executed if the LC oscillator is stopped. Only use this command when the LC oscillator is
operating.
• This command bit is automatically cleared when the RAM erase operation completes.
• Once the RAM erase command has been read in, the following time is required to complete the operation.
— Tclear = 5 [µs] + 4/fOSC (LC-oscillator) × 288
3. OSCSTP: The LC oscillator stop command stops the LC oscillator connected to pins 2 and 3 (OSCIN and OSCOUT).
The oscillator stop command is only executed when display is off. It is not executed if display is in progress.
• In external clock input mode, this command stops the acquisition of that clock signal.
4. TSTMOD: The test mode command is executed if the TESTIN pin (pin 5) is high. This command should not be used
by applications in normal operation.
No. 5159-7/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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LC74772V
y COMMAND 1 (System control setup 2)
First byte
DA0 to DA7
7
6
5
4
3
2
Register name
CSYN
MOD
CLK
POLT
State
0
0
0
1
0
1
0
1
Register content
Function
Command 1 identification code
HSYNC (pin 22) functions as the horizontal synchronizing
signal input
HSYNC (pin 22) functions as the composite synchronizing
signal input
The system clock has a positive polarity.
The system clock has a negative polarity.
1
CLK
MOD1
0
MOD1 MOD0
Operation
1 0 0 LC oscillator mode
0 1 Clock input (1 dot)
CLK
0 1 0 Clock input (NTSC)
0 MOD0 1 1 1 Clock input (PAL)
Note
The VSYNC pin (pin 21) must be tied to
ground or VDD in composite
synchronizing signal input mode.
This sets the clock polarity for system
operation when pin 2 is used as a clock
input.
Valid when the CTRL1 pin (pin 4) is high.
The input clock frequency in clock input
mode is either 4fsc or the dot clock
frequency.
z COMMAND 2 (Input control)
First byte
DA0 to DA7
7
6
5
4
3
2
Register name
VSYN
POLT
HSYN
POLT
State
0
0
1
0
0
1
0
1
Register content
Function
Command 2 identification code
The vertical synchronizing signal input polarity is low active.
The vertical synchronizing signal input polarity is high active.
The horizontal synchronizing signal input polarity is low active.
The horizontal synchronizing signal input polarity is high active.
0 Data is transferred in 16-bit units.
1 DATA
FMT
Continuous transfers with the upper 8 bits input first and then
1 the lower 8 bits
0
ATR
FMT
0 RV specifies the reverse video display function.
1 RV specifies system 3 output control.
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Note
Sets the pin 21 (VSYNC) signal input
polarity.
Sets the pin 22 (HSYNC) signal input
polarity.
Sets the COMMAND 14 data transfer
format.
COMMAND-14 Data 11: Valid in RV
RGB output mode.
No. 5159-8/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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LC74772V
{ COMMAND 3 (General-purpose port control)
First byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
PORT
SET
OUT
P11
OUT
P10
OUT
P9
State
0
0
1
1
0
1
0
1
0
1
0
1
Register content
Function
Command 3 identification code
System 4 functions as a normal character and border outputs.
System 4 functions as general-purpose ports.
The pin 11 output is set to low.
The pin 11 output is set to high.
The pin 10 output is set to low.
The pin 10 output is set to high.
The pin 9 output is set to low.
The pin 9 output is set to high.
Note
Controls the pin 10 (BLK4) and pin 11
(CHA4) outputs.
Sets the output when PORTSET is
set to 1.
Sets the output when PORTSET is
set to 1.
Sets the output for pin 9 during normal
operation (other than during a reset).
| COMMAND 4 (Display control: reverse video and blinking)
First byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
RVS
ON
BLK
ON
BLK1
BLK0
State
0
1
0
0
Register content
Function
Command 4 identification code
0—
Characters for which the attribute is specified are displayed
1 in reverse video.
0—
Characters for which the attribute is specified are
1 displayed blinking.
0
BLK1 BLK0
Operation
1 0 0 V × 25 (PAL: 0.5 s)
0 1 V × 30 (NTSC: 0.5 s)
0 1 0 V × 50 (PAL: 1.0 s)
1 1 V × 60 (NTSC: 1.0 s)
1
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Note
The blinking period setting
The duty is 60% for all types.
Character display on: 60%
Character display off: 40%
V: Vertical period
No. 5159-9/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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LC74772V
} COMMAND 5 (Display control: on/off settings for each output system)
First byte
DA0 to DA7
7
6
5
4
3
2
1
Register name
DSP4
DSP3
DSP2
State
0
1
0
1
0
1
0
1
Register content
Function
Command 5 identification code
System 4 output off
System 4 output on
System 3 output off
System 3 output on
0 System 2 output off
1 System 2 output on
0 System 1 (RGB) output off
0 DSP1
1 System 1 (RGB) output on
Note
Pin 10 (BLK4) and pin 11 (CHA4) output
control
Pin 14 (BLK3) and pin 15 (CHA3) output
control
Pin 16 (BLK2) and pin 17 (CHA2) output
control
Invalid in RGB output mode.
Pin 18 (BLK1) and pin 19 (CHA1) output
control
Functions as the RGB output control in
RGB output mode.
~ COMMAND 6 (Output control: systems 3 and 4 output control settings)
First byte
DA0 to DA7
7
6
5
4
3
Register name
DSPF
SL34
State
0
1
1
0
0
1
Register content
Function
Command 6 identification code
Sets the system 3 output conditions according to the command
described below.
Sets the system 4 output conditions according to the command
described below.
0 DSPRSG DSPGSG DSPBSG
Output selection
2
DSP
RSG
Signals other than R, G,
1 0 0 0 B are output.
0 0 1 B is output.
1
DSP
GSG
0 0 1 0 G is output.
0 1 1 G and B are output.
1
1 0 0 R is output.
0 1 0 1 R and B are output.
0
DSP
BSG
1 1 0 R and G are output.
1 1 1 1 All of R, G, B are output.
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Note
Only system 4 is valid in 4-system
output mode. System 4 cannot be set
when the general-purpose output port
usage is specified.
Note: The following registers are set to
1 during a reset.
DSPRSG
DSPGSG
DSPBSG
As a result, the “All of R, G, B are
output” state is selected during a
reset.
No. 5159-10/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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LC74772V
 COMMAND 8 (Output control: background color setting: RGB output mode)
First byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
BKCR
BKCG
BKCB
State
1
0
0
0
0
Register content
Function
Command 8 identification code
0 BKCR BKCG BKCB
Background color
1 0 0 0 Black
0 0 1 Blue
0 0 1 0 Green
0 1 1 Cyan
1 1 0 0 Red
1 0 1 Magenta
0 1 1 0 Yellow
1 1 1 1 White
Note
Background color setting in RGB output
mode
This command is invalid in 4-system
output mode.
• Invalid when pin 20 (OUTMOD) is high.
• Valid when pin 20 (OUTMOD) is low.
Second byte
DA0 to DA7
7
Register name
BKO4
F1
State
0
1
0
6
BKO4
F0
1
Register content
Function
BKO4F1 BKO4F0
Operation function
0 0 No background or border
0 1 Font size (black characters)
1 0 Border
1 1 Areas other than the font (all filled)
0
5
BKO3
F1
BKO3F1 BKO3F0
Operation function
1 0 0 No background or border
0 1 Font size (black characters)
4
BKO3 0 1 0 Border
F0 1 1 Areas other than the font (all filled)
1
0
3
BKO2
F1
BKO2F1 BKO2F0
Operation function
1 0 0 No background or border
0 1 Font size (black characters)
2
BKO2 0 1 0 Border
F0 1 1 Areas other than the font (all filled)
1
0
1
BKO1
F1
BKO1F1 BKO1F0
Operation function
1 0 0 No background or border
0 1 Font size
0
BKO1 0 1 0 Border
F0 1 1 Areas other than the font (all filled)
1
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Note
The system 4 output border setting
The system 3 output border setting
The system 2 output border setting
This command is invalid in RGB output
mode.
• Invalid when pin 20 (OUTMOD) is low.
• Valid when pin 20 (OUTMOD) is high.
The system 1 or RGB output border
setting
No. 5159-11/16


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Camcorder On-Screen Display LSI

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LC74772V
€ COMMAND 9 (Display start position setting)
First byte
DA0 to DA7
7
6
5
4
3
2
Register name
VP5
VP4
State
1
0
0
1
0
1
0
Register content
Function
Command 9 identification code
If VS is the vertical display start position then:
5
VS = H × (Σ 2nVPn) + 16H
n=0
Where H is horizontal period pulse period.
1
0
1 VP3
1
0
0 VP2
1
Second byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
VP1
VP0
HP5
HP4
HP3
HP2
HP1
HP0
State
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register content
Function
If VS is the horizontal display start position then:
5
HS = Tc × (Σ 2nHPn) + 12Tc
n=0
Where Tc is a single period of the LC oscillator connected to pins
2 and 3 (OSCIN and OSCOUT), or:
Tc is the period of the input clock (4fsc input) if CTRL1 (pin 4) is
high.
NTSC mode: 7.159 MHz = 4fsc × 1/2
PAL mode: 7.094 MHz = 4fsc × 2/5
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Note
Note
No. 5159-12/16


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LC74772V
 COMMAND 10 (Display line control)
First byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
LNF
SZ
LNF
OT4
LNF
OT3
LNF
SEL
State
1
0
1
0
0
1
0
1
0
1
0
1
Register content
Function
Command 10 identification code
Sets the character size.
Sets the system 4 display line.
Sets the system 3 display line.
The line specified by the next 6 bits is one of lines 1 to 6.
The line specified by the next 6 bits is one of lines 7 to 12.
Second byte
DA0 to DA7
7
6
5
Register name
LIN
126
State
0
0
0
1
Register content
Function
Clears the line 6 (12) setting.
Sets line 6 (12).
4
LIN 0 Clears the line 5 (11) setting.
115 1 Sets line 5 (11).
3
LIN 0 Clears the line 4 (10) setting.
104 1 Sets line 4 (10).
2
LIN 0 Clears the line 3 (9) setting.
93 1 Sets line 3 (9).
1
LIN 0 Clears the line 2 (8) setting.
82 1 Sets line 2 (8).
0
LIN 0 Clears the line 1 (7) setting.
71 1 Sets line 1 (7).
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Note
Invalid in general-purpose port mode.
Invalid in system 4 output setup mode.
Controls the line switching specified by
the six bits in the second byte.
Note
The character size or display line
setting
0: Character size specification = normal
Display line specification = off
1: Character size specification = double
size
Display line specification = on
No. 5159-13/16


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Camcorder On-Screen Display LSI

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LC74772V
11 COMMAND 11 (Display RAM write address setting)
First byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
VADR
3
VADR
2
VADR
1
VADR
0
State
1
0
1
1
0
1
0
1
0
1
0
1
Register content
Function
Command 11 identification code
The range of the display RAM vertical address (line address)
setting is from 0 to B (hexadecimal) (12 lines).
Values of C (hexadecimal) or larger are not allowed.
Second byte
DA0 to DA7
7
6
5
Register name
State
0
0
0
Register content
Function
4
HADR
4
0
1
3
HADR
3
0
1
2
HADR
2
0 The range of the display RAM horizontal address (character
address) setting is from 00 to 17 (hexadecimal) (24 characters).
1 Values of 18 (hexadecimal) or larger are not allowed.
1
HADR
1
0
1
0
HADR
0
0
1
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Note
Note
No. 5159-14/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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LC74772V
12 COMMAND 14 (Display RAM setup data)
First byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
BLK
RV
R
G
B
State
1
1
1
0
1
0
1
0
1
0
1
0
1
Register content
Function
Command 14 identification code
Blinking character specification
Reverse video character specification
R output specification (system 3 output in 4-system output mode)
G output specification (system 2 output in 4-system output mode)
B output specification (system 1 output in 4-system output mode)
Second byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
C7
C6
C5
C4
C3
C2
C1
C0
State
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register content
Function
Character code setting
There are 256 characters (00 to FF hexadecimal).
FE hexadecimal is handled as blank data.
Nothing is displayed, whatever the other conditions are set to.
FF hexadecimal functions as the transfer termination code for
character-code-only continuous transfers.
Continuous transfer mode is set up by setting the data 0 bit
(DATAFMT) in COMMAND 2 to 1.
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Note
Note
No. 5159-15/16


LC74772V (Sanyo Semicon Device)
Camcorder On-Screen Display LSI

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LC74772V
Display Screen Organization
The display screen consists of 12 lines of 24 characters each.
Thus the maximum number of characters that can be displayed is 288 characters.
The display memory address consists of a line address (VADR0, VADR1, VADR2, and VADR3 representing values
from 0 to B (hexadecimal)), and a column (character position) address (HADR0, HADR1, HADR2, HADR3, and
HADR4 representing values from 0 to 17 (hexadecimal)).
Display Screen Organization (Display memory address)
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s Anyone purchasing any products described or contained herein for an above-mentioned use shall:
ΠAccept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 1997. Specifications and information herein are subject to
change without notice.
No. 5159-16/16




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