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User’s Manual
µPD780208 Subseries
8-Bit Single-Chip Microcontrollers
µPD780204
µPD780204A
µPD780205
µPD780205Awww.DataSheet4U.com
µPD780206
µPD780208
µPD78P0208
Document No. U11302EJ4V0UM00 (4th edition)
Date Published July 2003 N CP(K)
c
Printed in Japan


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[MEMO]
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
www.DataSheet4U.comreset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
FIP and IEBus are trademarks of NEC Electronics Corporation.
MS-DOS, Windows, and Windows NT are either registered trademarks or trademarks of Microsoft Corporation
in the United States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
TRON stands for The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
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These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
The information in this document is current as of January, 2003. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
www.DataESlehceetrto4Uni.ccosmproduct depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
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NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Users Manual U11302EJ4V0UM
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Page
Throughout
p.29
p.32
p.33
p.42
p.43
p.48
p.67
p.90
p.91
p.92
p.93
p.94
p.103
p.133
p.144
p.171
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p.188
p.340
p.343
p.361
p.364
p.373
p.398
p.399
Major Revisions in This Edition
Description
Addition of the following products to target products
µPD780204A
µPD780205A
Deletion of the following package from target products
µPD78P0208KL-T (100-pin ceramic WQFN)
CHAPTER 1 OUTLINE
• Update of 1.6 78K/0 Series Lineup
• Addition of Note in 1.8 Overview of Functions
• Addition of Caution in Table 1-1 Mask Options in Mask ROM Versions
CHAPTER 2 PIN FUNCTIONS
• Addition of 2.2.12 VLOAD
• Modification of Table 2-1 Types of Pin I/O Circuits
CHAPTER 3 CPU ARCHITECTURE
• Addition of Caution in 3.1 Memory Space
• Modification of Note in Table 3-3 Special-Function Register List
CHAPTER 4 PORT FUNCTIONS
• Addition of Caution in 4.2.6 Port 8
• Addition of Caution in 4.2.7 Port 9
• Addition of Caution in 4.2.8 Port 10
• Addition of Caution in 4.2.9 Port 11
• Addition of Caution in 4.2.10 Port 12
CHAPTER 5 CLOCK GENERATOR
• Addition of Note in Figure 5-3 Format of Processor Clock Control Register
CHAPTER 6 16-BIT TIMER/EVENT COUNTER
• Modification of Caution in Figure 6-8 Format of External Interrupt Mode Register
• Modification of 6.6 (5) Valid edge setting
CHAPTER 8 WATCH TIMER
• Modification of Caution in Figure 8-2 Format of Timer Clock Select Register 2
CHAPTER 9 WATCHDOG TIMER
• Modification of Caution in Figure 9-2 Format of Timer Clock Select Register 2
CHAPTER 11 BUZZER OUTPUT CONTROLLER
• Modification of Caution in Figure 11-2 Format of Timer Clock Select Register 2
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
• Addition of Caution in Figure 16-2 Format of Interrupt Request Flag Register
• Modification of Caution in Figure 16-5 Format of External Interrupt Mode Register
CHAPTER 17 STANDBY FUNCTION
• Addition of description in Table 17-1 HALT Mode Operating Status
• Addition of description in Table 17-3 STOP Mode Operating Status
CHAPTER 19 µPD78P0208
• Modification of Table 19-2 Internal Memory Size Switching Register Setting Values
APPENDIX A DIFFERENCES BETWEEN µPD78044H, 780228, AND 780208 SUBSERIES
• Modification of description in Table A-1 Major Differences Between µPD78044H, 780228, and
780208 Subseries
APPENDIX B DEVELOPMENT TOOLS
• Modification of description
The mark shows major revised points.
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INTRODUCTION
Readers
This manual has been prepared for user engineers who wish to understand the functions of the
µPD780208 Subseries and design and develop its application systems and programs.
Purpose
This manual is intended to give users an understanding of the functions described in the Organization
below.
Organization The µPD780208 Subseries manual consists of two parts: this manual and Instructions (common to
the 78K/0 Series)
µPD780208 Subseries
User’s Manual
(This manual)
78K/0 Series
Instructions
User’s Manual
• Pin functions
• Internal block functions
• Interrupts
• Other on-chip peripheral functions
• CPU functions
• Instruction set
• Explanation of each instruction
How to Read This Manual
It is assumed that the reader of this manual has general knowledge in the fields of electrical
engineering, logic circuits, and microcontrollers.
www.DataSheet4U.com
For an understanding of functions in general:
Read this manual in the order of the CONTENTS.
For how to interpret the register format:
For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the
RA78K0, and is defined in the header file named sfrbit.h in the CC78K0.
To confirm the details of a register whose register name is known:
Refer to APPENDIX C REGISTER INDEX.
For the details of µPD780208 Subseries instruction functions:
Refer to 78K/0 Series Instructions User’s Manual (U12326E).
For the electrical specifications of the µPD780208 Subseries:
Refer to the separate µPD780204, 780205, 780206, 780208 Data Sheet (U10436E) and
µPD78P0208 Data Sheet (U11295E).
For application examples of the µPD780208 Subseries:
Refer to the separate 78K/0 Series Basics (II) Application Note (U10121E).
Conventions
Data significance:
Active low representation:
Note:
Caution:
Remark:
Numerical representation:
Higher digits on the left and lower digits on the right
xxx (overscore over pin or signal name)
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Binary .................. xxxx or xxxxB
Decimal ............... xxxx
Hexadecimal ....... xxxxH
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Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
µPD780204, 780205, 780206, 780208 Data Sheet
µPD78P0208 Data Sheet
µPD780208 Subseries Users Manual
78K/0 Series Instructions Users Manual
78K/0 Series Basic (II) Application Note
Document No.
U10436E
U11295E
This manual
U12326E
U10121E
Documents Related to Software Development Tools (User’s Manuals)
Document Name
Document No.
RA78K0 Assembler Package
Operation
U14445E
Language
U14446E
Structured Assembly Language
U11789E
CC78K0 C Compiler
Operation
U14297E
Language
U14298E
SM78K Series System Simulator Ver. 2.30 or Later
Operation (WindowsTM Based)
U15373E
External Part User Open Interface Specification U15802E
ID78K Series Integrated Debugger Ver. 2.30 or Later
Operation (Windows Based)
U15185E
RX78K0 Real-Time OS
Fundamentals
U11537E
Installation
U11536E
Project Manager Ver. 3.12 or Later (Windows Based)
U14610E
www.DaDtaoSchueemt4eUn.tcsomRelated to Hardware Development Tools (User’s Manuals)
Document Name
Document No.
IE-78K0-NS In-Circuit Emulator
U13731E
IE-78K0-NS-A In-Circuit Emulator
IE-780208-NS-EM1 Emulation Board
U14889E
U13691E
IE-78001-R-A In-Circuit Emulator
U14142E
IE-780208-R-EM Emulation Board
EEU-1501
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
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Documents Related to PROM Writing (User’s Manuals)
PG-1500 PROM Programmer
PG-1500 Controller
Document Name
PC-9800 Series (MS-DOSTM Based)
IBM PC Series (PC DOSTM Based)
Document No.
U11940E
EEU-1291
U10540E
Other Related Documents
Document Name
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
Semiconductor Device Mount Manual
Quality Grades on NEC Semiconductor Devices
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Document No.
X13769X
Note
C11531E
C10983E
C11892E
Note See the Semiconductor Device Mount Manualwebsite (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
www.DataSheet4U.com
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CONTENTS
CHAPTER 1 OUTLINE .........................................................................................................................
1.1 Features ...............................................................................................................................
1.2 Applications .........................................................................................................................
1.3 Ordering Information ..........................................................................................................
1.4 Quality Grade ......................................................................................................................
1.5 Pin Configuration (Top View) ............................................................................................
1.6 78K/0 Series Lineup ...........................................................................................................
1.7 Block Diagram .....................................................................................................................
1.8 Overview of Functions .......................................................................................................
1.9 Mask Options ......................................................................................................................
24
24
25
25
25
26
29
31
32
33
CHAPTER 2 PIN FUNCTIONS ..............................................................................................................
2.1 Pin Function List.................................................................................................................
2.1.1 Normal operating mode pins ..................................................................................................
2.1.2 PROM programming mode pins (µPD78P0208 only) ...........................................................
2.2 Description of Pin Functions ............................................................................................
2.2.1 P00 to P04 (Port 0) .................................................................................................................
2.2.2 P10 to P17 (Port 1) .................................................................................................................
2.2.3 P20 to P27 (Port 2) .................................................................................................................
2.2.4 P30 to P37 (Port 3) .................................................................................................................
2.2.5 P70 to P74 (Port 7) .................................................................................................................
2.2.6 P80 to P87 (Port 8) .................................................................................................................
2.2.7 P90 to P97 (Port 9) .................................................................................................................
2.2.8 P100 to P107 (Port 10) ...........................................................................................................
2.2.9 P110 to P117 (Port 11) ...........................................................................................................
2.2.10 P120 to P127 (Port 12) ...........................................................................................................
2.2.11 FIP0 to FIP12 ..........................................................................................................................
www.DataSheet4U.co2m.2.12 VLOAD ........................................................................................................................................
2.2.13 AVREF .......................................................................................................................................
2.2.14 AVDD .........................................................................................................................................
2.2.15 AVSS .........................................................................................................................................
2.2.16 RESET .....................................................................................................................................
2.2.17 X1 and X2 ................................................................................................................................
2.2.18 XT1 and XT2 ...........................................................................................................................
2.2.19 VDD ...........................................................................................................................................
2.2.20 VSS ............................................................................................................................................
2.2.21 VPP (µPD78P0208 only) ..........................................................................................................
2.2.22 IC (mask ROM version only) ..................................................................................................
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ...............................
34
34
34
37
38
38
38
39
39
40
40
40
41
41
41
41
42
42
42
42
42
42
42
42
42
42
42
43
CHAPTER 3 CPU ARCHITECTURE .................................................................................................... 48
3.1 Memory Space ..................................................................................................................... 48
3.1.1 Internal program memory space ............................................................................................ 53
3.1.2 Internal data memory space ................................................................................................... 54
3.1.3 Special-function register (SFR) area ...................................................................................... 54
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3.1.4 Data memory addressing ........................................................................................................ 55
3.2 Processor Registers ........................................................................................................... 60
3.2.1 Control registers ...................................................................................................................... 60
3.2.2 General-purpose registers ...................................................................................................... 63
3.2.3 Special-function registers (SFRs) ........................................................................................... 64
3.3 Instruction Address Addressing ...................................................................................... 68
3.3.1 Relative addressing ................................................................................................................. 68
3.3.2 Immediate addressing ............................................................................................................. 69
3.3.3 Table indirect addressing ........................................................................................................ 70
3.3.4 Register addressing ................................................................................................................ 71
3.4 Operand Address Addressing .......................................................................................... 72
3.4.1 Implied addressing .................................................................................................................. 72
3.4.2 Register addressing ................................................................................................................ 73
3.4.3 Direct addressing .................................................................................................................... 74
3.4.4 Short direct addressing ........................................................................................................... 75
3.4.5 Special-function register (SFR) addressing ........................................................................... 76
3.4.6 Register indirect addressing ................................................................................................... 77
3.4.7 Based addressing .................................................................................................................... 78
3.4.8 Based indexed addressing ..................................................................................................... 79
3.4.9 Stack addressing ..................................................................................................................... 79
CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 80
4.1 Port Functions ..................................................................................................................... 80
4.2 Port Configuration .............................................................................................................. 83
4.2.1 Port 0 ....................................................................................................................................... 83
4.2.2 Port 1 ....................................................................................................................................... 85
4.2.3 Port 2 ....................................................................................................................................... 86
4.2.4 Port 3 ....................................................................................................................................... 88
4.2.5 Port 7 ....................................................................................................................................... 89
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4.2.6 Port 8 ....................................................................................................................................... 90
4.2.7 Port 9 ....................................................................................................................................... 91
4.2.8 Port 10 ..................................................................................................................................... 92
4.2.9 Port 11 ..................................................................................................................................... 93
4.2.10 Port 12 ..................................................................................................................................... 94
4.3 Port Function Control Registers ...................................................................................... 95
4.4 Port Function Operations .................................................................................................. 98
4.4.1 Writing to I/O port .................................................................................................................... 98
4.4.2 Reading from I/O port ............................................................................................................. 98
4.4.3 Operations on I/O port ............................................................................................................ 98
4.5 Selection of Mask Option .................................................................................................. 99
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 100
5.1 Clock Generator Functions ............................................................................................... 100
5.2 Clock Generator Configuration......................................................................................... 100
5.3 Clock Generator Control Registers .................................................................................. 102
5.4 System Clock Oscillator .................................................................................................... 109
5.4.1 Main system clock oscillator ................................................................................................... 109
5.4.2 Subsystem clock oscillator ..................................................................................................... 110
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5.4.3 Divider ...................................................................................................................................... 113
5.4.4 When subsystem clock is not used ........................................................................................ 113
5.5 Clock Generator Operations ............................................................................................. 114
5.5.1 Main system clock operations ................................................................................................ 115
5.5.2 Subsystem clock operations ................................................................................................... 116
5.6 Changing System Clock and CPU Clock Settings ......................................................... 117
5.6.1 Time required for switchover between system clock and CPU clock .................................. 117
5.6.2 System clock and CPU clock switching procedure ............................................................... 118
CHAPTER 6 16-BIT TIMER/EVENT COUNTER ................................................................................... 119
6.1 Outline of Timers Incorporated in µPD780208 Subseries ............................................ 119
6.2 16-Bit Timer/Event Counter Functions ............................................................................ 120
6.3 16-Bit Timer/Event Counter Configuration ..................................................................... 122
6.4 16-Bit Timer/Event Counter Control Registers .............................................................. 127
6.5 16-Bit Timer/Event Counter Operations .......................................................................... 135
6.5.1 Interval timer operations ......................................................................................................... 135
6.5.2 PWM output operations .......................................................................................................... 137
6.5.3 Pulse width measurement operations .................................................................................... 138
6.5.4 External event counter operation ........................................................................................... 140
6.5.5 Square-wave output operation ............................................................................................... 142
6.6 16-Bit Timer/Event Counter Operating Precautions ...................................................... 143
CHAPTER 7 8-BIT TIMER/EVENT COUNTER .................................................................................... 145
7.1 8-Bit Timer/Event Counter Functions .............................................................................. 145
7.1.1 8-bit timer/event counter mode ............................................................................................... 145
7.1.2 16-bit timer/event counter mode ............................................................................................ 148
7.2 8-Bit Timer/Event Counter Configuration ....................................................................... 150
7.3 8-Bit Timer/Event Counter Control Registers................................................................. 153
7.4 8-Bit Timer/Event Counter Operations ............................................................................ 158
7.4.1 8-bit timer/event counter mode ............................................................................................... 158
www.DataSheet4U.co7m.4.2 16-bit timer/event counter mode ............................................................................................ 162
7.5 8-Bit Timer/Event Counter Operating Precautions ........................................................ 166
CHAPTER 8 WATCH TIMER ............................................................................................................... 168
8.1 Watch Timer Functions ...................................................................................................... 168
8.2 Watch Timer Configuration ............................................................................................... 169
8.3 Watch Timer Control Registers ........................................................................................ 169
8.4 Watch Timer Operations .................................................................................................... 173
8.4.1 Watch timer operation ............................................................................................................. 173
8.4.2 Interval timer operation ........................................................................................................... 173
CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 174
9.1 Watchdog Timer Functions ............................................................................................... 174
9.2 Watchdog Timer Configuration ........................................................................................ 175
9.3 Watchdog Timer Control Registers ................................................................................. 177
9.4 Watchdog Timer Operations ............................................................................................. 180
9.4.1 Watchdog timer operation ....................................................................................................... 180
9.4.2 Interval timer operation ........................................................................................................... 181
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CHAPTER 10 CLOCK OUTPUT CONTROLLER ................................................................................. 182
10.1 Clock Output Controller Functions .................................................................................. 182
10.2 Clock Output Controller Configuration ........................................................................... 183
10.3 Clock Output Function Control Registers ...................................................................... 183
CHAPTER 11 BUZZER OUTPUT CONTROLLER .............................................................................. 186
11.1 Buzzer Output Controller Functions ................................................................................ 186
11.2 Buzzer Output Controller Configuration ......................................................................... 186
11.3 Buzzer Output Function Control Registers .................................................................... 187
CHAPTER 12 A/D CONVERTER ......................................................................................................... 190
12.1 A/D Converter Functions ................................................................................................... 190
12.2 A/D Converter Configuration ............................................................................................ 190
12.3 A/D Converter Control Registers ..................................................................................... 194
12.4 A/D Converter Operations ................................................................................................. 197
12.4.1 Basic operations of A/D converter ......................................................................................... 197
12.4.2 Input voltage and conversion results ..................................................................................... 199
12.4.3 A/D converter operating mode ............................................................................................... 200
12.5 A/D Converter Precautions ............................................................................................... 202
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 ............................................................................... 205
13.1 Functions of Serial Interface Channel 0 .......................................................................... 206
13.2 Configuration of Serial Interface Channel 0 ................................................................... 207
13.3 Control Registers of Serial Interface Channel 0 ............................................................ 211
13.4 Operations of Serial Interface Channel 0 ........................................................................ 217
13.4.1 Operation stop mode .............................................................................................................. 217
13.4.2 3-wire serial I/O mode operation ............................................................................................ 218
13.4.3 SBI mode operation ................................................................................................................ 223
13.4.4 2-wire serial I/O mode operation ............................................................................................ 249
13.4.5 SCK0/P27 pin output manipulation ........................................................................................ 255
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CHAPTER 14 SERIAL INTERFACE CHANNEL 1 ............................................................................... 256
14.1 Functions of Serial Interface Channel 1 .......................................................................... 256
14.2 Configuration of Serial Interface Channel 1 ................................................................... 257
14.3 Control Registers of Serial Interface Channel 1 ............................................................ 260
14.4 Operations of Serial Interface Channel 1 ........................................................................ 268
14.4.1 Operation stop mode .............................................................................................................. 268
14.4.2 3-wire serial I/O mode operation ............................................................................................ 269
14.4.3 3-wire serial I/O mode operation with automatic transmit/receive function ......................... 272
CHAPTER 15 VFD CONTROLLER/DRIVER ........................................................................................ 299
15.1 VFD Controller/Driver Functions ...................................................................................... 299
15.2 VFD Controller/Driver Configuration ............................................................................... 301
15.3 VFD Controller/Driver Control Registers ........................................................................ 303
15.3.1 Control registers ...................................................................................................................... 303
15.3.2 One-display period and cut width ........................................................................................... 310
15.4 Selecting Display Mode ..................................................................................................... 311
15.5 Display Mode and Display Output.................................................................................... 312
15.6 Display Data Memory ......................................................................................................... 313
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15.7 Key Scan Flag and Key Scan Data .................................................................................. 314
15.7.1 Key scan flag ........................................................................................................................... 314
15.7.2 Key scan data .......................................................................................................................... 314
15.8 Light Leakage of VFD ......................................................................................................... 315
15.9 Display Examples ............................................................................................................... 317
15.9.1 Segment type (display mode 1: DSPM05 = 0) ...................................................................... 318
15.9.2 Dot type (display mode 1: DSPM05 = 0) ............................................................................... 320
15.9.3 Display type in which a segment spans two or more grids
(display mode 2: DSPM05 = 1) .............................................................................................. 322
15.10 Calculating Total Power Dissipation............................................................................... 326
15.10.1 Segment type (display mode 1: DSPM05 = 0) ...................................................................... 326
15.10.2 Dot type (display mode 1: DSPM05 = 0) ............................................................................... 329
15.10.3 Display type in which a segment spans two or more grids
(display mode 2: DSPM05 = 1) .............................................................................................. 332
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS .......................................................................... 335
16.1 Interrupt Function Types ................................................................................................... 335
16.2 Interrupt Sources and Configuration ............................................................................... 336
16.3 Interrupt Function Control Registers .............................................................................. 339
16.4 Interrupt Servicing Operations ......................................................................................... 347
16.4.1 Non-maskable interrupt request acknowledgment operation ................................................ 347
16.4.2 Maskable interrupt request acknowledgment operation ........................................................ 350
16.4.3 Software interrupt request acknowledgment operation ......................................................... 352
16.4.4 Multiple interrupt servicing ...................................................................................................... 353
16.4.5 Interrupt request hold .............................................................................................................. 356
16.5 Test Functions .................................................................................................................... 357
16.5.1 Test function control registers ................................................................................................ 357
16.5.2 Test input signal acknowledgment operation ........................................................................ 358
CHAPTER 17 STANDBY FUNCTION ................................................................................................... 359
www.DataShe1e7t4.1U.coSmtandby Function and Configuration .............................................................................. 359
17.1.1 Standby function ...................................................................................................................... 359
17.1.2 Standby function control register ............................................................................................ 360
17.2 Standby Function Operations ........................................................................................... 361
17.2.1 HALT mode ............................................................................................................................. 361
17.2.2 STOP mode ............................................................................................................................. 364
CHAPTER 18 RESET FUNCTION ........................................................................................................ 367
18.1 Reset Function .................................................................................................................... 367
CHAPTER 19 µPD78P0208 .................................................................................................................. 371
19.1 Internal Memory Size Switching Register ....................................................................... 372
19.2 Internal Expansion RAM Size Switching Register ......................................................... 374
19.3 PROM Programming ........................................................................................................... 375
19.3.1 Operating modes ..................................................................................................................... 375
19.3.2 PROM write procedure ........................................................................................................... 377
19.3.3 PROM read procedure ............................................................................................................ 381
19.4 Screening of One-Time PROM Version ........................................................................... 382
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CHAPTER 20 INSTRUCTION SET ....................................................................................................... 383
20.1 Conventions ........................................................................................................................ 384
20.1.1 Operand identifiers and description methods ........................................................................ 384
20.1.2 Description of “operation” column .......................................................................................... 385
20.1.3 Description of “flag operation” column ................................................................................... 385
20.2 Operation List ...................................................................................................................... 386
20.3 Instructions Listed by Addressing Type ......................................................................... 394
APPENDIX A DIFFERENCES BETWEEN µPD78044H, 780228, AND 780208 SUBSERIES ............ 398
APPENDIX B DEVELOPMENT TOOLS .............................................................................................. 399
B.1 Software Package ............................................................................................................... 401
B.2 Language Processing Software ........................................................................................ 401
B.3 Control Software ................................................................................................................. 402
B.4 PROM Programming Tools ................................................................................................ 403
B.4.1 Hardware ................................................................................................................................. 403
B.4.2 Software ................................................................................................................................... 403
B.5 Debugging Tools (Hardware) ............................................................................................ 404
B.5.1 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A ................................................ 404
B.5.2 When using in-circuit emulator IE-78001-R-A ....................................................................... 405
B.6 Debugging Tools (Software) ............................................................................................. 406
B.7 Embedded Software ........................................................................................................... 407
B.8 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to
IE-78001-R-A ........................................................................................................................ 408
B.9 Conversion Socket (EV-9200GF-100) Package Drawing and Recommended
Footprint ............................................................................................................................... 409
B.10 Notes on Target System Design ....................................................................................... 411
APPENDIX C REGISTER INDEX ......................................................................................................... 413
C.1 Register Index (by Register Name) .................................................................................. 413
www.DataSheet4U.coCm.2 Register Index (by Register Symbol) ............................................................................... 415
APPENDIX D REVISION HISTORY ....................................................................................................... 417
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LIST OF FIGURES (1/6)
Figure No.
Title
Page
2-1 Pin I/O Circuits ................................................................................................................................ 45
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
Memory Map (µPD780204 and µPD780204A) ..............................................................................
Memory Map (µPD780205 and µPD780205A) ..............................................................................
Memory Map (µPD780206) .............................................................................................................
Memory Map (µPD780208) .............................................................................................................
Memory Map (µPD78P0208) ..........................................................................................................
Data Memory Addressing (µPD780204 and µPD780204A) ..........................................................
Data Memory Addressing (µPD780205 and µPD780205A) ..........................................................
Data Memory Addressing (µPD780206) ........................................................................................
Data Memory Addressing (µPD780208) ........................................................................................
Data Memory Addressing (µPD78P0208) ......................................................................................
Program Counter Format ................................................................................................................
Program Status Word Format .........................................................................................................
Stack Pointer Format ......................................................................................................................
Data to Be Saved to Stack Memory ...............................................................................................
Data to Be Reset from Stack Memory ...........................................................................................
General-Purpose Register Configuration .......................................................................................
48
49
50
51
52
55
56
57
58
59
60
60
61
62
62
63
4-1 Port Types .......................................................................................................................................
4-2 Block Diagram of P00 and P04 ......................................................................................................
4-3 Block Diagram of P01 to P03 .........................................................................................................
4-4 Block Diagram of P10 to P17 .........................................................................................................
4-5 Block Diagram of P20, P21, P23 to P26 ........................................................................................
4-6 Block Diagram of P22 and P27 ......................................................................................................
www.DataS4h-e7et4U.comBlock Diagram of P30 to P37 .........................................................................................................
4-8 Block Diagram of P70 to P74 .........................................................................................................
4-9 Block Diagram of P80 to P87 .........................................................................................................
4-10
Block Diagram of P90 to P97 .........................................................................................................
4-11
Block Diagram of P100 to P107 .....................................................................................................
4-12
Block Diagram of P110 to P117 .....................................................................................................
4-13
Block Diagram of P120 to P127 .....................................................................................................
4-14
Format of Port Mode Register ........................................................................................................
4-15
Format of Pull-up Resistor Option Register ...................................................................................
80
84
84
85
86
87
88
89
90
91
92
93
94
96
97
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
16
Clock Generater Block Diagram ..................................................................................................... 101
Feedback Resistor of Subsystem Clock ........................................................................................ 102
Format of Processor Clock Control Register ................................................................................. 103
Format of Display Mode Register 0 ............................................................................................... 105
Format of Display Mode Register 1 ............................................................................................... 108
External Circuit of Main System Clock Oscillator .......................................................................... 109
External Circuit of Subsystem Clock Oscillator ............................................................................. 110
Examples of Incorrect Resonator Connection ............................................................................... 111
Main System Clock Stop Function ................................................................................................. 115
System Clock and CPU Clock Switching ....................................................................................... 118
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LIST OF FIGURES (2/6)
Figure No.
Title
Page
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
Block Diagram of 16-Bit Timer/Event Counter (Timer Mode) ....................................................... 123
Block Diagram of 16-Bit Timer/Event Counter (PWM Mode) ........................................................ 124
Block Diagram of 16-Bit Timer/Event Counter Output Controller ................................................. 125
Format of Timer Clock Select Register 0 ....................................................................................... 128
Format of 16-Bit Timer Mode Control Register ............................................................................. 130
Format of 16-Bit Timer Output Control Register ........................................................................... 131
Format of Port Mode Register 3 ..................................................................................................... 132
Format of External Interrupt Mode Register .................................................................................. 133
Format of Sampling Clock Select Register .................................................................................... 134
Interval Timer Configuration Diagram ............................................................................................ 135
Interval Timer Operation Timing ..................................................................................................... 136
Example of D/A Converter Configuration with PWM Output ......................................................... 137
TV Tuner Application Circuit Example ........................................................................................... 138
Configuration Diagram for Pulse Width Measurement in Free-Running Mode ............................ 139
Timing of Pulse Width Measurement Operation in Free-Running Mode
(with Both Edges Specified) ........................................................................................................... 139
Timing of Pulse Width Measurement Operation by Means of Restart
(with Both Edges Specified) ........................................................................................................... 140
External Event Counter Configuration Diagram ............................................................................ 141
External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 141
Square-Wave Output Operation Timing ......................................................................................... 142
16-Bit Timer Register Start Timing ................................................................................................. 143
Timing After Compare Register Change During Timer Count Operation ..................................... 143
Capture Register Data Retention Timing ....................................................................................... 144
www.DataSheet4U.7co-1m
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
Block Diagram of 8-Bit Timer/Event Counter ................................................................................. 151
Block Diagram of 8-Bit Timer/Event Counter Output Controller 1 ................................................ 152
Block Diagram of 8-Bit Timer/Event Counter Output Controller 2 ................................................ 152
Format of Timer Clock Select Register 1 ....................................................................................... 154
Format of 8-Bit Timer Mode Control Register ............................................................................... 155
Format of 8-Bit Timer Output Control Register .............................................................................. 156
Format of Port Mode Register 3 ..................................................................................................... 157
Interval Timer Operation Timing ..................................................................................................... 158
External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 160
Square-Wave Output Operation Timing ......................................................................................... 161
Interval Timer Operation Timing ..................................................................................................... 162
External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 164
Square-Wave Output Operation Timing ......................................................................................... 165
8-Bit Timer Register Start Timing ................................................................................................... 166
External Event Counter Operation Timing ..................................................................................... 166
Timing After Compare Register Change During Timer Count Operation ..................................... 167
User’s Manual U11302EJ4V0UM
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LIST OF FIGURES (3/6)
Figure No.
Title
Page
8-1 Watch Timer Block Diagram ........................................................................................................... 170
8-2 Format of Timer Clock Select Register 2 ....................................................................................... 171
8-3 Format of Watch Timer Mode Control Register ............................................................................. 172
9-1 Watchdog Timer Block Diagram ..................................................................................................... 176
9-2 Format of Timer Clock Select Register 2 ....................................................................................... 178
9-3 Format of Watchdog Timer Mode Register .................................................................................... 179
10-1
10-2
10-3
10-4
Remote Controlled Output Application Example ........................................................................... 182
Clock Output Controller Block Diagram ......................................................................................... 183
Format of Timer Clock Select Register 0 ....................................................................................... 184
Format of Port Mode Register 3 ..................................................................................................... 185
11-1
11-2
11-3
Buzzer Output Controller Block Diagram ....................................................................................... 186
Format of Timer Clock Select Register 2 ....................................................................................... 188
Format of Port Mode Register 3 ..................................................................................................... 189
12-1
A/D Converter Block Diagram ........................................................................................................ 191
12-2
Format of A/D Converter Mode Register ....................................................................................... 195
12-3
Format of A/D Converter Input Select Register ............................................................................. 196
12-4
Basic Operation of A/D Converter .................................................................................................. 198
12-5
Relationship Between Analog Input Voltage and A/D Conversion Result ................................... 199
12-6
A/D Conversion by Hardware Start ................................................................................................ 200
12-7
A/D Conversion by Software Start ................................................................................................. 201
12-8
Example of Method of Reducing Power Consumption in Standby Mode .................................... 202
www.DataS1h2e-e9t4U.comAnalog Input Pin Processing .......................................................................................................... 203
12-10 A/D Conversion End Interrupt Request Generation Timing .......................................................... 204
12-11 AVDD Pin Connection ....................................................................................................................... 204
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
Block Diagram of Serial Interface Channel 0 ................................................................................ 208
Format of Timer Clock Select Register 3 ....................................................................................... 212
Format of Serial Operating Mode Register 0 ................................................................................. 213
Format of Serial Bus Interface Control Register ........................................................................... 214
Format of Interrupt Timing Specification Register ......................................................................... 216
3-Wire Serial I/O Mode Timing ....................................................................................................... 221
RELT and CMDT Operations .......................................................................................................... 222
Circuit for Switching Transfer Bit Order ......................................................................................... 222
Example of Serial Bus Configuration with SBI .............................................................................. 224
SBI Transfer Timing ........................................................................................................................ 226
Bus Release Signal ......................................................................................................................... 227
Command Signal ............................................................................................................................. 227
Address ............................................................................................................................................ 228
Slave Selection by Address ............................................................................................................ 228
Commands ....................................................................................................................................... 229
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LIST OF FIGURES (4/6)
Figure No.
Title
Page
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-23
13-24
13-25
13-26
13-27
13-28
13-29
13-30
13-31
13-32
13-33
Data .................................................................................................................................................. 229
Acknowledge Signal ........................................................................................................................ 230
BUSY and READY Signals ............................................................................................................. 231
RELT, CMDT, RELD, and CMDD Operations (Master) ................................................................ 236
RELD and CMDD Operations (Slave) ............................................................................................ 236
ACKT Operation .............................................................................................................................. 237
ACKE Operations ............................................................................................................................ 238
ACKD Operations ............................................................................................................................ 239
BSYE Operation .............................................................................................................................. 239
Pin Configuration ............................................................................................................................. 242
Address Transmission from Master Device to Slave Device (WUP = 1) ..................................... 244
Command Transmission from Master Device to Slave Device .................................................... 245
Data Transmission from Master Device to Slave Device .............................................................. 246
Data Transmission from Slave Device to Master Device .............................................................. 247
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ................................................ 249
2-Wire Serial I/O Mode Timing ....................................................................................................... 253
RELT and CMDT Operations .......................................................................................................... 254
SCK0/P27 Pin Configuration .......................................................................................................... 255
14-1
14-2
14-3
14-4
14-5
14-6
www.DataSheet4U.1co4m-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
14-21
14-22
14-23
14-24
Block Diagram of Serial Interface Channel 1 ................................................................................ 258
Format of Timer Clock Select Register 3 ....................................................................................... 261
Format of Serial Operating Mode Register 1 ................................................................................. 262
Format of Automatic Data Transmit/Receive Control Register ..................................................... 264
Format of Automatic Data Transmit/Receive Interval Specification Register .............................. 265
3-Wire Serial I/O Mode Timing ....................................................................................................... 270
Circuit for Switching Transfer Bit Order ......................................................................................... 271
Basic Transmission/Reception Mode Operation Timing ............................................................... 279
Basic Transmission/Reception Mode Flowchart ............................................................................ 280
Buffer RAM Operation in 6-Byte Transmission/Reception
(in Basic Transmission/Reception Mode) ....................................................................................... 281
Basic Transmission Mode Operation Timing ................................................................................. 283
Basic Transmission Mode Flowchart .............................................................................................. 284
Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode) ........................... 285
Repeat Transmission Mode Operation Timing .............................................................................. 287
Repeat Transmission Mode Flowchart ........................................................................................... 288
Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) ........................ 289
Automatic Transmission/Reception Suspension and Restart ....................................................... 291
System Configuration with Busy Control Option ........................................................................... 292
Operation Timing When Using Busy Control Option (BUSY0 = 0) .............................................. 293
Busy Signal and Clearing Wait (BUSY0 = 0) ................................................................................ 293
Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0) ............................... 294
Operation Timing of Bit Slippage Detection Function Using Busy Signal (BUSY0 = 1) ............. 295
Automatic Transmit/Receive Interval .............................................................................................. 296
Operation Timing When Automatic Transmit/Receive Function Is Operating with
Internal Clock ................................................................................................................................... 297
User’s Manual U11302EJ4V0UM
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LIST OF FIGURES (5/6)
Figure No.
Title
Page
15-1
VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0) ........................................... 300
15-2
VFD Controller/Driver Block Diagram ............................................................................................ 302
15-3
Format of Display Mode Register 0 ............................................................................................... 305
15-4
Format of Display Mode Register 1 ............................................................................................... 307
15-5
Format of Display Mode Register 2 ............................................................................................... 308
15-6
Cut Width of Segment/Digit Signal ................................................................................................. 310
15-7
VFD Controller Display Start Timing .............................................................................................. 310
15-8
Selection of Display Mode .............................................................................................................. 311
15-9
Pin Configuration for 14-Segment Display ..................................................................................... 312
15-10 Relationship Between Display Data Memory Contents and Segment Output ............................. 313
15-11 Light Leakage due to Short Blanking Time .................................................................................... 315
15-12 Light Leakage due to CSG ............................................................................................................... 316
15-13 Waveform of Light Leakage due to CSG ......................................................................................... 316
15-14 Display Data Memory Configuration and Segment Data Reading Order
(Segment Type) ............................................................................................................................... 318
15-15 Relationship Between Display Data Memory Contents and Segment Outputs
in 10-Segment x 11-Digit Display Mode ........................................................................................ 319
15-16 Display Data Memory Configuration and Segment Data Reading Order (Dot Type) .................. 320
15-17 Relationship Between Display Data Memory Contents and Segment Outputs
in 35-Segment x 16-Digit Display Mode ........................................................................................ 321
15-18 Display Data Memory Configuration and Data Reading Order (Display Mode 2) ....................... 322
15-19 Segment Connection Example ....................................................................................................... 323
15-20 Grid Driving Timing ......................................................................................................................... 324
15-21 Data Memory Status in 23-Segment x 5-Grid Display Mode ........................................................ 325
15-22 Allowable Total Power Dissipation PT (TA = –40 to +85°C) .......................................................... 326
www.DataS1h5e-e2t43U.comRelationship Between Display Data Memory Contents and Segment Outputs
in 10-Segment x 11-Digit Display Mode ........................................................................................ 328
15-24 Relationship Between Display Data Memory Contents and Segment Outputs
in 35-Segment x 16-Digit Display Mode ........................................................................................ 331
15-25 Grid Driving Timing ......................................................................................................................... 333
15-26 Data Memory Status in 23-Segment x 5-Grid Display Mode ........................................................ 334
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
Basic Configuration of Interrupt Function ...................................................................................... 337
Format of Interrupt Request Flag Register .................................................................................... 340
Format of Interrupt Mask Flag Register ......................................................................................... 341
Format of Priority Specification Flag Register ............................................................................... 342
Format of External Interrupt Mode Register .................................................................................. 343
Format of Sampling Clock Select Register .................................................................................... 344
Noise Eliminator I/O Timing (When Rising Edge Is Detected) ..................................................... 345
Format of Program Status Word .................................................................................................... 346
Non-Maskable Interrupt Request Acknowledgment Flowchart ..................................................... 348
Non-Maskable Interrupt Request Acknowledgment Timing .......................................................... 348
Non-Maskable Interrupt Request Acknowledgment Operation ..................................................... 349
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LIST OF FIGURES (6/6)
Figure No.
Title
Page
16-12
16-13
16-14
16-15
16-16
16-17
16-18
16-19
Interrupt Request Acknowledge Processing Algorithm ................................................................. 351
Interrupt Request Acknowledgment Timing (Minimum Time) ....................................................... 352
Interrupt Request Acknowledgment Timing (Maximum Time) ...................................................... 352
Multiple Interrupt Servicing Example .............................................................................................. 354
Interrupt Request Hold .................................................................................................................... 356
Basic Configuration of Test Function ............................................................................................. 357
Format of Interrupt Request Flag Register 0H .............................................................................. 358
Format of Interrupt Mask Flag Register 0H ................................................................................... 358
17-1
17-2
17-3
17-4
17-5
Format of Oscillation Stabilization Time Select Register .............................................................. 360
HALT Mode Release by Interrupt Request Generation ................................................................ 362
HALT Mode Release by RESET Input ........................................................................................... 363
STOP Mode Release by Interrupt Request Generation ................................................................ 365
STOP Mode Release by RESET Input .......................................................................................... 366
18-1
18-2
18-3
18-4
Block Diagram of Reset Function ................................................................................................... 367
Timing of Reset by RESET Input ................................................................................................... 368
Timing of Reset due to Watchdog Timer Overflow ....................................................................... 368
Timing of Reset by RESET Input in STOP Mode .......................................................................... 368
19-1
19-2
19-3
19-4
19-5
www.DataSheet4U.1co9m-6
19-7
Format of Internal Memory Size Switching Register (IMS) ........................................................... 373
Format of Internal Expansion RAM Size Switching Register ........................................................ 374
Page Program Mode Flowchart ...................................................................................................... 377
Page Program Mode Timing ........................................................................................................... 378
Byte Program Mode Flowchart ....................................................................................................... 379
Byte Program Mode Timing ............................................................................................................ 380
PROM Read Timing ........................................................................................................................ 381
B-1 Configuration of Development Tools .............................................................................................. 400
B-2 EV-9200GF-100 Package Drawing (for Reference Purposes only) ............................................. 409
B-3 Recommended Footprint for EV-9200GF-100 (for Reference Purposes only) ............................ 410
B-4 Distance Between IE System and Conversion Adapter ................................................................ 411
B-5 Connection Conditions of Target System (When NP-100GF-TQ Is Used) .................................. 412
B-6 Connection Conditions of Target System (When NP-H100GF-TQ Is Used) ............................... 412
User’s Manual U11302EJ4V0UM
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LIST OF TABLES (1/2)
Table No.
Title
Page
1-1 Mask Options in Mask ROM Versions ........................................................................................... 33
2-1 Types of Pin I/O Circuits ................................................................................................................. 43
3-1 Internal ROM Capacity .................................................................................................................... 53
3-2 Vector Table .................................................................................................................................... 53
3-3 Special-Function Register List ........................................................................................................ 65
4-1 Port Functions ................................................................................................................................. 81
4-2 Port Configuration ........................................................................................................................... 83
4-3 Port Mode Register and Output Latch Setting When Alternate Function Is Used ...................... 95
4-4 Comparison Between Mask Option of Mask ROM Version and µPD78P0208 ............................ 99
5-1 Clock Generator Configuration ....................................................................................................... 100
5-2 Relationship Between CPU Clock and Minimum Instruction Execution Time ............................. 104
5-3 Maximum Time Required for CPU Clock Switchover .................................................................... 117
6-1 Timer/Event Counter Operations .................................................................................................... 120
6-2 16-Bit Timer/Event Counter Interval Time ..................................................................................... 121
6-3 16-Bit Timer/Event Counter Square-Wave Output Ranges .......................................................... 121
6-4 16-Bit Timer/Event Counter Configuration ..................................................................................... 122
6-5 16-Bit Timer/Event Counter Interval Time ..................................................................................... 136
6-6 16-Bit Timer/Event Counter Square-Wave Output Ranges .......................................................... 142
7-1 8-Bit Timer/Event Counter Interval Time ........................................................................................ 146
7-2 8-Bit Timer/Event Counter Square-Wave Output Ranges ............................................................ 147
www.DataS7h-e3et4U.comInterval Time When 8-Bit Timer/Event Counter Is Used as 16-Bit Timer/Event Counter ........... 148
7-4 Square-Wave Output Ranges When 8-Bit Timer/Event Counter
Is Used as 16-Bit Timer/Event Counter ......................................................................................... 149
7-5 8-Bit Timer/Event Counter Configuration ....................................................................................... 150
7-6 8-Bit Timer/Event Counter 1 Interval Time .................................................................................... 159
7-7 8-Bit Timer/Event Counter 2 Interval Time .................................................................................... 159
7-8 8-Bit Timer/Event Counter Square-Wave Output Ranges ............................................................ 161
7-9 Interval Time When 2-Channel 8-Bit Timer/Event Counter
(TM1 and TM2) Is Used as 16-Bit Timer/Event Counter .............................................................. 163
7-10
Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters
(TM1 and TM2) Are Used as 16-Bit Timer/Event Counter ........................................................... 165
8-1 Interval Timer Interval Time ............................................................................................................ 168
8-2 Watch Timer Configuration ............................................................................................................. 169
8-3 Interval Timer Interval Time ............................................................................................................ 173
9-1 Watchdog Timer Program Loop Detection Time ........................................................................... 174
9-2 Interval Time .................................................................................................................................... 174
9-3 Watchdog Timer Configuration ....................................................................................................... 175
9-4 Watchdog Timer Program Loop Detection Time ........................................................................... 180
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LIST OF TABLES (2/2)
Table No.
Title
Page
9-5 Interval Timer Interval Time ............................................................................................................ 181
10-1
Clock Output Controller Configuration ........................................................................................... 183
11-1
Buzzer Output Controller Configuration ......................................................................................... 186
12-1
A/D Converter Configuration ........................................................................................................... 190
13-1
13-2
13-3
13-4
Differences Between Channels 0 and 1 ......................................................................................... 205
Modes of Serial Interface Channel 0 .............................................................................................. 206
Configuration of Serial Interface Channel 0 ................................................................................... 207
Signals in SBI Mode ........................................................................................................................ 240
14-1
14-2
14-3
14-4
Modes of Serial Interface Channel 1 .............................................................................................. 256
Configuration of Serial Interface Channel 1 ................................................................................... 257
Interval Determined by CPU Processing (with Internal Clock Operation) .................................... 297
Interval Determined by CPU Processing (with External Clock Operation) .................................. 298
15-1
15-2
15-3
Relationship Between Display Output Pins and Port Pins ............................................................ 301
VFD Controller/Driver Configuration ............................................................................................... 301
Segment Lighting Timing ................................................................................................................ 324
16-1
16-2
16-3
16-4
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17-1
17-2
17-3
17-4
Interrupt Source List ........................................................................................................................ 336
Various Flags Corresponding to Interrupt Request Sources ........................................................ 339
Times from Maskable Interrupt Request Generation to Interrupt Servicing................................. 350
Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing ................................ 353
HALT Mode Operating Status ......................................................................................................... 361
Operation After HALT Mode Release ............................................................................................ 363
STOP Mode Operating Status ........................................................................................................ 364
Operation After STOP Mode Release ............................................................................................ 366
18-1
Hardware Status After Reset .......................................................................................................... 369
19-1
19-2
19-3
19-4
Differences Between µPD78P0208 and Mask ROM Versions ..................................................... 371
Internal Memory Size Switching Register Setting Values ............................................................. 373
Internal Expansion RAM Size Switching Register Setting Values ................................................ 374
PROM Programming Operating Modes ......................................................................................... 375
20-1
Operand Identifiers and Description Methods ............................................................................... 384
A-1 Major Differences Between µPD78044H, 780228, and 780208 Subseries ................................. 398
B-1 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A ....... 408
B-2 Distance Between IE System and Conversion Adapter ................................................................ 411
User’s Manual U11302EJ4V0UM
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UPD780206

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CHAPTER 1 OUTLINE
1.1 Features
Internal high-capacity ROM and RAM
Item
Part
Number
µPD780204
µPD780204A
µPD780205
µPD780205A
µPD780206
µPD780208
µPD78P0208
Program Memory
ROM
PROM
32 KB
40 KB
48 KB
60 KB
60 KBNote 1
Internal High-
Speed RAM
1024 bytes
Data Memory
Buffer RAM
VFD Display
RAM
64 bytes
80 bytes
Internal
Expansion RAM
None
1024 bytes
1024 bytesNote 2
Notes 1. 32, 40, 48, or 60 KB can be selected by setting the internal memory size switching register (IMS).
2. 0 or 1024 bytes can be selected by setting the internal expansion RAM size switching register (IXS).
Minimum instruction execution time can be changed from high speed (0.4 µs: @ 5.0 MHz operation with main
system clock) to ultra-low speed (122 µs: @ 32.768 kHz operation with subsystem clock)
74 I/O ports
VFD controller/driver: 53 display outputs in total
• Segments: 9 to 40
• Digits: 2 to 16
8-bit resolution A/D converter: 8 channels
• Power supply voltage (AVDD = 4.0 to 5.5 V)
www.DataSheSeet4rUia.cl oinmterface: 2 channels
• 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel
• 3-wire serial I/O mode (automatic transmit/receive function): 1 channel
Timer: 5 channels
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
15 vectored interrupt sources
One test input
Two types of on-chip clock oscillators (for main and subsystem clocks)
Power supply voltage: VDD = 2.7 to 5.5 V
24 User’s Manual U11302EJ4V0UM


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UPD780206

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CHAPTER 1 OUTLINE
1.2 Applications
Compact home stereo sets, cassette decks, tuners, CD players, VCRs, etc.
1.3 Ordering Information
Part Number
µPD780204GF-xxx-3BA
µPD780204AGF-xxx-3BA
µPD780205GF-xxx-3BA
µPD780205AGF-xxx-3BA
µPD780206GF-xxx-3BA
µPD780208GF-xxx-3BA
µPD78P0208GF-3BA
Package
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
Remark xxx indicates ROM code suffix.
1.4 Quality Grade
Part Number
µPD780204GF-xxx-3BA
µPD780204AGF-xxx-3BA
µPD780205GF-xxx-3BA
µPD780205AGF-xxx-3BA
µPD780206GF-xxx-3BA
µPD780208GF-xxx-3BA
µPD78P0208GF-3BA
Package
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
100-pin plastic QFP (14 x 20)
Remark xxx indicates ROM code suffix.
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Internal ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
One-time PROM
Quality Grade
Standard
Standard
Standard
Standard
Standard
Standard
Standard
User’s Manual U11302EJ4V0UM
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CHAPTER 1 OUTLINE
1.5 Pin Configuration (Top View)
(1) Normal operating mode
• 100-pin plastic QFP (14 x 20)
µPD780204GF-xxx-3BA, 780204AGF-xxx-3BA, 780205GF-xxx-3BA, 780205AGF-xxx-3BA,
µPD780206GF-xxx-3BA, 780208GF-xxx-3BA, 78P0208GF-3BA
VDD
P37
P36/BUZ
P35/PCL
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
RESET
X2
X1
IC (VPP)
XT2
P04/XT1
VDD
P27/SCK0
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P23/STB
P22/SCK1
P21/SO1
www.DataSheet4U.com P20/SI1
AVSS
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80 P87/FIP20
79 VLOAD
78 P90/FIP21
77 P91/FIP22
76 P92/FIP23
75 P93/FIP24
74 P94/FIP25
73 P95/FIP26
72 P96/FIP27
71 P97/FIP28
70 P100/FIP29
69 P101/FIP30
68 P102/FIP31
67 P103/FIP32
66 P104/FIP33
65 P105/FIP34
64 P106/FIP35
63 P107/FIP36
62 P110/FIP37
61 P111/FIP38
60 P112/FIP39
59 P113/FIP40
58 P114/FIP41
57 P115/FIP42
56 P116/FIP43
55 P117/FIP44
54 P120/FIP45
53 P121/FIP46
52 P122/FIP47
51 P123/FIP48
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
Remark The pin connection in parentheses is intended for the µPD78P0208.
26 User’s Manual U11302EJ4V0UM


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CHAPTER 1 OUTLINE
ANI0 to ANI7:
AVDD:
AVREF:
AVSS:
BUSY:
BUZ:
FIP0 to FIP52:
IC:
INTP0 to INTP3:
P00 to P04:
P10 to P17:
P20 to P27:
P30 to P37:
P70 to P74:
P80 to P87:
P90 to P97:
P100 to P107:
Analog input
Analog power supply
Analog reference voltage
Analog ground
Busy
Buzzer clock
Fluorescent indicator panel
Internally connected
External interrupt input
Port 0
Port 1
Port 2
Port 3
Port 7
Port 8
Port 9
Port 10
P110 to P117:
P120 to P127:
PCL:
RESET:
SB0, SB1:
SCK0, SCK1:
SI0, SI1:
SO0, SO1:
STB:
TI0 to TI2:
TO0 to TO2:
VDD:
VLOAD:
VPP:
VSS:
X1, X2:
XT1, XT2:
Port 11
Port 12
Programmable clock
Reset
Serial bus
Serial clock
Serial input
Serial output
Strobe
Timer input
Timer output
Power supply
Negative power supply
Programming power supply
Ground
Crystal (main system clock)
Crystal (subsystem clock)
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Users Manual U11302EJ4V0UM
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CHAPTER 1 OUTLINE
(2) PROM programming mode
• 100-pin plastic QFP (14 x 20)
µPD78P0208GF-3BA
VDD
D7
D6
D5
(D) D4
D3
D2
D1
D0
RESET
Open
(L)
VPP
Open
(L)
VDD
A7
A6
A5
(D) A4
A3
A2
A1
A0
VSS
(L)
(D) CE
OE
(L)
www.DataSheet4U.com
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80 (L)
79 VSS
78
77
76
75
74
73
72
71 (L)
70
69
68
67
66
65
64
63
62 A8
61 A16
60 A10
59
58
A11
A12
(D)
57 A13
56 A14
55 A15
54
53
52
(L)
51
Cautions 1. (L):
Connect independently to VSS via a pull-down resistor.
2. (D):
Connect via a driver.
3. VSS:
Connect to ground.
4. RESET: Set to low level.
5. Open: Do not connect to anything.
A0 to A16: Address bus
CE: Chip enable
D0 to D7: Data bus
OE: Output enable
PGM: Program
RESET: Reset
VDD: Power supply
VPP: Programming power supply
VSS: Ground
28 Users Manual U11302EJ4V0UM


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CHAPTER 1 OUTLINE
1.6 78K/0 Series Lineup
The 78K/0 Series product lineup is illustrated below. The part numbers in boxes indicate subseries names.
Products in mass production
Products under development
www.DataSheet4U7S.c8eoKrime/0s
100-pin
100-pin
100-pin
100-pin
80-pin
80-pin
80-pin
80-pin
64-pin
64-pin
64-pin
52-pin
52-pin
64-pin
64-pin
42/44-pin
Control
µPD78075B
µPD78078
µPD78070A
µ PD780058
µPD78058F
µPD78054
µPD780065
µPD780078
µPD780034A
µPD780024A
µPD780034AS
µPD780024AS
µPD78014H
µPD78018F
µPD78083
µPD78078Y
µPD78070AY
µPD780018AY
µPD780058Y
µPD78058FY
µ PD78054Y
µPD780078Y
µPD780034AY
µPD780024AY
µ PD78018FY
Y subseries products are compatible with I2C bus.
EMI-noise reduced version of the µPD78078
µ PD78054 with timer and enhanced external interface
ROMless version of the µPD78078
µ PD78078Y with enhanced serial I/O and limited functions
µ PD78054 with enhanced serial I/O
EMI-noise reduced version of the µ PD78054
µ PD78018F with UART and D/A converter, and enhanced I/O
µ PD780024A with expanded RAM
µPD780034A with timer and enhanced serial I/O
µ PD780024A with enhanced A/D converter
µ PD78018F with enhanced serial I/O
52-pin version of the µPD780034A
52-pin version of the µPD780024A
EMI-noise reduced version of the µ PD78018F
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
Inverter control
µPD780988
On-chip inverter controller and UART. EMI-noise reduced.
100-pin
80-pin
80-pin
80-pin
VFD drive
µPD780208
µPD780232
µPD78044H
µPD78044F
µ PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
µ PD78044F with N-ch open-drain I/O. Display output total: 34
Basic subseries for driving VFD. Display output total: 34
100-pin
100-pin
120-pin
120-pin
120-pin
100-pin
100-pin
100-pin
LCD drive
µPD780354
µPD780344
µPD780338
µPD780328
µPD780318
µPD780308
µPD78064B
µPD78064
µPD780354Y
µPD780344Y
µPD780308Y
µ PD78064Y
µ PD780344 with enhanced A/D converter
µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
µPD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
µPD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
µ PD78064 with enhanced SIO, and expanded ROM and RAM
EMI-noise reduced version of the µPD78064
Basic subseries for driving LCDs, on-chip UART
100-pin
80-pin
80-pin
80-pin
80-pin
64-pin
100-pin
80-pin
80-pin
Bus interface supported
µPD780948
µPD78098B
On-chip CAN controller
µ PD78054 with IEBusTM controller
µPD780816
µ PD780702Y
µPD780703AY
µ PD780833Y
On-chip IEBus controller
On-chip CAN controller
On-chip controller compliant with J1850 (Class 2)
Specialized for CAN controller function
Meter control
µPD780958
µPD780852
µPD780828B
For industrial meter control
On-chip automobile meter controller/driver
For automobile meter driver. On-chip CAN controller
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
Users Manual U11302EJ4V0UM
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CHAPTER 1 OUTLINE
The following lists the main functional differences between subseries products.
Non-Y subseries
Function
Subseries Name
ROM
Capacity
Timer
8-Bit 10-Bit 8-Bit
(Bytes) 8-Bit 16-Bit Watch WDT A/D A/D D/A
Serial Interface
I/O VDD External
MIN.
Value Expansion
Control µPD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (UART: 1 ch)
88 1.8 V
µPD78078 48 K to 60 K
µPD78070A
61 2.7 V
µPD780058 24 K to 60 K 2 ch
3 ch (time-division UART: 1 ch) 68 1.8 V
µPD78058F 48 K to 60 K
3 ch (UART: 1 ch)
69 2.7 V
µPD78054 16 K to 60 K
2.0 V
µPD780065 40 K to 48 K
4 ch (UART: 1 ch)
60 2.7 V
µPD780078 48 K to 60 K
2 ch
8 ch
3 ch (UART: 2 ch)
52 1.8 V
µPD780034A 8 K to 32 K
1 ch
3 ch (UART: 1 ch)
51
µPD780024A
8 ch
µPD780034AS
4 ch
39
µPD780024AS
4 ch
µPD78014H
8 ch 2 ch
53
µPD78018F 8 K to 60 K
µPD78083 8 K to 16 K
––
1 ch (UART: 1 ch)
33
Inverter µPD780988 16 K to 60 K 3 ch Note 1 ch 8 ch 3 ch (UART: 2 ch)
control
47 4.0 V
VFD
drive
µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
µPD780232 16 K to 24 K 3 ch – –
4 ch
2 ch
74 2.7 V
40 4.5 V
µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch
8 ch
1 ch
68 2.7 V
µPD78044F 16 K to 40 K
2 ch
LCD µPD780354 24 K to 32 K 4 ch 1 ch 1 ch 1 ch 8 ch 3 ch (UART: 1 ch)
www.DadtarSivheeet4Uµ.PcoDm780344
8 ch
66 1.8 V
µPD780338 48 K to 60 K 3 ch 2 ch
10 ch 1 ch 2 ch (UART: 1 ch)
54
µPD780328
62
µPD780318
70
µPD780308 48 K to 60 K 2 ch 1 ch
8 ch – – 3 ch (time-division UART: 1 ch) 57 2.0 V
µPD78064B 32 K
2 ch (UART: 1 ch)
µPD78064 16 K to 32 K
Bus µPD780948 60 K
2 ch 2 ch 1 ch 1 ch 8 ch – – 3 ch (UART: 1 ch)
79 4.0 V
interface µPD78098B 40 K to 60 K
supported µPD780816 32 K to 60 K
1 ch
2 ch
12 ch
2 ch
2 ch (UART: 1 ch)
69 2.7 V
46 4.0 V
Meter µPD780958 48 K to 60 K 4 ch 2 ch 1 ch – – – 2 ch (UART: 1 ch)
control
69 2.2 V
Dash-
board
control
µPD780852 32 K to 40 K 3 ch 1 ch 1 ch 1 ch 5 ch
µPD780828B 32 K to 60 K
3 ch (UART: 1 ch)
56 4.0 V
59
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
30 Users Manual U11302EJ4V0UM




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