MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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19-2724; Rev 1; 3/09
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
General Description
The MAX1061/MAX1063 low-power, 10-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed, byte-wide parallel interface. They operate
with a single +3V analog supply and feature a VLOGIC
pin that allows them to interface directly with a +1.8V to
+3.6V digital supply.
Power consumption is only 5.7mW (VDD = VLOGIC) at
the maximum sampling rate of 250ksps. Two software-
selectable power-down modes enable the MAX1061/
MAX1063 to be shut down between conversions;
accessing the parallel interface returns them to normal
operation. Powering down between conversions can
cut supply current to under 10µA at reduced sampling
rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1061 has
eight input channels and the MAX1063 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power consumption and space requirements.
The MAX1061 is available in a 28-pin QSOP package,
while the MAX1063 is available in a 24-pin QSOP. For
www.DaptainSh-ceeotm4Up.caotmible +5V, 10-bit versions, refer to the
MAX1060/MAX1064 data sheet.
Industrial Control Systems
Applications
Data Logging
Energy Management
Patient Monitoring
Data-Acquisition Systems Touch Screens
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
INL
(LSB)
MAX1061ACEI+ 0°C to +70°C 28 QSOP
±0.5
MAX1061BCEI+ 0°C to +70°C 28 QSOP
±1
MAX1061AEEI+ -40°C to +85°C 28 QSOP
±0.5
MAX1061BEEI+ -40°C to +85°C 28 QSOP
±1
+Denotes a lead(Pb)-free/RoHS-compliant package.
Ordering Information continued at end of data sheet.
Features
10-Bit Resolution, ±0.5 LSB Linearity
+3V Single-Supply Operation
User-Adjustable Logic Level (+1.8V to +3.6V)
Internal +2.5V Reference
Software-Configurable, Analog Input Multiplexer
8-Channel Single Ended/
4-Channel Pseudo-Differential (MAX1061)
4-Channel Single Ended/
2-Channel Pseudo-Differential (MAX1063)
Software-Configurable, Unipolar/Bipolar Inputs
Low Power
1.9mA (250ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)
Internal 3MHz Full-Power Bandwidth Track/Hold
Byte-Wide Parallel (8 + 2) Interface
Small Footprint: 28-Pin QSOP (MAX1061)
24-Pin QSOP (MAX1063)
Pin Configurations
TOP VIEW
HBEN 1
D7 2
D6 3
D5 4
D4 5
D3 6
MAX1063
24 VLOGIC
23 VDD
22 REF
21 REFADJ
20 GND
19 COM
D2 7
D1/D9 8
18 CH0
17 CH1
D0/D8 9
INT 10
RD 11
WR 12
16 CH2
15 CH3
14 CS
13 CLK
QSOP
Pin Configurations continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
VLOGIC to GND.........................................................-0.3V to +6V
CH0–CH7, COM to GND ............................-0.3V to (VDD + 0.3V)
REF, REFADJ to GND ................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND ...............................................-0.3V to +6V
Digital Outputs (D0–D9, INT) to GND.....-0.3V to (VLOGIC + 0.3V)
Continuous Power Dissipation (TA = +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C) ..........762mW
28-Pin QSOP (derate 8.0mW/°C above +70°C) ..........667mW
Operating Temperature Ranges
MAX1061_C_ _/MAX1063_C_ _ ..........................0°C to +70°C
MAX1061_E_ _/MAX1063_E_ _ .......................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
DC ACCURACY (Note 1)
Resolution
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
Gain Error
Gain Temperature Coefficient
SYMBOL
CONDITIONS
RES
INL
DNL
MAX106_A
MAX106_B
No missing codes over temperature
(Note 3)
MIN TYP MAX UNITS
10 Bits
±0.5
±1
LSB
±1 LSB
±2 LSB
±2 LSB
±2.0
ppm/°C
Channel-to-Channel Offset
Matching
±0.1
LSB
DYNAMIC SPECIFICATIONS (fIN(sine wave) = 50kHz, VIN = 2.5VP-P, 250ksps, external fCLK = 4.8MHz, bipolar input mode)
www.DataSheet4U.com
Signal-to-Noise Plus Distortion SINAD
60 dB
Total Harmonic Distortion
(Including 5th-Order Harmonic)
THD
-72 dB
Spurious-Free Dynamic Range
Intermodulation Distortion
Channel-to-Channel Crosstalk
Full-Linear Bandwidth
Full-Power Bandwidth
SFDR
IMD
fIN1 = 49kHz, fIN2 = 52kHz
fIN = 125kHz, VIN = 2.5VP-P (Note 4)
SINAD > 56dB
-3dB rolloff
72 dB
76 dB
-78 dB
250 kHz
3 MHz
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
External Clock Frequency
Duty Cycle
tCONV
tACQ
fCLK
External clock mode
External acquisition/internal clock mode
Internal acquisition/internal clock mode
External acquisition or external clock mode
External acquisition or external clock mode
Internal acquisition/internal clock mode
3.3
2.5 3.0 3.5 µs
3.2 3.6 4.1
625 ns
50 ns
<50
<200
ps
0.1 4.8 MHz
30 70 %
2 _______________________________________________________________________________________


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
ANALOG INPUTS
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Analog Input Voltage Range
Single Ended and Differential
(Note 6)
Unipolar, VCOM = 0
VIN
Bipolar, VCOM = VREF / 2
0
-VREF/2
VREF
+VREF/2
V
Multiplexer Leakage Current
On-/off-leakage current, VIN = 0 or VDD
±0.01 ±1
µA
Input Capacitance
CIN
INTERNAL REFERENCE
REF Output Voltage
REF Short-Circuit Current
REF Temperature Coefficient
TCREF
REFADJ Input Range
REFADJ High Threshold
Load Regulation
Capacitive Bypass at REFADJ
Capacitive Bypass at REF
EXTERNAL REFERENCE AT REF
TA = 0°C to +70°C
For small adjustments
To power down the internal reference
0 to 0.5mA output load (Note 7)
12 pF
2.49 2.5
15
±20
±100
VDD - 1.0
0.2
0.01
4.7
2.51 V
mA
ppm/°C
mV
V
mV/mA
1 µF
10 µF
REF Input Voltage Range
VREF
1.0
VDD +
50mV
V
REF Input Current
IREF
DIGITAL INPUTS AND OUTPUTS
www.DatIanSphueteHt4igUh.cVoomltage
VIH
Input Low Voltage
Input Hysteresis
Input Leakage Current
Input Capacitance
Output Low Voltage
Output High Voltage
Tri-State Leakage Current
Tri-State Output Capacitance
VIL
VHYS
IIN
CIN
VOL
VOH
ILEAKAGE
COUT
VREF = 2.5V, fSAMPLE = 250ksps
Shutdown mode
VLOGIC = 2.7V
VLOGIC = 1.8V
VLOGIC = 2.7V
VLOGIC = 1.8V
VIN = 0 or VDD
ISINK = 1.6mA
ISOURCE = 1mA
CS = VDD
CS = VDD
200 300
2
2.0
1.5
200
±0.1
15
VLOGIC - 0.5
±0.1
15
0.8
0.5
±1
0.4
±1
µA
V
V
mV
µA
pF
V
V
µA
pF
_______________________________________________________________________________________ 3


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
Positive Supply Current
VLOGIC Current
Power-Supply Rejection
SYMBOL
CONDITIONS
VDD
VLOGIC
IDD
ILOGIC
PSR
Operating mode,
fSAMPLE = 250ksps
Standby mode
Internal reference
External reference
Internal reference
External reference
Shutdown mode
CL = 20pF
fSAMPLE = 250ksps
Not converting
VDD = 3V ±10%, full-scale input
MIN TYP MAX UNITS
2.7 3.6 V
1.8
VDD + 0.3
V
2.3 2.6
1.9
0.9
2.3
1.2
mA
0.5 0.8
2 10 µA
150
µA
2 10
±0.4 ±0.9 mV
TIMING CHARACTERISTICS
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
CLK Period
CLK Pulse Width High
CLK Pulse Width Low
Data Valid to WR Rise Time
WR Rise to Data Valid Hold Time
www.DataWSRhetoetC4ULK.coFmall Setup Time
CLK Fall to WR Hold Time
CS to CLK or WR
Setup Time
tCP
tCH
tCL
tDS
tDH
tCWS
tCWH
tCSWS
208 ns
40 ns
40 ns
40 ns
0 ns
40 ns
40 ns
60 ns
CLK or WR to CS
Hold Time
tCSWH
0 ns
CS Pulse Width
WR Pulse Width
CS Rise to Output Disable
tCS
tWR (Note 8)
tTC CLOAD = 20pF, Figure 1
100 ns
60 ns
20 100 ns
4 _______________________________________________________________________________________


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS (continued)
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
RD Rise to Output Disable
RD Fall to Output Data Valid
HBEN to Output Data Valid
RD Fall to INT High Delay
CS Fall to Output Data Valid
SYMBOL
tTR
tDO
tDO1
tINT1
tDO2
CONDITIONS
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
MIN TYP MAX UNITS
20 70 ns
20 70 ns
20 110 ns
100 ns
110 ns
Note 1: Tested at VDD = +3V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
DOUT
3k
CLOAD
20pF
VLOGIC
3k
DOUT
CLOAD
20pF
www.DataSheet4U.com
a) HIGH-Z TO VOH AND VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________ 5


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics
(VDD = VLOGIC = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
200 400 600 800 1000 1200
OUTPUT CODE
0.25
0.20
0.15
0.10
0.05
0
-0.5
-0.10
-0.15
-0.20
-0.25
0
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
200 400 600 800 1000 1200
OUTPUT CODE
10,000
SUPPLY CURRENT
vs. SAMPLE FREQUENCY
1000 WITH INTERNAL
REFERENCE
100
WITH EXTERNAL
10 REFERENCE
1
0.1 1
10 100 1k 10k 100k 1M
fSAMPLE (Hz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
2.10
RL =
CODE = 1010100000
2.05
2.00
1.95
1.90
www.Data1S.8h5eet4U.com
1.80
2.7
3.0 3.3
VDD (V)
3.6
STANDBY CURRENT vs. TEMPERATURE
930
SUPPLY CURRENT vs. TEMPERATURE
2.2
RL =
CODE = 1010100000
2.1
2.0
1.9
1.8
1.7
1.6
-40
-15 10 35 60
TEMPERATURE (°C)
85
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
1.50
STANDBY CURRENT vs. SUPPLY VOLTAGE
930
920
910
900
890
880
2.7
1.2
3.0 3.3
VDD (V)
POWER-DOWN CURRENT
vs. TEMPERATURE
3.6
920
1.25
910
1.00
900
0.75
890
1.1
1.0
0.9
880
-40
-15 10 35 60
TEMPERATURE (°C)
85
0.50
2.7
3.0 3.3
VDD (V)
0.8
3.6 -40 -15 10 35 60
TEMPERATURE (°C)
6 _______________________________________________________________________________________
85


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics (continued)
(VDD = VLOGIC = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
2.53
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.53
OFFSET ERROR
vs. SUPPLY VOLTAGE
1.0
2.52 2.52
2.51 2.51
2.50 2.50
2.49 2.49
0.5
0
-0.5
2.48
2.7
1.0
3.0 3.3
VDD (V)
OFFSET ERROR
vs. TEMPERATURE
0.5
0
www.DataS-h0.e5 et4U.com
2.48
3.6 -40 -15 10 35 60 85
TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE
0.250
-1.0
2.7
3.0 3.3
VDD (V)
3.6
GAIN ERROR vs. TEMPERATURE
0.125
0
-0.250
-0.500
0
-0.125
-0.250
-0.375
-1.0
-40
250
200
150
100
50
2.7
-15 10 35 60
TEMPERATURE (°C)
-0.750
85 2.7
3.0 3.3
VDD (V)
-0.500
3.6 -40 -15 10 35 60 85
TEMPERATURE (°C)
LOGIC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
LOGIC SUPPLY CURRENT
vs. TEMPERATURE
250
200
150
100
3.0 3.3
VDD (V)
50
3.6 -40 -15 10 35 60 85
TEMPERATURE (°C)
20
0
-20
-40
-60
-80
-100
-120
-140
0
FFT PLOT
VDD = 3V
fIN = 50kHz
fSAMPLE = 250ksps
200 400 600 800 1000 1200
FREQUENCY (kHz)
_______________________________________________________________________________________ 7


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
PIN
MAX1061 MAX1063
11
22
33
44
55
66
77
88
99
10 10
11 11
12 12
13 13
14
15
16
www.DataSheet4U.com
17
18
19
20
21
22
14
15
16
17
18
23 19
24 20
25 21
26 22
27 23
28 24
NAME
HBEN
D7
D6
D5
D4
D3
D2
D1/D9
D0/D8
INT
RD
WR
CLK
CS
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
COM
GND
REFADJ
REF
VDD
VLOGIC
FUNCTION
High Byte Enable. Used to multiplex the 10-bit conversion result:
1: 2 MSBs are multiplexed on the data bus.
0: 8 LSBs are available on the data bus.
Tri-State Digital I/O Line (D7)
Tri-State Digital I/O Line (D6)
Tri-State Digital I/O Line (D5)
Tri-State Digital I/O Line (D4)
Tri-State Digital I/O Line (D3)
Tri-State Digital I/O Line (D2)
Tri-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
Tri-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
INT goes low when the conversion is complete and the output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on
the data bus.
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CS is
low in external acquisition mode, the first rising edge on WR ends acquisition and starts a
conversion.
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock. In
internal clock mode, connect this pin to either VDD or GND.
Active-Low Chip Select. When CS is high, digital outputs (D7–D0) are high impedance.
Analog Input Channel 7
Analog Input Channel 6
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5 LSB during conversion.
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a
0.01µF capacitor. When using an external reference, connect REFADJ to VDD to disable
the internal bandgap reference.
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to
GND when using the internal reference.
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.
Digital Power Supply. VLOGIC powers the digital outputs of the data converter and can
range from +1.8V to (VDD + 300mV).
8 _______________________________________________________________________________________


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Detailed Description
Converter Operation
The MAX1061/MAX1063 ADCs use a successive-
approximation (SAR) conversion technique and an
input track/hold (T/H) stage to convert an analog input
signal to a 10-bit digital output. Their parallel (8 + 2)
output format provides an easy interface to standard
microprocessors (µPs). Figure 2 shows the simplified
internal architecture of the MAX1061/MAX1063.
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH7 for the MAX1061
(Figure 3a) and to CH0–CH3 for the MAX1063 (Figure
3b), while IN- is switched to COM (Table 3).
In differential mode, IN+ and IN- are selected from ana-
log input pairs (Table 4) and are internally switched to
either of the analog inputs. This configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At
the end of the acquisition interval, the T/H switch
opens, retaining charge on CHOLD as a sample of the
signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node 0 to 0V within the
limits of 10-bit resolution. This action is equivalent to
transferring a 12pF[(VIN+) - (VIN-)] charge from CHOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
REF REFADJ
(CH7)
(CH6)
(CH5)
www.DataSheet(4CUH4.)com
CH3
CH2
CH1
CH0
COM
CLK
ANALOG
INPUT
MULTIPLEXER
CLOCK
AV =
2.05
T/H
CHARGE REDISTRIBUTION
10-BIT DAC
10
SUCCESSIVE-
APPROXIMATION
REGISTER
17k
1.22V
REFERENCE
COMP
CS
WR CONTROL LOGIC
AND
RD LATCHES
INT
( ) ARE FOR MAX1061 ONLY.
28
28
MUX
88
TRI-STATE, BIDIRECTIONAL
I/O INTERFACE
D0–D7
8-BIT DATA BUS
Figure 2. Simplified Internal Architecture for 8-/4-Channel MAX1061/MAX1063
MAX1061
MAX1063
HBEN
VDD
VLOGIC
GND
_______________________________________________________________________________________ 9


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
10-BIT CAPACITIVE DAC
REF
CH0
INPUT
MUX
CHOLD
12pF
–+
COMPARATOR
ZERO
CH1
CH2 RIN
CH3
CSWITCH
800
CH4 HOLD
TRACK
CH5 AT THE SAMPLING INSTANT,
CH6
CH7
T/H
SWITCH
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
COM IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
Figure 3a. MAX1061 Simplified Input Structure
10-BIT CAPACITIVE DAC
REF
CH0
INPUT
MUX
CHOLD
12pF
–+
ZERO
COMPARATOR
CH1
CH2
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COM
CSWITCH
TRACK
RIN
800
HOLD
T/H
SWITCH
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1 AND CH2/CH3
Figure 3b. MAX1063 Simplified Input Structure
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow each input channel to
swing within (GND - 300mV) to (VDD + 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD + 50mV) or be
less than (GND - 50mV).
If an off-channel analog input voltage exceeds the sup-
plies by more than 50mV, limit the forward-bias input
current to 4mA.
Track/Hold
The MAX1061/MAX1063 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this occurs approximately 1µs after writing the
control byte. In single-ended operation, IN- is connect-
ed to COM and the converter samples the positive (+)
input. In pseudo-differential operation, IN- connects to
the negative input (-), and the difference of (IN+) - (IN-)is
sampled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
tACQ = 7(RS + RIN)CIN
where RS is the source impedance of the input signal,
RIN (800) is the input resistance, and CIN (12pF) is
the ADC’s input capacitance. Source impedances
below 3khave no significant impact on the MAX1061/
MAX1063s’ AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX1061/MAX1063 T/H stage offers a 250kHz full-
linear and a 3MHz full-power bandwidth, enabling
these parts to use undersampling techniques to digitize
high-speed transients and measure periodic signals
with bandwidths exceeding the ADC's sampling rate.
To avoid high-frequency signals being aliased into the
frequency band of interest, anti-alias filtering is recom-
mended.
Starting a Conversion
Initiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1061/MAX1063 for either unipolar or bipolar opera-
tion. A write pulse (WR + CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
10 ______________________________________________________________________________________


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
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conversion. The sampling interval occurs at the end of
the acquisition interval. The ACQMOD (acquisition
mode) bit in the input control byte (Table 1) offers two
options for acquiring the signal: an internal and an
external acquisition. The conversion period lasts for 13
clock cycles in either the internal or external clock or
acquisition mode. Writing a new control byte during a
conversion cycle aborts the conversion and starts a
new acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval ends (three external
cycles or approximately 1µs in internal clock mode)
(Figure 4). Note that, when the internal acquisition is
combined with the internal clock, the aperture jitter can
be as high as 200ps. Internal clock users wishing to
achieve the 50ps jitter specification should always use
external acquisition mode.
External Acquisition
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi-
tion and conversion times. The user controls acquisition
and start of conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0, terminates
acquisition and starts conversion on WR’s rising edge
(Figure 5).
The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see the Power-Down
Modes section). Changing other bits in the control byte
corrupts the conversion.
Reading a Conversion
A standard interrupt signal, INT, is provided to allow the
MAX1061/MAX1063 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
when the conversion is complete and the output data is
ready (Figures 4 and 5). It returns high on the first read
cycle or if a new control byte is written.
Table 1. Control Byte Functional Description
BIT NAME
FUNCTION
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PD1 and PD0 select the various clock and power-down modes.
0 0 Full power-down mode. Clock mode is unaffected.
D7, D6
PD1, PD0
0
1 Standby power-down mode. Clock mode is unaffected.
1 0 Normal operation mode. Internal clock mode selected.
1 1 Normal operation mode. External clock mode selected.
D5
D4
D3
D2, D1, D0
ACQMOD
SGL/DIF
UNI/BIP
A2, A1, A0
ACQMOD = 0: Internal acquisition mode
ACQMOD = 1: External acquisition mode
SGL/DIF = 0: Pseudo-differential analog input mode
SGL/DIF = 1: Single-ended analog input mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
UNI/BIP = 0: Bipolar mode
UNI/BIP = 1: Unipolar mode
In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the sig-
nal can range from -VREF/2 to +VREF/2.
Address bits A2, A1, A0 select which of the 8/4 (MAX1061/MAX1063) channels are to be converted
(Tables 3 and 4).
______________________________________________________________________________________ 11


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
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CS
tCSWS
WR
D7–D0
INT
RD
HBEN
HIGH-Z
DOUT
tCS
tACQ
tWR tCSWH
tDS
CONTROL
BYTE
ACQMOD = 0
tDH
tCONV
tINT1
tD0 tD01
HIGH/LOW
BYTE VALID
HIGH/LOW
BYTE VALID
Figure 4. Conversion Timing Using Internal Acquisition Mode
tCS
CS
tCSWS
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WR
D7–D0
tWR
tDS
CONTROL
BYTE
ACQMOD = 1
tACQ
tCSHW
tCONV
tDH
CONTROL
BYTE
ACQMOD = 0
INT
tINT1
tTR
HIGH-Z
RD
HBEN
HIGH-Z
DOUT
tD0 tD01 tTR
HIGH/LOW
BYTE VALID
HIGH/LOW
BYTE VALID
HIGH-Z
Figure 5. Conversion Timing Using External Acquisition Mode
12 ______________________________________________________________________________________


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
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Selecting Clock Mode
The MAX1061/MAX1063 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The parts retain
the last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock modes, internal or external acquisition
can be used. At power-up, the MAX1061/MAX1063
enter the default external clock mode.
Internal Clock Mode
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. To select
this mode, bit D7 of the control byte must be set to 1
and D6 must be set to zero. The internal clock frequen-
cy is then selected, resulting in a conversion time of
3.6µs. When using the internal clock mode, tie the CLK
pin either high or low to prevent the pin from floating.
External Clock Mode
To select the external clock mode, bits D6 and D7 of
the control byte must be set to 1. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1061/MAX1063 with
clock frequencies lower than 100kHz is not recom-
mended, because it causes a voltage droop across the
hold capacitor in the T/H stage that results in degraded
performance.
Digital Interface
Input (control byte) and output data are multiplexed on
a tri-state parallel interface. This parallel interface (I/O)
can easily be interfaced with standard µPs. The signals
CS, WR, and RD control the write and read operations.
CS represents the chip-select signal, which enables a
µP to address the MAX1061/MAX1063 as an I/O port.
When high, CS disables the CLK, WR, and RD inputs
and forces the interface into a high-impedance (high-Z)
state.
Input Format
The control byte is latched into the device on pins
D7–D0 during a write command. Table 2 shows the
control byte format.
Output Format
The output format for both the MAX1061/MAX1063 is
binary in unipolar mode and two’s complement in bipo-
lar mode. When reading the output data, CS and RD
must be low. When HBEN = 0, the lower 8 bits are
read. With HBEN = 1, the upper 2 bits are available
and the output data bits D7–D2 are set either low in
unipolar mode or set to the value of the MSB in bipolar
mode (Table 5).
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CLK
WR
tCWH
CLK
ACQUISITION STARTS
tCP
ACQUISITION ENDS
CONVERSION STARTS
tCWS tCH
ACQMOD = 0
ACQUISITION STARTS
tCL
WR GOES HIGH WHEN CLK IS HIGH.
ACQUISITION ENDS
CONVERSION STARTS
WR
ACQMOD = 0
WR GOES HIGH WHEN CLK IS LOW.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
______________________________________________________________________________________ 13


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
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ACQUISITION STARTS
ACQUISITION ENDS
CLK
tDH
WR
ACQMOD = 1
WR GOES HIGH WHEN CLK IS HIGH.
tCWS
ACQMOD = 0
ACQUISITION STARTS
ACQUISITION ENDS
CLK
tDH
WR
ACQMOD = 1
tCWH
WR GOES HIGH WHEN CLK IS LOW. ACQMOD = 0
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
CONVERSION STARTS
CONVERSION STARTS
Table 2. Control Byte Format
D7 (MSB)
D6
D5
PD1 PD0 ACQMOD
D4
SGL/DIF
D3
UNI/BIP
D2
A2
D1 D0 (LSB)
A1 A0
Table 3. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
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A2 A1
A0
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
000+
001
+
010
+
011
+
100
+
101
+
110
+
111
*Channels CH4–CH7 apply to MAX1061 only.
CH7*
+
COM
-
-
-
-
-
-
-
-
14 ______________________________________________________________________________________


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
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Table 4. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
A2
A1
A0
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
000+ -
001 -+
010
+-
011
-+
100
+-
101
-+
110
+
111
-
*Channels CH4–CH7 apply to MAX1061 only.
CH7*
-
+
Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1061/MAX1063 in external
clock mode and sets INT high. After the power supplies
stabilize, the internal reset time is 10µs, and no conver-
sions should be attempted during this phase. When
using the internal reference, 500µs are required for
VREF to stabilize.
Internal and External Reference
The MAX1061/MAX1063 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.
An internal buffer is designed to provide +2.5V at REF for
www.DabtaoSthheetht4eU.McoAmX1061 and the MAX1063. The internally
trimmed +1.22V reference is buffered with a +2.05V/V
gain.
Table 5. Data-Bus Output (8 + 2 Parallel
Interface)
PIN HBEN = 0
D0 Bit 0 (LSB)
HBEN = 1
Bit 8
D1 Bit 1
Bit 9 (MSB)
BIPOLAR
(UNI/BIP = 0)
UNIPOLAR
(UNI/BIP = 1)
D2 Bit 2
Bit 9
0
D3 Bit 3
Bit 9
0
D4 Bit 4
Bit 9
0
D5 Bit 5
Bit 9
0
D6 Bit 6
D7 Bit 7
Bit 9
Bit 9
0
0
Internal Reference
With the internal reference, the full-scale range is +2.5V
with unipolar inputs and ±1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
(±100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with
an external capacitor (4.7µF min) connected between
REF and GND to reduce reference noise and switching
spikes from the ADC. To further minimize noise on the
reference, connect a 0.01µF capacitor between
REFADJ and GND.
External Reference
With both the MAX1061 and MAX1063, an external ref-
erence can be placed at either the input (REFADJ) or
the output (REF) of the internal reference buffer amplifier.
Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17k.
VDD = +3V
50k
50k
330k
GND 0.01µF
4.7µF
MAX1061
MAX1063
REFADJ
REF
GND
Figure 7. Reference Voltage Adjustment with External
Potentiometer
______________________________________________________________________________________ 15


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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When applying an external reference to REF, disable
the internal reference buffer by connecting REFADJ to
VDD. The DC input resistance at REF is 25k.
Therefore, an external reference at REF must deliver up
to 200µA DC load current during a conversion and
have an output impedance less than 10. If the refer-
ence has higher output impedance or is noisy, bypass
it close to the REF pin with a 4.7µF capacitor.
Power-Down Modes
Save power by placing the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode using bits D6 and D7 of the
control byte (Tables 1 and 2). In both software power-
down modes, the parallel interface remains active, but
the ADC does not convert.
Standby Mode
While in standby mode, the supply current is 850µA
(typ). The part powers up on the next rising edge on
WR and is ready to perform conversions. This quick
turn-on time allows the user to realize significantly
reduced power consumption for conversion rates
below 250ksps.
Shutdown Mode
Shutdown mode turns off all chip functions that draw qui-
escent current, reducing the typical supply current to
2µA immediately after the current conversion is complet-
ed. A rising edge on WR causes the MAX1061/MAX1063
to exit shutdown mode and return to normal operation.
To achieve full 10-bit accuracy with a 4.7µF reference
bypass capacitor, 500µs is required after power-up.
Waiting 500µs in standby mode, instead of in full-power
mode, can reduce power consumption by a factor of 3 or
more. When using an external reference, only 50µs is
required after power-up. Enter standby mode by per-
forming a dummy conversion with the control byte speci-
fying standby mode.
Note: Bypassing capacitors larger than 4.7µF between
REF and GND results in longer power-up delays.
Transfer Function
Table 6 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Figure 8 depicts the nominal, unipolar input/output (I/O)
transfer function and Figure 9 shows the bipolar I/O
transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
is binary, with 1 LSB = VREF / 1024.
Maximum Sampling Rate/
Achieving 300ksps
When running at the maximum clock frequency of
4.8MHz, the specified throughput of 250ksps is
achieved by completing a conversion every 19 clock
cycles: 1 write cycle, 3 acquisition cycles, 13 conver-
www.DataSheetO4UUTP.cUToCmODE
111 . . . 111
111 . . . 110
100 . . . 010
100 . . . 001
100 . . . 000
011 . . . 111
011 . . . 110
011 . . . 101
FS = REF + COM
ZS = COM
1 LSB = REF
1024
FULL-SCALE
TRANSITION
OUTPUT CODE
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
FS = REF + COM
2
ZS = COM
-FS = -REF + COM
2
1 LSB = REF
1024
000 . . . 001
000 . . . 000
01
(COM)
2
512
INPUT VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 8. Unipolar Transfer Function
100 . . . 001
100 . . . 000
- FS
*COM VREF / 2
COM*
INPUT VOLTAGE (LSB)
Figure 9. Bipolar Transfer Function
+FS - 1 LSB
16 ______________________________________________________________________________________


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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Table 6. Full Scale and Zero Scale for Unipolar and Bipolar Operation
UNIPOLAR MODE
Full scale
Zero scale
VREF + COM
COM
BIPOLAR MODE
Positive full scale
Zero scale
Negative full scale
VREF/2 + COM
COM
-VREF/2 + COM
sion cycles, and 2 read cycles. This assumes that the
results of the last conversion are read before the next
control byte is written. Throughputs up to 300ksps can
be achieved by first writing a control word to begin the
acquisition cycle of the next conversion, then reading
the results of the previous conversion from the bus
(Figure 10). This technique allows a conversion to be
completed every 16 clock cycles. Note that the switch-
ing of the data bus during acquisition or conversion
can cause additional supply noise, which can make it
difficult to achieve true 10-bit performance.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one star point (Figure 11) connecting the two ground
systems (analog and digital). For lowest noise opera-
tion, ensure the ground return to the star ground’s
www.DapbtaoleSw.heRereotsu4uUtep.cpdolmiygiitsalloswignimalpsefdaranacweayanfrdomasseshnosirttivaesapnoaslosgi-
and reference inputs.
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast com-
parator. Bypass VDD to the star ground with a network
of two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX1061/MAX1063s’ power-
supply pin. Minimize capacitor lead length for best sup-
ply-noise rejection; add an attenuation resistor (5) if
the power supply is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1061/MAX1063
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples. Aperture delay (tAD) is
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD (dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
______________________________________________________________________________________ 17


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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1 23
456
78
9 10 11 12 13 14 15 16
CLK
WR
RD
HBEN
CONTROL
D7–D0 BYTE
D7–D0 D9–D8
LOW HIGH
BYTE BYTE
STATE
ACQUISITION
SAMPLING INSTANT
Figure 10. Timing Diagram for Fastest Conversion
CONTROL BYTE
CONVERSION
D7–D0 D9–D8
LOW HIGH
BYTE BYTE
ACQUISITION
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
( )www.DataSThHeDet4U=.c2om0 x
log
⎝⎜
V22 + V32 + V42 + V52 / V1⎞⎠⎟
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order har-
monics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest distor-
tion component.
SUPPLIES
+3V VLOGIC = +2V/+3V GND
R* = 5
4.7µF
0.1µF
VDD GND COM +2V/+3V DGND
MAX1061
MAX1063
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 11. Power-Supply and Grounding Connections
18 ______________________________________________________________________________________


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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
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Typical Operating Circuits
µP
CONTROL
INPUTS
CLK VLOGIC
MAX1061 VDD
CS REF
WR REFADJ
RD
HBEN
D7
D6
D5
D4
D3
D2
D1/D9
D0/D8
INT
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
COM
GND
µP DATA BUS
+1.8V TO +3.6V
+3V
+2.5V
0.1µF
4.7µF
µP
CONTROL
INPUTS
OUTPUT STATUS
ANALOG
INPUTS
CLK VLOGIC
MAX1063 VDD
CS REF
WR REFADJ
RD
HBEN
INT
D7
D6
D5
D4
D3
D2
D1/D9
D0/D8
CH3
CH2
CH1
CH0
COM
GND
µP DATA BUS
+1.8V TO +3.6V
+3V
+2.5V
0.1µF
4.7µF
OUTPUT STATUS
ANALOG
INPUTS
Pin Configurations (continued)
Ordering Information (continued)
www.DataSheet4TOUP.cVoIEmW
HBEN 1
D7 2
D6 3
D5 4
D4 5
D3 6
D2 7
D1/D9 8
D0/D8 9
INT 10
RD 11
WR 12
CLK 13
CS 14
MAX1061
QSOP
28 VLOGIC
27 VDD
26 REF
25 REFADJ
24 GND
23 COM
22 CH0
21 CH1
20 CH2
19 CH3
18 CH4
17 CH5
16 CH6
15 CH7
PART
TEMP RANGE
PIN-PACKAGE
INL
(LSB)
MAX1063ACEG+ 0°C to +70°C
MAX1063BCEG+ 0°C to +70°C
MAX1063AEEG+ -40°C to +85°C
MAX1063BEEG+ -40°C to +85°C
24 QSOP
24 QSOP
24 QSOP
24 QSOP
±0.5
±1
±0.5
±1
+Denotes a lead(Pb)-free/RoHS-compliant package.
Chip Information
TRANSISTOR COUNT: 5781
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
28 QSOP
24 QSOP
PACKAGE CODE
E28+1
E24+2
DOCUMENT NO.
21-0055
21-0055
______________________________________________________________________________________ 19


MAX1063 (Maxim Integrated Products)
(MAX1061 / MAX1063) 10-Bit ADCs

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250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Revision History
REVISION
NUMBER
0
1
REVISION
DATE
4/03
3/09
DESCRIPTION
Initial release
Updated Ordering Information table with lead-free information and updated
Package Information section
PAGES CHANGED
1, 19, 20
www.DataSheet4U.com
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products.




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