SPEAr320 (ST Microelectronics)
SPEAr Embedded Microprocessors

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SPEAr320
Embedded MPU with ARM926 core
for factory automation and consumer applications
Preliminary data
Features
ARM926EJ-S 333 MHz core
High-performance 8-channel DMA
Dynamic power-saving features
Configurable peripheral functions multiplexed
on 102 shared I/Os
Memory:
– 32 KB ROM and 8 KB internal SRAM
– LPDDR-333/DDR2-666 external memory
interface
– SDIO/MMC card interface
– Serial SPI Flash interface
– Flexible static memory controller (FSMC)
up to 16-bit data bus width, supporting
NAND Flash
– External memory interface (EMI) up to 16-
bit data bus width, supporting NOR Flash
and FPGAs
Security
– C3 Cryptographic accelerator
Connectivity
– 2 x USB 2.0 Host
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– 1 x USB 2.0 Device
– 2 x fast Ethernet MII/SMII ports
– 2 x CAN interface
– 3 x SPI
– 2 x I2C
– 1 x I2S
– 1 x fast IrDA interface
– 3 x UART interface
– 1 x standard parallel device port
Peripherals supported
– TFT/STN LCD controller (resolution up to
1024 x 768 and up to 24 bpp)
– Touchscreen support
Miscellaneous functions
LFBGA289 (15 x 15 x 1.7 mm)
– Integrated real time clock, watchdog, and
system controller
– 8-channel 10-bit ADC, 1 Msps
– 4 x PWM timers
– JPEG CODEC accelerator
– 6 x 16-bit general purpose timers with and
programmable prescaler, 4 capture inputs
– Up to 102 GPIOs with interrupt capability
Applications
The SPEAr320 embedded MPU is configurable
for a range industrial and consumer applications
such as:
Programmable logic controllers
Factory automation
Printers
Table 1. Device summary
Order code
Temp
range, °C
Package Packing
SPEAR320-2 -40 to 85
LFBGA289
(15 x 15 mm,
pitch 0.8 mm)
Tray
November 2009
Doc ID 16755 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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Contents
Contents
SPEAr320
Description 5
1.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 CPU ARM 926EJ-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Mobile DDR/DDR2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Multichannel DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 SMII/MII Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9 MII Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.10 CAN controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.11 USB2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.12 USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.13 CLCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.14 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.15 Parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.16
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2.17
2.18
SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
I2S audio block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.19 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.19.1 UART0 with hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.19.2 UART1 and UART2 with software flow control . . . . . . . . . . . . . . . . . . . . 17
2.20 JPEG CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.21 Cryptographic co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.22 8-channel ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.23 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.23.1 Power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.23.2 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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SPEAr320
Contents
2.24 Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.25 General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.26 PWM timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.27 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.28 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Shared I/O pins (PL_GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1 Absolute minimum and maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2 Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.4 Overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5 General purpose I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6 LPDDR and DDR2 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.6.1 DDR2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.7 CLCD timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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5.8
5.7.1 CLCD timing characteristics direct clock . . . . . . . . . . . . . . . . . . . . . . . . 44
5.7.2 CLCD timing characteristics divided clock . . . . . . . . . . . . . . . . . . . . . . . 45
I2C timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.9 FSMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.9.1 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.9.2 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.10 Ether MAC 10/100/1000 Mbps (GMAC-Univ) timing characteristics . . . . 52
5.10.1 GMII Transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.10.2 MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.10.3 GMII-MII Receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.10.4 MDIO timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.11 SMI - Serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.12 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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Contents
SPEAr320
5.13
5.14
5.15
5.12.1 SPI master mode timings (Clock phase = 0) . . . . . . . . . . . . . . . . . . . . . 60
5.12.2 SPI master mode timings (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . 61
UART (Universal asynchronous receiver/transmitter) . . . . . . . . . . . . . . . 63
Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Power on reset (MRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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SPEAr320
1 Description
Description
The SPEAr320 is a member of the SPEAr family of embedded MPUs, optimized for
industrial automation and consumer applications. It is based on the powerful ARM926EJ-S
processor (up to 333 MHz), widely used in applications where high computation
performance is required.
In addition, SPEAr320 has an MMU that allows virtual memory management -- making the
system compliant with Linux operating system. It also offers 16 KB of data cache, 16 KB of
instruction cache, JTAG and ETM (Embedded Trace Macrocell) for debug operations.
A full set of peripherals allows the system to be used in many applications, some typical
applications being factory automation, printer and consumer applications.
Figure 1. Functional block diagram
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Description
SPEAr320
1.1 Main features
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ARM926EJ-S 32-bit RISC CPU, up to 333 MHz
– 16 Kbytes of instruction cache, 16 Kbytes of data cache
– 3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code
density, byte Java mode (Jazelle™) for direct execution of Java code.
– Tightly Coupled Memory
– AMBA bus interface
32-KByte on-chip BootRom
8-KByte on-chip SRAM
External DRAM memory interface:
– 8/16-bit (mobile DDR@166 MHz)
– 8/16-bit (DDR2@333 MHz)
Serial memory interface
SDIO interface supporting SPI, SD1, SFD4 and SD8 modes
8/16-bits NAND Flash controller (FSMC)
External memory interface (EMI) for connecting NOR Flash or FPGAs
Boot capability from NAND Flash, serial/parallel NOR Flash
Boot and field upgrade capability from USB
High performance 8-channel DMA controller
2x Ethernet MAC 10/100 Mbps with MII/SMII PHY interface
Two USB2.0 host (high-full-low speed) with integrated PHY transceiver
One USB2.0 device (high-full speed) with integrated PHY transceiver
2x CAN 2.0 interfaces
Up to 102 GPIOs with interrupt capability
Up to 4 PWM outputs
3x SPI master/slave (supporting Motorola, Texas instruments, National semiconductor
protocols) up to 41.5 Mbps
Standard Parallel Port (SPP device implementation)
I2S input-output for voice or modem interfaces
2x I2C master/slave interface (slow- fast-high speed, up to 1.2Mb/s)
3x UART: UART1 with hardware flow control (up to 460.8 kbaud), UART2 and UART3
with software flow control (baud rate > 6 Mbps)
ADC 10-bit, 1 Msps 8 inputs/1-bit DAC
JPEG CODEC accelerator 1 clock/pixel
Color LCD interface (up to 1024X768, 24-bits CLCD controller, TFT and STN panels)
Touchscreen support
C3 Crypto accelerator (DES/3DES/AES/SHA1)
Advanced power saving features
– Normal, Slow, Doze and Sleep modes CPU clock with software-programmable
frequency
– Enhanced dynamic power-domain management
– Clock gating functionality
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SPEAr320
Description
– Low frequency operating mode
– Automatic power saving controlled from application activity demands
Vectored interrupt controller
System and peripheral controller
– 3 pairs of 16-bit general purpose timers with programmable prescaler
– RTC with separate power supply allowing battery connection
– Watchdog timer
– Miscellaneous registers array for embedded MPU configuration
Programmable PLL for CPU and system clocks
JTAG IEEE 1149.1 boundary scan
ETM functionality multiplexed on primary pins
Supply voltages
– 1.2 V core, 1.8 V/2.5 V DDR, 2.5 V PLLs and 3.3 V I/Os
Operating temperature: - 40 to 85 °C
LFBGA289 (15 x 15 mm, pitch 0.8 mm)
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Architecture overview
2 Architecture overview
SPEAr320
The SPEAr320 internal architecture is based on several shared subsystem logic blocks
interconnected through a multilayer interconnection matrix.
The switch matrix structure allows different subsystem dataflow to be executed in parallel
improving the core platform efficiency.
High performance master agents are directly interconnected with the memory controller
reducing the memory access latency. The overall memory bandwidth assigned to each
master port can be programmed and optimized through an internal efficient weighted round-
robin arbitration mechanism.
Figure 2. Typical system architecture using SPEAr320
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2.1 CPU ARM 926EJ-S
The core of the SPEAr320 is an ARM926EJ reduced instruction set computer (RISC)
processor.
It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off
between high performance and high code density and includes features for efficient
execution of Java byte codes.
The ARM CPU and is clocked at a frequency up to 333 MHz. It has a 16-Kbyte instruction
cache, a 16-Kbyte data cache, and features a memory management unit (MMU) which
makes it fully compliant with Linux and VxWorks operating systems.
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SPEAr320
Architecture overview
It also includes an embedded trace module (ETM Medium+) for real-time CPU activity
tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed
trace mode, with normal or half-rate clock.
2.2 Embedded memory units
32 Kbytes of BootROM
8 Kbytes of SRAM
2.3 Mobile DDR/DDR2 memory controller
SPEAr320 integrates a high performance multi-channel memory controller able to support
low power Mobile DDR and DDR2 double data rate memory devices. The multi-port
architecture ensures memory is shared efficiently among different high-bandwidth client
modules.
It has 6 internal ports. One of them is reserved for register access during the controller
initialization while the other five are used to access the external memory.
It also includes the physical layer (PHY) and DLLs for fine tuning the timing parameters to
maximize the data valid windows at different frequencies.
2.4 Serial memory interface
SPEAr320 provides a serial memory interface (SMI), acting as an AHB slave interface (32-,
16- or 8-bit) to SPI-compatible off-chip memories.
These serial memories can be used either as data storage or for code execution.
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Main features:
Supports the following SPI-compatible Flash and EEPROM devices:
– STMicroelectronics M25Pxxx, M45Pxxx
– STMicroelectronics M95xxx, except M95040, M95020 and M95010
– ATMEL AT25Fxx
– YMC Y25Fxx
– SST SST25LFxx
Acts always as a SPI master and up to 2 SPI slave memory devices are supported
(with separate chip select signals), with up to 16 MB address space each
SMI clock signal (SMICLK) is generated by SMI (and input to all slaves) using a clock
provided by the AHB bus
SMICLK can be up to 50 MHz in fast read mode (or 20 MHz in normal mode). It can be
controlled by a programmable 7-bit prescaler allowing up to 127 different clock
frequencies.
2.5 External memory interface (EMI)
The EMI Controller provide a simple external memory interface that can be used for
example to connect to NOR FLash memory or FPGA devices.
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Architecture overview
Main features:
EMI bus master
16 and 8-bit transfers
Can access 4 different peripherals using CS#, one at a time.
Supports single asynchronous transfers.
Supports peripherals which use Byte Lane procedure
SPEAr320
2.6 Flexible static memory controller (FSMC)
SPEAr320 provides a Flexible Static Memory Controller (FSMC) which interfaces the AHB
bus to external parallel NAND Flash memories.
Provides an interface between AHB system bus and external NAND Flash memory
devices.
8/16-bit wide data path
FSMC performs only one access at a time and only one external device is accessed
Supports little-endian and big-endian memory architectures
AHB burst transfer handling to reduce access time to external devices
Supplies an independent configuration for each memory bank
Programmable timings to support a wide range of devices
– Programmable wait states (up to 31)
– Programmable bus turnaround cycles (up to 15)
– Programmable output enable and write enable delays (up to 15)
Independent chip select control for each memory bank
Shares the address bus and the data bus with all the external peripherals
Only chips selects are unique for each peripheral
External asynchronous wait control
Boot memory bank configurable at reset using external control pins
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2.7 Multichannel DMA controller
Within its basic subsystem, SPEAr320 provides an DMA controller (DMAC) able to service
up to 8 independent DMA channels for serial data transfers between single source and
destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and
peripheral-to-peripheral).
Each DMA channel can support a unidirectional transfer, with internal four-word FIFO per
channel.
2.8 SMII/MII Ethernet controller
SPEAr320 features two Ethernet MACs, one supporting SMII and one supporting SMII and
MII.
Each MAC channel has dedicated TX/RX signals while synchronization and clock signals
are common for PHY connection.
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SPEAr320
Architecture overview
The Figure 3 shows the typical SMII configuration (a generic example with four ports):
Figure 3. Typical SMII system
8
port
MAC
4 Tx
4 Rx
Sync
Clock
4 Tx
4 Rx
Sync
Quad
PHY
Quad
PHY
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Each Ethernet port provides the following features:
Compatible with IEEE Standard 802.3
10 and 100 Mbit/s operation
Full and half duplex operation
Statistics counter registers for RMON/MIB
Interrupt generation to signal receive and transmit completion
Automatic pad and CRC generation on transmitted frames
Automatic discard of frames received with errors
Address checking logic supports up to four specific 48-bit addresses
Supports promiscuous mode where all valid received frames are copied to memory
Hash matching of unicast and multicast destination addresses
External address matching of received frames
Physical layer management through MDIO interface
Supports serial network interface operation
Half duplex flow control by forcing collisions on incoming frames
Full duplex flow control with recognition of incoming pause frames and hardware
generation of transmitted pause frames
Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority
tagged frames
Multiple buffers per receive and transmit frame
Wake on LAN support
Jumbo frames of up to 10240 bytes supported
Configurable Endianess for the DMA Interface (AHB Master)
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Architecture overview
SPEAr320
2.9 MII Ethernet controller
SPEAr320 provides an Ethernet MAC 10/100 Universal (commonly referred to as MAC-
UNIV), enabling to transmit and receive data over Ethernet in compliance with the IEEE
802.3-2002 standard.
Main features:
Supports the default Media Independent Interface (MII) defined in the IEEE 802.3
specifications.
Supports 10/100 Mbps data transfer rates
Local FIFO available (4 Kbyte RX, 2 Kbyte TX)
Supports both half-duplex and full-duplex operation. In half-duplex operation,
CSMA/CD protocol is provided
Programmable frame length to support both standard and jumbo Ethernet frames with
size up to 16 Kbytes
32/64/128-bit data transfer interface on system-side.
A variety of flexible addresses filtering modes are supported
A set of control and status registers (CSRs) to control GMAC core operation
Native DMA with single-channel transmit and receive engines, providing 32/64/128-bit
data transfers
DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining
An AHB slave acting as programming interface to access all CSRs, for both DMA and
GMAC core subsystems
An AHB master for data transfer to system memory
32-bit AHB master bus width, supporting 32, 64, and 128-bit wide data transactions
It supports both big-endian and little-endian.
2.10 CAN controller
SPEAr320 has two CAN controllers for interfacing CAN 2.0 networks.
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Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 MBit/s
32 Message Objects(136 X 32 Message RAM)
Each Message Object has its own identifier mask
Maskable interrupt
Programmable loop-back mode for self-test operation
Disabled Automatic Retransmission mode for Time Triggered CAN applications
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SPEAr320
Architecture overview
2.11
USB2 host controller
SPEAr320 has two fully independent USB 2.0 hosts. Each consists of 5 major blocks:
EHCI capable of managing high-speed transfers (HS mode, 480 Mbps)
OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps)
Local 2-Kbyte FIFO
Local DMA
Integrated USB2 transceiver (PHY)
Both hosts can manage an external power switch, providing a control line to enable or
disable the power, and an input line to sense any over-current condition detected by the
external switch.
One host controller at time can perform high speed transfer.
2.12 USB2 device controller
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Main features:
Supports the 480 Mbps high-speed mode (HS) for USB 2.0, as well as the 12 Mbps
full-speed (FS) and the low-speed (LS modes) for USB 1.1
Supports 16 physical endpoints, configurable as different logical endpoints
Integrated USB transceiver (PHY)
Local 4 Kbyte FIFO shared among all the endpoints
DMA mode and slave-only mode are supported
In DMA mode, the UDC supports descriptor-based memory structures in application
memory
In both modes, an AHB slave is provided by UDC-AHB, acting as programming
interface to access to memory-mapped control and status registers (CSRs)
An AHB master for data transfer to system memory is provided, supporting 8, 16, and
32-bit wide data transactions on the AHB bus
A USB plug (UPD) detects the connection of a cable.
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SPEAr320
2.13
CLCD controller
SPEAr320 has a color liquid crystal display controller (CLCDC) that provides all the
necessary control signals to interface directly to a variety of color and monochrome LCD
panels.
Main features:
Resolution programmable up to 1024 x 768
16-bpp true-color non-palletized, for color STN and TFT
24-bpp true-color non-palletized, for color TFT
Supports single and dual panel mono super twisted nematic (STN) displays with 4 or 8-
bit interfaces
Supports single and dual-panel color and monochrome STN displays
Supports thin film transistor (TFT) color displays
15 gray-level mono, 3375 color STN, and 32 K color TFT support
1, 2, or 4 bits per pixel (bpp) palletized displays for mono STN
1, 2, 4 or 8-bpp palletized color displays for color STN and TFT
Programmable timing for different display panels
256 entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM physically frame, line
and pixel clock signals
AC bias signal for STN and data enable signal for TFT panels patented gray scale
algorithm
Supports little and big-endian
2.14 GPIOs
A maximum of 102 GPIOs are available when part of the embedded or customizations IPs
are not needed (see "Pin description" table).
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Within its basic subsystem, SPEAr320 provides a base General Purpose Input/Output
(GPIO) block (basGPIO). The base GPIO block provides 6 programmable inputs or outputs.
Each input/output can be controlled in two distinct modes:
Software mode, through an APB interface.
Hardware mode, through a hardware control interface.
Main features of the base GPIO block are:
Six individually programmable input/output pins (default to input at reset)
An APB slave acting as control interface in "software mode"
Programmable interrupt generation capability on any number of pins.
Hardware control capability of GPIO lines for different system configurations.
Bit masking in both read and write operation through address lines.
Other GPIO blocks are present in the reconfigurable array subsystem (RAS).
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Architecture overview
2.15
Parallel port
Main features:
Slave mode device interface for Standard parallel port host
Supports unidirectional 8-bit data transfer from host to slave
Supports 9th bit for parity/data/command etc.
Maskable interrupts for data, device reset, auto line feed
APB input clock frequency required is 83 MHz for acknowledgement timings
Conforms to AMBA-APB specifications
2.16
SSP
SPEAr320 provides one synchronous serial port (SSP) block that offers a master or slave
interface to enables synchronous serial communication with slave or master peripherals
Main features:
Master or slave operation.
Programmable clock bit rate and prescale.
Separate transmit and receive first-in, first-out memory buffers, 16-bits wide, 8 locations
deep.
Programmable choice of interface operation:
– SPI (Motorola)
– Microwire (National Semiconductor)
– TI synchronous serial.
Programmable data frame size from 4 to 16-bits.
Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts.
Internal loopback test mode available.
DMA interface
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Architecture overview
SPEAr320
2.17
I2C
The SPEAr320 has 2 I2C interfaces;
Main features:
Compliance to the I2C bus specification (Philips)
Supports three modes:
– Standard (100 kbps)
– Fast (400 kbps)
– High-speed (3.4 Mbps)
Clock synchronization
Master and slave mode configuration possible
Multi-master mode (bus arbitration)
7-bit or 10-bit addressing
7-bit or 10-bit combined format transfers
Slave bulk transfer mode
Ignores CBUS addresses (predessor to I2C that used to share the I2C bus)
Transmit and receive buffers
Interrupt or polled-mode operation
handles bit and byte waiting at all bus speeds
Digital filter for the received SDA and SCL lines
Handles component parameters for configurable software driver support
Supports APB data bus widths of 8, 16 and 32-bits.
2.18 I2S audio block
The SPEAr320 has one I2S interface.
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Main features:
Conversion of AHB protocol to I2S protocol.
Supports 2.0 audio outputs (master mode only)
Supports 32 (16L + 16R) and 64-bit (32L + 32R) of raw PCM data length
48 kHz audio sampling rate
MIC/line-In recording (master/slave modes)
The the I2S audio blocks can be used to provide "Audio Play" and "Audio Record" capability.
The Audio Play function works in master mode only but Audio Record can be used in both
master and slave modes. In master mode, it outputs clock and WS signals in addition to
stereo data. In slave mode, the clock and the WS signal has to be provided externally.
2.19
UARTs
The SPEAr320 has 2 UARTs featuring software flow control and 1 UART featuring hardware
and/or software flow control.
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Architecture overview
2.19.1
2.19.2
UART0 with hardware flow control
Main features:
Separate 16 x 8 (16 locations deep x 8-bit wide) transmit and 16 x 12 receive FIFOs to
reduce CPU interrupts
Speed up to 3 Mbps
Hardware and/or software flow control
UART1 and UART2 with software flow control
Main features:
Separate 16 x 8 (16 location deep x 8-bit wide) transmit and 16x12 receive FIFOs to
reduce CPU interrupts
Speed up to 5 Mbps.
2.20 JPEG CODEC
SPEAr320 provides a JPEG CODEC with header processing (JPGC), able to decode (or
encode) image data contained in the SPEAr320 RAM, from the JPEG (or BMP) format to
the BMP (or JPEG) format.
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Main features:
Compliance with the baseline JPEG standard (ISO/IEC 10918-1)
Single-clock per pixel encoding/decoding
Support for up to four channels of component color
8-bit/channel pixel depths
Programmable quantization tables (up to four)
Programmable Huffman tables (two AC and two DC)
Programmable minimum coded unit (MCU)
Configurable JPEG header processing
Support for restart marker insertion
Use of two DMA channels and of two 8 x 32-bits FIFO's (local to the JPEG) for efficient
transferring and buffering of encoded/decoded data from/to the CODEC core.
2.21
Cryptographic co-processor (C3)
SPEAr320 has an embedded Channel Control Coprocessor (C3). C3 is a high-performance
instruction driven DMA based co-processor. It executes instruction flows generated by the
host processor. After it has been set-up by the host it runs in a completely autonomous way
(DMA data in, data processing, DMA data out), until the completion of all the requested
operations.
C3 has been used to accelerate the processing of cryptographic, security and network
security applications. It can be used for other types of data intensive applications as well.
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Architecture overview
SPEAr320
Hardware cryptographic co-processor features are listed below:
Supported cryptographic algorithms:
– Advanced encryption standard (AES) cipher in ECB, CBC, CTR modes.
– Data encryption standard (DES) cipher in ECB and CBC modes.
– SHA-1, HMAC-SHA-1, MD5, HMAC-MD5 digests.
Instruction driven DMA based programmable engine.
AHB master port for data access from/to system memory.
AHB slave port for co-processor register accesses and initial engine-setup.
The co-processor is fully autonomous (DMA input reading, cryptographic operation
execution, DMA output writing) after being set up by the host processor.
The co-processor executes programs written by the host in memory, it can execute an
unlimited list of programs.
The co-processor supports hardware chaining of cryptographic blocks for optimized
execution of data-flow requiring multiple algorithms processing over the same set of
data (for example encryption + hashing on the fly).
2.22 8-channel ADC
Main features:
Successive approximation conversion method
10-bit resolution @1 Msps
Hardware supporting up to 13.5 bits resolution at 8 ksps by oversampling and
accumulation
Eight analog input (AIN) channels, ranging from 0 to 2.5 V
INL ± 1 LSB, DNL ± 1 LSB
Programmable conversion speed, (min. conversion time is 1 µs)
Programmable averaging of results from 1 (No averaging) up to 128
Programmable auto scan for all the eight channels.
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2.23 System controller
The System Controller provides an interface for controlling the operation of the overall
system.
Main features:
Power saving system mode control
Crystal oscillator and PLL control
Configuration of system response to interrupts
Reset status capture and soft reset generation
Watchdog and timer module clock enable
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SPEAr320
Architecture overview
2.23.1
Power saving system mode control
Using three mode control bits, the system controller switch the SPEAr320 to any one of four
different modes: DOZE, SLEEP, SLOW and NORMAL.
SLEEP mode: In this mode the system clocks, HCLK and CLK, are disabled and the
System Controller clock SCLK is driven by a low speed oscillator (nominally 32768 Hz).
When either a FIQ or an IRQ interrupt is generated (through the VIC) the system enters
DOZE mode. Additionally, the operating mode setting in the system control register
automatically changes from SLEEP to DOZE.
DOZE mode: In this mode the system clocks, HCLK and CLK, and the System
Controller clock SCLK are driven by a low speed oscillator. The System Controller
moves into SLEEP mode from DOZE mode only when none of the mode control bits
are set and the processor is in Wait-for-interrupt state. If SLOW mode or NORMAL
mode is required the system moves into the XTAL control transition state to initialize the
crystal oscillator.
SLOW mode: During this mode, both the system clocks and the System Controller
clock are driven by the crystal oscillator. If NORMAL mode is selected, the system goes
into the "PLL control" transition state. If neither the SLOW nor the NORMAL mode
control bits are set, the system goes into the "Switch from XTAL" transition state.
NORMAL mode: In NORMAL mode, both the system clocks and the System Controller
clock are driven by the PLL output. If the NORMAL mode control bit is not set, then the
system goes into the "Switch from PLL" transition state.
2.23.2 Clock and reset system
The clock system is a fully programmable block that generates all the clocks necessary to
the chip.
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The default operating clock frequencies are:
Clock @ 333 MHz for the CPU.
Clock @ 166 MHz for AHB bus and AHB peripherals.
Clock @ 83 MHz for, APB bus and APB peripherals.
Clock @ 333 MHz for DDR memory interface.
The default values give the maximum allowed clock frequencies. The clock frequencies are
fully programmable through dedicated registers.
The clock system consists of 2 main parts: a multi clock generator block and two internal
PLLs.
The multi clock generator block, takes a reference signal (which is usually delivered by the
PLL), generates all clocks for the IPs of SPEAr320 according to dedicated programmable
registers.
Each PLL uses an oscillator input of 24 MHz to generate a clock signal at a frequency
corresponding at the highest of the group. This is the reference signal used by the multi
clock generator block to obtain all the other requested clocks for the group. Its main feature
is electromagnetic interference reduction capability.
The user can set up the PLL in order to modulate the VCO with a triangular wave. The
resulting signal has a spectrum (and power) spread over a small programmable range of
frequencies centered on F0 (the VCO frequency), obtaining minimum electromagnetic
emissions. This method replaces all the other traditional methods of EMI reduction, such as
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Architecture overview
SPEAr320
filtering, ferrite beads, chokes, adding power layers and ground planes to PCBs, metal
shielding and so on. This gives the customer appreciable cost savings.
In sleep mode the SPEAr320 runs with the PLL disabled so the available frequency is 24
MHz or a sub-multiple (/2, /4, /8).
2.24
Vectored interrupt controller (VIC)
The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in
response to peripheral interrupts. There are 32 interrupt lines and the VIC uses a separate
bit position for each interrupt source. Software controls each request line to generate
software interrupts.
2.25
General purpose timers
SPEAr320 provides 6 general purpose timers (GPTs) acting as APB slaves.
Each GPT consists of 2 channels, each one made up of a programmable 16-bit counter and
a dedicated 8-bit timer clock prescaler. The programmable 8-bit prescaler performs a clock
division by 1 up to 256, and different input frequencies can be chosen through configuration
registers (a frequency range from 3.96 Hz to 48 MHz can be synthesized).
Two different modes of operation are available :
Auto-reload mode, an interrupt source is activated, the counter is automatically cleared
and then it restarts incrementing.
Single-shot mode, an interrupt source is activated, the counter is stopped and the GPT
is disabled.
2.26 PWM timers
SPEAr320 provides 4 PWM timers.
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Main features:
Prescaler to define the input clock frequency to each timer
Programmable duty cycle from 0% to 100%
Programmable pulse length
APB slave interface for register programming
2.27
Watchdog timer
The ARM watchdog module consists of a 32-bit down counter with a programmable timeout
interval that has the capability to generate an interrupt and a reset signal on timing out. The
watchdog module is intended to be used to apply a reset to a system in the event of a
software failure.
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SPEAr320
Architecture overview
2.28
RTC oscillator
The RTC provides a 1-second resolution clock. This keeps time when the system is inactive
and can be used to wake the system up when a programmed alarm time is reached. It has a
clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a
secured time update.
Main features:
Tme-of-day clock in 24 hour mode
Calendar
Alarm capability
Isolation mode, allowing RTC to work even if power is not supplied to the rest of the
device.
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Pin description
3 Pin description
SPEAr320
The following tables describe the pinout of the SPEAr320 listed by functional block.
List of abbreviations:
PU = Pull Up
PD = Pull Down
3.1 Required external components
1. DDR_COMP_1V8: place an external 121 kΩ resistor between ball P4 and ball R4
2. USB_TX_RTUNE: connect an external 43.2 kΩ pull-down resistor to ball K5
3. DIGITAL_REXT: place an external 121 kΩ resistor between ball G4 and ball F4.
3.2 Dedicated pins
Table 2. Master clock, RTC, Reset and 3.3 V comparator pin descriptions
Group
Signal name
Ball Direction
Function
Pin type
Master Clock
RTC
MCLK_XI
MCLK_XO
RTC_XI
RTC_XO
P1
P2
E2
E1
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Reset
MRESET#
M17
3.3 V Comp.
DIGITAL_REXT
DIGITAL_GND_R
EX
G4
F4
Input
Output
Input
Output
Input
Output
Power
24 MHz (typical)
crystal in
24 MHz (typical)
crystal out
32 kHz crystal in
32 kHz crystal out
Main Reset
Configuration
Oscillator 2.5 V
capable
Oscillator 1V
capable
TTL Schmitt
trigger input
buffer, 3.3 V
tolerant, PU
Analog, 3.3 V
capable
Power
Power
Table 3. Power supply pin description
Group
Signal name
Ball Value
DIGITAL
GROUND
ANALOG
GROUND
GND
AGND
G6 G7 G8 G9 G10 G11 H6 H7 H8 H9 H10 H11 J6
J7 J8 J9 J10 J11 K6 K7 K8 K9 K10 K11 L6 L7 L8
L9 L10 M8 M9 M10
0V
F2, G1, J2, L1, L3, L5, N2, N4, P3, R3, N12
0V
I/O
VDD3v3
F5 F6 F7 F10 F11 F12 G5 J12 K12 L12 M12 3.3 V
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SPEAr320
Pin description
Table 3. Power supply pin description
Group
Signal name
Ball
CORE
VDD
F8 F9 G12 H5 H12 J5 L11 M6 M7 M11
USB
HOST0 PHY
HOST0_VDDbc
HOST0_VDDb3
L2
K4
USB
HOST1 PHY
HOST1_VDDbc
HOST1_VDDb3
K3
J1
USB DEVICE
PHY
DEVICE_VDDbc
DEVICE_VDDb3
HOST_VDDbs
N1
N3
M3
OSCI (master
clock)
MCLK_VDD
MCLK_VDD2v5
R1
R2
PLL1
DITH1_AVDD
G2
PLL2
DITH2_AVDD
M4
DDR I/O
SSTL_VDDe
M5 N5 N6 N7 N8 N9 N10 N11
ADC
OSCI RTC
ADC_AVDD
RTC_VDD
N13
F1
Value
1.2 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
1.2 V
1.2 V
2.5 V
2.5 V
2.5 V
1.8 V
2.5 V
1.5 V
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Pin description
SPEAr320
Table 4. Debug pin descriptions
Group
Signal name
Ball
TEST_0
K16
TEST_1
TEST_2
K15
K14
TEST_3
K13
TEST_4
J15
BOOT_SEL
J14
DEBUG
nTRST
L16
TDO
TCK
TDI
TMS
L15
L17
L14
L13
Direction
Function
Pin type
Input
Test configuration
ports. For
functional mode,
they have to be
set to zero.
TTL input buffer,
3.3 V tolerant, PD
Input
Output
Input
Input
Input
Test reset input
TTL Schmitt
trigger input
buffer, 3.3 V
tolerant, PU
Test data output
TTL output buffer,
3.3 V capable 4
mA
Test clock
Test data input
Test mode select
TTL Schmitt
trigger input
buffer, 3.3 V
tolerant, PU
Table 5. Serial memory interface (SMI) pin description
Group
Signal name
Ball Direction
Function
Pin type
SMI_DATAIN
M13
Input
Serial Flash input TTL Input Buffer
data 3.3 V tolerant, PU
SMI
SMI_DATAOUT M14
Output
Serial Flash
output data
TTL output buffer
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SMI_CLK
N17
I/O Serial Flash clock 3.3 V capable 4
SMI_CS_0
SMI_CS_1
M15
M16
Output
Serial Flash chip
select
mA
Table 6. USB pin descriptions
Group
Signal name
Ball
DEV_DP
M1
DEV_DM
M2
USB DEV
DEV_VBUS
HOST1_DP
HOST1_DM
G3
H1
H2
Direction
I/O
Input
I/O
Function
Pin type
USB Device D+
USB Device D-
Bidirectional
analog buffer 5 V
tolerant
USB Device
VBUS
TTL input buffer
3.3 V tolerant, PD
USB HOST1 D+
USB HOST1 D-
Bidirectional
analog buffer 5 V
tolerant
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SPEAr320
Pin description
Table 6. USB pin descriptions (continued)
Group
Signal name
Ball Direction
HOST1_VBUS
H3
Output
HOST1_OVRC
USB HOST
HOST0_DP
HOST0_DM
HOST0_VBUS
J4
K1
K2
J3
Input
I/O
Output
HOST0_OVRC
USB_TXRTUNE
USB_ANALOG_T
EST
H4
K5
L4
Input
Output
Output
Function
Pin type
USBHOST1
VBUS
TTL output buffer
3.3 V capable,
4 mA
USB Host1
Over-Current
TTL input buffer
3.3 V tolerant, PD
USB HOST0 D+
USB HOST0 D-
Bidirectional
analog buffer 5 V
tolerant
USB HOST0
VBUS
TTL output buffer
3.3 V capable,
4 mA
USB Host0
Over-current
TTL Input Buffer
3.3 V tolerant, PD
Reference resistor
Analog
Analog Test
Output
Analog
Table 7. ADC pin description
Group
Signal name
Ball
AIN_0
AIN_1
AIN_2
N16
N15
P17
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ADC
AIN_3
AIN_4
AIN_5
AIN_6
AIN_7
P16
P15
R17
R16
R15
ADC_VREFN
N14
ADC_VREFP
P14
Direction
Function
Pin type
Input
ADC analog input
channel
Analog buffer
2.5 V tolerant
ADC negative
voltage reference
ADC positive
voltage reference
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Pin description
SPEAr320
Table 8. DDR pin description
Group
Signal name
Ball
DDR_ADD_0
DDR_ADD_1
DDR_ADD_2
DDR_ADD_3
DDR_ADD_4
DDR_ADD_5
DDR_ADD_6
DDR_ADD_7
DDR_ADD_8
DDR_ADD_9
DDR_ADD_10
T2
T1
U1
U2
U3
U4
U5
T5
R5
P5
P6
DDR
DDR_ADD_11
DDR_ADD_12
DDR_ADD_13
DDR_ADD_14
DDR_BA_0
DDR_BA_1
R6
T6
U6
R7
P7
P8
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DDR_BA_2
DDR_RAS
DDR_CAS
DDR_WE
DDR_CLKEN
DDR_CLK_P
R8
U8
T8
T7
U7
T9
DDR_CLK_N
U9
Direction
Function
Pin type
Output
Address Line
SSTL_2/SSTL_18
Output
Bank select
Output
Output
Output
Output
Output
Row Add. Strobe
Col. Add. Strobe
Write enable
Clock enable
Differential clock
Differential
SSTL_2/SSTL_18
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SPEAr320
Pin description
Table 8.
Group
DDR
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DDR pin description (continued)
Signal name
Ball Direction
DDR_CS_0
DDR_CS_1
DDR_ODT_0
DDR_ODT_1
P9
R9
T3
T4
Output
I/O
DDR_DATA_0
DDR_DATA_1
DDR_DATA_2
DDR_DATA_3
DDR_DATA_4
DDR_DATA_5
DDR_DATA_6
DDR_DATA_7
DDR_DQS_0
DDR_nDQS_0
DDR_DM_0
DDR_GATE_0
DDR_DATA_8
DDR_DATA_9
DDR_DATA_10
DDR_DATA_11
DDR_DATA_12
DDR_DATA_13
DDR_DATA_14
DDR_DATA_15
DDR_DQS_1
DDR_nDQS_1
DDR_DM_1
DDR_GATE_1
DDR_VREF
DDR_MEM_COM
P_GND
DDR_MEM_COM
P_REXT
P11
R11
T11
U11
T12
R12
P12
P13
U10
T10
U12
R10
T17
T16
U17
U16
U14
U13
T13
R13
U15
T15
T14
R14
P10
R4
P4
I/O
Output
Output
I/O
I/O
I/O
I/O
Input
Power
Power
DDR2_EN J13 Input
Function
Chip Select
On-Die
Termination
Enable lines
Pin type
SSTL_2/SSTL_18
Data Lines
(Lower byte)
Lower Data
Strobe
Differential
SSTL_2/SSTL_18
Lower Data Mask
Lower Gate Open
Data Lines
(Upper byte)
SSTL_2/SSTL_18
Upper Data
Strobe
Differential
SSTL_2/SSTL_18
Upper Data Mask
SSTL_2/SSTL_18
Upper Gate Open
Reference Voltage
Analog
Return for Ext.
Resistors
Power
Ext. Resistor
Analog
Configuration
TTL Input Buffer
3.3 V Tolerant, PU
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Pin description
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3.3
Table 9.
Shared I/O pins (PL_GPIOs)
The 98 PL_GPIO and 4 PL_CLK pins have the following characteristics:
– Output buffer: TTL 3.3 V capable up to 10 mA
– Input buffer: TTL, 3.3 V tolerant, selectable internal pull up/pull down (PU/PD)
Configuration modes
The following modes can be selected by programming the RAS control registers.
Mode 1: SMII automation networking mode
Mode 2: MII automation networking mode
Mode 3: Expanded automation mode
Mode 4: Printer mode
The peripherals available are shown in Table 9: Available peripherals in each configuration
mode. Details of each PL_GPIO pin are given in Table 10: PL_GPIO pin description on
page 29
Mode 1 is the default mode for SPEAr320.
Boot pins
The status of the boot pins is read at startup by the BootROM. Refer to the description of the
Boot register in the SPEAr320 user manual.
Alternate functions
Other peripheral functions are listed in the Alternate Functions column of Table 10:
PL_GPIO pin description and can be individually enabled/disabled via RAS control register
1. Refer to the user manual for the register descriptions.
Available peripherals in each configuration mode
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1 8-bit
8 2 SMII 1 1 2
4 1 1(1) 3(2) 3(3)
2 8-bit
8 2 MII(4)
2 4 1 1(1) 3(2) 3(3)
3 16-bit 16-bit
1 SMII
2 3 2(1) 1(2) 3(3)
4 8-bit
8 2 SMII
14
2(2) 3(3)
1. Assuming I2C0 alternate functions are enabled on PL5 and PL4 (see Table 10)
2. Assuming that SSP0alternate functions are enabled on PL9 thru PL6 (see Table 10)
3. Assuming that UART0 alternate functions are enabled on PL3 and PL3 and optionally on PL42-37 if hardware flow control is
used (see Table 10)
4. Assuming that MII0 alternate functions are enabled on PL27 thru 10 (see Table 10)
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SPEAr320
Pin description
Table 10. PL_GPIO pin description
PL /
pin
number
Alternate
function
(enabled
by RAS
register 1)
Configuration mode (enabled by RAS register 2)
12
3
4
Function in Function in
RAS GPIO debug trace
mode mode (ETM)
97/H16
96/H15
95/H14
94/H13
93/G17
92/G16
91/G15
90/G14
89/F17
88/F16
87/G13
86/E17
85/F15
84/D17
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82/E15
81/C17
80/D16
79/F14
78/D15
77/B17
76/F13
75/E14
74/C16
CLD0
CLD1
CLD2
CLD3
CLD4
CLD5
CLD6
CLD7
CLD8
CLD9
CLD10
CLD11
CLD12
CLD13
CLD14
CLD15
CLD16
CLD17
CLD18
CLD19
CLD20
CLD21
CLD22
CLD23
MII1_TXCLK
MII1_TXD0
MII1_TXD1
MII1_TXD2
MII1_TXD3
MII1_TXEN
MII1_TXER
MII1_RXCLK
MII1_RXDV
MII1_RXER
MII1_RXD0
MII1_RXD1
MII1_RXD2
MII1_RXD3
MII1_COL
MII1_CRS
MII1_MDIO
MII1_MDC
0
0
0
0
0
0
EMI_A0
EMI_A1
EMI_A2
EMI_A3
EMI_A4
EMI_A5
EMI_A6
EMI_A7
EMI_A8
EMI_A9
EMI_A10
EMI_A11
EMI_A12
EMI_A13
EMI_A14
EMI_A15
EMI_A16
EMI_A17
EMI_A18
EMI_A19
EMI_A20
EMI_A21
EMI_A22
EMI_A23
0
0
0
0
0
0
0
0
0
0
0
0
SPP_DATA0
SPP_DATA1
SPP_DATA2
SPP_DATA3
SPP_DATA4
SPP_DATA5
SPP_DATA6
SPP_DATA7
SPP_STRBn
SPP_ACKn
SPP_BUSY
SPP_PERROR
GPIO_97
GPIO_96
GPIO_95
GPIO_94
GPIO_93
GPIO_92
GPIO_91
GPIO_90
GPIO_89
GPIO_88
GPIO_87
GPIO_86
GPIO_85
GPIO_84
GPIO_83
GPIO_82
GPIO_81
GPIO_80
GPIO_79
GPIO_78
GPIO_77
GPIO_76
GPIO_75
GPIO_74
ARM_TRACE_C
LK
ARM_TRACE_P
KTA[0]
ARM_TRACE_P
KTA[1]
ARM_TRACE_P
KTA[2]
ARM_TRACE_P
KTA[3]
ARM_TRACE_P
KTB[0]
ARM_TRACE_P
KTB[1]
ARM_TRACE_P
KTB[2]
ARM_TRACE_P
KTB[3]
ARM_TRACE_S
YNCA
ARM_TRACE_S
YNCB
ARM_PIPESTAT
A[0]
ARM_PIPESTAT
A[1]
ARM_PIPESTAT
A[2]
ARM_PIPESTAT
B[0]
ARM_PIPESTAT
B[1]
ARM_PIPESTAT
B[2]
ARM_TRACE_P
KTA[4]
ARM_TRACE_P
KTA[5]
ARM_TRACE_P
KTA[6]
ARM_TRACE_P
KTA[7]
ARM_TRACE_P
KTB[4]
ARM_TRACE_P
KTB[5]
ARM_TRACE_P
KTB[6]
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Pin description
SPEAr320
Table 10. PL_GPIO pin description (continued)
PL /
pin
number
Alternate
function
(enabled
by RAS
register 1)
Configuration mode (enabled by RAS register 2)
12
3
4
Function in Function in
RAS GPIO debug trace
mode mode (ETM)
73/A17
CLAC
0
EMI_D8/
FSMC_D8
SPP_SELECT
72/B16
CLFP
0
EMI_D9/
FSMC_D9
SPP_AUTOFDn
71/D14
CLLP
0
EMI_D10/
FSMC_D10
SPP_FAULTn
70/C15
CLLE
0
EMI_D11/
FSMC_D11
SPP_INITn
69/A16
CLPOWER
0
EMI_WAIT
SPP_SELINn
68/B15
FSMC_D0
FSMC_D0
EMI_D0/
FSMC_D0
FSMC_D0
67/C14
FSMC_D1
FSMC_D1
EMI_D1/
FSMC_D0
FSMC_D1
66/E13
FSMC_D2
FSMC_D2
EMI_D2/
FSMC_D2
FSMC_D2
65/B14
FSMC_D3
FSMC_D3
EMI_D3/
FSMC_D3
FSMC_D3
64/D13
FSMC_D4
FSMC_D4
EMI_D4/
FSMC_D4
FSMC_D4
63/C13
FSMC_D5
FSMC_D5
EMI_D5/
FSMC_D5
FSMC_D5
62/A15 H7
FSMC_D6
FSMC_D6
EMI_D6/
FSMC_D6
FSMC_D6
61/E12 H6
FSMC_D7
FSMC_D7
EMI_D7/
FSMC_D7
FSMC_D7
60/A14 H5
FSMC_ADDR_
LE
FSMC_ADDR_
LE
FSMC_ADDR_LE
FSMC_ADDR_L
E
59/B13 H4
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58/D12 H3
FSMC_WE
FSMC_RE
FSMC_WE
FSMC_RE
EMI_WE/
FSMC_WE
EMI_OE/
FSMC_RE
FSMC_WE
FSMC_RE
57/E11 H2
FSMC_CMD_
LE
FSMC_CMD_
LE
FSMC_CMD_LE FSMC_CMD_LE
56/C12 H1
FSMC_RDY
/BSY
FSMC_RDY/
BSY
FSMC_RDY/BSY
FSMC_RDY/
BSY
55/A13 H0
FSMC_CS0 FSMC_CS0
EMI_CE0/
FSMC_CS0
FSMC_CS0
54/E10 B3
FSMC_CS1 FSMC_CS1
EMI_CE1/
FSMC_CS1
FSMC_CS1
53/D11 B2
FSMC_CS2 FSMC_CS2
EMI_CE2/
FSMC_CS2
FSMC_CS2
52/B12 B1
FSMC_CS3 FSMC_CS3
EMI_CE_3/
FSMC_CS3
FSMC_CS3
51/D10 B0
SD_CD
SD_CD
EMI_BYTEN0
SD_CD
50/A12
TMR_CPTR4 SD_DAT7
SD_DAT7
EMI_BYTEN1
SD_DAT7
49/C11
TMR_CPTR3 SD_DAT6
SD_DAT6
EMI_D12/
FSMC_D12
SD_DAT6
GPIO_73
GPIO_72
GPIO_71
GPIO_70
GPIO_69
GPIO_68
GPIO_67
GPIO_66
GPIO_65
GPIO_64
GPIO_63
GPIO_62
GPIO_61
GPIO_60
GPIO_59
GPIO_58
GPIO_57
GPIO_56
GPIO_55
GPIO_54
GPIO_53
GPIO_52
GPIO_51
GPIO_50
GPIO_49
ARM_TRACE_P
KTB[7]
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