AD5422 (Analog Devices)
(AD5412 / AD5422) Current Source & Voltage Output DAC

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Data Sheet
Single Channel, 12-/16-Bit, Serial Input, Current
Source and Voltage Output DACs, HART Connectivity
AD5412/AD5422
FEATURES
12-/16-bit resolution and monotonicity
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or
0 mA to 24 mA
±0.01% FSR typical total unadjusted error (TUE)
±3 ppm FSR/°C output drift
Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V
10% overrange
±0.01% FSR typical TUE
±2 ppm FSR/°C output drift
Flexible serial digital interface
On-chip output fault detection
On-chip reference: 10 ppm/°C maximum
Optional regulated DVCC output
Asynchronous clear function
Power supply range
AVDD: 10.8 V to 40 V
AVSS: −26.4 V to −3 V/0 V
Current loop compliance voltage: AVDD – 2.5 V
Temperature range: −40°C to +105°C
TSSOP and LFCSP packages
APPLICATIONS
Process controls
Actuator controls
PLC
HART network connectivity (LFCSP package only)
GENERAL DESCRIPTION
The AD5412/AD5422 are low cost, precision, fully integrated
12-/16-bit digital-to-analog converters (DAC) offering a pro-
grammable current source and programmable voltage output
designed to meet the requirements of industrial process control
applications.
The output current range is programmable at 4 mA to 20 mA,
0 mA to 20 mA, or an overrange function of 0 mA to 24 mA.
The LFCSP version of this product has a CAP2 pin so that the
HART signals can be coupled onto the current output of the
AD5412/AD5422.
Voltage output is provided from a separate pin that can be
configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V
output ranges; an overrange of 10% is available on all ranges.
Analog outputs are short and open-circuit protected and can
drive capacitive loads of 1 µF.
The device operates with an AVDD power supply range from 10.8 V
to 40 V. Current loop compliance voltage is 0 V to AVDD − 2.5 V.
The flexible serial interface is SPI- and MICROWIRE™-compatible
and can be operated in 3-wire mode to minimize the digital
isolation required in isolated applications.
The device also includes a power-on-reset function, ensuring
that the device powers up in a known state. The part also includes
an asynchronous clear pin (CLEAR) that sets the outputs to
zero-scale/midscale voltage output or the low end of the
selected current range.
The total output error is typically ±0.01% in current mode and
±0.01% in voltage mode.
Table 1. Pin-Compatible Devices
Part No. Description
AD5410 Single channel, 12-bit, serial input current source DAC
AD5420 Single channel, 16-bit, serial input current source DAC
COMPANION PRODUCTS
HART Modem: AD5700, AD5700-1
Rev. M
Document Feedback
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Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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AD5422 (Analog Devices)
(AD5412 / AD5422) Current Source & Voltage Output DAC

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AD5412/AD5422
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Companion Products ....................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
AC Performance Characteristics .............................................. 10
Timing Characteristics .............................................................. 10
Absolute Maximum Ratings.......................................................... 13
ESD Caution................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 16
General......................................................................................... 16
Voltage Output............................................................................ 18
Current Output ........................................................................... 23
Terminology .................................................................................... 27
Theory of Operation ...................................................................... 29
Architecture................................................................................. 29
Serial Interface ............................................................................ 30
Power-On State ........................................................................... 31
Data Register ............................................................................... 33
Control Register.......................................................................... 33
Reset Register.............................................................................. 34
Status Register............................................................................. 34
AD5412/AD5422 Features ............................................................ 35
Data Sheet
Fault Alert.................................................................................... 35
Voltage Output Short Circuit Protection ................................ 35
Voltage Output Overrange ........................................................ 35
Voltage Output Force-Sense ..................................................... 35
Asynchronous Clear (CLEAR) ................................................. 35
Internal Reference ...................................................................... 35
External Current Setting Resistor ............................................ 35
Digital Power Supply.................................................................. 36
External Boost Function............................................................ 36
External Compensation Capacitor........................................... 36
HART Communication............................................................. 36
Digital Slew Rate Control.......................................................... 36
IOUT Filtering Capacitors (LFCSP Package)............................. 37
Applications Information .............................................................. 39
Voltage and Current Output Ranges on the Same Terminal 39
Driving Inductive Loads............................................................ 39
Transient Voltage Protection .................................................... 39
Galvanically Isolated Interface ................................................. 39
Microprocessor Interfacing....................................................... 39
Layout Guidelines....................................................................... 40
Thermal and Supply Considerations ....................................... 40
Industrial Analog Output Module ........................................... 41
Industrial HART Capable Analog Output Application ........ 41
Outline Dimensions ....................................................................... 43
Ordering Guide .......................................................................... 44
Rev. M | Page 2 of 44


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(AD5412 / AD5422) Current Source & Voltage Output DAC

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Data Sheet
REVISION HISTORY
7/2016—Rev. L to Rev. M
Changed −40°C to +85°C to −40°C to +105°C and CP-40-1 to
CP-40-9........................................................................... Throughout
Changes to Table 2 ............................................................................5
Added Table 3; Renumbered Sequentially .....................................9
Changes to Figure 6.........................................................................14
Changes to Thermal and Supply Conditions Section ................40
Updated Outline Dimensions........................................................43
Changes to Ordering Guide...........................................................44
7/2015—Rev. K to Rev. L
Change to IOUT to GND Parameter, Table 5 .................................11
Change to Voltage and Current Output Ranges on the Same
Terminal Section .............................................................................37
3/2015—Rev. J to Rev. K
Changes to Table 4 ............................................................................9
Changes to Table 6 ..........................................................................13
Changes to Power-On State Section .............................................29
10/2014—Rev. I to Rev. J
Changes to Power-On State Section .............................................29
Changes to Table 25 ........................................................................39
10/2013—Rev. H to Rev. I
Added Figure 34 and Figure 35; Renumbered Sequentially......18
Changes to Figure 78 ......................................................................37
Changes to Industrial Analog Output Module Section .............39
Changes to Industrial HART Capable Analog Output
Application Section.........................................................................39
6/2013—Rev. G to Rev. H
Change to REFOUT Pin, Table 6 ..................................................12
Changes to Voltage and Current Output Ranges on the Same
Terminal Section and Figure 75 ....................................................36
3/2013—Rev. F to Rev. G
Changed TSSOP_EP θJA from 42°C/W to 35°C/W, Changed
LFCSP θJA from 28°C/W to 33°C/W, and Added Endnote 2.....11
Added Figure 67 ..............................................................................30
Changes to REXT Description; Table 15......................................31
Changes to Table 21 ........................................................................33
Changes to Thermal and Supply Considerations Section .........38
Changes to Table 25 ........................................................................39
7/2012—Rev. E to Rev. F
Updated Outline Dimensions........................................................40
Changes to Ordering Guide...........................................................40
AD5412/AD5422
5/2012—Rev. D to Rev. E
Reorganized Layout ........................................................... Universal
Changes to Product Title..................................................................1
Changes to Features Section, Applications Section, and General
Description Section; Added Companion Products Section.............1
Changes to Figure 1 ..........................................................................3
Change to Offset Error Temperature Coefficient (TC)
Parameter, Table 1 .............................................................................4
Changes to Table 6 ..........................................................................12
Changes to Power-On State Section .............................................29
Added HART Communication Section and Figure 68,
Renumbered Sequentially ..............................................................33
Added Voltage and Current Output Ranges on the Same
Terminal Section and Figure 74 ....................................................36
Added Industrial HART Capable Analog Output Application
Section ..............................................................................................38
Added Figure 79 ..............................................................................39
11/2011—Rev. C to Rev. D
Changes to Table 15 ........................................................................29
3/2010—Rev. B to Rev. C
Changes to AVSS to GND Parameter in Table 5.........................10
2/2010—Rev. A to Rev. B
Changes to Thermal and Supply Considerations Section and
Table 25.............................................................................................36
8/2009—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................4
Changes to Table 3 ............................................................................7
Changes to Introduction to Table 4 ................................................8
Changes to Introduction to Table 5 and to Table 5 ....................10
Changes to Pin Configurations and Function Descriptions
Section, Added Figure 6, Renumbered Subsequent Figures .....11
Changes to Theory of Operation Section ....................................26
Changes to Architecture Section...................................................26
Changes to AD5412/AD5422 Features Section ..........................31
Added IOUT Filtering Capacitors (LFCSP Package) Section,
Including Figure 69 to Figure 72 and Table 24............................33
Changes to Thermal and Supply Considerations Section .........36
Updated Outline Dimensions........................................................38
Changes to Ordering Guide...........................................................39
5/2009—Revision 0: Initial Version
Rev. M | Page 3 of 44


AD5422 (Analog Devices)
(AD5412 / AD5422) Current Source & Voltage Output DAC

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AD5412/AD5422
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
DVCC
SELECT
DVCC
CLEAR
SELECT
CLEAR
LATCH
SCLK
SDIN
SDO
AD5412/AD5422
4.5V LDO
INPUT SHIFT
REGISTER
AND CONTROL
LOGIC
12/16
12-/16-BIT
DAC
POWER-ON
RESET
VREF
RANGE
SCALING
*CAP1 *CAP2
AVSS AVDD
R2 R3
RSET
REFOUT
*PINS ONLY ON LFCSP OPTION.
REFIN
GND
Figure 1.
CCOMP
BOOST
IOUT
FAULT
RSET
+VSENSE
VOUT
–VSENSE
Rev. M | Page 4 of 44


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Data Sheet
AD5412/AD5422
SPECIFICATIONS
AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
VOLTAGE OUTPUT
Output Voltage Ranges
Accuracy
Resolution
Total Unadjusted Error (TUE)
B Version
A Version
Relative Accuracy (INL)2
Differential Nonlinearity (DNL)
Bipolar Zero Error
Bipolar Zero Error Temperature
Coefficient (TC)3
Zero-Scale Error
Zero-Scale Error TC3
Offset Error
Offset Error TC3
Gain Error
Gain Error TC3
Full-Scale Error
Full-Scale Error TC3
Min
0
0
−5
−10
16
12
−0.1
−0.05
−0.3
−0.1
−0.008
−0.032
−1
−1
−6
−9
−1.5
−5
−8
−3.5
−4
−6
−1.5
−0.07
−0.05
−0.07
−0.05
Typ Max
5
10
+5
+10
±0.01
±0.05
±0.2
±3
+0.1
+0.05
+0.3
+0.1
+0.008
+0.032
+1
+1.3
+6
+9
+1.5
±0.3
±2
±0.2
±2
±0.004
±1
±3
±0.001
±1
±2
+5
+8
+3.5
+4
+6
+1.5
+0.07
+0.05
+0.07
+0.05
Unit Test Conditions/Comments
V
V
V
V
Output unloaded
Bits AD5422
Bits AD5412
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
LSB
LSB
mV
mV
mV
ppm FSR/°C
TA = 25°C
TA = −40°C to +85°C
TA = 25°C
AD5422
AD5412
TA = −40°C to +85°C, guaranteed monotonic
Guaranteed monotonic
TA = −40°C to +85°C, bipolar output range
Bipolar output range
TA = 25°C, bipolar output range
Bipolar output range
mV
mV
mV
ppm FSR/°C
mV
mV
mV
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
TA = −40°C to +85°C
TA = 25°C
TA = −40°C to +85°C, unipolar output range
Unipolar output range
TA = 25°C, unipolar output range
Unipolar output range
TA = 25°C
TA = −40°C to +85°C
TA = 25°C
TA = −40°C to +85°C
Rev. M | Page 5 of 44


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(AD5412 / AD5422) Current Source & Voltage Output DAC

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AD5412/AD5422
Parameter1
OUTPUT CHARACTERISTICS3
Headroom
Output Voltage Drift vs. Time
Short-Circuit Current
Load
Capacitive Load Stability
RLOAD = ∞
RLOAD = 1 kΩ
RLOAD = ∞
DC Output Impedance
Power-On Time
DC PSRR
CURRENT OUTPUT
Output Current Ranges
Accuracy (Internal RSET)
Resolution
TUE
B Version
A Version
INL4
DNL
Offset Error
Offset Error TC3
Gain Error
Gain TC3
Full-Scale Error
Full-Scale TC3
Data Sheet
Min
1
0
0
4
16
12
−0.3
−0.13
−0.5
−0.3
−0.024
−0.032
−1
−1
−0.27
−0.40
−0.12
−0.18
−0.20
−0.03
−0.22
−0.24
−0.06
−0.2
−0.40
−0.1
Typ Max
0.5 0.8
90
20
20
5
1
0.3
10
90 130
3 12
24
20
20
±0.08
±0.15
±0.08
±16
±28
±0.006
±0.006
±10
±21
±0.08
±6
±13
+0.3
+0.13
+0.5
+0.3
+0.024
+0.032
+1
+1.3
+0.27
+0.40
+0.12
+0.18
+0.20
+0.03
+0.22
+0.24
+0.06
+0.2
+0.40
+0.1
Unit Test Conditions/Comments
V
ppm FSR
mA
kΩ
nF
nF
µF
µs
µV/V
µV/V
Output unloaded
Drift after 1000 hours, TA = 125°C
TA = 25°C
External compensation capacitor of 4 nF
connected
Output unloaded
mA
mA
mA
Bits AD5422
Bits AD5412
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
LSB
LSB
% FSR
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
% FSR
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
TA = 25°C
TA = −40°C to +85°C
TA = 25°C
AD5422
AD5412
TA = −40°C to +85°C, guaranteed monotonic
Guaranteed monotonic
TA = −40°C to +85°C
TA = 25°C
TA = −40°C to +85°C
TA = −40°C to +85°C, AD5422
AD5422
AD5422, TA = 25°C
TA = −40°C to +85°C, AD5412
AD5412
AD5412, TA = 25°C
TA = −40°C to +85°C
TA = −40°C to +85°C
TA = 25°C
TA = −40°C to +85°C
Rev. M | Page 6 of 44


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(AD5412 / AD5422) Current Source & Voltage Output DAC

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Data Sheet
AD5412/AD5422
Parameter1
Accuracy (External RSET)
Resolution
TUE
B Version
A Version
INL4
DNL
Offset Error
Offset Error TC3
Gain Error
Gain TC3
Full-Scale Error
Full-Scale Error TC3
OUTPUT CHARACTERISTICS3
Current Loop Compliance Voltage
Output Current Drift vs. Time
Min
16
12
−0.15
−0.06
−0.3
−0.1
−0.012
−0.032
−1
−1
−0.1
−0.12
−0.03
−0.08
−0.15
−0.05
−0.15
−0.06
0
Resistive Load
Inductive Load
DC PSRR
Output Impedance
Output Current Leakage When Output
Disabled
REFERENCE INPUT/OUTPUT
Reference Input3
Reference Input Voltage
DC Input Impedance
Reference Output
Output Voltage
Reference TC3, 5
Output Noise (0.1 Hz to 10 Hz)3
Noise Spectral Density3
Output Voltage Drift vs. Time3
Capacitive Load3
Load Current3
Short-Circuit Current3
Load Regulation3
4.95
27
4.995
Typ Max
Unit
Test Conditions/Comments
Bits AD5422
Bits AD5412
±0.01
±0.02
±0.006
±3
±5
±0.003
±4
±0.01
±7
±9
+0.15
+0.06
+0.3
+0.1
+0.012
+0.032
+1
+1.3
+0.1
+0.12
+0.03
+0.08
+0.15
+0.05
+0.15
+0.06
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
LSB
LSB
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
% FSR
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
TA = 25°C
TA = −40°C to +85°C
TA = 25°C
AD5422
AD5412
TA = −40°C to +85°C, guaranteed monotonic
Guaranteed monotonic
TA = −40°C to +85°C
TA = 25°C
TA = −40°C to +85°C
TA = −40°C to +85°C
TA = 25°C
TA = 25°C
TA = −40°C to +85°C
AVDD − 2.5 V
Drift after 1000 hours, TA = 125°C
50
ppm FSR
Internal RSET
20
ppm FSR
External RSET
1200
50 mH TA = 25 °C
1 µA/V
50 MΩ
60 pA
5 5.05
40
5 5.005
1.8 10
10
100
50
600
5
7
95
V
kΩ
ppm/°C
µV p-p
nV/√Hz
ppm
nF
mA
mA
ppm/mA
For specified performance
TA = 25°C
At 10 kHz
Drift after 1000 hours, TA = 125°C
Rev. M | Page 7 of 44


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(AD5412 / AD5422) Current Source & Voltage Output DAC

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AD5412/AD5422
Data Sheet
Parameter1
DIGITAL INPUTS3
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current
Pin Capacitance
DIGITAL OUTPUTS3
SDO
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output Capacitance
FAULT
Output Low Voltage, VOL
Output Low Voltage, VOL
Output High Voltage, VOH
POWER REQUIREMENTS
AVDD
AVSS
|AVSS| + AVDD
DVCC
Input Voltage
Output Voltage
Output Load Current3
Short-Circuit Current3
AIDD
AISS
DICC
Power Dissipation
Min
2
−1
DVCC − 0.5
−1
3.6
10.8
−26.4
10.8
2.7
Typ
10
5
0.6
4.5
5
20
2.5
3.4
3.9
0.24
0.5
1.1
128
120
Max
0.8
+1
0.4
+1
0.4
40
0
52.8
5.5
3
4
4.4
0.3
0.6
1.4
1
Unit
V
V
µA
pF
V
V
µA
pF
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
Test Conditions/Comments
JEDEC compliant
Per pin
Per pin
Sinking 200 µA
Sourcing 200 µA
10 kΩ pull-up resistor to DVCC
At 2.5 mA
10 kΩ pull-up resistor to DVCC
Internal supply disabled
DVCC, which can be overdriven up to 5.5 V
Outputs unloaded
Outputs disabled
Current output enabled
Voltage output enabled
Outputs unloaded
Outputs disabled
Current output enabled
Voltage output enabled
VIH = DVCC, VIL = GND
AVDD = 40 V, AVSS = 0 V, outputs unloaded
AVDD = +24 V, AVSS = −24 V, outputs unloaded
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 When the AD5412/AD5422 is powered with AVSS = 0 V, INL for the 0 V to 5 V and 0 V to 10 V ranges is measured beginning from Code 256 for the AD5422 and Code 16
for the AD5412.
3 Guaranteed by design and characterization; not production tested.
4 For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412.
5 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +105°C.
Rev. M | Page 8 of 44


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Data Sheet
AD5412/AD5422
AVDD = 15 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. Voltage over range enabled.
Table 3.
Parameter1
VOLTAGE OUTPUT
Output Voltage Ranges
Accuracy
Resolution
Total Unadjusted Error (TUE)
B Version
Relative Accuracy (INL)2
Differential Nonlinearity (DNL)
Bipolar Zero Error
Bipolar Zero Error Temperature Coefficient (TC)3
Zero-Scale Error
Zero-Scale Error TC3
Offset Error
Offset Error TC3
Gain Error
Gain Error TC3
Full-Scale Error
Full-Scale Error TC3
Min
Typ Max
Unit
Test Conditions/Comments
0 5.5 V
0 11 V
−5.5 +5.5 V
−11 +11 V
Output unloaded
16 Bits AD5422
12 Bits AD5412
−0.13
−0.10
−0.008
−0.032
−1
−9
−18
−6
−0.13
−0.13
±0.01
±3
±2
±2
±3
±2
+0.13
+0.10
+0.008
+0.032
+1.3
+9
+18
+6
+0.13
+0.13
% FSR
% FSR
% FSR
% FSR
LSB
mV
ppm FSR/°C
mV
ppm FSR/°C
mV
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
TA = 25°C
AD5422
AD5412
Guaranteed monotonic
Bipolar output range
Bipolar output range
Unipolar output range
Unipolar output range
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 When the AD5412/AD5422 is powered with AVSS = 0 V, INL for the 0 V to 5.5 V and 0 V to 11 V ranges is measured beginning from Code 256 for the AD5422 and Code
16 for the AD5412.
3 Guaranteed by design and characterization; not production tested.
Rev. M | Page 9 of 44


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AD5412/AD5422
Data Sheet
AC PERFORMANCE CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = +5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Voltage Output
Output Voltage Settling Time
25 µs
10 V step to ±0.03 % FSR
32 µs 20 V step to ±0.03 % FSR
18 µs
5 V step to ±0.03 % FSR
8 µs 512 LSB step to ±0.03 % FSR (16-Bit LSB)
Slew Rate
0.8 V/µs
Power-On Glitch Energy
10 nV-sec
Digital-to-Analog Glitch Energy
10 nV-sec
Glitch Impulse Peak Amplitude
20 mV
Digital Feedthrough
1 nV-sec
Output Noise (0.1 Hz to 10 Hz Bandwidth)
0.1
LSB p-p 16-bit LSB
Output Noise (100 kHz Bandwidth)
200 µV rms
1/f Corner Frequency
1 kHz
Output Noise Spectral Density
150 nV/√Hz Measured at 10 kHz, midscale output, 10 V range
AC PSRR
−75 dB 200 mV 50 Hz/60 Hz sine wave superimposed on power
supply voltage
Current Output
Output Current Settling Time
10 µs 16 mA step to 0.1% FSR
40 µs 16 mA step to 0.1% FSR, L = 1 mH
AC PSRR
−75 dB 200 mV 50 Hz/60 Hz sine wave superimposed on power
supply voltage
1 Guaranteed by characterization, not production tested.
TIMING CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8V, GND = 0 V, REFIN = +5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter1, 2, 3
WRITE MODE
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX
33
13
13
13
5
5
5
40
20
5
Unit
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns min
ns min
µs max
Description
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
CLEAR pulse width
CLEAR activation time
Rev. M | Page 10 of 44


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Data Sheet
AD5412/AD5422
Parameter1, 2, 3
READBACK MODE
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
DAISY-CHAIN MODE
t21
t22
t23
t24
t25
t26
t27
t28
t29
Limit at TMIN, TMAX
90
40
40
13
40
5
5
40
35
35
90
40
40
13
40
5
5
40
35
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO4 = 15 pF)
LATCH rising edge to SDO tristate (CL SDO4 = 15 pF)
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO4 = 15 pF)
1 Guaranteed by characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 CL SDO = capacitive load on SDO output.
Timing Diagrams
SCLK
LATCH
SDIN
CLEAR
IOUT, VOUT
12
t2
t1
t3
24
t4
t5
t6
DB23
t7
t9
t8
DB0
t10
Figure 2. Write Mode Timing Diagram
Rev. M | Page 11 of 44


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AD5412/AD5422
Data Sheet
SCLK
12
t12
t11
t13
24
t14
t15
12
89
22 23 24
LATCH
SDIN
t16
DB23
t17
SDO
INPUT WORD SPECIFIES
REGISTER TO BE READ
UNDEFINED DATA
t18
DB0
DB23
XX
NOP CONDITION
X X DB15
DB0
t19
DB0
FIRST 8 BITS ARE
DON’T CARE BITS
Figure 3. Readback Mode Timing Diagram
SELECTED REGISTER
DATA CLOCKED OUT
t20
SCLK
LATCH
SDIN
SDO
12
24 25 26
t22
t21
t23
48
t24
t25
DB23
INPUT WORD FOR DAC N
DB0
t29
t26
DB23
t27
INPUT WORD FOR DAC N – 1
DB23
DB0 DB23
UNDEFINED
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Mode Timing Diagram
t28
DB0
DB0
t20
Rev. M | Page 12 of 44


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Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
80 mA do not cause SCR latch-up.
Table 6.
Parameter
AVDD to GND
AVSS to GND
AVDD to AVSS
DVCC to GND
Digital Inputs to GND
Digital Outputs to GND
REFIN/REFOUT to GND
VOUT to GND
IOUT to GND
Operating Temperature Range (TA)
Industrial1
Storage Temperature Range
Junction Temperature (TJ max)
24-Lead TSSOP_EP Package
θJA Thermal Impedance2
40-Lead LFCSP Package
θJA Thermal Impedance2
Power Dissipation
Lead Temperature
Soldering
ESD (Human Body Model)
Rating
−0.3 V to +48 V
+0.3 V to −28 V
−0.3 V to +60 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to +7 V
AVSS to AVDD
AVSS to AVDD
−40°C to +105°C
−65°C to +150°C
125°C
35°C/W
33°C/W
(TJ max – TA)/θJA
JEDEC industry standard
J-STD-020
2 kV
1 Power dissipated on chip must be derated to keep the junction temperature
below 125°C, assuming that the maximum power dissipation condition is
sourcing 24 mA into GND from IOUT with a 4 mA on-chip current.
2 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with thermal vias. See JEDEC JESD51.
AD5412/AD5422
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. M | Page 13 of 44


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AD5412/AD5422
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
AVSS 1
DVCC 2
FAULT 3
GND 4
CLEAR SELECT 5
CLEAR 6
LATCH 7
AD5412/
AD5422
TOP VIEW
(Not to Scale)
24 AVDD
23 –VSENSE
22 +VSENSE
21 VOUT
20 BOOST
19 IOUT
18 NC
SCLK 8
SDIN 9
SDO 10
17 CCOMP
16 DVCC SELECT
15 REFIN
GND 11
14 REFOUT
GND 12
13 RSET
NOTES
1. NC = NO CONNECT
2. THE PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT VOLTAGE RANGE
IS UNIPOLAR. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED
PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE AVSS PIN. IT IS
RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A
COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
Figure 5. TSSOP Pin Configuration
NC 1
FAULT 2
GND 3
CLEAR SELECT 4
CLEAR 5
LATCH 6
SCLK 7
SDIN 8
SDO 9
NC 10
AD5412/
AD5422
TOP VIEW
(Not to Scale)
30 NC
29 CAP2
28 CAP1
27 BOOST
26 IOUT
25 NC
24
23
22
DCNVCCOCCMPSELECT
21 NC
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT
VOLTAGE RANGE IS UNIPOLAR. THE EXPOSED PADDLE CAN BE LEFT
ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION
IS MADE AT THE AVSS PIN. IT IS RECOMMENDED THAT THE PADDLE BE
THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
Figure 6. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
1
14, 37
AVSS
2 39 DVCC
3 2 FAULT
4, 12 3, 15 GND
18 1, 10, 11, 19, 20, NC
21, 22, 25, 30,
31, 35, 38, 40
5 4 CLEAR
SELECT
6 5 CLEAR
7 6 LATCH
8 7 SCLK
98
10 9
SDIN
SDO
11
12, 13
GND
13 16 RSET
14 17 REFOUT
15 18 REFIN
Description
Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be
connected to 0 V if the output voltage range is unipolar.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. This pin can also be configured as a
4.5 V LDO output by leaving the DVCC SELECT pin floating.
Fault Alert. This pin is asserted low when an open circuit is detected in current mode or
an overtemperature is detected. Open drain output must be connected to a pull-up resistor.
These pins must be connected to 0 V.
No Connection. Do not connect to these pins.
Selects the voltage output clear value, either zero-scale or midscale code (see Table 22).
Active High Input. Asserting this pin sets the current output to the bottom of the selected
range or sets the voltage output to the user selected value (zero-scale or midscale).
Positive Edge Sensitive Latch. A rising LATCH edge parallel loads the input shift register
data into the DAC register, also updating the output.
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This
operates at clock speeds of up to 30 MHz.
Serial Data Input. Data must be valid on the rising edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback
mode. Data is valid on the rising edge of SCLK (see Figure 3 and Figure 4).
Ground Reference Pin.
An external, precision, low drift 15 kΩ current setting resistor can be connected to this
pin to improve the IOUT temperature drift performance. See the AD5412/AD5422 Features
section.
Internal Reference Voltage Output. REFOUT = 5 V ± 5 mV.
External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for a
specified performance.
Rev. M | Page 14 of 44


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Data Sheet
TSSOP
16
Pin No.
LFCSP
23
17 24
19
20
N/A
21
22
23
24
25 (EPAD)
26
27
28, 29
32
33
34
36
41 (EPAD)
AD5412/AD5422
Mnemonic
DVCC
SELECT
CCOMP
IOUT
BOOST
CAP1, CAP2
VOUT
+VSENSE
−VSENSE
AVDD
Exposed
paddle
Description
When connected to GND, this pin disables the internal supply, and an external supply
must be connected to the DVCC pin. Leave this pin unconnected to enable the internal
supply. In this case, it is recommended to connect a 0.1 μF capacitor between DVCC and
GND. See the AD5412/AD5422 Features section.
Optional compensation capacitor connection for the voltage output buffer. Connecting
a 4 nF capacitor between this pin and the VOUT pin allows the voltage output to drive up
to 1 µF. It should be noted that the addition of this capacitor reduces the bandwidth of
the output amplifier, increasing the settling time.
Current Output Pin.
Optional External Transistor Connection. Connecting an external transistor reduces the
power dissipated in the AD5412/AD5422. See the AD5412/AD5422 Features section.
Connection for Optional Output Filtering Capacitor. See the AD5412/AD5422 Features
section.
Buffered Analog Output Voltage. The output amplifier is capable of directly driving a
1 kΩ, 2000 pF load.
Sense connection for the positive voltage output load connection.
Sense connection for the negative voltage output load connection.
Positive Analog Supply Pin. Voltage ranges from 10.8 V to 60 V.
Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This paddle can be connected
to 0 V if the output voltage range is unipolar. The paddle can be left electrically unconnected
provided that a supply connection is made at the AVSS pin. It is recommended that the
paddle be thermally connected to a copper plane for enhanced thermal performance.
Rev. M | Page 15 of 44


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AD5412/AD5422
TYPICAL PERFORMANCE CHARACTERISTICS
GENERAL
900
800 TA = 25°C
700
600
DVCC = 5V
500
400
300
200
100 DVCC = 3V
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOGIC VOLTAGE (V)
Figure 7. DICC vs. Logic Input Voltage
5
AIDD
4
3
TA = 25°C
2 VOUT = 0V
OUTPUT UNLOADED
1
0
–1 AISS
–2
10 12 14 16 18 20 22 24 26 28
AVDD/|AVSS| (V)
Figure 8. AIDD/AISS vs. AVDD/|AVSS|
5.0
4.5
ITOAU=T
25°C
= 0mA
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10 15 20 25 30 35 40
AVDD (V)
Figure 9. AIDD vs. AVDD
Data Sheet
9
TA = 25°C
8
7
6
5
4
3
2
1
0
–21 –19 –17 –15 –13 –11 –9 –7 –5 –3 –1
LOAD CURRENT (mA)
Figure 10. DVCC Output Voltage vs. Load Current
1
AVDD
3
REFERENCE OUTPUT
1
CH1 2.00V
CH3 5.00V
M200µs
CH3
Figure 11. REFOUT Turn-on Transient
2.1V
1
CH1 2µV
M2.00s
LINE 1.8V
Figure 12. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)
Rev. M | Page 16 of 44


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Data Sheet
1
CH1 20µV
M2.00s
LINE 0V
Figure 13. REFOUT Output Noise (100 kHz Bandwidth)
5.003
5.002
50 DEVICES SHOWN
AVDD = 24V
5.001
5.000
4.999
4.998
4.997
–40
–20
0 20 40
TEMPERATURE (°C)
60
Figure 14. Reference Voltage vs. Temperature
80
AD5412/AD5422
45
40 AVDD = 24V
35
30
25
20
15
10
5
0
01
23456789
TEMPERATURE COEFFICIENT (ppm/°C)
10
Figure 15. Reference Temperature Coefficient Histogram
5.0005
5.0000
4.9995
TA = 25°C
AVDD = 24V
4.9990
4.9985
4.9980
4.9975
4.9970
4.9965
4.9960
4.9955
012345678
LOAD CURRENT (mA)
Figure 16. Reference Voltage vs. Load Current
9
Rev. M | Page 17 of 44


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AD5412/AD5422
VOLTAGE OUTPUT
0.0025
0.0020
0.0015
AVDD = +24V
AVSS = –24V
TA = 25°C
0.0010
0.0005
0
–0.0005
–0.0010
–0.0015
–0.0020
–0.0025
0
±10V RANGE
±5V RANGE
+5V RANGE
+10V RANGE
10,000 20,000 30,000 40,000 50,000 60,000
CODE
Figure 17. Integral Nonlinearity Error vs. DAC Code, Dual Supply
0.0025
0.0020
0.0015
+5V RANGE
+10V RANGE
AVDD = 24V
AVSS = 0V
TA = 25°C
0.0010
0.0005
0
–0.0005
–0.0010
–0.0015
–0.0020
–0.0025
0
10,000 20,000 30,000 40,000 50,000 60,000
CODE
Figure 18. Integral Nonlinearity Error vs. DAC Code, Single Supply
1.0
AVDD = +24V
0.8 AVSS = –24V
TA = 25°C
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
±10V RANGE
±5V RANGE
+10V RANGE
+5V RANGE
10,000 20,000 30,000 40,000 50,000 60,000
CODE
Figure 19. Differential Nonlinearity Error vs. DAC Code, Dual Supply
Data Sheet
1.0
0.8 +5V RANGE
+10V RANGE
0.6
AVDD = 24V
AVSS = 0V
TA = 25°C
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
10,000 20,000 30,000 40,000 50,000 60,000
CODE
Figure 20. Differential Nonlinearity Error vs. DAC Code, Single Supply
0.005
0.003
AVDD = +24V
AVSS = –24V
TA = 25°C
0.001
–0.001
–0.003
–0.005
–0.007
–0.009
0
±10V RANGE
±5V RANGE
+5V RANGE
+10V RANGE
10,000 20,000 30,000 40,000 50,000 60,000
CODE
Figure 21. Total Unadjusted Error vs. DAC Code, Dual Supply
0.030
0.025
0.020
+5V RANGE
+10V RANGE
AVDD = 24V
AVSS = 0V
TA = 25°C
0.015
0.010
0.005
0
–0.005
–0.010
0
10,000 20,000 30,000 40,000 50,000 60,000
CODE
Figure 22. Total Unadjusted Error vs. DAC Code, Single Supply
Rev. M | Page 18 of 44


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Data Sheet
0.0015
0.0010
AVDD = +24V
AVSS = –24V
0.0005
0
–0.0005
–0.0010
–0.0015
–40
+5V RANGE MAX INL
±5V RANGE MAX INL
+5V RANGE MIN INL
±5V RANGE MIN INL
+10V RANGE MAX INL
±10V RANGE MAX INL
+10V RANGE MIN INL
±10V RANGE MIN INL
–20 0 20 40 60 80
TEMPERATURE (°C)
Figure 23. Integral Nonlinearity Error vs. Temperature
1.0
AVDD = +24V
0.8 AVSS = –24V
ALL RANGES
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–40
–20
0 20 40
TEMPERATURE (°C)
60
80
Figure 24. Differential Nonlinearity Error vs. Temperature
0.015
0.010
0.005
0
AVDD = +24V
AVSS = –24V
OUTPUT UNLOADED
–0.005
–0.010
–0.015
–40
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
–20 0 20 40
TEMPERATURE (°C)
60
Figure 25. Total Unadjusted Error vs. Temperature
80
AD5412/AD5422
0.012
0.010
0.008
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
–40
AVDD = +24V
AVSS = –24V
OUTPUT UNLOADED
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
–20 0 20 40 60 80
TEMPERATURE (°C)
Figure 26. Full-Scale Error vs. Temperature
1.5
AVDD = +24V
AVSS = –24V
1.0 OUTPUT UNLOADED
+10V RANGE
0.5
0 +5V RANGE
–0.5
–1.0
–1.5
–40
–20 0 20 40 60
TEMPERATURE (°C)
Figure 27. Offset Error vs. Temperature
80
1.5
AVDD = +24V
AVSS = –24V
1.0 OUTPUT UNLOADED
+10V RANGE
0.5
0 +5V RANGE
–0.5
–1.0
–1.5
–40
–20
0 20 40
TEMPERATURE (°C)
60
Figure 28. Bipolar Zero Error vs. Temperature
80
Rev. M | Page 19 of 44


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AD5412/AD5422
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
–40
AVDD = +24V
AVSS = –24V
OUTPUT UNLOADED
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
–20 0 20 40 60
TEMPERATURE (°C)
Figure 29. Gain Error vs. Temperature
80
1.3
AVDD = +24V
AVSS = –24V
OUTPUT UNLOADED
0.8
0.3
–0.2
–0.7
–1.2
–40
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
–20 0 20 40
TEMPERATURE (°C)
60
Figure 30. Zero-Scale Error vs. Temperature
80
0.0015
0.0010
TA = 25°C
±10V RANGE
0.0005
0
–0.0005
–0.0010
–0.0015
10 12 14 16 18 20 22 24 26
AVDD/|AVSS| (V)
Figure 31. Integral Nonlinearity Error vs. AVDD/|AVSS|
28
Data Sheet
1.0
0.8
TA = 25°C
±10V RANGE
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
10 12 14 16 18 20 22 24 26 28
AVDD/|AVSS| (V)
Figure 32. Differential Nonlinearity Error vs. AVDD/|AVSS|
0.0050
0.0045
0.0040
0.0035
0.0030
TA = 25°C
±10V RANGE
0.0025
0.0020
0.0015
0.0010
0.0005
0
10 12 14 16 18 20 22 24 26
AVDD/|AVSS| (V)
Figure 33. Total Unadjusted Error vs. AVDD/|AVSS|
28
2.5
TA = 25°C
0V TO 10V RANGE
2.0
1.5
1.0
0.5
0
0 5 10 15 20 25 30 35
RLOAD (k)
Figure 34.VOUT Headroom
Rev. M | Page 20 of 44


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Data Sheet
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
0
TA = 25°C
0V TO 10V RANGE
5 10 15 20 25 30 35
RLOAD (k)
Figure 35.VOUT Footroom
0.05
0.04
0.03
0.02
0.01
0
–0.01
AVDD = +15V
AVSS = –15V
TA = 25°C
±10V RANGE
–0.02
–0.03
–0.04
–0.05
–20 –15 –10 –5 0 5 10 15 20
SOURCE/SINK CURRENT (mA)
Figure 36. Source and Sink Capability of Output Amplifier,
Full-Scale Code Loaded
0.05
0.04
0.03
0.02
0.01
AVDD = +15V
AVSS = –15V
TA = 25°C
±10V RANGE
0
–0.01
–0.02
–0.03
–0.04
–0.05
–20 –15 –10 –5 0 5 10 15 20
SOURCE/SINK CURRENT (mA)
Figure 37. Source and Sink Capability of Output Amplifier,
Zero-Scale Loaded
AD5412/AD5422
12
AVDD = +24V
AVSS = –24V
8 ±10V RANGE
TA = 25°C
OUTPUT UNLOADED
4
0
–4
–8
–12
–10 –5 0 5 10 15 20 25 30
TIME (µs)
Figure 38. Full-Scale Positive Step
12
8
4 AVDD = +24V
AVSS = –24V
±10V RANGE
0
TA = 25°C
OUTPUT UNLOADED
–4
–8
–12
–10 –5 0 5 10 15 20 25 30
TIME (µs)
Figure 39. Full-Scale Negative Step
4
2
0
–2
–4
–6
–8
–10
–12
–14
–16
–1
0x8000 TO 0x7FFF
0x7FFF TO 0x8000
AVDD = +24V
AVSS = –24V
TA = 25°C
±10V RANGE
1 3 5 7 9 11 13 15
TIME (µs)
Figure 40. Digital-to-Analog Glitch
Rev. M | Page 21 of 44


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AD5412/AD5422
1
CH1 5.0µV
M 5.00ms
TAAAVVDS=SD2==5°–+C2244VV
LINE 1.8V
Figure 41. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
1
CH1 50.0µV
M 5.00ms
ATAAVVDS=SD2==5°–+C2244VV
LINE 0V
Figure 42. Peak-to-Peak Noise (100 kHz Bandwidth)
Data Sheet
35
AVDD = +15V
30 AVSS = –15V
TA = 25°C
25
20
15
10
5
0
0 2 4 6 8 10 12 14 16 18 20
TIME (µs)
Figure 43. VOUT vs. Time on Power-Up
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Data Sheet
CURRENT OUTPUT
0.004
0.002
0
EXTERNAL RSET
INTERNAL RSET
EXTERNAL RSET, BOOST TRANSISTOR
INTERNAL RSET, BOOST TRANSISTOR
–0.002
–0.004
–0.006
AVDD = 24V
–0.008
AVSS = –24V/0V
TA = 25°C
RLOAD = 250
–0.010
0 10,000 20,000
30,000 40,000
CODE
50,000
Figure 44. Integral Nonlinearity vs. Code
60,000
1.0
AVDD = 24V
0.8 AVSS = –24V/0V
TA = 25°C
0.6 RLOAD = 250
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
EXTERNAL RSET
INTERNAL RSET
EXTERNAL RSET, BOOST TRANSISTOR
INTERNAL RSET, BOOST TRANSISTOR
10,000 20,000 30,000 40,000 50,000 60,000
CODE
Figure 45. Differential Nonlinearity vs. Code
0.05
0.03
0.01
–0.01
–0.03
–0.05
–0.07
–0.09
AVDD = 24V
AVSS = –24V/0V
TA = 25°C
RLOAD = 250
–0.11
–0.13
–0.15
0
EXTERNAL RSET
INTERNAL RSET
EXTERNAL RSET, BOOST TRANSISTOR
INTERNAL RSET, BOOST TRANSISTOR
10,000 20,000 30,000 40,000 50,000
CODE
60,000
Figure 46. Total Unadjusted Error vs. Code
AD5412/AD5422
0.004
0.002
AVDD = 24V
AVSS = –24V/0V
0mA TO 24mA RANGE
0
–0.002
–0.004
–0.006
–0.008
–0.010
–40
–20
0 20 40 60 80
TEMPERATURE (°C)
Figure 47. Integral Nonlinearity vs. Temperature, Internal RSET
0.003
0.002
AVDD = 24V
AVSS = –24V/0V
0mA TO 24mA RANGE
0.001
0
–0.001
–0.002
–0.003
–40
–20
0 20 40 60 80
TEMPERATURE (°C)
Figure 48. Integral Nonlinearity vs. Temperature, External RSET
1.0
0.8
AAAVLVLDSSDR==AN–224G4VEVS/0V
INTERNAL AND EXTERNAL RSET
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–40
–20
0 20 40 60 80
TEMPERATURE (°C)
Figure 49. Differential Nonlinearity vs. Temperature
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AD5412/AD5422
0.10
0.05
AVDD = 24V
AVSS = –24V/0V
0
–0.05
–0.10
–0.15
–0.20
–0.25
–40
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
–20 0 20 40
TEMPERATURE (°C)
60
Figure 50. Total Unadjusted Error vs. Temperature
80
0.10
0.05
0
AVDD = 24V
AVSS = –24V/0V
–0.05
–0.10
–0.15
–0.20
–0.25
–40
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
–20 0 20 40 60
TEMPERATURE (°C)
Figure 51. Offset Error vs. Temperature
80
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–40
AVDD = 24V
AVSS = –24V/0V
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
–20 0 20 40 60
TEMPERATURE (°C)
Figure 52. Gain Error vs. Temperature
80
Data Sheet
0.015
0.010
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
0.005
0
–0.005
–0.010
–0.015
10 15 20 25 30 35 40
AVDD (V)
Figure 53. Integral Nonlinearity Error vs. AVDD, External RSET
0.020
0.015
0.010
0.005
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
0
–0.005
–0.010
–0.015
–0.020
10 15 20 25 30 35 40
AVDD (V)
Figure 54. Integral Nonlinearity Error vs. AVDD, Internal RSET
1.0
0.8 TA = 25°C
0mA TO 24mA RANGE
0.6 AVSS = 0V
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
10 15 20 25 30 35 40
AVDD (V)
Figure 55. Differential Nonlinearity Error vs. AVDD, External RSET
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Data Sheet
1.0
0.8
TA = 25°C
0.6 0mA TO 24mA RANGE
0.4 AVSS = 0V
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
10 15 20 25 30 35 40
AVDD (V)
Figure 56. Differential Nonlinearity Error vs. AVDD, Internal RSET
0.025
0.020
0.015
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
0.010
0.005
0
–0.005
–0.010
–0.015
10 15 20 25 30 35
AVDD (V)
Figure 57. Total Unadjusted Error vs. AVDD, External RSET
40
0.05
0.03
0.01
–0.01
–0.03
–0.05
–0.07
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
–0.09
–0.11
–0.13
–0.15
10 15 20 25 30 35 40
AVDD (V)
Figure 58. Total Unadjusted Error vs. AVDD, Internal RSET
AD5412/AD5422
2.5
AVDD = 15V
AVSS = 0V
IOUT = 24mA
2.0 RLOAD = 500
1.5
1.0
0.5
0
–40 –20
0
20 40
60 80
TEMPERATURE (°C)
Figure 59. Compliance Voltage Headroom vs. Temperature
3.5
AVDD = 24V
3.0
AVSS = 0V
TA = 25°C
RLOAD = 250
2.5
2.0
1.5
1.0
0.5
0 0 100 200 300 400 500
TIME (µs)
Figure 60. Output Current vs. Time on Power-Up
600
20
10
0
AVDD = 24V
AVSS = 0V
TA = 25°C
–10 RLOAD = 250
–20
–30
–40
–50
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TIME (µs)
Figure 61. Output Current vs. Time on Output Enable
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AD5412/AD5422
70
60
50
40
30
20
TA = 25°C
10
AVDD = 40V
AVSS = 0V
OUTPUT DISABLED
0
–10
0
5 10 15 20 25 30 35 40 45
COMPLIANCE VOLTAGE (V)
Figure 62. Output Leakage Current vs. Compliance Voltage
30
AVDD = 24V
AVSS = 0V
20 TA = 25°C
RLOAD = 250
10
0x8000 TO 0x7FFF
0x7FFF TO 0x8000
0
–10
–20
–30
0
2 4 6 8 10 12 14 16 18 20
TIME (µs)
Figure 63. Digital to Analog Glitch
Data Sheet
25
TA = 25°C
20 AVDD = 24V
AVSS = 0V
RLOAD = 300
15
10
5
0
–1 0 1 2 3 4 5 6 7
TIME (µs)
Figure 64. 4 mA to 20 mA Output Current Step
8
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Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy, or INL, is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL vs. code plot can be seen in Figure 17.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures monoton-
icity. This DAC is guaranteed monotonic by design. A typical
DNL vs. code plot can be seen in Figure 19.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5412/AD5422
are monotonic over their full operating temperature range.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding) or 0x0000 (twos complement
coding). A plot of bipolar zero error vs. temperature can be seen
in Figure 28.
Bipolar Zero Temperature Coefficient (TC)
Bipolar zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in ppm FSR/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output should be
full-scale − 1 LSB. Full-scale error is expressed in percent of
full-scale range (% FSR).
Negative Full-Scale Error/Zero-Scale Error
Negative full-scale error is the error in the DAC output voltage
when 0x0000 (straight binary coding) or 0x8000 (twos complement
coding) is loaded to the DAC register. Ideally, the output voltage
should be negative full-scale − 1 LSB. A plot of zero-scale error
vs. temperature can be seen in Figure 30.
Zero-Scale Temperature Coefficient (TC)
Zero-scale TC is a measure of the change in zero-scale error
with a change in temperature. Zero-scale error TC is expressed
in ppm FSR/°C.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for the
output to settle to a specified level for a full-scale input change.
Slew Rate
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage-output
DAC is usually limited by the slew rate of the amplifier used at
its output. Slew rate is measured from 10% to 90% of the output
signal and is expressed in V/µs.
AD5412/AD5422
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed in % FSR. A plot of gain error vs. temperature
can be seen in Figure 29.
Gain Error Temperature Coefficient (TC)
Gain error TC is a measure of the change in gain error with
changes in temperature. Gain error TC is expressed in ppm
FSR/°C.
Total Unadjusted Error (TUE)
TUE is a measure of the output error taking all the various
errors into account, namely INL error, offset error, gain error,
and output drift over supplies, temperature, and time. TUE is
expressed in % FSR.
Current Loop Voltage Compliance
The maximum voltage at the IOUT pin for which the output
current is equal to the programmed value.
Power-On Glitch Energy
Power-on glitch energy is the impulse injected into the analog
output when the AD5412/AD5422 is powered on. It is specified
as the area of the glitch in nV-sec. See Figure 43 and Figure 60.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state, but the output voltage remains constant. It is normally
specified as the area of the glitch in nV-sec and is measured
when the digital input code is changed by 1 LSB at the major
carry transition (0x7FFF to 0x8000). See Figure 40 and
Figure 63.
Glitch Impulse Peak Amplitude
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in millivolt and is measured when the digital input
code is changed by 1 LSB at the major carry transition (0x7FFF
to 0x8000). See Figure 40 and Figure 63.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus.
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AD5412/AD5422
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the power supply voltage.
Voltage Reference TC
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given temperature
range expressed in ppm/°C, as follows:
TC
=
VRVEFRnEoFmma×x
VREFmin
TempRange
× 10 6
Data Sheet
where:
VREFmax is the maximum reference output measured over the
total temperature range.
VREFmin is the minimum reference output measured over the total
temperature range.
VREFnom is the nominal reference output voltage, 5 V.
TempRange is the specified temperature range, −40°C to
+105°C.
Load Regulation
Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/mA.
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Data Sheet
THEORY OF OPERATION
The AD5412/AD5422 are precision digital-to-current loop and
voltage output converters designed to meet the requirements of
industrial process control applications. They provide a high
precision, fully integrated, low cost single-chip solution for
generating current loop and unipolar/bipolar voltage outputs.
Current ranges are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA
to 20 mA; the voltage ranges available are 0 V to 5 V, ±5 V, 0 V
to 10 V, and ±10 V; a 10% overrange is available on all voltage
output ranges. The current and voltage outputs are available on
separate pins, and only one is active at any time. The desired
output configuration is user selectable via the control register.
ARCHITECTURE
The DAC core architecture of the AD5412/AD5422 consists
of two matched DAC sections. A simplified circuit diagram is
shown in Figure 65. The four MSBs of the 12-/16-bit data-word
are decoded to drive 15 switches, E1 to E15. Each of these switches
connects one of 15 matched resistors to either ground or the
reference buffer output. The remaining 8/12 bits of the data-
word drive the S0 to S7/S11 switches of an 8-/12-bit voltage
mode R-2R ladder network.
2R 2R
2R
2R 2R 2R
VOUT
2R
S0 S1
S7/S11 E1
E2
E15
8-12 BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 65. DAC Ladder Structure
The voltage output from the DAC core is either converted to
a current (see Figure 66) which is then mirrored to the supply
rail so that the application simply sees a current source output
with respect to ground or it is buffered and scaled to output a
software selectable unipolar or bipolar voltage range (see
Figure 67). The current and voltage are output on separate
pins and cannot be output simultaneously.
AVDD
12-/16-BIT
DAC
R2 R3
T1
A1
T2
A2
IOUT
RSET
Figure 66. Voltage-to-Current Conversion Circuitry
AD5412/AD5422
AD5412/AD5422
12-/16-BIT
DAC
RANGE
SCALING
REFIN
+VSENSE
VOUT
–VSENSE
R1
RLOAD
–1V TO +3V VCM
Figure 67. Voltage Output
Voltage Output Amplifier
The voltage output amplifier is capable of generating both unipolar
and bipolar output voltages. It is capable of driving a load of
1 kΩ in parallel with 1 μF (with an external compensation
capacitor) to GND. The source and sink capabilities of the
output amplifier can be seen in Figure 37. The slew rate is
1 V/μs with a full-scale settling time of 25 μs maximum (10 V
step). Figure 67 shows the voltage output driving a load, RLOAD,
on top of a common-mode voltage (VCM) of −1 V to +3 V. In
output module applications where a cable could possibly
become disconnected from +VSENSE, resulting in the amplifier
loop being broken and possibly resulting in large destructive
voltages on VOUT, include an optional resistor (R1) between
+VSENSE and VOUT, as shown in Figure 67, of a value between
2 kΩ and 5 kΩ to ensure the amplifier loop is kept closed. If
remote sensing of the load is not required, connect +VSENSE
directly to VOUT and connect −VSENSE directly to GND. When
changing ranges on the voltage output, a glitch may occur. For
this reason, it is recommended that the output be disabled by
setting the OUTEN bit of the control register to logic low before
changing the output voltage range; this prevents a glitch from
occurring.
Driving Large Capacitive Loads
The voltage output amplifier is capable of driving capacitive
loads of up to 1 μF with the addition of a nonpolarized 4 nF
compensation capacitor between the CCOMP and VOUT pins.
Without the compensation capacitor, up to 20 nF capacitive
loads can be driven.
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AD5412/AD5422
Data Sheet
SERIAL INTERFACE
The AD5412/AD5422 are controlled over a versatile 3-wire
serial interface that operates at clock rates of up to 30 MHz. It is
compatible with SPI, QSPI™, MICROWIRE, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the rising edge of SCLK.
The input register consists of eight address bits and 16 data bits,
as shown in Table 8. The 24-bit word is unconditionally latched
on the rising edge of the LATCH pin. Data continues to be clocked
in irrespective of the state of LATCH. On the rising edge of
LATCH, the data that is present in the input register is latched;
in other words, the last 24 bits to be clocked in before the rising
edge of LATCH is the data that is latched. The timing diagram
for this operation is shown in Figure 2.
Table 8. Input Shift Register Format
MSB
D23 to D16
D15 to D0
Address byte
Data-word
LSB
Table 9. Address Byte Functions
Address Word Function
00000000
No operation (NOP)
00000001
Data register
00000010
Readback register value as per read address
(see Table 10)
01010101
Control register
01010110
Reset register
Standalone Operation
The serial interface works with both a continuous and non-
continuous serial clock. A continuous SCLK source can be used
only if LATCH is taken high after the correct number of data
bits have been clocked in. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used, and
LATCH must be taken high after the final clock to latch the
data. The rising edge of SCLK that clocks in the MSB of the
data-word marks the beginning of the write cycle. Exactly 24
rising clock edges must be applied to SCLK before LATCH is
brought high. If LATCH is brought high before the 24th rising
SCLK edge, the data written is invalid. If more than 24 rising
SCLK edges are applied before LATCH is brought high, the
input data is also invalid.
CONTROLLER
DATA OUT
SERIAL CLOCK
CONTROL OUT
DATA IN
AD5412/
AD54221
SDIN
SCLK
LATCH
SDO
SDIN
AD5412/
AD54221
SCLK
LATCH
SDO
SDIN
AD5412/
AD54221
SCLK
LATCH
SDO
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 68. Daisy Chaining the AD5412/AD5422
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain the devices together as shown in Figure 68.
This daisy-chain mode can be useful in system diagnostics and
in reducing the number of serial interface lines. Daisy-chain
mode is enabled by setting the DCEN bit of the control register
to 1. The first rising edge of SCLK that clocks in the MSB of the
data-word marks the beginning of the write cycle. SCLK is
continuously applied to the input shift register. If more than
24 clock pulses are applied, the data ripples out of the shift
register and appears on the SDO line. This data is valid on the
rising edge of SCLK, having been clocked out on the previous
falling SCLK edge. By connecting the SDO of the first device to
the SDIN input of the next device in the chain, a multidevice
interface is constructed. Each device in the system requires
24 clock pulses. Therefore, the total number of clock cycles
must equal 24 × n, where n is the total number of AD5412/
AD5422 devices in the chain. When the serial transfer to all
devices is complete, LATCH is taken high. This latches the
input data in each device in the daisy chain. The serial clock
can be a continuous or a gated clock.
A continuous SCLK source can be used only if LATCH is taken
high after the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used, and LATCH must be taken high after the final
clock to latch the data (see Figure 4 for a timing diagram).
Rev. M | Page 30 of 44




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