MAX1070 (Maxim Integrated Products)
(MAX1070 / MAX1071) 10-Bit ADCs

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1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
General Description
The MAX1070/MAX1071 low-power, high-speed, serial-
output, 10-bit, analog-to-digital converters (ADCs) oper-
ate at up to 1.5Msps. These devices feature true-differen-
tial inputs, offering better noise immunity, distortion
improvements, and a wider dynamic range over single-
ended inputs. A standard SPI™/QSPI™/MICROWIRE™
interface provides the clock necessary for conversion.
These devices easily interface with standard digital signal
processor (DSP) synchronous serial interfaces.
The MAX1070/MAX1071 operate from a single +2.7V to
+3.6V supply voltage and require an external reference.
The MAX1070 has a unipolar analog input, while the
MAX1071 has a bipolar analog input. These devices fea-
ture a partial power-down mode and a full power-down
mode for use between conversions, which lower the sup-
ply current to 1mA (typ) and 1µA (max), respectively. Also
featured is a separate power-supply input (VL), which
allows direct interfacing to +1.8V to VDD digital logic. The
fast conversion speed, low-power dissipation, excellent
AC performance, and DC accuracy (±0.5 LSB INL) make
the MAX1070/MAX1071 ideal for industrial process con-
trol, motor control, and base-station applications.
The MAX1070/MAX1071 come in a 12-pin TQFN pack-
age, and are available in the commercial (0°C to +70°C)
and extended (-40°C to +85°C) temperature ranges.
Applications
Data Acquisition
Bill Validation
Motor Control
Communications
Portable Instruments
Pin Configuration
Features
1.5Msps Sampling Rate
Only 18mW (typ) Power Dissipation
Only 1µA (max) Shutdown Current
High-Speed, SPI-Compatible, 3-Wire Serial Interface
61dB S/(N + D) at 525kHz Input Frequency
Internal True-Differential Track/Hold (T/H)
External Reference
No Pipeline Delays
Small 12-Pin TQFN Package
PART
MAX1070CTC-T
MAX1070ETC-T
MAX1071CTC-T
MAX1071ETC-T
Ordering Information
TEMP RANGE PIN-
PACKAGE
0°C to +70°C 12 TQFN-12
-40°C to +85°C 12 TQFN-12
0°C to +70°C 12 TQFN-12
-40°C to +85°C 12 TQFN-12
INPUT
Unipolar
Unipolar
Bipolar
Bipolar
Typical Operating Circuit
TOP VIEW
AIN+ N.C. SCLK
12 11 10
AIN- 1
REF 2
RGND 3
MAX1070
MAX1071
9 CNVST
8 DOUT
7 VL
456
VDD N.C. GND
TQFN
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
+2.7V TO +3.6V
+1.8V TO VDD
10µF
DIFFERENTIAL +
INPUT
VOLTAGE -
REF
4.7µF
0.01µF
0.01µF
VDD
0.01µF
VL
AIN+ DOUT
AIN-
MAX1070
MAX1071 CNVST
SCLK
REF
RGND
GND
10µF
µC/DSP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.


MAX1070 (Maxim Integrated Products)
(MAX1070 / MAX1071) 10-Bit ADCs

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1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
VL to GND ................-0.3V to the lower of (VDD + 0.3V) and +6V
Digital Inputs
to GND .................-0.3V to the lower of (VDD + 0.3V) and +6V
Digital Output
to GND ....................-0.3V to the lower of (VL + 0.3V) and +6V
Analog Inputs and
REF to GND..........-0.3V to the lower of (VDD + 0.3V) and +6V
RGND to GND .......................................................-0.3V to +0.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
12-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW
Operating Temperature Ranges
MAX107_ CTC ...................................................0°C to +70°C
MAX107_ ETC.................................................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V, VL = VDD, VREF = 2.048V, fSCLK = 24.0MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at VDD = 3V and TA = +25°C.)
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Resolution
Relative Accuracy
INL (Note 1)
10 Bits
±0.5 LSB
Differential Nonlinearity
Offset Error
DNL (Note 2)
±0.5
±2
LSB
LSB
Offset-Error Temperature
Coefficient
±1 ppm/°C
Gain Error
Offset nulled
±2 LSB
Gain Temperature Coefficient
±2 ppm/°C
DYNAMIC SPECIFICATIONS (fIN = 525kHz sine wave, VIN = VREF, unless otherwise noted.)
Signal-to-Noise Plus Distortion
SINAD
60 61
dB
Total Harmonic Distortion
THD Up to the 5th harmonic
-80 -74
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Minimum Conversion Time
Maximum Throughput Rate
Minimum Throughput Rate
SFDR
IMD
fIN1 = 250kHz, fIN2 = 300kHz
-3dB point
S/(N + D) > 56dB, single ended
tCONV (Note 3)
(Note 4)
-80 -74
dB
-78 dB
15 MHz
2 MHz
0.667
µs
1.5 Msps
10 ksps
Track-and-Hold Acquisition Time
Aperture Delay
tACQ (Note 5)
125 ns
5 ns
Aperture Jitter
External Clock Frequency
fSCLK
(Note 6)
(Note 7)
30 ps
24.0 MHz
2 _______________________________________________________________________________________


MAX1070 (Maxim Integrated Products)
(MAX1070 / MAX1071) 10-Bit ADCs

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1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V, VL = VDD, VREF = 2.048V, fSCLK = 24.0MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at VDD = 3V and TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
ANALOG INPUTS (AIN+, AIN-)
Differential Input Voltage Range
Absolute Input Voltage Range
DC Leakage Current
Input Capacitance
Input Current (Average)
REFERENCE INPUT (REF)
AIN+ - AIN-, MAX1070
VIN AIN+ - AIN-, MAX1071
0
-VREF / 2
VREF
+VREF / 2
V
0
VDD
V
±1 µA
Per input pin
16 pF
Time averaged at maximum throughput rate
50
µA
REF Input Voltage Range
VREF
1.0
VDD +
50mV
V
Input Capacitance
DC Leakage Current
Input Current (Average)
DIGITAL INPUTS (SCLK, CNVST)
Input-Voltage Low
Input-Voltage High
Input Leakage Current
DIGITAL OUTPUT (DOUT)
Output Load Capacitance
Output-Voltage Low
Output-Voltage High
Output Leakage Current
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
VIL
VIH
IIL
COUT
VOL
VOH
IOL
VDD
VL
Analog Supply Current,
Normal Mode
IDD
Analog Supply Current,
Partial Power-Down Mode
IDD
Time averaged at maximum throughput rate
20
±1
200
0.7 x VL
0.05
0.3 x VL
±10
For stated timing performance
ISINK = 5mA, VL 1.8V
ISOURCE = 1mA, VL 1.8V
Output high impedance
VL - 0.5V
±0.2
30
0.4
±10
Static, fSCLK = 24.0
Static, no SCLK
Operational, 1.5Msps
fSCLK = 24.0MHz
No SCLK
2.7 3.6
1.8 VDD
57
45
68
1
1
pF
µA
µA
V
V
µA
pF
V
V
µA
V
V
mA
mA
Analog Supply Current,
Full Power-Down Mode
Digital Supply Current (Note 8)
Positive-Supply Rejection
IDD
fSCLK = 24.0MHz
No SCLK
Operational, full-scale input at 1.5Msps
Static, fSCLK = 24.0MHz
Partial/full power-down mode,
fSCLK = 24.0MHz
Static, no SCLK (all modes)
PSR Full-scale input, 3V +20%, -10%
1
0.3
0.3
0.15
0.1
0.1
±0.2
1
1
0.5
0.3
1
±3.0
µA
mA
µA
mV
_______________________________________________________________________________________ 3


MAX1070 (Maxim Integrated Products)
(MAX1070 / MAX1071) 10-Bit ADCs

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1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V, VL = VDD, VREF = 2.048V, fSCLK = 24.0MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted.
Typical values are at VDD = 3V and TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Pulse-Width High
VL = 2.7V to VDD
18.7
tCH VL = 1.8V to VDD, minimum recommended
(Note 7)
22.5
ns
SCLK Pulse-Width Low
VL = 2.7V to VDD
18.7
tCL VL = 1.8V to VDD, minimum recommended
(Note 7)
22.5
ns
SCLK Rise to DOUT Transition
DOUT Remains Valid After SCLK
CNVST Fall to SCLK Fall
CNVST Pulse Width
Power-Up Time; Full Power-Down
Restart Time; Partial Power-Down
tDOUT
tDHOLD
tSETUP
tCSW
tPWR-UP
tRCV
CL = 30pF, VL = 2.7V to VDD
CL = 30pF, VL = 1.8V to VDD
VL = 1.8V to VDD
VL = 1.8V to VDD
VL = 1.8V to VDD
17
ns
24
4 ns
10 ns
20 ns
2 ms
16 Cycles
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: 1.5Msps operation guaranteed for VL > 2.7V. See the Typical Operating Characteristics section for recommended sampling
speeds for VL < 2.7V.
Note 8: Digital supply current is measured with the VIH level equal to VL, and the VIL level equal to GND.
CNVST
SCLK
tSETUP
DOUT
tCL tCH
tDHOLD
tDOUT
Figure 1. Detailed Serial-Interface Timing
VL
tCSW
DOUT
6k
DOUT
6kCL
GND
a) HIGH-Z TO VOH, VOL TO VOH,
AND VOH TO HIGH-Z
CL
GND
b) HIGH-Z TO VOL, VOH TO VOL,
AND VOL TO HIGH-Z
Figure 2. Load Circuits for Enable/Disable Times
4 _______________________________________________________________________________________


MAX1070 (Maxim Integrated Products)
(MAX1070 / MAX1071) 10-Bit ADCs

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1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
Typical Operating Characteristics
(VDD = +3V, VL = VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.)
MAXIMUM RECOMMENDED fSCLK vs. VL
25
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1070)
0.2
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1071)
0.2
23 0.1 0.1
21 0 0
19 -0.1 -0.1
17
1.8 2.1 2.4 2.7 3.0 3.3 3.6
VL (V)
-0.2
0
256 512 768
DIGITAL OUTPUT CODE
1024
-0.2
-512
-256 0
256
DIGITAL OUTPUT CODE
512
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1070)
0.2
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1071)
0.2
0.1 0.1
00
-0.1 -0.1
-0.2
0
256 512 768
DIGITAL OUTPUT CODE
1024
OFFSET ERROR
vs. TEMPERATURE (MAX1071)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-40
-15 10 35 60
TEMPERATURE (°C)
85
-0.2
-512
-256 0
256
DIGITAL OUTPUT CODE
512
GAIN ERROR
vs. TEMPERATURE (MAX1070)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-40
-15 10 35 60
TEMPERATURE (°C)
85
OFFSET ERROR
vs. TEMPERATURE (MAX1070)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-40
-15 10 35 60
TEMPERATURE (°C)
85
GAIN ERROR
vs. TEMPERATURE (MAX1071)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-40
-15 10 35 60
TEMPERATURE (°C)
85
_______________________________________________________________________________________ 5


MAX1070 (Maxim Integrated Products)
(MAX1070 / MAX1071) 10-Bit ADCs

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1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
Typical Operating Characteristics (continued)
(VDD = +3V, VL = VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.)
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1070)
61.5
DYNAMIC PERFORMANCE
vs. INPUT FREQUENCY (MAX1071)
61.5
THD vs. INPUT FREQUENCY
-82
61.4 61.4
-84 MAX1070
61.3
SNR
61.2
61.1
61.0
100
SINAD
200 300 400
ANALOG INPUT FREQUENCY (kHz)
500
61.3
SNR
61.2
61.1
61.0
100
SINAD
200 300 400
ANALOG INPUT FREQUENCY (kHz)
500
-86
-88
-90 MAX1071
-92
100
200 300 400
ANALOG INPUT FREQUENCY (kHz)
500
SFDR vs. INPUT FREQUENCY
90
88
MAX1070
86
84
MAX1071
82
80
100
200 300 400
ANALOG INPUT FREQUENCY (kHz)
500
FFT PLOT (MAX1070)
0
fIN = 500kHz
-20 SINAD = 61.2dB
SNR = 61.2dB
THD = -83.5dB
-40 SFDR = 83.8dB
-60
-80
-100
-120
-140
0
125 250 375 500 625 750
ANALOG INPUT FREQUENCY (kHz)
FFT PLOT (MAX1071)
0
fIN = 500kHz
-20 SINAD = 61.3dB
SNR = 61.3dB
-40
THD = -90dB
SFDR = 85.4dB
-60
-80
-100
-120
-140
0
125 250 375 500 625 750
ANALOG INPUT FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION
vs. SOURCE IMPEDANCE
-50
-60
fIN = 500kHz
-70
-80
fIN = 100kHz
-90
-100
10
100
SOURCE IMPEDANCE ()
1000
TWO-TONE IMD PLOT (MAX1070)
0
fIN1 = 250.102kHz
-20 fIN2 = 299.966kHz
IMD = -86.6dB
-40
fIN1
-60
fIN2
-80
-100
-120
-140
0
125 250 375 500 625 750
ANALOG INPUT FREQUENCY (kHz)
TWO-TONE IMD PLOT (MAX1071)
0
fIN1 = 250.102kHz
-20 fIN2 = 299.966kHz
IMD = -83.4dB
-40
-60 fIN1
fIN2
-80
-100
-120
-140
0
125 250 375 500 625 750
ANALOG INPUT FREQUENCY (kHz)
6 _______________________________________________________________________________________


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(MAX1070 / MAX1071) 10-Bit ADCs

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1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
Typical Operating Characteristics (continued)
(VDD = +3V, VL = VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.)
VDD/VL FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
1.0
0.8
0.6 VDD, fSCLK = 24MHz
0.4
0.2 VL, NO SCLK
VDD, NO SCLK
0
-40
-15 10 35 60
TEMPERATURE (°C)
85
VL PARTIAL/FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
100
75
VL = 3V, fSCLK = 24MHz
50
VL = 1.8V, fSCLK = 24MHz
25
0
-40
-15 10 35 60
TEMPERATURE (°C)
85
VDD SUPPLY CURRENT vs. TEMPERATURE
9
CONVERSION
6
3
PARTIAL POWER-DOWN
0
-40
-15 10 35 60
TEMPERATURE (°C)
85
VDD SUPPLY CURRENT
vs. CONVERSION RATE
9
6
3
0
0 250 500 750 1000 1250 1500
fSAMPLE (kHz)
VL SUPPLY CURRENT vs. TEMPERATURE
0.5
0.4
CONVERSION, VL = 3V
0.3
0.2 CONVERSION, VL = 1.8V
0.1
0
-40
-15 10 35 60
TEMPERATURE (°C)
85
VL SUPPLY CURRENT
vs. CONVERSION RATE
250
200
150 VL = 3V
100
50
0
0
VL = 1.8V
250 500 750 100 1250 1500
fSAMPLE (kHz)
_______________________________________________________________________________________ 7


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1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
PIN
1
2
3
4
5, 11
6
7
8
9
10
12
NAME
AIN-
REF
RGND
VDD
N.C.
GND
VL
DOUT
CNVST
SCLK
AIN+
EP
Pin Description
Negative Analog Input
FUNCTION
External Reference Voltage Input. VREF sets the analog input range. Bypass REF with a 0.01µF
capacitor and a 4.7µF capacitor to RGND.
Reference Ground. Connect RGND to GND.
Positive Analog Supply Voltage (+2.7V to 3.6V). Bypass VDD with a 0.01µF capacitor and a 10µF
capacitor to GND.
No Connection
Ground. GND is internally connected to EP.
Positive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01µF capacitor and a 10µF capacitor
to GND.
Serial Data Output. Data is clocked out on the rising edge of SCLK.
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
Positive Analog Input
Exposed Paddle. EP is internally connected to GND.
Detailed Description
The MAX1070/MAX1071 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 10-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1070/MAX1071.
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1070/MAX1071, which is composed of
a T/H, a comparator, and a switched-capacitor digital-to-
analog converter (DAC). The T/H enters its tracking mode
on the 14th SCLK rising edge of the previous conversion.
Upon power-up, the T/H enters its tracking mode immedi-
ately. The positive input capacitor is connected to AIN+.
The negative input capacitor is connected to AIN-. The
T/H enters its hold mode on the falling edge of CNVST
and the difference between the sampled positive and
negative input voltages is converted. The time required
for the T/H to acquire an input signal is determined by
how quickly its input capacitance is charged. If the input
signal’s source impedance is high, the acquisition time
lengthens. The acquisition time, tACQ, is the minimum
time needed for the signal to be acquired. It is calculated
by the following equation:
tACQ 8 x (RS + RIN) x 16pF
where RIN = 200, and RS is the source impedance of
the input signal.
Note: tACQ is never less than 125ns, and any source
impedance below 12does not significantly affect the
ADC’s AC performance.
Input Bandwidth
The ADC’s input-tracking circuitry has a 15MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes that clamp the analog input
to VDD and GND allow the analog input pins to swing
from GND - 0.3V to VDD + 0.3V without damage. Both
inputs must not exceed VDD or be lower than GND for
accurate conversions.
8 _______________________________________________________________________________________


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(MAX1070 / MAX1071) 10-Bit ADCs

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1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
REF
AIN+
T/H
AIN-
VDD VL
10-BIT
SAR
ADC
OUTPUT
BUFFER
DOUT
CIN+ RIN+
AIN+
CAPACITIVE
DAC
VAZ
COMP
CONTROL
LOGIC
MAX1070
MAX1071
CONTROL
LOGIC AND
TIMING
RGND
GND
CNVST
SCLK
AIN-
CIN- RIN- ACQUISITION MODE
CIN+ RIN+
AIN+
CAPACITIVE
DAC
Figure 3. Functional Diagram
Serial Interface
Initialization After Power-Up
and Starting a Conversion
Upon initial power-up, the MAX1070/MAX1071 require a
complete conversion cycle to initialize the internal cali-
bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a con-
version is initiated. SCLK runs the conversion and the
data can then be shifted out serially on DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. Figures
1 and 5 show timing diagrams, which outline the serial-
interface operation.
A CNVST falling edge initiates a conversion sequence:
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance
to logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the con-
version is determined.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions tDOUT after each
SCLK’s rising edge and remains valid 4ns (tDHOLD)
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 10 data bits, 2 sub-bits (S1 and S0), and 3
VAZ
COMP
CONTROL
LOGIC
AIN-
CIN-
RIN-
HOLD CONVERSION MODE
Figure 4. Equivalent Input Circuit
leading zeros, at least 16 rising clock edges are need-
ed to shift out these bits. For continuous operation, pull
CNVST high between the 14th and the 16th SCLK ris-
ing edges. If CNVST stays low after the falling edge of
the 16th SCLK cycle, the DOUT line goes to a high-
impedance state on either CNVST’s rising edge or the
next SCLK’s rising edge.
Partial Power-Down and
Full Power-Down Modes
Power consumption can be reduced significantly by
placing the MAX1070/MAX1071 in either partial power-
down mode or full power-down mode. Partial power-
down mode is ideal for infrequent data sampling and
fast wake-up time applications. Pull CNVST high after
the 3rd SCLK rising edge and before the 14th SCLK
rising edge to enter and stay in partial power-down
mode (see Figure 6). This reduces the supply current
to 1mA. Drive CNVST low and allow at least 14 SCLK
cycles to elapse before driving CNVST high to exit par-
tial power-down mode.
Full power-down mode is ideal for infrequent data sam-
pling and very low supply-current applications. The
MAX1070/MAX1071 have to be in partial power-down
mode in order to enter full power-down mode. Perform the
SCLK/CNVST sequence described above to enter partial
_______________________________________________________________________________________ 9


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CNVST
SCLK
tSETUP
12
34
POWER-MODE SELECTION WINDOW
8
tACQUIRE
CONTINUOUS-CONVERSION
14 16 SELECTION WINDOW
HIGH IMPEDANCE
DOUT
Figure 5. Interface-Timing Sequence
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
CNVST
SCLK
DOUT
MODE
ONE 8-BIT TRANSFER
CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
1ST SCLK RISING EDGE
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
0 0 0 D9 D8 D7 D6 D5
NORMAL
PPD
Figure 6. SPI Interface—Partial Power-Down Mode
CNVST
SCLK
DOUT
MODE
FIRST 8-BIT TRANSFER
EXECUTE PARTIAL POWER-DOWN TWICE
SECOND 8-BIT TRANSFER
1ST SCLK RISING EDGE
1ST SCLK RISING EDGE
0 0 0 D9 D8 D7 D6 D5
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
00000000
NORMAL
PPD
RECOVERY
FPD
Figure 7. SPI Interface—Full Power-Down Mode
power-down mode. Then repeat the same sequence to
enter full power-down mode (see Figure 7). Drive CNVST
low, and allow at least 14 SCLK cycles to elapse before
driving CNVST high to exit full power-down mode. In par-
tial/full power-down mode, maintain a logic low or a logic
high on SCLK to minimize power consumption.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1070. Figure 9 shows the bipolar transfer function for
the MAX1071. The MAX1070 output is straight binary,
while the MAX1071 output is two’s complement.
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Applications Information
External Reference
An external reference is required for the MAX1070/
MAX1071. Use a 4.7µF and 0.01µF bypass capacitor on
the REF pin for best performance. The reference input
structure allows a voltage range of +1V to VDD.
How to Start a Conversion
An analog-to-digital conversion is initiated by CNVST
and clocked by SCLK, and the resulting data is clocked
out on DOUT by SCLK. With SCLK idling high or low, a
falling edge on CNVST begins a conversion. This causes
the analog input stage to transition from track to hold
mode, and DOUT to transition from high impedance to
being actively driven low. A total of 16 SCLK cycles are
required to complete a normal conversion. If CNVST is
low during the 16th falling SCLK edge, DOUT returns to
high impedance on the next rising edge of CNVST or
SCLK, enabling the serial interface to be shared by multi-
ple devices. If CNVST returns high after the 14th, but
before the 16th SCLK rising edge, DOUT remains active
so continuous conversions can be sustained. The high-
est throughput is achieved when performing continuous
conversions. Figure 10 illustrates a conversion using a
typical serial interface.
Connection to
Standard Interfaces
The MAX1070/MAX1071 serial interface is fully compati-
ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 28.8MHz.
SPI and MICROWIRE
When using SPI or MICROWIRE, the MAX1070/MAX1071
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CNVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
10 bits from the ADC. DOUT transitions on SCLK rising
edges. DOUT is guaranteed to be valid tDOUT later and
remains valid until tDHOLD after the following SCLK rising
edge. When using CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1, the data is clocked into the µP on the
following rising edge. When using CPOL = 0 and CPHA
= 1 or CPOL = 1 and CPHA = 0, the data is clocked
into the µP on the next falling edge. See Figure 11 for
connections and Figures 12 and 13 for timing. See the
Timing Characteristics section to determine the best
mode to use.
OUTPUT CODE
111...111
111...110
111...101
FULL-SCALE
TRANSITION
000...011
000...010
000...001
000...000
012 3
FS = VREF
ZS = 0
1 LSB = VREF
1024
DIFFERENTIAL INPUT
VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 8. Unipolar Transfer Function (MAX1070 Only)
OUTPUT CODE
011...111
011...110
000...010
000...001
000...000
111...111
111...110
111...101
FS = VREF
2
ZS = 0
- FS = -VREF
2
1 LSB = VREF
1024
FULL-SCALE
TRANSITION
100...001
100...000
-FS 0 FS
DIFFERENTIAL INPUT
FS - 3/2 LSB
VOLTAGE (LSB)
Figure 9. Bipolar Transfer Function (MAX1071 Only)
______________________________________________________________________________________ 11


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CNVST
SCLK
DOUT
1 14 16
0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 0
Figure 10. Continuous Conversion with Burst/Continuous Clock
1
0
I/O
SCK
MISO
+3V TO +5V
A) SPI
SS
CS
SCK
MISO
+3V TO +5V
B) QSPI
SS
I/O
SK
SI
CNVST
SCLK
DOUT
MAX1070
MAX1071
CNVST
SCLK
DOUT
MAX1070
MAX1071
CNVST
SCLK
DOUT
C) MICROWIRE
Figure 11. Common Serial-Interface Connections to the MAX1070/MAX1071
MAX1070
MAX1071
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CNVST
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
SCLK
1
HIGH-Z
DOUT
89
16
D9 D8
D7 D6
D5 D4 D3 D2 D1 D0 S1 S0
HIGH-Z
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
SCLK
1
14 16 1
DOUT
0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 0 0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
SCLK
HIGH-Z
DOUT
2
16
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
HIGH-Z
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 10 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1070/MAX1071 require 16 clock cycles
from the µP to clock out the 10 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
10 data bits, 2 sub-bits, and a trailing zero with the data
in MSB-first format.
DSP Interface to the TMS320C54_
The MAX1070/MAX1071 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1070/MAX1071 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.
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VL
MAX1070 SCLK
MAX1071
CNVST
DOUT
DVDD
CLKX TMS320C54_
CLKR
FSX
FSR
DR
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
For continuous conversion, set the serial port to trans-
mit a clock, and pulse the frame sync signal for a clock
period before data transmission. The serial-port config-
uration (SPC) register should be set up with internal
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
This setup allows continuous conversions provided that
the data-transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to execute conversions and
read the data without CPU intervention. Connect the VL
pin to the TMS320C54_ supply voltage when the
MAX1070/MAX1071 are operating with an analog sup-
ply voltage higher than the DSP supply voltage. The
word length can be set to 8 bits with FO = 1 to imple-
ment the power-down modes. The CNVST pin must idle
high to remain in either power-down state.
Another method of connecting the MAX1070/MAX1071
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Figure 16 where serial clock (CLOCK) drives the CLKR
and SCLK and the convert signal (CONVERT) drives
the FSR and CNVST.
The serial port must be set up to accept an external
receive-clock and external receive-frame sync.
The SPC register should be written as follows:
TXM = 0, external frame sync
MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
VL
MAX1070
MAX1071 SCLK
CNVST
DOUT
DVDD
TMS320C54_
CLKR
FSR
DR
CLOCK
CONVERT
Figure 16. Interfacing to the TMS320C54_ External Clocks
This setup allows continuous conversion, provided that
the DRR is serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
intervention. Connect the VL pin to the TMS320C54_
supply voltage when the MAX1070/MAX1071 are oper-
ating with an analog supply voltage higher than the
DSP supply voltage.
The MAX1070/MAX1071 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CNVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).
DSP Interface to the ADSP21_ _ _
The MAX1070/MAX1071 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices,
Inc. Figure 19 shows the direct connection of the
MAX1070/MAX1071 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface
with the MAX1070/MAX1071. For continuous conver-
sions, idle CNVST low and pulse it high for one clock
cycle during the LSB of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
sions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL
14 ______________________________________________________________________________________


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CNVST
SCLK
1
1
DOUT
S0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 0 0
Figure 17. DSP Interface—Continuous Conversion
CNVST
SCLK
1
1
DOUT
0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 0
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
00
registers should be configured for late framing (LAFR =
1) and for an active-low frame (LTFS = 1, LRFS = 1) sig-
nal. This is also the best way to enter the power-down
modes by setting the word length to 8 bits (SLEN =
1001). Connect the VL pin to the ADSP21_ _ _ supply
voltage when the MAX1070/MAX1071 are operating with
a supply voltage higher than the DSP supply voltage
(see Figures 17 and 18).
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the VDD power supply can
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1070/MAX1071 are mea-
sured using the end-points method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of CNVST and the instant when an actual
sample is taken.
______________________________________________________________________________________ 15


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VL
MAX1070 SCLK
MAX1071
CNVST
DOUT
VDDINT
TCLK ADSP21_ _ _
RCLK
TFS
RFS
DR
Figure 19. Interfacing to the ADSP21_ _ _
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The theoretical minimum analog-to-digital
noise is caused by quantization error, and results directly
from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantiza-
tion noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
ENOB = (SINAD 1.76)
6.02
VDD
10µF
0.1µF
SUPPLIES
GND
10µF
0.1µF
VL
VDD
GND RGND
VL
MAX1070
MAX1071
DGND VL
DIGITAL
CIRCUITRY
Figure 20. Power-Supply Grounding Condition
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
THD
=
20
x
log

V22
+
V32
+ V42
+
V52
V1 
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dB for a full-scale input.
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Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the sig-
nal-to-noise plus distortion (SINAD) is equal to 56dB.
Intermodulation Distortion
Any device with nonlinearities creates distortion prod-
ucts when two sine waves at two different frequencies
(f1 and f2) are input into the device. Intermodulation
distortion (IMD) is the total power of the IM2 to IM5
intermodulation products to the Nyquist frequency rela-
tive to the total input power of the two input tones, f1
and f2. The individual input tone levels are at -7dBFS.
The intermodulation products are as follows:
• 2nd-order intermodulation products (IM2): f1 + f2,
f2 - f1
• 3rd-order intermodulation products (IM3): 2f1 - f2,
2f2 - f1, 2f1 + f2, 2f2 + f1
• 4th-order intermodulation products (IM4): 3f1 - f2,
3f2 - f1, 3f1 + f2, 3f2 + f1
• 5th-order intermodulation products (IM5): 3f1 - 2f2,
3f2 - 2f1, 3f1 + 2f2, 3f2 + 2f1
Chip Information
TRANSISTOR COUNT: 13,016
PROCESS: BiCMOS
______________________________________________________________________________________ 17


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Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
1
2
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.




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