HD74LV2GT00A (Renesas Technology)
Dual 2-input NAND Gates / CMOS Logic Level Shifter

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HD74LV2GT00A
Dual 2-input NAND Gates / CMOS Logic Level Shifter
REJ03D0137–0200Z
(Previous ADE-205-662A (Z))
Rev.2.00
Oct.14.2003
Description
The HD74LV2GT00A has dual two-input NAND gates in an 8 pin package. The input protection circuitry
on this device allows over voltage tolerance on the input, allowing the device to be used as a logic–level
translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS
Logic while operating at the high-voltage power supply. Low voltage and high-speed operation is suitable
for the battery powered products (e.g., notebook computers), and the low power consumption extends the
battery life.
Features
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
Logic-level translate function
3.0 V CMOS logic 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic 3.3 V CMOS logic (@VCC = 3.3 V)
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
HD74LV2GT00AUSE SSOP-8 pin
Package Code
TTP-8DBV
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Rev.2.00, Oct.14.2003, page 1 of 7


HD74LV2GT00A (Renesas Technology)
Dual 2-input NAND Gates / CMOS Logic Level Shifter

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HD74LV2GT00A
Outline and Article Indication
HD74LV2GT00A
Index band
Lot No.
SSOP-8
Function Table
Inputs
A
L
L
H
H
H : High level
L : Low level
B
L
H
L
H
YMW
T00
Y : Year code
(the last digit of year)
M : Month code
W : Week code
Marking
Output Y
H
H
H
L
Rev.2.00, Oct.14.2003, page 2 of 7


HD74LV2GT00A (Renesas Technology)
Dual 2-input NAND Gates / CMOS Logic Level Shifter

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HD74LV2GT00A
Pin Arrangement
1A 1
1B 2
2Y 3
GND 4
8 VCC
7 1Y
6 2B
5 2A
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit Test Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
VCC
VI
VO
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation
at Ta = 25°C (in still air) *3
IIK
IOK
IO
ICC or IGND
PT
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
200
V
V
V Output : H or L
VCC : OFF
mA VI < 0
mA VO < 0 or VO > VCC
mA VO = 0 to VCC
mA
mW
Storage temperature
Tstg
–65 to 150
°C
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and
furthermore no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00, Oct.14.2003, page 3 of 7


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Dual 2-input NAND Gates / CMOS Logic Level Shifter

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HD74LV2GT00A
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise / fall time
Symbol
VCC
VIN
VOUT
Topr
tr, tf
Ratings
3.0 to 5.5
0 to 5.5
0 to VCC
–40 to +85
0 to 100 (VCC = 3.0 to 3.6 V)
0 to 20 (VCC = 4.5 to 5.5 V)
Unit
V
V
V
°C
ns
Electrical Characteristic
Ta = –40 to 85°C
Item
Symbol VCC (V) * Min Typ Max Unit Test condition
Input voltage
VIH 3.0 to 3.6 1.5
—V
4.5 to 5.5 2.0
VIL 3.0 to 3.6 — — 0.6
Hysteresis voltage
VH
4.5 to 5.5
3.3
0.10
0.8
— V VT+ – VT–
5.0 — 0.15 —
Output voltage
VOH Min to Max VCC–0.1 —
— V IOH = –50 µA
3.0
2.48 —
IOH = –6 mA
4.5
3.8 —
IOH = –12 mA
VOL Min to Max — — 0.1
IOL = 50 µA
3.0 — — 0.44 IOL = 6 mA
4.5 — — 0.55 IOL = 12 mA
Input current
Quiescent
supply current
IIN
0 to 5.5
±1 µA VIN = 5.5 V or GND
ICC 5.5
— — 10 µA VIN = VCC or GND,
IO = 0
ICC
Output leakage current IOFF
5.5
0
— — 1.5 mA One input VIN = 3.4 V,
other input VCC or GND
— — 5 µA VO = 5.5 V
Input capacitance CIN 5.0
— 2.5 — pF VIN = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
Rev.2.00, Oct.14.2003, page 4 of 7


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Dual 2-input NAND Gates / CMOS Logic Level Shifter

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HD74LV2GT00A
Switching Characteristics
VCC = 3.3 ± 0.3 V
Item
Propagation
delay time
Symbol
tPLH
tPHL
Ta = 25°C
Min Typ
— 7.0
— 7.5
Max
10.0
12.0
Ta = –40 to 85°C
Test
FROM
Min Max Unit Conditions (Input)
1.0 12.0 ns CL = 15 pF A or B
1.0 14.0
CL = 50 pF
TO
(Output)
Y
VCC = 5.0 ±0.5 V
Item
Propagation
delay time
Symbol
tPLH
tPHL
Ta = 25°C
Min Typ
— 5.0
— 5.5
Max
6.9
7.9
Ta = –40 to 85°C
Test
FROM
Min Max Unit Conditions (Input)
1.0 8.0 ns CL = 15 pF A or B
1.0 9.0
CL = 50 pF
TO
(Output)
Y
Operating Characteristics
CL = 50 pF
Item
Power dissipation
capacitance
Symbol
CPD
Ta = 25°C
VCC (V) Min
Typ
5.0 —
11.0
Max Unit
— pF
Test Conditions
f = 10 MHz
Test Circuit
VCC
Pulse
generator
Input
50
Output
CL
Note: Operating current test time, output is open.
Rev.2.00, Oct.14.2003, page 5 of 7


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Dual 2-input NAND Gates / CMOS Logic Level Shifter

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HD74LV2GT00A
Waveforms
Input
tr
90%
Vref
10%
tf
90%
Vref
10%
Output
50%
tPHL
50%
tPLH
VI
GND
VOH
VOL
VCC (V)
INPUTS
VI tr / tf
Vref
3.3±0.3 2.5 V 3.0 ns 50%
5.0±0.5 3 V 3.0 ns 1.5 V
Notes: 1. Input waveform : PRR 1 MHz, Zo = 50 .
2. The output are measured one at a time with one transition per measurement.
Rev.2.00, Oct.14.2003, page 6 of 7


HD74LV2GT00A (Renesas Technology)
Dual 2-input NAND Gates / CMOS Logic Level Shifter

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HD74LV2GT00A
Package Dimensions
2.0 ± 0.2
1.5 ± 0.2
(0.5) (0.5) (0.5)
Unit: mm
8
0.2
+
0.1
0.05
Package Code
JEDEC
JEITA
Mass (reference value)
TTP–8DBV
0.010 g
Rev.2.00, Oct.14.2003, page 7 of 7


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Dual 2-input NAND Gates / CMOS Logic Level Shifter

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