AD5290 (Analog Devices)
Compact 30V/+-15V 256-Position Digital Potentiometer

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Preliminary Technical Data
Compact +30V/±15V 256-Position Digital
Potentiometer
AD5290
FEATURES
256-position
+2.7V to +30V Single Supply Operation
±2.7V to ±15V Dual Supply Operation
End-to-end resistance 10 kΩ, 50 kΩ, 100 kΩ
Low temperature coefficient 35 ppm/°C
Power-on preset to midscale
SPI compatible interface
Automotive temperature range –40°C to +105°C
Compact MSOP-10 (3 mm × 4.9 mm) package
APPLICATIONS
Programmable Gain and Offset
Programmable Power Supply
Industrial Actuator Control
LED Array Driver
Audio Volume Control
General Purpose DAC Replacement
Mechanical Potentiometer Replacement
GENERAL OVERVIEW
The AD5290 is a low cost, compact 2.9 mm × 3 mm
+30V/±15V, 256-position digital potentiometer. This device
performs the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.
The wiper settings are controllable through an SPI compatible
digital interface. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the RDAC latch.
The AD5290 is available in 10k, 50k, and 100kin compact
MSOP-10 package. AD5290 can be operated from a single
supply +2.7 V to +30 V or dual supply ±2.7 V to ±15 V. All
parts are guaranteed to operate over the automotive
temperature range of -40°C to +105°C.
SDO
SDI
CLK
CS
FUNCTIONAL BLOCK DIAGRAM
AD5290
Q
8-Bit
8 8-Bit
SERIAL
LATCH
REG
8
D
CK
RS
POR
VDD
A
W
B
VSS
Figure 1.
DG ND
Note:
The terms digital potentiometer and RDAC are used interchangeably.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.


AD5290 (Analog Devices)
Compact 30V/+-15V 256-Position Digital Potentiometer

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AD5290
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD/VSS = ±15V±10% or ±5V±10%, VA = +VDD, VB = VSS/0V, -40°C < TA < +105°C unless otherwise noted)
Table 1.
Parameter
Symbol
Conditions
Min
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆RAB
(∆RAB/RAB)/∆T*106
RW
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Resolution
N
Differential Nonlinearity4
DNL
Integral Nonlinearity4
INL
Voltage Divider Temperature Coefficient
(∆VW/VW)/∆T*106
Full-Scale Error
VWFSE
Zero-Scale Error
VWZSE
RESISTOR TERMINALS
Voltage Range5
VA,B,W
Capacitance6 A, B
CA,B
Capacitance6 W
CW
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
ICM
VIH
VIL
VOH
VOL
Input Current
Input Capacitance
POWER SUPPLIES
Power Supply Range
Power Supply Range
Supply Current6
Supply Current
Supply Current
Power Dissipation7
Power Supply Sensitivity
II
CI
VDD/VSS
VDD
IDD
IDD
ISS
PDISS
PSS
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3dB
BW
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
VAB = VDD,
Wiper = no connect
VDD = 30 V
VDD = 5 V
Code = 0x80
Code = 0xFF
Code = 0x00
f = 1 MHz, measured to
GND, Code = 0x80
f = 1 MHz, measured to
GND, Code = 0x80
VA = VB = VW
VDD = +5V or +15V
VDD = +5V or +15V
RL = 2.2 kto +5 V
IOL = 1.6mA, VLOGIC = +5V,
VDD = +15V
VIN = 0 V or +15 V
Dual Supply Range
Single Supply Range, VSS =
0V
VIH = 5 V or VIL = 0 V, VDD =
+5 V
VIH = 5 V or VIL = 0 V, VDD =
+15 V
VIH = 5 V or VIL = 0 V, VSS = -
5 V or –15 V
VIH = 5 V or VIL = 0 V, VDD =
+15 V, VSS = -15 V
VDD = +15V ±10%, or
VSS = -15V ±10%, Code =
Midscale
RAB = 10 kΩ/50 kΩ/100 kΩ,
Code = 0x80
–1
–2
–30
–1
–1
–3
0
VSS
2.4
4.9
±2.7
+2.7
Typ1
±0.1
±0.25
35
50
200
±0.1
±0.3
5
–1
1
45
60
1
5
0.1
0.75
0.02
11
±0.01
525/125/60
Max
+1
+2
+30
120
400
8
+1
+1
0
3
VDD
0.8
0.4
±1
±16.5
+30
10
2
0.1
30
±0.02
Unit
LSB
LSB
%
ppm/°C
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
nA
V
V
V
V
µA
pF
V
V
µA
mA
mA
mW
%/%
kHz
Rev. Pr C | Page 2 of 11


AD5290 (Analog Devices)
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Total Harmonic Distortion
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage Density
THDW
tS
eN_WB
VA =1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kΩ
VA = 5 V, VB = 0 V,
±1 LSB error band
RWB = 25 kΩ
AD5290
0.05 %
4 µs
14 nV/√Hz
Rev. Pr C | Page 3 of 11


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AD5290
TIMING CHARACTERISTICS— 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD/VSS = ±15V±10% or ±5V±10%, VA = +VDD, VB = 0V, -40°C < TA < +105°C unless otherwise noted.)
Table 2.
Parameter
Symbol Conditions
Min Typ1 Max Unit
SPI INTERFACE TIMING CHARACTERISTICS6, 8,9 (Specifications Apply to All Parts)
Clock Frequency
fCLK
4 MHz
Input Clock Pulsewidth
tCH, tCL
Clock level high or low 120
ns
Data Setup Time
tDS
30 ns
Data Hold Time
tDH
20 ns
CLK to SDO Propagation Delay
tPD
RPU = 1K, CL < 20pF
10
100 ns
CS Setup Time
tCSS
120 ns
CS High Pulsewidth
tCSW
150 ns
CLK Fall to CS Fall Hold Time
tCSH0
TBD ns
CLK Fall to CS Rise Hold Time
tCSH1
120 ns
CS Rise to Clock Rise Setup
tCS1
120 ns
NOTES
1. Typical specifications represent average readings at +25°C and VDD = 5 V.
2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3. VAB = VDD, Wiper (VW) = no connect.
4. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA=VDD and VB=0 V.
5. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6. Guaranteed by design and not subject to production test.
7. PDISS is calculated from (IDD × VDD+ ISS × VSS) CMOS logic level inputs result in minimum power dissipation.
8. All dynamic characteristics use VDD / VSS = ±5 V.
9. See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V.
Rev. Pr C | Page 4 of 11


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ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C, unless otherwise noted.)
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
VA, VB, VW to GND
Maximum Current
IWB, IWA Pulsed
IWB Continuous (RWB ≤ 1 kΩ, A open)1
IWA Continuous (RWA ≤ 1 kΩ, B open)1
Digital Inputs Voltage to GND
Digital Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Value
–0.3 V to +33 V
–0.3 V to +33 V
+0.3 V to –16.5 V
VSS , VDD
±20 mA
±5 mA
±5 mA
VDD + 0.3 V
0 V, +30 V
–40°C to +105°C
150°C
AD5290
Storage Temperature
–65°C to +150°C
Lead Temperature (Soldering, 10 – 30 sec) 245°C
Thermal Resistance2 θJA: MSOP-10
230°C/W
NOTES
1 Maximum terminal current is bounded by the maximum current handling
of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Rev. Pr C | Page 5 of 11


AD5290 (Analog Devices)
Compact 30V/+-15V 256-Position Digital Potentiometer

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1
B2
VSS 3
GND 4
CS 5
10 W
9 VDD
AD5290 8 SDO
TOP VIEW 7 SDI
6 CLK
Figure 2. AD5290 Pin Configuration
AD5290
Table 7. AD5290 Pin Function Descriptions
Pin Menmonic
Description
1A
A Terminal. VSS VA VDD
2B
B Terminal. VSS VB VDD
3 VSS
Negative Supply. Connect to zero volts for single supply applications.
4 GND
Digital Ground.
5 CS
Chip Select Input, Active Low. When CS returns high, data will be loaded into the Wiper
Register
6 CLK
Serial Clock Input. Positive edge triggered
7 SDI
Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
8 SDO
Serial Data Output Pin. Internal N-Ch FET with open-drain output that requires external pull-
up resistor. It shifts out the previous 8 SDI bits that allows daisy-chain operation of multiple
packages
9 VDD
Positive Power Supply
10 W
W Terminal. VSS VW VDD
Rev. Pr C | Page 6 of 11


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SPI Interface
Table 4. AD5290 Serial Data-Word Format
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
27 20
AD5290
1
SDI
0
1
CLK
0
1
CS
0
1
VOUT
0
D7 D6 D5 D4 D3 D2 D1 D0
RDAC REGISTER LOAD
Figure 3. AD5290 SPI Interface Timing Diagram
(VA = VDD, VB = 0 V, VW = )VOUT
SDI
(DATA IN)
1
0
Dx
CLK
CS
1
0
tCSHO
tCSS
1
0
tCH
VDD
VOUT
0
Dx
tDS
tCL
tCH tCS1
tCSH1
tCSW
tS
±1LSB
Figure 2. SPI Interface Detailed Timing Diagram (VA = VDD, VB = 0 V, VW = )VOUT
Rev. Pr C | Page 7 of 11


AD5290 (Analog Devices)
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OPERATION
The AD5290 is a 256-position digitally controlled variable
resistor device that can be controlled digitally through SPI
interface.
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
DETERMINING THE VARIABLE RESISTANCE
AND VOLTAGE
Rheostat Mode Operation
If only the W-to-B or W-to-A terminals are used as variable
resistors, the unused terminal can be opened or shorted with W.
This operation is called rheostat mode (Figure 3).
A
W
A
W
A
W
BB
B
Figure 3. Rheostat Mode Configuration
The nominal resistance (RAB) of the RDAC has 256 contact
points accessed by the wiper terminal, plus the B terminal
contact if RWB is considered. The 8-bit data in the RDAC latch is
decoded to select one of the 256 settings. Assuming that a 10
kΩ part is used, the wiper’s first connection starts at the B
terminal for data 0x00. Such connection yields a minimum of
60 Ω resistance between terminals W and B because of the 60 Ω
wiper contact resistance. The second connection is the first tap
point, which corresponds to 99 Ω (RWB = (1) × RAB/256 + RW)
for data 0x01, and so on. Each LSB data value increase moves
the wiper up the resistor ladder until the last tap point is reached
at 10020 Ω ((255) × RAB/256 + RW). Figure 6 shows a simplified
diagram of the equivalent RDAC circuit. The general equation
determining RWB is
R
WB (D)
=
D
256
×
R AB
+
RW
where:
(1)
D is the decimal equivalent of the 8-bit binary code.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on-resistance of
the internal switch.
Table 1. RWB vs. Codes; RAB = 10 kΩ and
the A Terminal Is Opened
D (Dec) RWB (Ω) Output State
255
10020
Full-Scale (RAB + RW)
128
5060
Midscale
1 99 1 LSB
0 60 Zero-Scale (Wiper Contact Resistance)
AD5290
Since a finite wiper resistance of 60 Ω is present in the zero-
scale condition, care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
complementary resistance RWA. When these terminals are used,
the B terminal can be opened or shorted to W. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
R WA
(D)
=
256 D
256
×
R AB
+
RW
Table 2. RWA vs. Codes; RAB =10 kΩ and
B Terminal Is Opened
D (Dec) RWA (Ω) Output State
255 60 Full-Scale
128
5060
Midscale
1 10020 1 LSB
0 10060 Zero-Scale
(2)
The typical distribution of the resistance tolerance from device
to device is process lot dependent, and it is possible to have
±30% tolerance.
A
RS
D7
D6
D5
RS
D4
D3
D2 RS
D1
D0
W
RDAC
LATCH
AND
RS
DECODER
RW
B
Figure 6. AD5290 Equivalent RDAC Circuit
Potentiometer Mode Operation
If all three terminals are used, the operation is called the
potentiometer mode. The most common configuration is the
voltage divider operation (Figure 7).
Rev. Pr C | Page 8 of 11


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VI
A
W VO
B
AD5290
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5290 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS returns to logic high. If
dataword contains more than 8-bit, the extra MSB bits will be
ignored.
Figure 7. Potentiometer Mode Configuration
Ignoring the effect of the wiper resistance, the transfer function
is simply
VW (D)
=
D
256
VA
A more accurate calculation, which includes the wiper
resistance effect, yields
(3)
VW (D)
=
D
256
R AB
+
RW
RAB + 2R W
VA
(4)
If there is an applied voltage at the B terminal, then the transfer
function becomes
VW
(D )
=
D
256
V
A
+
256 D
256
VB
(5)
Unlike in rheostat mode operation where the absolute tolerance
is high, potentiometer mode operation yields an almost ratio-
metric function of D/256 with a relatively small error contributed
by the RW terms, and therefore the tolerance effect is almost
cancelled. Although the thin film step resistor RS and CMOS
switches resistance RW have very different temperature coeffi-
cients, the ratiometric adjustment also reduces the overall
temperature coefficient effect to 5 ppm/°C, except at low value
codes where RW dominates.
Potentiometer mode operations include others such as op amp
input, feedback resistor networks, and other voltage scaling
applications. A, W, and B terminals can in fact be input or
output terminals provided that |VA|, |VW|, and |VB| do not
exceed |VDD| and |VSS|.
SPI COMPATIBLE 3-WIRE SERIAL BUS
The AD5290 contains a 3-wire SPI compatible digital interface
(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in Table .
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. CS should start high, when it
goes low, the clock loads data into the serial register on each
positive clock edge (see Figure 3).
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in 8 and Figure 9. This
applies to the digital input pins SDI, CLK, and CS.
340
LOGIC
VSS
Figure 8. ESD Protection of Digital Pins
A,B,W
VSS
Figure 9. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5290 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed VDD or GND will be clamped by the internal forward
biased diodes (see Figure 10).
VDD
A
W
B
VSS
Figure 10. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 10), it is important to power
VDD–to-GND and VSS-to-GND before applying any voltage to
terminals A, B, and W; otherwise, the diode will be forward
biased such that VDD will be powered unintentionally and may
affect the rest of the user’s circuit. The ideal power-up sequence
is in the following order: GND, VSS,VDD, digital inputs, and then
Rev. Pr C | Page 9 of 11


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VA/B/W. The relative order of powering VA, VB, VW, and the
digital inputs is not important as long as they are powered after
VDD and VSS with respect to GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic
capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 4). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
AD5290
m
uC MOSI
SCLK SS
AD5290
VDD
AD5290
U1
SDI SDO
CS CLK
Rp AD5290
2.2K
U2
SDI SDO
CS CLK
Figure 12. Daisy Chain Configuration
Figure 4. Power Supply Bypassing
DAISY CHAIN OPERATION
The serial data output pin (SDO) can be used to daisy chain
multiple devices for simultaneous operations, see Figure 12. The
SDO pin contains an open drain N-Ch FET and requires a pull-
up resistor. Users need to tie the SDO pin of one package to the
SDI pin of the next package. If many devices are daisy-chained,
users may need to increase the clock period to accommodate
the time delay introduced by the pull-up resistors and the
capacitive loading at the SDO-SDI interface, see Figure 12.
If two AD5290 are daisy chained, this requires total 16 bits of
data. The first 8 bits goes to U2 and the second 8 bits goes to
U1. The CS should be kept low until all 16 bits are clocked into
their respective serial registers. The CS is then pulled high to
complete the operation.
Rev. Pr C | Page 10 of 11


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OUTLINE DIMENSIONS
3.00 BSC
10
3.00 BSC
1
6
4.90 BSC
5
PIN 1
0.95
0.85
0.75
0.50 BSC
1.10 MAX
0.15
0.00
0.27
0.17
COPLANARITY
0.10
SEATING 0.23
PLANE 0.08
COMPLIANT TO JEDEC STANDARDS MO-187BA
0.80
0.60
0.40
Figure 5. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
AD5290
Ordering Guide
Model1
RAB (kΩ) Temperature Range
AD5290YRMZ10
10 –40°C to +105°C
AD5290YRMZ10-RL7
10
–40°C to +105°C
AD5290YRMZ50
50 –40°C to +105°C
AD5290YRMZ50-RL7
50
–40°C to +105°C
AD5290YRMZ100
100 –40°C to +105°C
AD5290YRMZ100-RL7
100
–40°C to +105°C
AD5290EVAL
NOTES:
1. Z in Model Number denotes Lead Free Package
Package Description
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
Evaluation Board
Package Option
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
Branding
D4U
D4U
D4T
D4T
D4V
D4V
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. Pr C | Page 11 of 11




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