LTC2242-10 (Linear Technology)
250Msps ADC

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LTC2242-10
10-Bit, 250Msps ADC
FEATURES
wwwn.daStaashmeeptl4eu.cRoamte: 250Msps
n 60.5dB SNR
n 78dB SFDR
n 1.2GHz Full Power Bandwidth S/H
n Single 2.5V Supply
n Low Power Dissipation: 740mW
n LVDS, CMOS, or Demultiplexed CMOS Outputs
n Selectable Input Ranges: ±0.5V or ±1V
n No Missing Codes
n Optional Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Data Ready Output Clock
n Pin Compatible Family
250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit)
210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit)
170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit)
185Msps: LTC2220-1 (12-Bit)*
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)*
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*
n 64-Pin 9mm × 9mm QFN Package
APPLICATIONS
n Wireless and Wired Broadband Communication
n Cable Head-End Systems
n Power Amplifier Linearization
n Communications Test Equipment
DESCRIPTION
The LTC®2242-10 is a 250Msps, sampling 10-bit A/D con-
verter designed for digitizing high frequency, wide dynamic
range signals. The LTC2240-10 is perfect for demanding
communications applications with AC performance that
includes 60.5dB SNR and 78dB SFDR. Ultralow jitter of
95fsRMS allows IF undersampling with excellent noise
performance.
DC specs include ±0.4LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data
rate or two demultiplexed buses running at half data rate
with either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 2.625V.
The ENC+ and ENCinputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance over a wide range of clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
*LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.
TYPICAL APPLICATION
REFH
REFL
ANALOG
INPUT
FLEXIBLE
REFERENCE
+
INPUT
S/H
CLOCK/DUTY
CYCLE
CONTROL
ENCODE
INPUT
2.5V
VDD
10-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
0.5V
TO 2.625V
OVDD
D9
• CMOS
• OR
• LVDS
D0
OGND
224210 TA01
SFDR vs Input Frequency
85
80
75
70
65
1V RANGE
60
2V RANGE
55
50
45
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
224210 G11
224210fc
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LTC2242-10 (Linear Technology)
250Msps ADC

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LTC2242-10
ABSOLUTE MAXIMUM RATINGS
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ...............................................2.8V
wwwD.diagtaitsahleOetu4utp.cuomt Ground Voltage (OGND) ........ –0.3V to 1V
Analog Input Voltage (Note 3).......–0.3V to (VDD + 0.3V)
Digital Input Voltage......................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation .............................................1500mW
Operating Temperature Range
LTC2242C-10 ........................................... 0°C to 70°C
LTC2242I-10 ........................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
AIN+ 1
AIN+ 2
AIN– 3
AIN– 4
REFHA 5
REFHA 6
REFLB 7
REFLB 8
REFHB 9
REFHB 10
REFLA 11
REFLA 12
VDD 13
VDD 14
VDD 15
GND 16
65
48 D7+/DA4
47 D7/DA3
46 D6+/DA2
45 D6/DA1
44 D5+/DA0
43 D5/DNC
42 OVDD
41 OGND
40 D4+/DNC
39 D4/CLKOUTA
38 D3+/CLKOUTB
37 D3/OFB
36 CLKOUT+/DB9
35 CLKOUT/DB8
34 OVDD
33 OGND
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 20°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2242CUP-10#PBF
LTC2242CUP-10#TRPBF LTC2242UP-10
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2242IUP-10#PBF
LTC2242IUP-10#TRPBF LTC2242UP-10
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2242CUP-10#PBF
LTC2242CUP-10#TR
LTC2242UP-10
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2242IUP-10#PBF
LTC2242IUP-10#TR
LTC2242UP-10
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
CONDITIONS
Differential Analog Input (Note 5)
Differential Analog Input
(Note 6)
External Reference
MIN TYP MAX
10
–1 ±0.4 1
–0.7 ±0.2 0.7
–17 ±5 17
–3.5 ±0.7 3.5
UNITS
Bits
LSB
LSB
mV
%FS
224210fc
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LTC2242-10 (Linear Technology)
250Msps ADC

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LTC2242-10
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Offset Drift
www.datasheet4u.com
Full-Scale Drift
Internal Reference
External Reference
±10 μV/C
±60 ppm/C
±45 ppm/C
Transition Noise
SENSE = 1V
0.18 LSBRMS
ANALOG INPUT The denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
VIN
VIN, CM
IIN
ISENSE
IMODE
ILVDS
tAP
tJITTER
PARAMETER
Analog Input Range (AIN+ – AIN–)
Analog Input Common Mode (AIN+ + AIN–)/2
Analog Input Leakage Current
SENSE Input Leakage
MODE Pin Pull-Down Current to GND
LVDS Pin Pull-Down Current to GND
Sample and Hold Acquisition Delay Time
Sample and Hold Acquisition Delay Time Jitter
Full Power Bandwidth
CONDITIONS
2.375V < VDD < 2.625V (Note 7)
Differential Input (Note 7)
0 < AIN+, AIN– < VDD
0V < SENSE < 1V
Figure 8 Test Circuit
MIN TYP MAX UNITS
±0.5 to ±1
V
1.2
1.25 1.3
V
–1
1 μA
–1
1 μA
7 μA
7 μA
0.4 ns
95
1200
fsRMS
MHz
DYNAMIC ACCURACY The denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
SNR
Signal-to-Noise Ratio (Note 10)
10MHz Input
60.6 dB
70MHz Input
l 59.2 60.5
dB
140MHz Input
60.5 dB
240MHz Input
60.4 dB
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic
(Note 11)
10MHz Input
70MHz Input
140MHz Input
l 63
78
75
74
dB
dB
dB
240MHz Input
73 dB
Spurious Free Dynamic Range
4th Harmonic or Higher
(Note 11)
10MHz Input
70MHz Input
140MHz Input
l 71
85
85
85
dB
dB
dB
240MHz Input
85 dB
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
(Note 12)
10MHz Input
70MHz Input
140MHz Input
l 58.2
60.4
60.4
60.3
dB
dB
dB
240MHz Input
60.2 dB
IMD
Intermodulation Distortion
fIN1 = 135MHz, fIN2 = 140MHz
81 dBc
224210fc
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LTC2242-10 (Linear Technology)
250Msps ADC

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LTC2242-10
INTERNAL REFERENCE CHARACTERISTICS (Note 4)
PARAMETER
VCM Output Voltage
wwwV.dCaMtaOsuhtepeutt4Tue.mcopmco
VCM Line Regulation
VCM Output Resistance
CONDITIONS
IOUT = 0
2.375V < VDD < 2.625V
–1mA < IOUT < 1mA
MIN TYP MAX
UNITS
1.225 1.25 1.275
V
±35 ppm/°C
3 mV/V
DIGITAL INPUTS AND DIGITAL OUTPUTS The denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
ENCODE INPUTS (ENC+, ENC)
CONDITIONS
MIN TYP MAX
UNITS
VID
Differential Input Voltage
(Note 7)
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 7)
0.2
1.2
1.5
1.5
2.0
V
V
V
RIN Input Resistance
CIN Input Capacitance
LOGIC INPUTS (OE, SHDN)
(Note 7)
4.8 kΩ
2 pF
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIN Input Current
CIN Input Capacitance
LOGIC OUTPUTS (CMOS MODE)
VDD = 2.5V
VDD = 2.5V
VIN = 0V to VDD
(Note 7)
1.7
–10
3
0.7
10
V
V
μA
pF
OVDD = 2.5V
COZ
ISOURCE
ISINK
VOH
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
High Level Output Voltage
VOL Low Level Output Voltage
OVDD = 1.8V
VOH High Level Output Voltage
VOL Low Level Output Voltage
LOGIC OUTPUTS (LVDS MODE)
OE = High (Note 7)
VOUT = 0V
VOUT = 2.5V
IO = –10μA
IO = –500μA
IO = 10μA
IO = 500μA
IO = –500μA
IO = 500μA
3
37
23
2.495
2.45
0.005
0.07
1.75
0.07
pF
mA
mA
V
V
V
V
V
V
VOD
Differential Output Voltage
100Ω Differential Load
VOS
Output Common Mode Voltage
100Ω Differential Load
247
1.125
350
1.250
454
1.375
mV
V
224210fc
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LTC2242-10 (Linear Technology)
250Msps ADC

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LTC2242-10
POWER REQUIREMENTS The denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VDD Analog Supply Voltage
wwwP.dSaLEtaEPsheet4u.cSolmeep Mode Power
PNAP Nap Mode Power
LVDS OUTPUT MODE
(Note 8)
SHDN = High, OE = High, No CLK
SHDN = High, OE = Low, No CLK
2.375
2.5
1
28
2.625
V
mW
mW
OVDD
IVDD
Output Supply Voltage
Analog Supply Current
(Note 8)
2.375
2.5
285
2.625
320
V
mA
IOVDD
PDISS
Output Supply Current
Power Dissipation
58 70
mA
858 975
mW
CMOS OUTPUT MODE
OVDD
IVDD
Output Supply Voltage
Analog Supply Current
(Note 8)
(Note 7)
0.5
2.5 2.625
285 320
V
mA
PDISS
Power Dissipation
740 mW
TIMING CHARACTERISTICS The denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fS Sampling Frequency
tL ENC Low Time (Note 7)
(Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
1
250
1.9 2 500
1.5 2 500
MHz
ns
ns
tH ENC High Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
1.9 2 500
1.5 2 500
ns
ns
tAP Sample-and-Hold Aperture Delay
0.4 ns
tOE Output Enable Delay
LVDS OUTPUT MODE
tD ENC to DATA Delay
tC ENC to CLKOUT Delay
DATA to CLKOUT Skew
Rise Time
Fall Time
Pipeline Latency
CMOS OUTPUT MODE
tD ENC to DATA Delay
tC ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline
Latency
Full Rate CMOS
Demuxed Interleaved
Demuxed Simultaneous
(Note 7)
(Note 7)
(Note 7)
(tC – tD) (Note 7)
(Note 7)
(Note 7)
(tC – tD) (Note 7)
5 10
1
1
–0.6
1.7
1.7
0
0.5
0.5
5
2.8
2.8
0.6
1
1
–0.6
1.7
1.7
0
5
2.8
2.8
0.6
5
5 and 6
ns
ns
ns
ns
ns
ns
Cycles
ns
ns
ns
Cycles
Cycles
Cycles
224210fc
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LTC2242-10 (Linear Technology)
250Msps ADC

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LTC2242-10
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
wwwr.edlaiatbaislihtyeeant4dul.icfeotmime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 2.5V, fSAMPLE = 250MHz, LVDS outputs, differential
ENC+/ENC= 2VP-P sine wave, input range = 2VP-P with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from
a “best straight line” fit to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 and 11 1111 1111 in 2’s
complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
Note 9: VDD = 2.5V, fSAMPLE = 250MHz, differential ENC+/ENC= 2VP-P
sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF.
Note 10: SNR minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.2dB lower.
Note 11: SFDR minimum values are for LVDS mode. Typical values are for
both LVDS and CMOS modes.
Note 12: SINAD minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.2dB lower.
TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C unless otherwise noted, Note 4)
Integral Nonlinearity
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
256 512 768
OUTPUT CODE
1024
224210 G01
Differential Nonlinearity
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
256 512 768
OUTPUT CODE
1024
224210 G02
8192 Point FFT, fIN = 5MHz,
–1dB, 2V Range, LVDS Mode
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
20 40 60 80 100 120
FREQUENCY (MHz)
224210 G03
224210fc
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250Msps ADC

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LTC2242-10
TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C unless otherwise noted, Note 4)
8192 Point FFT, fIN = 70MHz,
–1dB, 2V Range, LVDS Mode
www.datas0heet4u.com
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
20 40 60 80 100 120
FREQUENCY (MHz)
224210 G04
8192 Point FFT, fIN = 500MHz,
–1dB, 1V Range, LVDS Mode
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
20 40 60 80 100 120
FREQUENCY (MHz)
224210 G07
SNR vs Input Frequency, –1dB,
LVDS Mode
62
61
2V RANGE
60
59
58 1V RANGE
57
56
55
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
224210 G10
8192 Point FFT, fIN = 140MHz,
–1dB, 2V Range, LVDS Mode
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
20 40 60 80 100 120
FREQUENCY (MHz)
224210 G05
8192 Point FFT, fIN = 1GHz,
–1dB, 1V Range, LVDS Mode
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
20 40 60 80 100 120
FREQUENCY (MHz)
224210 G08
SFDR (HD2 and HD3) vs Input
Frequency, –1dB, LVDS Mode
85
80
75
70
65
1V RANGE
60
2V RANGE
55
50
45
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
224210 G11
8192 Point FFT, fIN = 240MHz,
–1dB, 2V Range, LVDS Mode
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
20 40 60 80 100 120
FREQUENCY (MHz)
224210 G06
8192 Point 2-Tone FFT,
fIN = 135MHz and 140MHz,
–1dB, 2V Range, LVDS Mode
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
20 40 60 80 100 120
FREQUENCY (MHz)
224210 G09
SFDR (HD4+) vs Input Frequency,
–1dB, LVDS Mode
95
90
85 1V RANGE
2V RANGE
80
75
70
65
60
0 100 200 300 400 500 600 700 800 9001000
INPUT FREQUENCY (MHz)
224210 G12
224210fc
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LTC2242-10 (Linear Technology)
250Msps ADC

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LTC2242-10
TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C unless otherwise noted, Note 4)
SFDR and SNR vs Sample Rate,
2V Range, fIN = 30MHz, –1dB,
LVDS Mode
www.data9s0heet4u.com
85
SFDR
80
75
70
65
SNR
60
55
0 50 100 150 200 250 300
SAMPLE RATE (Msps)
224210 G13
SFDR vs Input Level, fIN = 70MHz,
2V Range
90
80
dBFS
70
60
50
dBc
40
30
20
10
0
–50
–40 –30 –20 –10
INPUT LEVEL (dBFS)
0
224210 G14
SNR vs SENSE, fIN = 5MHz, –1dB
61.0
60.5
60.0
59.5
59.0
58.5
58.0
57.5
0.5
0.6 0.7 0.8 0.9
SENSE PIN (V)
1
224210 G15
IVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
300
290
280
2V RANGE
270
1V RANGE
260
250
240
230
220
0
50 100 150 200
SAMPLE RATE (Msps)
250
224210 G16
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
60
50
LVDS OUTPUTS
OVDD = 2.5V
40
30
20
CMOS OUTPUTS
OVDD = 1.8V
10
0
0 50 100 150 200 250
SAMPLE RATE (Msps)
224210 G17
224210fc
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250Msps ADC

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LTC2242-10
PIN FUNCTIONS (CMOS Mode)
AIN+ (Pins 1, 2): Positive Differential Analog Input.
AIN– (Pins 3, 4): Negative Differential Analog Input.
wwwR.dEatFaHshAeet(4Pui.cnosm 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11,
12 with a 2.2μF ceramic capacitor and to ground with 1μF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins
5, 6 with 0.1μF ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5,
6 with a 2.2μF ceramic capacitor and to ground with 1μF
ceramic capacitor.
VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC+ (Pin 17): Encode Input. Conversion starts on the
positive edge.
ENC(Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1μF
ceramic for single-ended encode signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation
high impedance. Connecting SHDN to
with the
VDD and
outputs at
OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin function.
DNC (Pins 21, 22, 40, 43): Do not connect these pins.
DB0-DB9 (Pins 23, 24, 27, 28, 29, 30, 31, 32, 35, 36):
Digital Outputs, B Bus. DB9 is the MSB. At high impedance
in full rate CMOS mode.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OVDD (Pins 26, 34, 42, 49): Positive Supply for the
Output Drivers. Bypass to ground with 0.1μF ceramic chip
capacitor.
OFB (Pin 37): Over/Under Flow Output for B Bus. High
when an over or under flow has occurred. At high imped-
ance in full rate CMOS mode.
CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux
mode with interleaved update, latch B bus data on the fall-
ing edge of CLKOUTB. In demux mode with simultaneous
update, latch B bus data on the rising edge of CLKOUTB.
This pin does not become high impedance in full rate
CMOS mode.
CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A
bus data on the falling edge of CLKOUTA.
DA0-DA9 (Pins 44, 45, 46, 47, 48, 51, 52, 53, 54, 55):
Digital Outputs, A Bus. DA9 is the MSB.
OFA (Pin 56): Over/Under Flow Output for A Bus. High
when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demux CMOS mode with simultaneous
update. Connecting LVDS to 2/3VDD selects demux CMOS
mode with interleaved update. Connecting LVDS to VDD
selects LVDS mode.
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3VDD selects offset
binary output format and turns the clock duty cycle stabilizer
on. Connecting MODE to 2/3VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer on.
Connecting MODE to VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. Connecting SENSE to VDD selects the internal
reference and a ±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of ±VSENSE. ±1V is the largest valid
input range.
VCM (Pin 60): 1.25V Output and Input Common Mode Bias.
Bypass to ground with 2.2μF ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
224210fc
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250Msps ADC

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LTC2242-10
PIN FUNCTIONS (LVDS Mode)
AIN+ (Pins 1, 2): Positive Differential Analog Input.
AIN(Pins 3, 4): Negative Differential Analog Input.
wwwR.dEatFaHshAeet(4Pui.cnosm 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11,
12 with a 2.2μF ceramic capacitor and to ground with 1μF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins
5, 6 with 0.1μF ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5,
6 with a 2.2μF ceramic capacitor and to ground with 1μF
ceramic capacitor.
VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC+ (Pin 17): Encode Input. Conversion starts on the
positive edge.
ENC(Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1μF
ceramic for single-ended encode signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation with the outputs at
high impedance. Connecting SHDN to VDD and OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin function.
DNC (Pins 21, 22, 23, 24): Do not connect these pins.
D0/D0+ to D9/D9+ (Pins 27, 28, 29, 30, 31, 32, 37,
38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54):
LVDS Digital Outputs. All LVDS outputs require differential
100Ω termination resistors at the LVDS receiver. D9/D9+
is the MSB.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OVDD (Pins 26, 34, 42, 49): Positive Supply for the Out-
put Drivers. Bypass to ground with 0.1μF ceramic chip
capacitor.
CLKOUT/CLKOUT+ (Pins 35 to 36): LVDS Data Valid
Output. Latch data on rising edge of CLKOUT, falling
edge of CLKOUT+.
OF/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output.
High when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demux CMOS mode with simultaneous
update. Connecting LVDS to 2/3VDD selects demux CMOS
mode with interleaved update. Connecting LVDS to VDD
selects LVDS mode.
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3VDD selects offset
binary output format and turns the clock duty cycle stabilizer
on. Connecting MODE to 2/3VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer on.
Connecting MODE to VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. Connecting SENSE to VDD selects the internal
reference and a ±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of ±VSENSE. ±1V is the largest valid
input range.
VCM (Pin 60): 1.25V Output and Input Common Mode Bias.
Bypass to ground with 2.2μF ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
10
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250Msps ADC

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FUNCTIONAL BLOCK DIAGRAM
LTC2242-10
www.datashAeINe+ t4u.com
INPUT
AIN– S/H
VCM
2.2μF
1.25V
REFERENCE
RANGE
SELECT
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
VDD
GND
SHIFT REGISTER
AND CORRECTION
SENSE
REF
BUF
REFH
REFL INTERNAL CLOCK SIGNALS
DIFFERENTIAL
DIFF
REF
AMP
INPUT
LOW JITTER
CLOCK
CONTROL
LOGIC
DRIVER
REFLB REFHA
2.2μF
0.1μF
1μF
REFLA REFHB
0.1μF ENC+
1μF
ENC
M0DE LVDS SHDN OE
OUTPUT
DRIVERS
OVDD
+
+–
OF
D9
+
–+
D0
CLKOUT
OGND
224210 F01
Figure 1. Functional Block Diagram
224210fc
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250Msps ADC

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LTC2242-10
TIMING DIAGRAMS
LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
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ANALOG
INPUT
ENC
ENC+
D0-D9, OF
CLKOUT
CLKOUT+
tAP
N
tH N + 1
tL
N+2
N+3
N+4
tD
N–5
tC
N–4
N–3
N–2
N–1
224210 TD01
ANALOG
INPUT
ENC
ENC+
DA0-DA9, OFA
CLKOUTB
CLKOUTA
DB0-DB9, OFB
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
N
tH N + 1
tL
N+2
N+3
N+4
tD
N–5
tC
N–4
N–3
N–2
N–1
HIGH IMPEDANCE
224210 TD02
12
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250Msps ADC

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LTC2242-10
TIMING DIAGRAMS
Demultiplexed CMOS Outputs with Interleaved Update
All Outputs Are Single-Ended and Have CMOS Levels
www.datasheet4u.com
ANALOG
INPUT
ENC
ENC+
DA0-DA9, OFA
DB0-DB9, OFB
tAP
N
tH N + 1
tL
N+2
tD
N–6
N–5
tD
N–4
N+3
N+4
N–3
N–1
N–2
tC tC
CLKOUTB
CLKOUTA
224210 TD03
Demultiplexed CMOS Outputs with Simultaneous Update
All Outputs Are Single-Ended and Have CMOS Levels
ANALOG
INPUT
ENC
ENC+
DA0-DA9, OFA
DB0-DB9, OFB
CLKOUTB
CLKOUTA
tAP
N
tH N + 1
tL
tD
N–6
tD
N–5
tC
N+2
N+3
N–4
N–3
N+4
N–2
N–1
224210 TD04
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250Msps ADC

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LTC2242-10
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
wwwS.diagtansahle-etto4-uN.coomise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamen-
tal input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula-
tion distortion is defined as the ratio of the RMS value of
either input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or spuri-
ous noise that is the largest spectral component excluding
the input signal and DC. This value is expressed in decibels
relative to the RMS value of a full scale input signal.
Full Power Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
( )THD = 20Log⎛⎝⎜ V22 + V32 + V42 + ...Vn2 / V1⎞⎠⎟
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the second
through nth harmonics. The THD calculated in this data
sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are ap-
plied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n = 0,
1, 2, 3, etc. The 3rd order intermodulation products are
Aperture Delay Time
The time from when a rising ENC+ equals the ENCvoltage
to the instant that the input signal is held by the sample
and hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
CONVERTER OPERATION
As shown in Figure 1, the LTC2242-10 is a CMOS pipelined
multi-step converter. The converter has five pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section). For
optimal performance the analog inputs should be driven
differentially. The encode input is differential for improved
common mode noise immunity. The LTC2242-10 has two
phases of operation, determined by the state of the dif-
ferential ENC+/ENCinput pins. For brevity, the text will
refer to ENC+ greater than ENCas ENC high and ENC+
less than ENCas ENC low.
14
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250Msps ADC

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LTC2242-10
APPLICATIONS INFORMATION
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
wwwI.dnaotapseheraett4iou.nc,omthe ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input is
held. While ENC is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H dur-
ing this high phase of ENC. When ENC goes back low, the
first stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When ENC goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third and fourth stages, resulting in a fourth stage residue
that is sent to the fifth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2242-10
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (CSAMPLE) through
NMOS transistors. The capacitors shown attached to
each input (CPARASITIC) are the summation of all other
capacitance associated with each input.
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
When ENC transitions from low to high, the sampled input
LTC2242-10
VDD
10Ω
AIN+
VDD
10Ω
AIN–
VDD
CPARASITIC
1.8pF
CPARASITIC
1.8pF
RON
CSAMPLE
2pF
14Ω
CSAMPLE
RON 2pF
14Ω
ENC+
ENC
1.5V
6k
6k
1.5V
Figure 2. Equivalent Input Circuit
224210 F02
voltage is held on the sampling capacitors. During the
hold phase when ENC is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such
as the change seen with input frequencies near Nyquist,
then a larger charging glitch will be seen.
Common Mode Bias
For optimal performance the analog inputs should be driven
differentially. Each input should swing ±0.5V for the 2V
range or ±0.25V for the 1V range, around a common mode
voltage of 1.25V. The VCM output pin (Pin 60) may be used
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
224210fc
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250Msps ADC

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LTC2242-10
APPLICATIONS INFORMATION
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with a 2.2μF or greater capacitor.
www.datasheet4u.com
Input Drive Impedance
As with all high performance, high speed ADCs, the dy-
namic performance of the LTC2242-10 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR. At the falling edge of ENC, the
sample-and-hold circuit will connect the 2pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge the
sampling capacitor during the sampling period 1/(2fS);
however, this is not always possible and the incomplete
settling may degrade the SFDR. The sampling glitch has
been designed to be as linear as possible to minimize the
effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2242-10 being driven by an RF
transformer with a center tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen
by the ADC does not exceed 100Ω for each ADC input.
A disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of most op amps will limit the SFDR at high
input frequencies.
Figure 5 shows a capacitively-coupled input circuit. The im-
pedance seen by the analog inputs should be matched.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from
10Ω
0.1μF T1
ANALOG
1:1
INPUT
25Ω
25Ω 0.1μF
25Ω 25Ω
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
VCM
2.2μF
AIN+
AIN+
12pF
AIN–
AIN–
LTC2242-10
224210 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
50Ω
ANALOG
INPUT
0.1μF
HIGH SPEED
DIFFERENTIAL
AMPLIFIER 25Ω
++
CM
––
3pF
25Ω
3pF
VCM
2.2μF
AIN+
AIN+
12pF
AIN–
AIN–
LTC2242-10
224210 F04
Figure 4. Differential Drive with an Amplifier
0.1μF
100Ω 100Ω
25Ω
ANALOG
INPUT
0.1μF
25Ω
VCM
2.2μF
AIN+
LTC2242-10
AIN+
12pF AIN
AIN
224210 F05
Figure 5. Capacitively-Coupled Drive
16
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250Msps ADC

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APPLICATIONS INFORMATION
the sample-and-hold charging glitches and limiting the
wideband noise at the converter input. For input frequen-
wwwc.dieatsashhiegeht4eur.ctohman 100MHz, the capacitor may need to be
decreased to prevent excessive signal loss.
The AIN+ and AIN– inputs each have two pins to reduce
package inductance. The two AIN+ and the two AIN– pins
should be shorted together.
For input frequencies above 100MHz the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer
gives better high frequency response than a flux coupled
center tapped transformer. The coupling capacitors allow
the analog inputs to be DC biased at 1.25V. In Figure 8 the
series inductors are impedance matching elements that
maximize the ADC bandwidth.
Reference Operation
Figure 9 shows the LTC2242-10 reference circuitry consist-
ing of a 1.25V bandgap reference, a difference amplifier
and switching and control circuit. The internal voltage
reference can be configured for two pin selectable input
ranges of 2V (±1V differential) or 1V (±0.5V differential).
Tying the SENSE pin to VDD selects the 2V range; typing
the SENSE pin to VCM selects the 1V range.
The 1.25V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required
for the 1.25V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifier generates the high and low
reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has four pins: two each of REFHA
and REFHB for the high reference and two each of REFLA
and REFLB for the low reference. The multiple output pins
are needed to reduce package inductance. Bypass capaci-
tors must be connected as shown in Figure 9.
LTC2242-10
10Ω
0.1μF
ANALOG
INPUT
0.1μF
T1
12Ω
25Ω 0.1μF
25Ω 12Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
VCM
2.2μF
AIN+
AIN+
8pF
AIN–
AIN–
LTC2242-10
224210 F06
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 100MHz and 250MHz
10Ω
0.1μF
ANALOG
INPUT
0.1μF
T1
25Ω 0.1μF
25Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
VCM
2.2μF
AIN+
AIN+ LTC2242-10
AIN–
AIN–
224210 F07
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 250MHz and 500MHz
10Ω
0.1μF
ANALOG
INPUT
0.1μF
T1
2.7nH
25Ω 0.1μF
25Ω 2.7nH
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
VCM
2.2μF
AIN+
AIN+ LTC2242-10
AIN–
AIN–
224210 F08
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 500MHz
224210fc
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250Msps ADC

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LTC2242-10
APPLICATIONS INFORMATION
1.25V
www.datasheet4u.com
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
1μF
LTC2242-10
VCM
2.2μF
2Ω 1.25V BANDGAP
REFERENCE
1V 0.5V
SENSE
REFLB
0.1μF
REFHA
RANGE
DETECT
AND
CONTROL
BUFFER
INTERNAL ADC
HIGH REFERENCE
the SENSE pin is driven externally, it should be bypassed
to ground as close to the device as possible with a 1μF
ceramic capacitor.
Input Range
The input range can be set based on the application.
The 2V input range will provide the best signal-to-noise
performance while maintaining excellent SFDR. The 1V
input range will have better SFDR performance, but the
SNR will degrade by 1.7dB. See the Typical Performance
Characteristics section.
2.2μF
1μF
REFLA
0.1μF
REFHB
DIFF AMP
INTERNAL ADC
LOW REFERENCE
224210 F09
Figure 9. Equivalent Reference Circuit
1.25V
8k
0.75V
12k
VCM
2.2μF
SENSE LTC2242-10
1μF
224210 F10
Figure 10. 1.5V Range ADC
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by ap-
plying its output directly or through a resistor divider to
SENSE. It is not recommended to drive the SENSE pin
with a logic device. The SENSE pin should be tied to the
appropriate level as close to the converter as possible. If
Driving the Encode Inputs
The noise performance of the LTC2242-10 can depend
on the encode signal quality as much as on the analog
input. The ENC+/ENCinputs are intended to be driven
differentially, primarily for noise immunity from com-
mon mode noise sources. Each input is biased through
a 4.8k resistor to a 1.5V bias. The bias resistors set the
DC operating point for transformer coupled drive circuits
and can set the logic threshold for single-ended drive
circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the ampli-
tude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at both
inputs as common mode noise. The encode inputs have a
common mode range of 1.2V to 2.0V. Each input may be
driven from ground to VDD for single-ended drive.
18
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APPLICATIONS INFORMATION
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LTC2242-10
VDD
CLOCK
INPUT
T1
MA/COM
0.1μF ETC1-1-13
••
50Ω
0.1μF
50Ω
ENC+
8.2pF 100Ω
0.1μF
ENC–
VDD 1.5V BIAS
4.8k
VDD 1.5V BIAS
4.8k
Figure 11. Transformer Driven ENC+/ENC
LTC2242-10
TO INTERNAL
ADC CIRCUITS
224210 F11
VTHRESHOLD = 1.5V
ENC+
1.5V ENCLTC2242-10
0.1μF
224210 F12a
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
LVDS
CLOCK
0.1μF
ENC+
100Ω 0.1μF
LTC2242-10
ENC
224210 F12b
Figure 12b. ENC Drive Using LVDS
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2242-10 is 250Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 1.9ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used if
the input clock has a non 50% duty cycle. This circuit uses
the rising edge of the ENC+ pin to sample the analog input.
The falling edge of ENC+ is ignored and the internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 40% to 60% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2242-10 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTC2242-10 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
224210fc
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250Msps ADC

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LTC2242-10
APPLICATIONS INFORMATION
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
www.dat(a2sVheReatn4gue.c) om
>+1.000000V
+0.998047V
+0.996094V
OF
1
0
0
D9 – D0
(Offset Binary)
11 1111 1111
11 1111 1111
11 1111 1110
+0.001953V
0.000000V
–0.001953V
–0.003906V
0
0
0
0
10 0000 0001
10 0000 0000
01 1111 1111
01 1111 1110
–0.998047V
–1.000000V
<–1.000000V
0
0
1
00 0000 0001
00 0000 0000
00 0000 0000
D9 – D0
(2’s Complement)
01 1111 1111
01 1111 1111
01 1111 1110
00 0000 0001
00 0000 0000
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
10 0000 0000
Digital Output Modes
The LTC2242-10 can operate in several digital output
modes: LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternate clock cycles (interleaved mode) or simultaneously
(simultaneous mode). For details on the clock timing, refer
to the timing diagrams.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should
be connected to GND, 1/3VDD, 2/3VDD or VDD. An external
resistor divider can be used to set the 1/3VDD or 2/3VDD
logic values. Table 2 shows the logic states for the LVDS
pin.
Table 2. LVDS Pin Function
LVDS
DIGITAL OUTPUT MODE
GND Full-Rate CMOS
1/3VDD
Demultiplexed CMOS, Simultaneous Update
2/3VDD
Demultiplexed CMOS, Interleaved Update
VDD LVDS
Digital Output Buffers (CMOS Modes)
Figure 13a shows an equivalent circuit for a single
output buffer in the CMOS output mode. Each buffer is
powered by OVDD and OGND, which are isolated from the
ADC power and ground. The additional N-channel transistor
in the output driver allows operation down to voltages as
low as 0.5V. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2242-10 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an 74VCX245
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Digital Output Buffers (LVDS Mode)
Figure 13b shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT+ to OUTor vice versa which creates a
±350mV differential voltage across the 100Ω termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100Ω
termination resistor, even if the signal is not used (such as
OF+/OFor CLKOUT+/CLKOUT). To minimize noise the PC
board traces for each LVDS output pair should be routed
close together. To minimize clock skew all LVDS PC board
traces should have about the same length.
20
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250Msps ADC

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LTC2242-10
APPLICATIONS INFORMATION
LTC2242-10
www.datasheet4u.cVoDDm
DATA
FROM
LATCH
PREDRIVER
LOGIC
OE
OVDD 0.5V
LTC2242-10
VDD TO 2.625V
0.1μF
OVDD
0.1μF
2.5V
OVDD
43Ω
TYPICAL
DATA
OUTPUT
OGND
D
10k 10k
+ 1.25V
D
D
OUT+
100Ω
OUT
D
LVDS
RECEIVER
224210 F13a
Figure 13a. Digital Output Buffer in CMOS Mode
Data Format
The LTC2242-10 parallel digital output can be selected
for offset binary or 2’s complement format. The format
is selected with the MODE pin. Connecting MODE to GND
or 1/3VDD selects offset binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 3 shows the logic
states for the MODE pin.
Table 3. MODE Pin Function
MODE PIN
0
1/3VDD
2/3VDD
VDD
OUTPUT FORMAT
Offset Binary
Offset Binary
2’s Complement
2’s Complement
CLOCK DUTY
CYCLE STABILIZER
Off
On
On
Off
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates an
overflow or underflow on the B data bus. In LVDS mode,
a differential logic high on the OF+/OFpins indicates an
overflow or underflow.
Output Clock
The ADC has a delayed version of the ENC+ input available
as a digital output, CLKOUT. The CLKOUT pin can be used
3.5mA
OGND
224210 F13b
Figure 13b. Digital Output in LVDS Mode
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. In
all CMOS modes, A bus data will be updated just after
CLKOUTA rises and can be latched on the falling edge of
CLKOUTA. In demux CMOS mode with interleaved update,
B bus data will be updated just after CLKOUTB rises and
can be latched on the falling edge of CLKOUTB. In demux
CMOS mode with simultaneous update, B bus data will be
updated just after CLKOUTB falls and can be latched on
the rising edge of CLKOUTB. In LVDS mode, data will be
updated just after CLKOUT+/CLKOUTrises and can be
latched on the falling edge of CLKOUT+/CLKOUT.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example if the converter is driving a DSP powered
by a 1.8V supply then OVDD should be tied to that same
1.8V supply.
In the CMOS output mode, OVDD can be powered with
any voltage up to 2.625V. OGND can be powered with any
voltage from GND up to 1V and must be less than OVDD.
The logic outputs will swing between OGND and OVDD.
In the LVDS output mode, OVDD should be connected to a
2.5V supply and OGND should be connected to GND.
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LTC2242-10
APPLICATIONS INFORMATION
Output Enable
The outputs may be disabled with the output enable pin,
wwwO.dEat.aIsnheCeMt4uO.cSomor LVDS output modes OE high disables all
data outputs including OF and CLKOUT. The data access
and bus relinquish times are too slow to allow the outputs
to be enabled and disabled during full speed operation.
The output Hi-Z state is intended for use during long
periods of inactivity.
The Hi-Z state is not a truly open circuit; the output pins
that make an LVDS output pair have a 20k resistance be-
tween them. Therefore in the CMOS output mode, adjacent
data bits will have 20k resistance in between them, even
in the Hi-Z state.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors
have to recharge and stabilize. Connecting SHDN to VDD
and OE to GND results in nap mode, which typically dis-
sipates 28mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap mode all digital outputs are disabled
and enter the Hi-Z state.
GROUNDING AND BYPASSING
The LTC2242-10 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with an
internal ground plane is recommended. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particular,
care should be taken not to run any digital signal alongside
an analog signal or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB
pins. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capaci-
tors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recommended. The 2.2μF capacitor between REFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2242-10 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
HEAT TRANSFER
Most of the heat generated by the LTC2242-10 is trans-
ferred from the die through the bottom-side exposed
pad and package leads onto the printed circuit board. For
good electrical and thermal performance, the exposed
pad should be soldered to a large grounded pad on the
PC board. It is critical that all ground pins are connected
to a ground plane of sufficient area.
Clock Sources for Undersampling
Undersampling is especially demanding on the clock source
and the higher the input frequency, the greater the sensitivity
to clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required, a
canned oscillator from vendors such as Saronix or Vectron
can be placed close to the ADC and simply connected
directly to the ADC. If there is any distance to the ADC,
some source termination to reduce ringing that may occur
even over a fraction of an inch is advisable. You must not
allow the clock to overshoot the supplies or performance
will suffer. Do not filter the clock signal with a narrow band
filter unless you have a sinusoidal clock source, as the
rise and fall time artifacts present in typical digital clock
signals will be translated into phase noise.
22
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250Msps ADC

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LTC2242-10
APPLICATIONS INFORMATION
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a
www.dlatetarscheloest4eu.tcoomthe ADC may be beneficial. This filter should
be close to the ADC to both reduce roundtrip reflection
times, as well as reduce the susceptibility of the traces
between the filter and the ADC. If the circuit is sensitive
to close-in phase noise, the power supply for oscillators
and any buffers must be very stable, or propagation de-
lay variation with supply will translate into phase noise.
Even though these clock sources may be regarded as
digital devices, do not operate them on a digital supply.
If your clock is also used to drive digital devices such as
an FPGA, you should locate the oscillator, and any clock
fan-out devices close to the ADC, and give the routing
to the ADC precedence. The clock signals to the FPGA
should have series termination at the driver to prevent
high frequency noise from the FPGA disturbing the sub-
strate of the clock fan-out device. If you use an FPGA as a
programmable divider, you must re-time the signal using
the original oscillator, and the re-timing flip-flop as well
as the oscillator should be close to the ADC, and powered
with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated in
the waveguides that exist between the layers of multilayer
PCBs. The differential pairs must be close together and
distanced from other signals. The differential pair should
be guarded on both sides with copper distanced at least
3x the distance between the traces, and grounded with
vias no more than 1/4 inch apart.
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LTC2242-10
APPLICATIONS INFORMATION
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250Msps ADC

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APPLICATIONS INFORMATION
Silkscreen Top
www.datasheet4u.com
LTC2242-10
Layer 2 GND Plane
Layer 1 Component Side
Layer 3 Power/Ground Plane
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250Msps ADC

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LTC2242-10
APPLICATIONS INFORMATION
Layer 4 Power/Ground Planes
www.datasheet4u.com
Layer Back Solder Side
Layer 5 Power/Ground Planes
Silk Screen Back, Solder Side
26
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250Msps ADC

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PACKAGE DESCRIPTION
www.datasheet4u.com
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
LTC2242-10
7.15 ±0.05
(4 SIDES)
8.10 ±0.05
9.50 ±0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM
OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT,
SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1
LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
9 .00 ± 0.10
(4 SIDES)
PIN 1 TOP MARK
(SEE NOTE 5)
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
0.75 ± 0.05
7.15 ± 0.10
(4-SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
63 64
PIN 1
CHAMFER
0.40 ± 0.10
1
2
0.200 REF
0.00 – 0.05
(UP64) QFN 1003
0.25 ± 0.05
0.50 BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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250Msps ADC

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LTC2242-10
RELATED PARTS
PART NUMBER
LTC1748
wwwL.dTCat1a7s5h0eet4u.com
LT®1993-2
LT1994
LTC2202
LTC2208
LTC2220
LTC2220-1
LTC2221
LTC2224
LTC2230
LTC2231
LTC2240-10
LTC2240-12
LTC2241-10
LTC2242-12
LTC2242-12
LTC2255
LTC2284
LT5512
LT5514
LT5515
LT5516
LT5517
LT5522
DESCRIPTION
14-Bit, 80Msps, 5V ADC
14-Bit, 80Msps, 5V Wideband ADC
High Speed Differential Op Amp
Low Noise, Low Distortion Fully Differential
Input/Output Amplifier/Driver
16-Bit, 10Msps, 3.3V ADC, Lowest Noise
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
12-Bit, 170Msps, 3.3V ADC, LVDS Outputs
12-Bit, 185Msps, 3.3V ADC, LVDS Outputs
12-Bit, 135Msps, 3.3V ADC, LVDS Outputs
12-Bit, 135Msps, 3.3V ADC, High IF Sampling
10-Bit, 170Msps, 3.3V ADC, LVDS Outputs
10-Bit, 135Msps, 3.3V ADC, LVDS Outputs
10-Bit, 170Msps, 2.5V ADC, LVDS Outputs
12-Bit, 170Msps, 2.5V ADC, LVDS Outputs
10-Bit, 210Msps, 2.5V ADC, LVDS Outputs
12-Bit, 210Msps, 2.5V ADC, LVDS Outputs
12-Bit, 250Msps, 2.5V ADC, LVDS Outputs
14-Bit, 125Msps, 3V ADC, Lowest Power
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
DC to 3GHz High Signal Level Downconverting Mixer
Ultralow Distortion IF Amplifier/ADC Driver with Digitally
Controlled Gain
1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator
800MHz to 1.5GHz Direct Conversion Quadrature Demodulator
40MHz to 900MHz Direct Conversion Quadrature Demodulator
600MHz to 2.7GHz High Linearity Downconverting Mixer
COMMENTS
76.3dB SNR, 90dB SFDR, 48-Pin TSSOP
Up to 500MHz IF Undersampling, 90dB SFDR
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
Low Distortion: –94dBc at 1MHz
150mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
1250mW, 78dB SNR, 100dB SFDR, 48-Pin QFN
890mW, 67.7dB SNR, 84dB SFDR, 64-Pin QFN
910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
660mW, 67.8dB SNR, 84dB SFDR, 64-Pin QFN
630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
890mW, 61.2dB SNR, 78dB SFDR, 64-Pin QFN
660mW, 61.2dB SNR, 78dB SFDR, 64-Pin QFN
445mW, 60.6dB SNR, 78dB SFDR, 64-Pin QFN
445mW, 65.5dB SNR, 78dB SFDR, 64-Pin QFN
585mW, 60.6dB SNR, 78dB SFDR, 64-Pin QFN
585mW, 65.5dB SNR, 78dB SFDR, 64-Pin QFN
740mW, 65.5dB SNR, 78dB SFDR, 64-Pin QFN
395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
450MHz to 1dB BW, 47dB OIP3, Digital Gain Control
10.5dB to 33dB in 1.5dB/Step
High IIP3: 20dBm at 1.9GHz, Integrated LO
Quadrature Generator
High IIP3: 21.5dBm at 900MHz, Integrated LO
Quadrature Generator
High IIP3: 21dBm at 800MHz, Integrated LO
Quadrature Generator
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
28 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
224210fc
LT 1107 REV C • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2006




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