MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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19-2854; Rev 5; 8/11
EVAALVUAAILTAIOBNLEKIT
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
General Description
The MAX1027/MAX1029/MAX1031 are serial 10-bit ana-
log-to-digital converters (ADCs) with an internal reference
and an internal temperature sensor. These devices fea-
ture on-chip FIFO, scan mode, internal clock mode, inter-
nal averaging, and AutoShutdown™. The maximum
sampling rate is 300ksps using an external clock. The
MAX1031 has 16 input channels, the MAX1029 has 12
input channels, and the MAX1027 has 8 input channels.
All input channels are configurable for single-ended or
differential inputs in unipolar or bipolar mode. All three
devices operate from a +3V supply and contain a 10MHz
SPI™/QSPI™/MICROWIRE™-compatible serial port.
The MAX1031 is available in 28-pin, 5mm x 5mm, TQFN
with exposed pad and 24-pin QSOP packages. The
MAX1027/MAX1029 are only available in QSOP pack-
ages. All three devices are specified over the extended
-40°C to +85°C temperature range.
________________________Applications
System Supervision
Data-Acquisition Systems
Industrial Control Systems
Patient Monitoring
Data Logging
Instrumentation
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Features
o Internal Temperature Sensor (±0.7°C Accuracy)
o 16-Entry First-In/First-Out (FIFO)
o Analog Multiplexer with True Differential
Track/Hold
16-, 12-, 8-Channel Single Ended
8-, 6-, 4-Channel True Differential
(Unipolar or Bipolar)
o Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing
Codes Over Temperature
o Scan Mode, Internal Averaging, and Internal Clock
o Low-Power Single +3V Operation
1mA at 300ksps
o Internal 2.5V Reference or External Differential
Reference
o 10MHz 3-Wire SPI/QSPI/MICROWIRE-Compatible
Interface
o Space-Saving 28-Pin 5mm x 5mm TQFN Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1027BCEE+T 0°C to +70°C
16 QSOP
MAX1027BEEE+T -40°C to +85°C
16 QSOP
MAX1029BCEP+T 0°C to +70°C
20 QSOP
MAX1029BEEP+T -40°C to +85°C
20 QSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Ordering Information continued at end of data sheet.
Pin Configurations
TOP VIEW
+
AIN0 1
AIN1 2
AIN2 3
AIN3 4 MAX1027
AIN4 5
AIN5 6
REF-/AIN6 7
CNVST/AIN7 8
16 EOC
15 DOUT
14 DIN
13 CS
12 SCLK
11 VDD
10 GND
9 REF+
QSOP
Pin Configurations continued at end of data sheet.
+
AIN0 1
AIN1 2
AIN2 3
AIN3 4
AIN4 5
MAX1029
AIN5 6
AIN6 7
AIN7 8
AIN8 9
AIN9 10
20 EOC
19 DOUT
18 DIN
17 CS
16 SCLK
15 VDD
14 GND
13 REF+
12 CNVST/AIN11
11 REF-/AIN10
QSOP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.


MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (VDD + 0.3V)
AIN0–AIN13, REF-/AIN_, CNVST/AIN_,
REF+ to GND.........................................-0.3V to (VDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
28-Pin TQFN (derate 20.8mW/°C above +70°C) .......1667mW
Operating Temperature Ranges
MAX10__C__.......................................................0°C to +70°C
MAX10__E__ ....................................................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V, fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
DC ACCURACY (Note 1)
Resolution
Integral Nonlinearity
RES
INL
Differential Nonlinearity
Offset Error
DNL No missing codes over temperature
Gain Error
(Note 2)
Offset Error Temperature
Coefficient
Gain Temperature Coefficient
Channel-to-Channel Offset
Matching
DYNAMIC SPECIFICATIONS (30kHz sine wave input, 2.5VP-P, 300ksps, fSCLK = 4.8MHz)
Signal-to-Noise Plus Distortion
SINAD
Total Harmonic Distortion
THD Up to the 5th harmonic
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
IMD fin1 = 29.9kHz, fin2 = 30.1kHz
Full-Power Bandwidth
-3dB point
Full-Linear Bandwidth
S/(N + D) > 68dB
MIN
10
TYP
±0.5
±0.5
±2
±0.8
±0.1
62
-79
-81
-74
1
100
MAX UNITS
±1.0
±1.0
±2.0
±2.0
Bits
LSB
LSB
LSB
LSB
ppm/°C
FSR
ppm/°C
LSB
dB
dBc
dBc
dBc
MHz
kHz
2 _______________________________________________________________________________________


MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V, fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.)
PARAMETER
CONVERSION RATE
Power-Up Time
Acquisition Time
Conversion Time
SYMBOL
tPU
tACQ
tCONV
External Clock Frequency
fSCLK
Aperture Delay
Aperture Jitter
ANALOG INPUT
Input Voltage Range
Input Leakage Current
Input Capacitance
INTERNAL TEMPERATURE SENSOR
Measurement Error (Note 7)
CONDITIONS
External reference
Internal reference (Note 3)
Internally clocked
Externally clocked (Note 4)
Externally clocked conversion
Data I/O
Unipolar
Bipolar (Note 5)
VIN = VDD
During acquisition time (Note 6)
TA = +25°C
TA = TMIN to TMAX
MIN TYP MAX UNITS
0.8
μs
65
0.6 μs
3.5
2.7
μs
0.1 4.8
MHz
10
30 ns
<50 ps
0
-VREF/2
±0.01
24
VREF
VREF/2
±1
V
μA
pF
±0.7
±1.2
±2.5
°C
Temperature Measurement Noise
0.1 °CRMS
Temperature Resolution
Power-Supply Rejection
INTERNAL REFERENCE
REF Output Voltage
REF Temperature Coefficient
Output Resistance
REF Output Noise
REF Power-Supply Rejection
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
REF+ Input Voltage Range
REF+ Input Current
TCREF
PSRR
VREF-
VREF+
IREF+
VREF+ = 2.5V, fSAMPLE = 300ksps
VREF+ = 2.5V, fSAMPLE = 0
1/8 °C
0.3 °C/V
2.48 2.50 2.52
V
±30 ppm/°C
6.5 kΩ
200 μVRMS
-70 dB
0 500 mV
1.0 VDD + 50mV V
40
±0.1
100
±5
μA
_______________________________________________________________________________________ 3


MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V, fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
DIGITAL INPUTS (SCLK, DIN, CS, CNVST) (Note 8)
CONDITIONS
Input Voltage Low
VIL
Input Voltage High
Input Hysteresis
Input Leakage Current
VIH
VHYST
IIN
VIN = 0 or VDD
Input Capacitance
DIGITAL OUTPUTS (DOUT, EOC)
CIN
Output Voltage Low
VOL
ISINK = 2mA
ISINK = 4mA
Output Voltage High
Tri-State Leakage Current
Tri-State Output Capacitance
VOH
IL
COUT
ISOURCE = 1.5mA
CS = VDD
CS = VDD
POWER REQUIREMENTS
Supply Voltage
VDD
During temp sense
Supply Current (Note 9)
Internal
reference
IDD
fSAMPLE = 300ksps
fSAMPLE = 0, REF on
Shutdown
External
reference
During temp sense
fSAMPLE = 300ksps
Shutdown
Power-Supply Rejection
PSR VDD = 2.7V to 3.6V; full-scale input
MIN TYP MAX UNITS
VDD x 0.3
VDD x 0.7
200
±0.01 ±1.0
15
V
V
mV
μA
pF
VDD - 0.5
±0.05
15
0.4
0.8
±1
V
V
μA
pF
2.7 3.6
2400 2700
1750 2000
1000 1200
0.2 5
1550 2000
1050 1200
0.2 5
±0.2 ±1.4
V
μA
mV
Note 1: Tested at VDD = +2.7V, unipolar input mode.
Note 2: Offset nulled.
Note 3: Time for reference to power up and settle to within 1 LSB.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: The operational input voltage range for each individual input of a differentially configured pair is from GND to VDD. The
operational input voltage difference is from -VREF/2 to +VREF/2.
Note 6: See Figure 3 (Input Equivalent Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating
Characteristics section.
Note 7: Fast automated test, excludes self-heating effects.
Note 8: When CNVST is configured as a digital input, do not apply a voltage between VIL and VIH.
Note 9: Supply current is specified depending on whether an internal or external reference is used for voltage conversions.
Temperature measurements always use the internal reference.
4 _______________________________________________________________________________________


MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
TIMING CHARACTERISTICS (Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Clock Period
Externally clocked conversion
tCP
Data I/O
208
100
ns
SCLK Duty Cycle
tCH
40 60 %
SCLK Fall to DOUT Transition
CS Rise to DOUT Disable
CS Fall to DOUT Enable
DIN to SCLK Rise Setup
tDOT
tDOD
tDOE
tDS
CLOAD = 30pF
CLOAD = 30pF
CLOAD = 30pF
40 ns
40 ns
40 ns
40 ns
SCLK Rise to DIN Hold
CS Fall to SCLK Rise Setup Time
CS Fall to SCLK Rise Hold Time
CS Rise to SCLK Rise Hold Time
CS Rise to SCLK Rise Setup Time
tDH
tCSS0
tCSH0
tCSH1
tCSS1
0 ns
40 ns
0 ns
0 ns
40 ns
CNVST Pulse Width
tCSW
CKSEL = 00, CKSEL = 01 (temp sense)
CKSEL = 01 (voltage conversion)
40
1.4
ns
μs
CS or CNVST Rise to EOC
Low (Note 10)
tTS Temp sense
Voltage conversion
tRP Reference power-up
56
7 μs
65
Note 10: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-
ence needs to be powered up, the total time is additive. The internal reference is always used for temperature measure-
ments..
Typical Operating Characteristics
(VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
fSAMPLE = 300ksps
256 512 768
OUTPUT CODE (DECIMAL)
1024
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
fSAMPLE = 300ksps
256 512 768
OUTPUT CODE (DECIMAL)
1024
65
64
63
62
61
60
59
58
57
56
55
1
SINAD vs. FREQUENCY
10 100
FREQUENCY (kHz)
1k
_______________________________________________________________________________________ 5


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(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Typical Operating Characteristics (continued)
(VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.)
SFDR vs. FREQUENCY
100
90
80
70
60
50
1
10 100
FREQUENCY (kHz)
1k
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2000
1800 INTERNAL REFERENCE
1600
1400
1200
1000 EXTERNAL REFERENCE
800
600
400
200
0 fSAMPLE = 300ksps
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
1.0
VDD = 3V
0.8
THD vs. FREQUENCY
-50
-60
-70
-80
-90
-100
1
10 100
FREQUENCY (kHz)
1k
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.5
0.4
0.3
0.2
0.1
VDD = 3V
0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
2.502
VDD = 3V
2.501
SUPPLY CURRENT vs. SAMPLING RATE
1800
1600 VDD = 3V
1400
1200 INTERNAL REFERENCE
1000
800
600 EXTERNAL REFERENCE
400
200
0
1 10 100 1k
SAMPLING RATE (ksps)
SUPPLY CURRENT vs. TEMPERATURE
1800
INTERNAL REFERENCE
1600
1400 VDD = 3V
fSAMPLE = 300ksps
1200
1000 EXTERNAL REFERENCE
800
600
-40
-15 10 35 60
TEMPERATURE (°C)
85
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.520
VDD = 3V
2.510
0.6
2.500
2.500
0.4
2.499
2.490
0.2
2.498
2.480
0
-40
-15 10 35 60
TEMPERATURE (°C)
85
2.497
2.7
3.0 3.3
VDD (V)
2.470
3.6 -40 -15 10 35 60
TEMPERATURE (°C)
6 _______________________________________________________________________________________
85


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(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Typical Operating Characteristics (continued)
(VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.)
OFFSET ERROR vs. SUPPLY VOLTAGE
0.70
0.65
OFFSET ERROR vs. TEMPERATURE
0.8
fSAMPLE = 300ksps
0.7
GAIN ERROR vs. SUPPLY VOLTAGE
0
fSAMPLE = 300ksps
0.60 0.6 -0.1
0.55
fSAMPLE = 300ksps
0.50
2.7
3.0
VDD (V)
3.3
3.6
GAIN ERROR vs. TEMPERATURE
0.5
fSAMPLE = 300ksps
0.3
0.1
-0.1
-0.3
-40
-15 10 35 60
TEMPERATURE (°C)
85
0.5
0.4
-40
-15 10 35 60
TEMPERATURE (°C)
85
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-40
-15 10 35 60
TEMPERATURE (°C)
85
-0.2
2.7
1.0
3.0 3.3
VDD (V)
SAMPLING ERROR
vs. SOURCE IMPEDANCE
3.6
0.5
0
-0.5
-1.0
0
2468
SOURCE IMPEDANCE (kΩ)
10
_______________________________________________________________________________________ 7


MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Pin Description
MAX1031
TQFN
MAX1031
QSOP
MAX1029
MAX1027
NAME
FUNCTION
2–12, 26,
27, 28
13
1–14
15
1–10
— AIN0–13 Analog Inputs
— AIN0–9 Analog Inputs
1–6 AIN0–5 Analog Inputs
REF-/AIN14
Negative Input for External Differential Reference/Analog Input 14.
See Table 3 for details on programming the setup register.
— — 11 — REF-/AIN10 Negative Input for External Differential Reference/Analog Input 10.
See Table 3 for details on programming the setup register.
——
7
REF-/AIN6
Negative Input for External Differential Reference/Analog Input 6.
See Table 3 for details on programming the setup register.
14 16 — — CNVST/ Active-Low Conversion Start Input/Analog Input 15. See Table 3
AIN15 for details on programming the setup register.
— — 12 — CNVST/ Active-Low Conversion Start Input/Analog Input 11. See Table 3
AIN11 for details on programming the setup register.
— — — 8 CNVST/ Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
AIN7
details on programming the setup register.
15 17 13
9
REF+
Positive Reference Input. Bypass to GND with a 0.1μF capacitor.
16
18
14
10
GND
Ground
18 19
15 11
VDD Power Input. Bypass to GND with a 0.1μF capacitor.
Serial Clock Input. Clocks data in and out of the serial interface
20 20 16 12 SCLK (duty cycle must be 40% to 60%). See Table 3 for details on
programming the clock mode.
21 21 17 13
CS
Active-Low Chip Select Input. When CS is low, the serial interface
is enabled. When CS is high, DOUT is high impedance.
22 22 18 14
DIN Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
23
23
19
15
DOUT
Serial Data Output. Data is clocked out on the falling edge of
SCLK. High impedance when CS is connected to VDD.
24
24
20 16
EOC
End of Conversion Output. Data is valid after EOC pulls low.
1, 17, 19,
N.C.
No Connection. Not internally connected.
25
————
EP Exposed Pad (TQFN Only). Connect EP to GND.
8 _______________________________________________________________________________________


MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
CS
SCLK
DIN
DOUT
tCSS0
tCH
tCL
tDH
tDS
tDOE
tCP
tDOT
tCSH1
tCSH0
tCSS1
tDOD
Figure 1. Detailed Serial-Interface Timing Diagram
CS
DIN
SCLK
SERIAL INTERFACE
DOUT
CNVST
AIN1
AIN2
AIN15
REF-
REF+
OSCILLATOR
CONTROL
EOC
TEMP
SENSE
T/H
MAX1027
MAX1029
MAX1031
12-BIT
SAR
ADC
FIFO AND
ACCUMULATOR
INTERNAL
REFERENCE
Figure 2. Functional Diagram
_______________________________________________________________________________________ 9


MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Detailed Description
The MAX1027/MAX1029/MAX1031 are low-power, seri-
al-output, multichannel ADCs with temperature-sensing
capability for temperature-control, process-control, and
monitoring applications. These 10-bit ADCs have inter-
nal track and hold (T/H) circuitry that supports single-
ended and fully differential inputs. Data is converted
from an internal temperature sensor or analog voltage
sources in a variety of channel and data-acquisition
configurations. Microprocessor (μP) control is made
easy through a 3-wire SPI/QSPI/MICROWIRE-compati-
ble serial interface.
Figure 2 shows a simplified functional diagram of the
MAX1027/MAX1029/MAX1031 internal architecture.
The MAX1027 has eight single-ended analog input
channels or four differential channels. The MAX1029
has 12 single-ended analog input channels or six differ-
ential channels. The MAX1031 has 16 single-ended
analog input channels or eight differential channels.
Converter Operation
The MAX1027/MAX1029/MAX1031 ADCs use a fully dif-
ferential, successive-approximation register (SAR) con-
version technique and an on-chip T/H block to convert
temperature and voltage signals into a 10-bit digital
result. Both single-ended and differential configurations
are supported, with a unipolar signal range for single-
ended mode and bipolar or unipolar ranges for differ-
ential mode.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequen-
cy signals aliasing into the frequency band of interest.
Analog Input Protection
Internal ESD protection diodes clamp all pins to VDD
and GND, allowing the inputs to swing from (GND -
0.3V) to (VDD + 0.3V) without damage. However, for
accurate conversions near full scale, the inputs must
not exceed VDD by more than 50mV or be lower than
GND by 50mV. If an off-channel analog input voltage
exceeds the supplies, limit the input current to 2mA.
3-Wire Serial Interface
The MAX1027/MAX1029/MAX1031 feature a serial
interface compatible with SPI/QSPI and MICROWIRE
devices. For SPI/QSPI, ensure the CPU serial interface
runs in master mode so it generates the serial clock
signal. Select the SCLK frequency of 10MHz or less,
and set clock polarity (CPOL) and phase (CPHA) in the
μP control registers to the same value. The MAX1027/
MAX1029/MAX1031 operate with SCLK idling high or
low, and thus operate with CPOL = CPHA = 0 or CPOL
= CPHA = 1. Set CS low to latch input data at DIN on
the rising edge of SCLK. Output data at DOUT is
updated on the falling edge of SCLK. Bipolar true-dif-
ferential results and temperature sensor results are
available in two’s complement format, while all others
are in binary.
Serial communication always begins with an 8-bit input
data byte (MSB first) loaded from DIN. Send a second
byte, immediately following the setup byte, to write to
the unipolar mode or bipolar mode registers (see
Tables 1, 3, 4, and 5). A high-to-low transition on CS ini-
tiates the data input operation. The input data byte and
the subsequent data bytes are clocked from DIN into
the serial interface on the rising edge of SCLK.
Tables 1–7 detail the register descriptions. Bits 5 and 4,
CKSEL1 and CKSEL0, respectively, control the clock
modes in the setup register (see Table 3). Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request the programmed inter-
nally timed conversions without tying up the serial bus.
In clock mode 01, use CNVST to request conversions
one channel at a time, controlling the sampling speed
without tying up the serial bus. Request and start inter-
nally timed conversions through the serial interface by
writing to the conversion register in the default clock
mode, 10. Use clock mode 11 with SCLK up to 4.8MHz
for externally timed acquisitions to achieve sampling
rates up to 300ksps. Clock mode 11 disables scanning
and averaging. See Figures 4–7 for timing specifica-
tions and how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the
last-requested operation and is waiting for the next input
data byte (for clock modes 00 and 10). For clock mode
01, EOC goes low after the ADC completes each
requested operation. EOC goes high when CS or
CNVST goes low. EOC is always high in clock mode 11.
Single-Ended/Differential Input
The MAX1027/MAX1029/MAX1031 use a fully differen-
tial ADC for all conversions. The analog inputs can be
configured for either differential or single-ended con-
versions by writing to the setup register (see Table 3).
Single-ended conversions are internally referenced to
GND (Figure 3).
10 ______________________________________________________________________________________


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AIN0-AIN15
(SINGLE ENDED);
AIN0, AIN2,
AIN4…AIN14
(DIFFERENTIAL)
HOLD
GND
(SINGLE ENDED);
AIN1, AIN3,
AIN5…AIN15
(DIFFERENTIAL)
REF
GND DAC
CIN+
CIN-
HOLD
VDD/2
COMPARATOR
+
-
HOLD
Figure 3. Equivalent Input Circuit
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from
the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
and AIN14/AIN15. AIN0–AIN7 are available on the
MAX1027, MAX1029, and MAX1031. AIN8–AIN11 are
only available on the MAX1029 and MAX1031.
AIN12–AIN15 are only available on the MAX1031. See
Tables 2–5 for more details on configuring the inputs.
For the inputs that can be configured as CNVST or an
analog input, only one can be used at a time. For the
inputs that can be configured as REF- or an analog
input, the REF- configuration excludes the analog input.
Unipolar/Bipolar
Address the unipolar and bipolar registers through the
setup register (bits 1 and 0). Program a pair of analog
channels for differential operation by writing a 1 to the
appropriate bit of the bipolar or unipolar register.
Unipolar mode sets the differential input range from 0
to VREF. A negative differential analog input in unipolar
mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to ±VREF / 2. The digital output code is binary in unipo-
lar mode and two’s complement in bipolar mode (see
the transfer function graphs, Figures 8 and 9).
In single-ended mode, the MAX1027/MAX1029/
MAX1031 always operate in unipolar mode. The analog
inputs are internally referenced to GND with a full-scale
input range from 0 to VREF.
True Differential Analog Input T/H
The equivalent circuit of Figure 3 shows the
MAX1027/MAX1029/MAX1031s’ input architecture. In
track mode, a positive input capacitor is connected to
AIN0–AIN15 in single-ended mode (and AIN0, AIN2,
AIN4…AIN14 in differential mode). A negative input
capacitor is connected to GND in single-ended mode
(or AIN1, AIN3, AIN5…AIN15 in differential mode). For
external track-and-hold timing, use clock mode 01.
After the T/H enters hold mode, the difference between
the sampled positive and negative input voltages is
converted. The time required for the T/H to acquire an
input signal is determined by how quickly its input
capacitance is charged. If the input signal’s source
impedance is high, the required acquisition time
lengthens. The acquisition time, tACQ, is the maximum
time needed for a signal to be acquired, plus the power-
up time. It is calculated by the following equation:
( )t ACQ = 9 x RS + RIN x 24pF + tPWR
where RIN = 1.5kΩ, RS is the source impedance of the
input signal, and tPWR = 1μs, the power-up time of the
device. The varying power-up times are detailed in the
explanation of the clock mode conversions.
tACQ is never less than 1.4μs, and any source imped-
ance below 300Ω does not significantly affect the
ADC’s AC performance. A high-impedance source can
be accommodated either by lengthening tACQ or by
placing a 1μF capacitor between the positive and neg-
ative analog inputs.
Internal FIFO
The MAX1027/MAX1029/MAX1031 contain a FIFO
buffer that can hold up to 16 ADC results plus one tem-
perature result. This allows the ADC to handle multiple
internally clocked conversions and a temperature mea-
surement, without tying up the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros and the LSB followed by two sub-bits.
After each falling edge of CS, the oldest available byte
of data is available at DOUT, MSB first. When the FIFO
is empty, DOUT is zero.
The first 2 bytes of data read out after a temperature
measurement always contain the temperature result
preceded by four leading zeros, MSB first. If another
______________________________________________________________________________________ 11


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temperature measurement is performed before the first
temperature result is read out, the old measurement is
overwritten by the new result. Temperature results are
in degrees Celsius (two’s complement) at a resolution
of 1/8 of a degree. See the Temperature Measurements
section for details on converting the digital code to a
temperature.
Internal Clock
The MAX1027/MAX1029/MAX1031 operate from an inter-
nal oscillator, which is accurate within 10% of the 4.4MHz
nominal clock rate. The internal oscillator is active in
clock modes 00, 01, and 10. Read out the data at clock
speeds up to 10MHz. See Figures 4–7 for details on tim-
ing specifications and starting a conversion.
Applications Information
Register Descriptions
The MAX1027/MAX1029/MAX1031 communicate
between the internal registers and the external circuitry
through the SPI/QSPI-compatible serial interface. Table
1 details the registers and the bit names. Tables 2–7
show the various functions within the conversion regis-
ter, setup register, averaging register, reset register,
unipolar register, and bipolar register.
Conversion Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use.
Use the following formula to calculate the total conver-
sion time for an internally timed conversion in clock
modes 00 and 10 (see the Electrical Characteristics
section as applicable):
total conversion time = tCONV x navg x nresult + tTS + tRP
where:
tCONV = tACQ(max) + tCONV(max)
navg = samples per result (amount of averaging)
nresult = number of FIFO results requested; determined
by number of channels being scanned or by NSCAN1,
NSCAN0
tTS = time required for temperature measurement; set
to zero if temp measurement is not requested
tRP = internal reference wake-up; set to zero if the inter-
nal reference is already powered up or if the external
reference is being used
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high, including any time
required to turn on the internal reference. Conversion
time in externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles.
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by writing
to the conversion register. Table 2 details channel
selection, the four scan modes, and how to request a
temperature measurement. Request a scan by writing
to the conversion register when in clock mode 10 or 11,
or by applying a low pulse to the CNVST pin when in
clock mode 00 or 01.
A conversion is not performed if it is requested on a
channel that has been configured as CNVST or REF-.
Do not request conversions on channels 8–15 on the
MAX1027 and channels 12–15 on the MAX1029. Set
CHSEL3:CHSEL0 to the lower channel’s binary value. If
the last two channels are configured as a differential
Table 1. Input Data Byte (MSB First)
REGISTER NAME
Conversion
Setup
Averaging
Reset
Unipolar Mode (Setup)
Bipolar Mode (Setup)
BIT 7
1
0
0
0
UCH0/1
BCH0/1
BIT 6
CHSEL3
1
0
0
UCH2/3
BCH1/2
BIT 5
CHSEL2
CKSEL1
1
0
UCH4/5
BCH4/5
BIT 4
CHSEL1
CKSEL0
AVGON
1
UCH6/7
BCH6/7
BIT 3
CHSEL0
REFSEL1
NAVG1
RESET
UCH8/9*
BCH8/9*
BIT 2
BIT 1
BIT 0
SCAN1
SCAN0
TEMP
REFSEL0 DIFFSEL1 DIFFSEL0
NAVG0 NSCAN1 NSCAN0
XXX
UCH10/11* UCH12/13** UCH14/15**
BCH10/11* BCH12/13** BCH14/15**
*Unipolar/bipolar channels 8–15 are only valid on the MAX1029 and MAX1031.
**Unipolar/bipolar channels 12–15 are only valid on the MAX1031.
X = Don’t care.
12 ______________________________________________________________________________________


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Table 2. Conversion Register*
BIT
NAME
BIT
FUNCTION
— 7 (MSB) Set to 1 to select conversion register.
CHSEL3 6 Analog input channel select.
CHSEL2 5 Analog input channel select.
CHSEL1 4 Analog input channel select.
CHSEL0 3 Analog input channel select.
SCAN1 2 Scan mode select.
SCAN0 1 Scan mode select.
TEMP
Set to 1 to take a single temperature
0 (LSB) measurement. The first conversion result
of a scan contains temperature information.
*See below for bit details.
CHSEL3 CHSEL2 CHSEL1 CHSEL0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SELECTED
CHANNEL (N)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
SCAN1 SCAN0
SCAN MODE (CHANNEL N IS
SELECTED BY BITS CHSEL3–CHSEL0)
0 0 Scans channels 0 through N.
0 1 Scans channels N through the highest
numbered channel.
1 0 Scans channel N repeatedly. The averaging
register sets the number of results.
1 1 No scan. Converts channel N once only.
pair and one of them has been reconfigured as CNVST
or REF-, the pair is ignored.
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the requested range, plus one temperature result
if selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the averaging register (see Table 6). Select
scan mode 11 to return only one result from a single
channel.
Setup Register
Write a byte to the setup register to configure the clock,
reference, and power-down modes. Table 3 details the
bits in the setup register. Bits 5 and 4 (CKSEL1 and
CKSEL0) control the clock mode, acquisition and sam-
pling, and the conversion start. Bits 3 and 2 (REFSEL1
and REFSEL0) control internal or external reference use.
Bits 1 and 0 (DIFFSEL1 and DIFFSEL0) address the
unipolar mode and bipolar mode registers and configure
the analog input channels for differential operation.
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control the
unipolar/bipolar mode address registers. Set bits 1 and
0 (DIFFSEL1 and DIFFSEL0) to 10 to write to the unipo-
lar mode register. Set bits 1 and 0 to 11 to write to the
bipolar mode register. In both cases, the setup byte
must be followed immediately by 1 byte of data written
to the unipolar register or bipolar register. Hold CS low
and run 16 SCLK cycles before pulling CS high. If the
last 2 bits of the setup register are 00 or 01, neither the
unipolar mode register nor the bipolar mode register is
written. Any subsequent byte is recognized as a new
input data byte. See Tables 4 and 5 to program the
unipolar and bipolar mode registers.
If a channel is configured as both unipolar and bipolar,
the unipolar setting takes precedence. In unipolar
mode, AIN+ can exceed AIN- by up to VREF. The out-
put format in unipolar mode is binary. In bipolar mode,
either input can exceed the other by up to VREF / 2. The
output format in bipolar mode is two's complement.
Averaging Register
Write to the averaging register to configure the ADC to
average up to 32 samples for each requested result,
and to independently control the number of results
requested for single-channel scans.
Table 2 details the four scan modes available in the con-
version register. All four scan modes allow averaging as
long as the AVGON bit, bit 4 in the averaging register, is
______________________________________________________________________________________ 13


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Table 3. Setup Register*
BIT NAME
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
FUNCTION
Set to zero to select setup register.
Set to 1 to select setup register.
Clock mode and CNVST configuration. Resets to 1 at power-up.
Clock mode and CNVST configuration.
Reference mode configuration.
Reference mode configuration.
Unipolar/bipolar mode register configuration for differential mode.
Unipolar/bipolar mode register configuration for differential mode.
*See below for bit details.
CKSEL1
0
0
1
1
CKSEL0
0
1
0
1
CONVERSION CLOCK
Internal
Internal
Internal
External (4.8MHz max)
ACQUISITION/SAMPLING
Internally timed
Externally timed through CNVST
Internally timed
Externally timed through SCLK
CNVST CONFIGURATION
CNVST
CNVST
AIN15/11/7
AIN15/11/7
REFSEL1 REFSEL0
00
01
10
11
VOLTAGE REFERENCE
Internal
External single ended
Internal
External differential
AutoShutdown
Reference off after scan; need
wake-up delay.
Reference off; no wake-up delay.
Reference always on; no wake-up
delay.
Reference off; no wake-up delay.
REF- CONFIGURATION
AIN14/10/6
AIN14/10/6
AIN14/10/6
REF-
DIFFSEL1 DIFFSEL0
FUNCTION
0 0 No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged.
0 1 No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged.
1 0 One byte of data follows the setup byte and is written to the unipolar mode register.
1 1 One byte of data follows the setup byte and is written to the bipolar mode register.
14 ______________________________________________________________________________________


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set to 1. Select scan mode 10 to scan the same channel
multiple times. Clock mode 11 disables averaging.
Reset Register
Write to the reset register (as shown in Table 7) to clear
the FIFO or to reset all registers to their default states.
Set the RESET bit to 1 to reset the FIFO. Set the reset
bit to zero to return the MAX1027/MAX1029/MAX1031
to its default power-up state.
Power-Up Default State
The MAX1027/MAX1029/MAX1031 power up with all
blocks in shutdown, including the reference. All registers
power up in state 00000000, except for the setup regis-
ter, which powers up in clock mode 10 (CKSEL1 = 1).
Temperature Measurements
The MAX1027/MAX1029/MAX1031 perform tempera-
ture measurements with an internal diode-connected
transistor. The diode bias current changes from 68μA
to 4μA to produce a temperature-dependent bias volt-
age difference. The second conversion result at 4μA is
subtracted from the first at 68μA to calculate a digital
value that is proportional to absolute temperature. The
output data appearing at DOUT is the above digital
code minus an offset to adjust from Kelvin to Celsius.
The reference voltage used for the temperature mea-
surements is derived from the internal reference source
to ensure a resolution of 1/8 of a degree.
Output Data Format
Figures 4–7 illustrate the conversion timing for the
MAX1027/MAX1029/MAX1031. The 10-bit conversion
result is output in MSB-first format with four leading
zeroes and two trailing sub-bits. The 12-bit temperature
measurement is output with four leading zeros. DIN
data is latched into the serial interface on the rising
edge of SCLK. Data on DOUT transitions on the falling
edge of SCLK. Conversions in clock modes 00 and 01
are initiated by CNVST. Conversions in clock modes 10
and 11 are initiated by writing an input data byte to the
conversion register. Data is binary for unipolar mode and
two’s complement for bipolar mode.
Table 4. Unipolar Mode Register (Addressed Through Setup Register)
BIT NAME
UCH0/1
UCH2/3
UCH4/5
UCH6/7
UCH8/9
UCH10/11
UCH12/13
UCH14/15
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
FUNCTION
Set to 1 to configure AIN0 and AIN1 for unipolar differential conversion.
Set to 1 to configure AIN2 and AIN3 for unipolar differential conversion.
Set to 1 to configure AIN4 and AIN5 for unipolar differential conversion.
Set to 1 to configure AIN6 and AIN7 for unipolar differential conversion.
Set to 1 to configure AIN8 and AIN9 for unipolar differential conversion (MAX1029/MAX1031 only).
Set to 1 to configure AIN10 and AIN11 for unipolar differential conversion (MAX1029/MAX1031 only).
Set to 1 to configure AIN12 and AIN13 for unipolar differential conversion (MAX1031 only).
Set to 1 to configure AIN14 and AIN15 for unipolar differential conversion (MAX1031 only).
Table 5. Bipolar Mode Register (Addressed Through Setup Register)
BIT NAME
BCH0/1
BCH2/3
BCH4/5
BCH6/7
BCH8/9
BCH10/11
BCH12/13
BCH14/15
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
FUNCTION
Set to 1 to configure AIN0 and AIN1 for bipolar differential conversion.
Set to 1 to configure AIN2 and AIN3 for bipolar differential conversion.
Set to 1 to configure AIN4 and AIN5 for bipolar differential conversion.
Set to 1 to configure AIN6 and AIN7 for bipolar differential conversion.
Set to 1 to configure AIN8 and AIN9 for bipolar differential conversion (MAX1029/MAX1031 only).
Set to 1 to configure AIN10 and AIN11 for bipolar differential conversion (MAX1029/MAX1031 only).
Set to 1 to configure AIN12 and AIN13 for bipolar differential conversion (MAX1031 only).
Set to 1 to configure AIN14 and AIN15 for bipolar differential conversion (MAX1031 only).
______________________________________________________________________________________ 15


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10-Bit 300ksps ADCs with FIFO,
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Table 6. Averaging Register*
BIT NAME
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
FUNCTION
Set to zero to select averaging register.
Set to zero to select averaging register.
Set to 1 to select averaging register.
Set to 1 to turn averaging on. Set to zero to turn averaging off.
Configures the number of conversions for single channel scans.
Configures the number of conversions for single channel scans.
Single channel scan count. (Scan mode 10 only.)
Single channel scan count. (Scan mode 10 only.)
*See below for bit details.
AVGON
0
1
1
1
1
NAVG1
x
0
0
1
1
NAVG0
x
0
1
0
1
FUNCTION
Performs 1 conversion for each requested result.
Performs 4 conversions and returns the average for each requested result.
Performs 8 conversions and returns the average for each requested result.
Performs 16 conversions and returns the average for each requested result.
Performs 32 conversions and returns the average for each requested result.
NSCAN1
0
0
1
1
NSCAN0
0
1
0
1
FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
Scans channel N and returns 4 results.
Scans channel N and returns 8 results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
Table 7. Reset Register
BIT NAME
RESET
x
x
x
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
FUNCTION
Set to zero to select reset register.
Set to zero to select reset register.
Set to zero to select reset register.
Set to 1 to select reset register.
Set to zero to reset all registers. Set to 1 to clear the FIFO only.
Reserved. Don’t care.
Reserved. Don’t care.
Reserved. Don’t care.
16 ______________________________________________________________________________________


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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Internally Timed Acquisitions and
Conversions Using CNVST
Performing Conversions in Clock Mode 00
In clock mode 00, the wake up, acquisition, conversion,
and shutdown sequences are initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 4 for clock mode 00 timing.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1027/MAX1029/
MAX1031 then wake up, scan all requested channels,
store the results in the FIFO, and shut down. After the
scan is complete, EOC is pulled low and the results are
available in the FIFO. Wait until EOC goes low before
pulling CS low to communicate with the serial interface.
EOC stays low until CS or CNVST is pulled low again. A
temperature measurement result, if requested, pre-
cedes all other FIFO results.
Do not initiate a second CNVST before EOC goes low;
otherwise, the FIFO can become corrupted.
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
Performing Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using the
internal oscillator. See Figure 5 for clock mode 01 timing.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4μs to complete the acquisition. If the internal
reference needs to wake up, an additional 65μs is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement are internally
timed. In this case, hold CNVST low for at least 40ns.
Set CNVST high to begin a conversion. After the con-
version is complete, the ADC shuts down and pulls
EOC low. EOC stays low until CS or CNVST is pulled
low again. Wait until EOC goes low before pulling CS or
CNVST low.
If averaging is turned on, multiple CNVST pulses need
to be performed before a result is written to the FIFO.
Once the proper number of conversions has been per-
formed to generate an averaged FIFO result, as speci-
fied by the averaging register, the scan logic
automatically switches the analog input multiplexer to
the next-requested channel. If a temperature measure-
ment is programmed, it is performed after the first rising
edge of CNVST following the input data byte written to
the conversion register. The result is available on DOUT
once EOC has been pulled low.
CNVST
CS
SCLK
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
DOUT
MSB1
LSB1 MSB2
EOC
SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION. X = DON'T CARE.
Figure 4. Clock Mode 00
______________________________________________________________________________________ 17


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10-Bit 300ksps ADCs with FIFO,
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CNVST
(ACQUISITION1)
CS
(ACQUISITION2)
SCLK
(CONVERSION1)
(CONVERSION2)
DOUT
MSB1
LSB1
EOC
REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. X = DON'T CARE.
Figure 5. Clock Mode 01
MSB2
DIN
CS
SCLK
(CONVERSION BYTE)
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
DOUT
MSB1
LSB1 MSB2
EOC
THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED. X = DON'T CARE.
Figure 6. Clock Mode 10
Internally Timed Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 10
In clock mode 10, the wake up, acquisition, conversion,
and shutdown sequences are initiated by writing an
input data byte to the conversion register, and are per-
formed automatically using the internal oscillator. This
is the default clock mode upon power-up. See Figure 6
for clock mode 10 timing.
Initiate a scan by writing a byte to the conversion regis-
ter. The MAX1027/MAX1029/MAX1031 then power up,
scan all requested channels, store the results in the
FIFO, and shut down. After the scan is complete, EOC
is pulled low and the results are available in the FIFO. If
a temperature measurement is requested, the tempera-
ture result precedes all other FIFO results. EOC stays
low until CS is pulled low again.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
18 ______________________________________________________________________________________


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10-Bit 300ksps ADCs with FIFO,
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DIN
CS
SCLK
(ACQUISITION1)
(CONVERSION BYTE)
(CONVERSION1)
(ACQUISITION2)
DOUT
MSB1
EOC
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. X = DON'T CARE.
LSB1
MSB2
Figure 7. Clock Mode 11
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the eighth and ninth cycles, the pulse
width must be less than 100μs. To continuously convert
at 16 cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
If reference mode 00 is requested, or if an external ref-
erence is selected but a temperature measurement is
being requested, wait 65μs with CS high after writing
the conversion byte to extend the acquisition and allow
the internal reference to power up. To perform a tem-
perature measurement, write 24 bytes (192 cycles) of
zeros after the conversion byte. The temperature result
appears on DOUT during the last 2 bytes of the 192
cycles.
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than 8 SCLK cycles), the
second byte of data that is read out contains the next 8
bits (not b7–b0). The remaining bits are lost for that
entry. If the first byte of an entry in the FIFO is read out
fully, but the second byte is read out partially, the rest
of the entry is lost. The remaining data in the FIFO is
uncorrupted and can be read out normally after taking
CS low again, as long as the 4 leading bits (normally
zeros) are ignored. Internal registers that are written
partially through the SPI contain new values, starting at
the MSB up to the point that the partial write is stopped.
The part of the register that is not written contains previ-
ously written values. If CS is pulled low before EOC
goes low, a conversion cannot be completed and the
FIFO is corrupted.
Transfer Function
Figure 8 shows the unipolar transfer function for single-
ended or differential inputs. Figure 9 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = VREF / 1024V for
unipolar and bipolar operation, and 1 LSB = 0.125°C
for temperature measurements.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Do not use wire-
wrap boards. For the TQFN package, connect its
exposed pad to GND. Board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
signals parallel to one another or run digital lines under-
neath the MAX1027/MAX1029/MAX1031 package. High-
frequency noise in the VDD power supply can affect
performance. Bypass the VDD supply with a 0.1μF
capacitor to GND, close to the VDD pin. Minimize capac-
itor lead lengths for best supply-noise rejection. If the
power supply is very noisy, connect a 10Ω resistor in
series with the supply to improve power-supply filtering.
______________________________________________________________________________________ 19


MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
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OUTPUT CODE
11 . . . 111
11 . . . 110
11 . . . 101
FULL-SCALE
TRANSITION
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
01
(COM)
23
INPUT VOLTAGE (LSB)
FS = VREF + VCOM
ZS = VCOM
1 LSB = VREF
1024
FS
FS - 3/2 LSB
Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF
OUTPUT CODE
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
FS =
VREF
2
+ VCOM
ZS = COM
-FS = -VREF
2
1 LSB = VREF
1024
100 . . . 001
100 . . . 000
- FS
*VCOM VREF/2
COM*
INPUT VOLTAGE (LSB)
+FS - 1 LSB
Figure 9. Bipolar Transfer Function, Full Scale (±FS) = ±VREF/2
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1027/MAX1029/MAX1031 is measured using
the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD (dB) = 20 x log (SignalRMS/NoiseRMS)
20 ______________________________________________________________________________________


MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
TOP VIEW
+
AIN0 1
AIN1 2
AIN2 3
AIN3 4
AIN4 5
MAX1031
AIN5 6
AIN6 7
AIN7 8
AIN8 9
AIN9 10
AIN10 11
AIN11 12
QSOP
24 EOC
23 DOUT
22 DIN
21 CS
20 SCLK
19 VDD
18 GND
17 REF+
16 CNVST/AIN15
15 REF-/AIN14
14 AIN13
13 AIN12
Pin Configurations (continued)
21 20 19 18 17 16 15
DIN 22
DOUT 23
EOC 24
N.C. 25
AIN0 26
MAX1031
AIN1 27
AIN2 28
+
14 CNVST/AIN15
13 REF-/AIN14
12 AIN13
11 AIN12
10 AIN11
9 AIN10
8 AIN9
1 234567
TQFN
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
( )THD
=
20
x
log
⎝⎜
V22 + V32 + V42 + V52
/ V1⎠⎟
where V1 is the fundamental amplitude, and V2–V5 are
the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest distor-
tion component.
Ordering Information (continued)
PART
TEMP RANGE
PIN-PACKAGE
MAX1031BCEG+T 0°C to +70°C
24 QSOP
MAX1031BEEG+T -40°C to +85°C
24 QSOP
MAX1031BCTI+T
0°C to +70°C
28 TQFN-EP*
MAX1031BETI+T
-40°C to +85°C
28 TQFN-EP*
*EP = Exposed pad (connect to GND).
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
16 QSOP
20 QSOP
24 QSOP
28 TQFN-EP
PACKAG
E CODE
E16+5
E20+3
E24+3
T2855+8
DOCUMENT
NO.
21-0055
21-0140
LAND
PATTERN NO.
90-0167
90-0168
90-0172
90-0026
______________________________________________________________________________________ 21


MAX1029 (Maxim Integrated Products)
(MAX1027 - MAX1031) 10-Bit 300ksps ADCs

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Revision History
REVISION REVISION
NUMBER DATE
DESCRIPTION
3
3/09
In the General Description section, corrected the text stating that all three devices
operate from a +5V supply to a +3V supply.
Removed the Grade A devices from the Ordering Information table and Electrical
4 11/09 Characteristics table.
Updated Ordering Information, General Description, Electrical Characteristics, Typical
5
8/11
Operating Characteristics, Pin Description, and Figure 1.
PAGES
CHANGED
1
1, 3, 21
1–9, 11, 21
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.




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