ADE7569 (Analog Devices)
Single-Phase Energy Measurement IC

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Data Sheet
Single-Phase Energy Measurement IC
with 8052 MCU, RTC, and LCD Driver
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
GENERAL FEATURES
Wide supply voltage operation: 2.4 V to 3.7 V
Internal bipolar switch between regulated and battery inputs
Ultralow power operation with power saving modes (PSM)
Full operation: 4 mA to 1.6 mA (PLL clock dependent)
Battery mode: 3.2 mA to 400 µA (PLL clock dependent)
Sleep mode
Real-time clock (RTC) mode: 1.5 µA
RTC and LCD mode: 38 µA (LCD charge pump enabled)
Reference: 1.2 V ± 0.1% (10 ppm/°C drift)
64-lead RoHS package option
Low profile quad flat package (LQFP)
Operating temperature range: −40°C to +85°C
ENERGY MEASUREMENT FEATURES
Proprietary analog-to-digital converters (ADCs) and digital
signal processing (DSP) provide high accuracy active
(watt), reactive (var), and apparent energy (volt ampere
(VA)) measurement
<0.1% error on active energy over a dynamic range of
1000 to 1 at 25°C
<0.5% error on reactive energy over a dynamic range of
1000 to 1 at 25°C (ADE7169 and ADE7569 only)
<0.5% error on root mean square (rms) measurements
over a dynamic range of 500 to 1 for current (Irms) and
100 to 1 for voltage (Vrms) at 25°C
Supports IEC 62053-21, IEC 62053-22, and IEC 62053-23;
EN 50470-3 Class A, Class B, and Class C; and ANSI C12-16
Differential input with programmable gain amplifiers (PGAs)
supports shunts, current transformers, and di/dt current
sensors (ADE7169 and ADE7569 only)
2 current inputs for antitamper detection in the ADE7116/
ADE7166/ADE7169
High frequency outputs proportional to Irms, active, reactive,
or apparent power (AP)
Table 1. Features Available on Each Device
Feature
Part No.
Antitamper
ADE7116, ADE7166, ADE7169
Watt, VA, Irms, Vrms
ADE7116, ADE7166, ADE7169, ADE7566,
ADE7569
Var ADE7169, ADE7569
di/dt Sensor
ADE7169, ADE7569
MICROPROCESSOR FEATURES
8052-based core
Single-cycle 4 MIPS 8052 core
8052-compatible instruction set
32.768 kHz external crystal with on-chip PLL
2 external interrupt sources
External reset pin
Low power battery mode
Wake up from input/output (I/O), temperature change1,
alarm, and universal asynchronous receiver/transmitter
(UART)
LCD driver operation
Temperature measurement
Real-time clock (RTC)
Counter for seconds, minutes, and hours
Automatic battery switchover for RTC backup
Operation down to 2.4 V
Ultralow battery supply current: 1.5 µA
Selectable output frequency: 1 Hz to 16 kHz
Embedded digital crystal frequency compensation for
calibration and temperature variation of 2 ppm resolution
Integrated LCD driver
108-segment driver for the ADE7566/ADE7569 and
104-segment driver for the ADE7116/ADE7166/ADE7169
2×, 3×, or 4× multiplexing
LCD voltages generated internally1 or with external resistors
Internal adjustable drive voltages up to 5 V independent
of power supply level1
On-chip peripherals
UART interface
SPI or I2C
Watchdog timer
Power supply management with user selectable levels
Memory: 16 kB flash memory, 512 bytes RAM
Development tools
Single pin emulation
IDE based assembly and C-source debugging
1 Not available in the ADE7116.
Rev. C
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ADE7569 (Analog Devices)
Single-Phase Energy Measurement IC

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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
TABLE OF CONTENTS
General Features ............................................................................... 1 
Energy Measurement Features........................................................ 1 
Microprocessor Features.................................................................. 1 
Revision History ............................................................................... 3 
General Description ......................................................................... 4 
Functional Block Diagrams............................................................. 4 
Specifications..................................................................................... 6 
Energy Metering ........................................................................... 6 
Analog Peripherals ....................................................................... 7 
Digital Interface ............................................................................ 8 
Timing Specifications ................................................................ 10 
Absolute Maximum Ratings.......................................................... 15 
Thermal Resistance .................................................................... 15 
ESD Caution................................................................................ 15 
Pin Configurations and Function Descriptions ......................... 16 
Typical Performance Characteristics ........................................... 22 
Performance Curves for the ADE7169 and ADE7569 Only. 25 
Terminology .................................................................................... 26 
Special Function Register (SFR) Mapping .................................. 27 
Power Management........................................................................ 30 
Power Management Register Details ....................................... 30 
Power Supply Architecture........................................................ 33 
Battery Switchover...................................................................... 33 
Power Supply Management (PSM) Interrupt ......................... 34 
Using the Power Supply Features ............................................. 36 
Operating Modes ............................................................................ 38 
PSM0 (Normal Mode) ............................................................... 38 
PSM1 (Battery Mode) ................................................................ 38 
PSM2 (Sleep Mode).................................................................... 38 
3.3 V Peripherals and Wake-Up Events................................... 39 
Transitioning Between Operating Modes ............................... 40 
Using the Power Management Features .................................. 40 
Energy Measurement ..................................................................... 41 
Access to Energy Measurement SFRs ...................................... 41 
Access to Internal Energy Measurement Registers................ 41 
Energy Measurement Registers ................................................ 44 
Energy Measurement Internal Register Details ..................... 45 
Interrupt Status/Enable SFRs .................................................... 48 
Analog Inputs.............................................................................. 50 
Analog-to-Digital Conversion.................................................. 51 
Fault Detection ........................................................................... 55 
di/dt Current Sensor and Digital Integrator for the
ADE7169/ADE7569 ................................................................... 56 
Power Quality Measurements................................................... 58 
Phase Compensation ................................................................. 60 
RMS Calculation ........................................................................ 60 
Active Power Calculation .......................................................... 63 
Active Energy Calculation ........................................................ 65 
Reactive Power Calculation (ADE7169/ADE7569) ............... 68 
Reactive Energy Calculation (ADE7169/ADE7569).............. 69 
Apparent Power Calculation..................................................... 73 
Apparent Energy Calculation ................................................... 74 
Ampere Hour Accumulation.................................................... 75 
Energy to Frequency Conversion............................................. 76 
Energy Register Scaling ............................................................. 77 
Energy Measurement Interrupts .............................................. 77 
Temperature, Battery, and Supply Voltage Measurements........ 78 
Temperature Measurement ....................................................... 80 
Battery Measurement................................................................. 80 
External Voltage Measurement ................................................ 81 
8052 MCU Core Architecture....................................................... 83 
MCU Registers............................................................................ 83 
Basic 8052 Registers ................................................................... 85 
Standard 8052 SFRs.................................................................... 86 
Memory Overview ..................................................................... 86 
Addressing Modes...................................................................... 87 
Instruction Set ............................................................................ 89 
Read-Modify-Write Instructions ............................................. 91 
Instructions That Affect Flags .................................................. 91 
Dual Data Pointers ......................................................................... 93 
Interrupt System ............................................................................. 94 
Standard 8052 Interrupt Architecture ..................................... 94 
Interrupt Architecture ............................................................... 94 
Interrupt Registers...................................................................... 94 
Interrupt Priority........................................................................ 95 
Interrupt Flags ............................................................................ 96 
Interrupt Vectors ........................................................................ 98 
Interrupt Latency........................................................................ 98 
Context Saving............................................................................ 98 
Watchdog Timer ............................................................................. 99 
Rev. C | Page 2 of 152


ADE7569 (Analog Devices)
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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Writing to the Watchdog Timer SFR (WDCON,
Address 0xC0) .......................................................................... 100 
Watchdog Timer Interrupt...................................................... 100 
LCD Driver ................................................................................... 101 
LCD Registers ........................................................................... 101 
LCD Setup ................................................................................. 104 
LCD Timing and Waveforms ................................................. 104 
Blink Mode................................................................................ 105 
Display Element Control......................................................... 105 
Voltage Generation .................................................................. 106 
LCD External Circuitry........................................................... 107 
LCD Function in PSM2 Mode ............................................... 107 
Flash Memory ............................................................................... 109 
Flash Memory Overview......................................................... 109 
Flash Memory Organization................................................... 110 
Using the Flash Memory ......................................................... 110 
Protecting the Flash Memory ................................................. 114 
In Circuit Programming ......................................................... 115 
Timers ............................................................................................ 116 
Timer Registers......................................................................... 116 
Timer 0 and Timer 1................................................................ 118 
Timer 2 ...................................................................................... 119 
Phase-Locked Loop (PLL) .......................................................... 121 
PLL Registers ............................................................................ 121 
Real-Time Clock (RTC) .............................................................. 122 
RTC SFRs .................................................................................. 122 
Read and Write Operations .................................................... 125 
RTC Modes ............................................................................... 125 
RTC Interrupts ..........................................................................125 
RTC Calibration ........................................................................126 
UART Serial Interface...................................................................127 
UART SFRs ................................................................................127 
UART Operation Modes ..........................................................130 
UART Baud Rate Generation ..................................................131 
UART Additional Features ......................................................133 
Serial Peripheral Interface (SPI)..................................................134 
SPI Registers ..............................................................................134 
SPI Pins.......................................................................................137 
SPI Master Operating Modes ..................................................138 
SPI Interrupt and Status Flags .................................................139 
I2C-Compatible Interface .............................................................140 
Serial Clock Generation ...........................................................140 
Slave Addresses..........................................................................140 
I2C Registers...............................................................................140 
Read and Write Operations .....................................................141 
I2C Receive and Transmit FIFOs.............................................142 
I/O Ports .........................................................................................143 
Parallel I/O.................................................................................143 
I/O Registers ..............................................................................144 
Port 0...........................................................................................147 
Port 1...........................................................................................147 
Port 2...........................................................................................147 
Determining the Version of the Device .....................................148 
Outline Dimensions......................................................................149 
Ordering Guide .........................................................................149 
REVISION HISTORY
10/15—Rev. B to Rev. C
Deleted ADE7156 and 64-Lead LFCSP_VQ Package ... Universal
Changes to Figure 46 ......................................................................53
Updated Outline Dimensions......................................................150
Changes to Ordering Guide.........................................................151
11/08—Rev. A to Rev. B
Added ADE7116/ADE7156 .............................................. Universal
Changes to Table 1 ............................................................................1
Added Figure 2 ..................................................................................5
Changes to Table 13 ........................................................................16
Added Figure 10 and Table 14; Renumbered Sequentially........19
Added Exposed Pad Notation to Outline Dimensions ............148
Changes to Ordering Guide.........................................................149
12/07—Rev. 0 to Rev. A
Added ADE7166/ADE7169.............................................. Universal
Changes to Table 1 ............................................................................1
Changes to Ordering Guide.........................................................144
11/07—Revision 0: Initial Version
Rev. C | Page 3 of 152


ADE7569 (Analog Devices)
Single-Phase Energy Measurement IC

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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
GENERAL DESCRIPTION
The ADE7116/ADE7166/ADE7169/ADE7566/ADE75691
integrate the Analog Devices, Inc., energy (ADE) metering IC
analog front end and fixed function DSP solution with an
enhanced 8052 MCU core, an RTC, an LCD driver, and all the
peripherals to make an electronic energy meter with an LCD
display in a single device.
The ADE measurement core includes active, reactive, and apparent
energy calculations, as well as voltage and current rms measure-
ments. This information is accessible for energy billing by using
the built in energy scalars. Many power line supervisory features
such as SAG, peak, and zero crossing are included in the energy
measurement DSP to simplify energy meter design.
The microprocessor functionality includes a single cycle 8052
core, a real-time clock with a power supply backup pin, an SPI
or I2C interface, and a UART interface. The ready to use infor-
mation from the ADE core reduces the program memory size
requirement, making it easy to integrate complicated design
into 16 kB of flash memory.
The ADE7116/ADE7166/ADE7169/ADE7566/ADE7569 also
include a 108-/104-segment LCD driver. In the ADE7166/
ADE7169/ADE7566/ADE7569, this driver generates voltages
capable of driving LCDs up to 5 V.
1 Patents pending.
FUNCTIONAL BLOCK DIAGRAMS
IP 52
IN 53
VP 49
VN 50
DGND 63
AGND 54
VBAT 58
57 43 42
38 39 40 41 39 38 7 6
45 11 43 42 41 40 39 38 37 36 5 6 7 8 9 10
1.20V
REF
+
PGA1
ADC
+
PGA2
ADC
SPI/I2C
SERIAL
INTERFACE
3 × 16-BIT
COUNTER
TIMERS
ENERGY
MEASUREMENT
DSP
ADE7566/ADE7569
3V/5V LCD
CHARGE PUMP
108-SEGMENT
LCD DRIVER
TEMP
SENSOR
TEMP
ADC
BATTERY
ADC
POWER SUPPLY
CONTROL AND
MONITORING
PROGRAM MEMORY
16kB FLASH
USER RAM
256 BYTES
USER XRAM
256 BYTES
VDCIN
ADC
LDO
POR
LDO
SINGLE
CYCLE
8052
MCU
WATCHDOG
TIMER
DOWNLOADER
DEBUGGER
UART
TIMER
UART
SERIAL
PORT
PLL
RTC OSC
64 60
61 62 59 56 51 44
36 37
47 46 48
12 P2.0/FP18
13 P2.1/FP17
14 P2.2/FP16
44 P2.3 (SDEN/P2.3)
16 LCDVP2
18 LCDVA
17 LCDVB
15 LCDVC
4 COM0
...
1 COM3
35 FP0
...
20 FP15
14 FP16
13 FP17
12 FP18
11 FP19
10 FP20
9 FP21
8 FP22
7 FP23
6 FP24
5 FP25
55 FP26
1 FP27
2 FP28
45
Figure 1. ADE7566/ADE7569 Functional Block Diagram
Rev. C | Page 4 of 152


ADE7569 (Analog Devices)
Single-Phase Energy Measurement IC

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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
IPA 52
IN 53
IPB 55
VP 49
VN 50
DGND 63
AGND 54
VBAT 58
57 43 42
38 39 40 41 39 38 7 6
45 11 43 42 41 40 39 38 37 36 5 6 7 8 9 10
12 P2.0/FP18
1.20V
REF
SPI/I2C
SERIAL
INTERFACE
3 × 16-BIT
COUNTER
TIMERS
ADE7116/ADE7166/ADE7169
13 P2.1/FP17
14 P2.2/FP16
44 P2.3 (SDEN/P2.3)
19 LCDVP1
+
PGA1
PGA1
+
ADC
ADC
ENERGY
MEASUREMENT
DSP
3V/5V LCD
CHARGE PUMP
16 LCDVP2
18 LCDVA
17 LCDVB
15 LCDVC
4 COM0
...
+
PGA2
ADC
PROGRAM MEMORY
16kB FLASH
SINGLE
CYCLE
8052
MCU
104-SEGMENT
LCD DRIVER
WATCHDOG
TIMER
1 COM3
35 FP0
...
20 FP15
14 FP16
TEMP
SENSOR
TEMP
ADC
BATTERY
ADC
POWER SUPPLY
CONTROL AND
MONITORING
USER RAM
256 BYTES
USER XRAM
256 BYTES
VDCIN
ADC
LDO
POR
LDO
DOWNLOADER
DEBUGGER
UART
TIMER
UART
SERIAL
PORT
PLL
RTC OSC
13 FP17
12 FP18
11 FP19
10 FP20
9 FP21
8 FP22
7 FP23
6 FP24
5 FP25
1 FP27
64 60
61 62 59 56 51 44
36 37
2 FP28
47 46 48 45
Figure 2. ADE7116/ADE7166/ADE7169 Functional Block Diagram
Rev. C | Page 5 of 152


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Single-Phase Energy Measurement IC

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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
SPECIFICATIONS
VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
ENERGY METERING
Table 2.
Parameter
Min Typ
Max Unit
MEASUREMENT ACCURACY1
Phase Error Between Channels2
PF = 0.8 Capacitive
±0.05
Degrees
PF = 0.5 Inductive
±0.05
Degrees
Active Energy Measurement Error2
0.1 % of reading
AC Power Supply Rejection2
Output Frequency Variation
0.01 %
DC Power Supply Rejection2
Output Frequency Variation
0.01 %
Active Energy Measurement Bandwidth1
8
kHz
Reactive Energy Measurement Error2, 3
0.5
% of reading
Vrms Measurement Error2
Vrms Measurement Bandwidth1
Irms Measurement Error2
Irms Measurement Bandwidth1
ANALOG INPUTS
0.5 % of reading
3.9 kHz
0.5 % of reading
3.9 kHz
Maximum Signal Levels
±400 mV peak
ADE7566/ADE7569
±400 mV peak
ADE7116/ADE7166/ADE7169
±250 mV peak
Input Impedance (DC)
770 kΩ
ADC Offset Error2
±10 mV
±1 mV
Gain Error2
Current Channel
±3 %
Voltage Channel
±3 +3 %
Gain Error Match
±0.2 %
CF1 AND CF2 PULSE OUTPUT
Maximum Output Frequency
13.5 kHz
Duty Cycle
Active High Pulse Width
FAULT DETECTION4
Fault Detection Threshold
Inactive Input ≠ Active Input
Input Swap Threshold
Inactive Input > Active Input
Accuracy Fault Mode Operation
IPA Active, IPB = AGND
IPB Active, IPA = AGND
Fault Detection Delay
Swap Delay
50 %
90 ms
6.25 % of active
6.25 % of active
0.1 % of reading
0.1 % of reading
3 Seconds
3 Seconds
Test Conditions/Comments
Phase lead: 37°
Phase lag: 60°
Over a dynamic range of 1000 to 1 at 25°C
VDD = 3.3 V + 100 mV rms/120 Hz
IPx = VP = ±100 mV rms
VDD = 3.3 V ± 117 mV dc
Over a dynamic range of 1000 to 1 at 25°C
Over a dynamic range of 100 to 1 at 25°C
Over a dynamic range of 500 to 1 at 25°C
VP − VN differential input
IP − IN differential input
IPA − IN and IPB − IN differential inputs
PGA1 = PGA2 = 1
PGA1 = 16
IPA = IPB = 0.4 V dc or IP = 0.4 V dc
VP − VN = 0.4 V dc
VP − VN = 400 mV peak, IPA − IN = 250 mV,
PGA1 = 2 sine wave
If CF1 or CF2 frequency, >5.55 Hz
If CF1 or CF2 frequency, <5.55 Hz
IPA or IPB active
IPA or IPB active
Over a dynamic range of 500 to 1
Over a dynamic range of 500 to 1
1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
2 See the Terminology section for definition.
3 This function is not available in the ADE7166 or ADE7566.
4 This function is not available in the ADE7566 or ADE7569.
Rev. C | Page 6 of 152


ADE7569 (Analog Devices)
Single-Phase Energy Measurement IC

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Data Sheet
ANALOG PERIPHERALS
Table 3.
Parameter
INTERNAL ADCs (BATTERY, TEMPERATURE, VDCIN)1
Power Supply Operating Range
No Missing Codes2
Conversion Delay3
ADC Gain
VDCIN Measurement
VBAT Measurement
Temperature Measurement
ADC Offset
VDCIN Measurement at 3 V
VBAT Measurement at 3.7 V
Temperature Measurement at 25°C
VDCIN Analog Input
Maximum Signal Levels
Input Impedance (DC)
Low VDCIN Detection Threshold
POWER-ON RESET (POR)
VDD POR
Detection Threshold
POR Active Timeout Period
VSWOUT POR
Detection Threshold
POR Active Timeout Period
VINTD POR
Detection Threshold
POR Active Timeout Period
VINTA POR
Detection Threshold
POR Active Timeout Period
BATTERY SWITCHOVER
Voltage Operating Range (VSWOUT)
VDD to VBAT Switching
Switching Threshold (VDD)
Switching Delay
VBAT to VDD Switching
Switching Threshold (VDD)
Switching Delay
VSWOUT to VBAT Leakage Current
LCD, CHARGE PUMP ACTIVE4
Charge Pump Capacitance Between LCDVP1 and
LCDVP2
LCDVA, LCDVB, LCDVC Decoupling Capacitance
LCDVA
LCDVB
LCDVC
V1 Segment Line Voltage
V2 Segment Line Voltage
V3 Segment Line Voltage
DC Voltage Across Segment and COMx Pin
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Min
Typ Max Unit
Test Conditions/Comments
2.4
3.7 V
Measured on VSWOUT
8 Bits
38 µs
15.3 mV/LSB
14.6 mV/LSB
0.78 °C/LSB
206 LSB
205 LSB
129 LSB
0 3.3 V
1 MΩ
1.09 1.2 1.27 V
2.5 2.95 V
33 ms
1.8 2.2 V
20 ms
2.0 2.25 V
16 ms
2.05 2.25 V
120 ms
2.4 3.7 V
2.5 2.95 V
10 ns
30 ms
2.5 2.95 V
30 ms
10 nA
100
470
0
0
0
LCDVA − 0.1
LCDVB − 0.1
LCDVC − 0.1
nF
1.75
3.5
5.3
LCDVA
LCDVB
LCDVC
50
nF
V
V
V
V
V
V
mV
Rev. C | Page 7 of 152
When VDD to VBAT switch activated by VDD
When VDD to VBAT switch activated by VDCIN
Based on VDD > 2.75 V
VBAT = 0 V, VSWOUT = 3.43 V, TA = 25°C
1/3 bias mode
1/3 bias mode
Current on segment line = −2 µA
Current on segment line = −2 µA
Current on segment line = −2 µA
LCDVC − LCDVB, LCDVC − LCDVA, or
LCDVB − LCDVA


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
Parameter
LCD, RESISTOR LADDER ACTIVE
Leakage Current
V1 Segment Line Voltage
V2 Segment Line Voltage
V3 Segment Line Voltage
ON-CHIP REFERENCE
Reference Error
Power Supply Rejection
Temperature Coefficient2
Min
Typ Max Unit
Test Conditions/Comments
±20 nA
LCDVA − 0.1
LCDVA V
LCDVB − 0.1
LCDVB V
LCDVC − 0.1
LCDVC V
1/2 and 1/3 bias modes, no load
Current on segment line = −2 µA
Current on segment line = −2 µA
Current on segment line = −2 µA
±0.9
80
10 50
mV
dB
ppm/°C
TA = 25°C
1 This function is not available in the ADE7116.
2 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
3 Delay between ADC conversion request and interrupt set.
4 This function is not available in the ADE7116.
DIGITAL INTERFACE
Table 4.
Parameter
LOGIC INPUTS1
All Inputs Except XTAL1, XTAL2, BCTRL,
INT0, INT1, RESET
Input High Voltage, VINH
Input Low Voltage, VINL
BCTRL, INT0, INT1, RESET
Input High Voltage, VINH
Input Low Voltage, VINL
Input Currents
RESET
Port 0, Port 1, Port 2
Input Capacitance
FLASH MEMORY
Endurance2
Data Retention3
CRYSTAL OSCILLATOR4
Crystal Equivalent Series Resistance
Crystal Frequency
XTAL1 Input Capacitance
XTAL2 Output Capacitance
MCU CLOCK RATE (fCORE)
LOGIC OUTPUTS
Output High Voltage, VOH
ISOURCE
Output Low Voltage, VOL5
ISINK
START-UP TIME6
PSM0 Power-On Time
From Power Saving Mode 1 (PSM1)
PSM1 to PSM0
From Power Saving Mode 2 (PSM2)
PSM2 to PSM1
PSM2 to PSM0
Min Typ Max Unit Test Conditions/Comments
2.0 V
0.8 V
1.3 V
0.8 V
−3.75
10
100
±100
−8.5
nA
nA
µA
pF
RESET = VSWOUT = 3.3 V
Internal pull-up disabled, input = 0 V or VSWOUT
Internal pull-up enabled, input = 0 V, VSWOUT = 3.3 V
All digital inputs
20,000
20
Cycles
Years TJ = 85°C
30 50 kΩ
32 32.768 33.5 kHz
12 pF
12 pF
4.096
MHz Crystal = 32.768 kHz and CD bits = 000
32 kHz Crystal = 32.768 kHz and CD bits = 111
2.4 V VDD = 3.3 V ± 5%
80 µA
0.4 V
2 mA
VDD = 3.3 V ± 5%
880 ms VDD at 2.75 V to PSM0 code execution
130 ms VDD at 2.75 V to PSM0 code execution
48 ms Wake-up event to PSM1 code execution
186 ms VDD at 2.75 V to PSM0 code execution
Rev. C | Page 8 of 152


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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Parameter
POWER SUPPLY INPUTS
VDD
VBAT
INTERNAL POWER SUPPLY SWITCH (VSWOUT)
VBAT to VSWOUT On Resistance
VDD to VSWOUT On Resistance
VBAT to/from VDD Switching Open Time
BCTRL State Change and Switch Delay
VSWOUT Output Current Drive
POWER SUPPLY OUTPUTS
VINTA
VINTD
VINTA Power Supply Rejection
VINTD Power Supply Rejection
POWER SUPPLY CURRENTS
Current in Normal Mode (PSM0)
Current in PSM1
Current in PSM2
Min Typ Max Unit Test Conditions/Comments
3.13 3.3
2.4 3.3
3.46 V
3.7 V
22 Ω
VBAT = 2.4 V
10.2 Ω
VDD = 3.13 V
40 ns
18 µs
6 mA
2.3
2.3
60
50
2.70 V
2.70 V
dB
dB
4
5.3 mA
fCORE = 4.096 MHz, LCD and meter active
2.1 mA fCORE = 1.024 MHz, LCD and meter active
1.6 mA fCORE = 32.768 kHz, LCD and meter active
3
3.9 mA
fCORE = 4.096 MHz, metering ADC and DSP powered down
3.2
5.05 mA
fCORE = 4.096 MHz, LCD active, VBAT = 3.7 V
880 µA fCORE = 1.024 MHz, LCD active
38 µA LCD active with charge pump at 3.3 V + RTC, VBAT = 3.3 V
1.5 µA RTC only, TA = 25°C, VBAT = 3.3 V
1 Specifications guaranteed by design.
2 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
3 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
4 Recommended crystal specifications.
5 Test carried out with all the I/Os set to a low output level.
6 Delay between power supply valid and execution of first instruction by 8052 core.
Rev. C | Page 9 of 152


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
TIMING SPECIFICATIONS
AC inputs during testing were driven at VSWOUT − 0.5 V for Logic 1
and at 0.45 V for Logic 0. Timing measurements were made at VIH
minimum for Logic 1 and at VIL maximum for Logic 0, as shown in
Figure 3.
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded VOH/VOL level
occurs, as shown in Figure 3.
CLOAD for all outputs is equal to 80 pF, unless otherwise noted.
VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless
otherwise noted.
VSWOUT – 0.5V
0.45V
0.2VSWOUT + 0.9V
TEST POINTS
0.2VSWOUT – 0.1V
VLOAD – 0.1V
VLOAD
VLOAD + 0.1V
TIMING
REFERENCE
POINTS
VLOAD – 0.1V
VLOAD
VLOAD – 0.1V
Figure 3. Timing Waveform Characteristics
Table 5. Clock Input (External Clock Driven XTAL1) Parameter
Parameter
tCK
tCKL
tCKH
tCKR
tCKF
1/tCORE
Description
XTAL1 period
XTAL1 width low
XTAL1 width high
XTAL1 rise time
XTAL1 fall time
Core clock frequency1
Min
32.768 kHz External Crystal
Typ Max
30.52
6.26
6.26
9
9
1.024
Unit
µs
µs
µs
ns
ns
MHz
1 The internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can
operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).
Table 6. I2C Compatible Interface Timing Parameters (400 kHz)
Parameter
Description
tBUF Bus free time between stop condition and start condition
tL SCLK low pulse width
tH SCLK high pulse width
tSHD Start condition hold time
tDSU Data setup time
tDHD Data hold time
tRSU Setup time for repeated start
tPSU Stop condition setup time
tR Rise time of both SCLK and SDATA
tF Fall time of both SCLK and SDATA
tSUP1 Pulse width of spike suppressed
Typ
1.3
1.36
1.14
251.35
740
400
12.5
400
200
300
50
Unit
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
1 Input filtering on both the SCLK and SDATA inputs suppresses noise spikes of <50 ns.
tBUF
tSUP
tR
SDATA (I/O)
MSB
LSB
ACK
MSB
tPSU
tDSU
tSHD
tDHD
tDSU
tH
tDHD
tRSU
SCLK (I)
PS
STOP
START
CONDITION CONDITION
1
2 TO 7
8
tL tSUP
9
Figure 4. I2C Compatible Interface Timing
S(R)
REPEATED
START
tF
tR
1
tF
Rev. C | Page 10 of 152


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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters
Parameter
Description
tSL SCLK low pulse width
tSH SCLK high pulse width
tDAV Data output valid after SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
Min
2SPIR × tCORE1
2SPIR × tCORE1
0
tCORE1
Typ
19
19
19
19
1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz.
Max
3 × tCORE1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
(SPICPOL = 0)
SCLK
(SPICPOL = 1)
MOSI
tSH
tDAV
tSL
tSR
tDF
MSB
tDR
BITS [6:1]
tSF
LSB
MISO
MSB IN
BITS [6:1]
tDSU
tDHD
Figure 5. SPI Master Mode Timing (SPICPHA = 1)
LSB IN
Rev. C | Page 11 of 152


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters
Parameter
Description
tSL SCLK low pulse width
tSH SCLK high pulse width
tDAV Data output valid after SCLK edge
tDOSU Data output setup before SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
Min
2SPIR × tCORE1
2SPIR × tCORE1
0
tCORE1
Typ
(SPIR + 1) × tCORE1
(SPIR + 1) × tCORE1
19
19
19
19
1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz.
Max
3 × tCORE1
75
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
(SPICPOL = 0)
SCLK
(SPICPOL = 1)
MOSI
tSH tSL
tDOSU
tDAV
tDF
MSB
tDR
BITS [6:1]
tSR tSF
LSB
MISO
MSB IN
BITS [6:1]
LSB IN
tDSU tDHD
Figure 6. SPI Master Mode Timing (SPICPHA = 0)
Rev. C | Page 12 of 152


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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters
Parameter
Description
tSS SS to SCLK edge
tSL SCLK low pulse width
tSH SCLK high pulse width
tDAV Data output valid after SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
tSFS SS high after SCLK edge
Min
145
6 × tCORE1
6 × tCORE1
0
2 × tCORE1 + 0.5 µs
0
1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz.
Typ
19
19
19
19
Max
25
SS
SCLK
(SPICPOL = 0)
SCLK
(SPICPOL = 1)
tSS
tSH
tSL
tSFS
tSR tSF
Unit
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
MISO
MOSI
tDAV
tDF
MSB
tDR
BITS [6:1]
MSB IN
BITS [6:1]
tDSU
tDHD
Figure 7. SPI Slave Mode Timing (SPICPHA = 1)
LSB
LSB IN
Rev. C | Page 13 of 152


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters
Parameter
Description
tSS SS to SCLK edge
tSL SCLK low pulse width
tSH SCLK high pulse width
tDAV Data output valid after SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
tDOSS Data output valid after SS edge
tSFS SS high after SCLK edge
Min
145
6 × tCORE1
6 × tCORE1
0
2 × tCORE1+ 0.5 µs
0
0
1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz.
Typ
19
19
19
19
SS
tSS
tSFS
SCLK
(SPICPOL = 0)
SCLK
(SPICPOL = 1)
tSH tSL
tSR tSF
MISO
tDOSS
tDAV
tDF
MSB
tDR
BITS [6:1]
LSB
Data Sheet
Max Unit
ns
ns
ns
25 ns
ns
µs
ns
ns
ns
ns
ns
ns
MOSI
MSB IN
BITS [6:1]
LSB IN
tDSU
tDHD
Figure 8. SPI Slave Mode Timing (SPICPHA = 0)
Rev. C | Page 14 of 152


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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 11.
Parameter
VDD to DGND
VBAT to DGND
VDCIN to DGND
Input LCD Voltage to AGND, LCDVA,
LCDVB, LCDVC1
Analog Input Voltage to AGND, VP, VN,
IP, IPA, IPB, and IN
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
(Industrial)
Storage Temperature Range
64-Lead LQFP, Power Dissipation
Lead Temperature (Soldering, 30 sec)
Rating
−0.3 V to +3.7 V
−0.3 V to +3.7 V
−0.3 V to VSWOUT + 0.3 V
−0.3 V to VSWOUT + 0.3 V
−2 V to +2 V
−0.3 V to VSWOUT + 0.3 V
−0.3 V to VSWOUT + 0.3 V
−40°C to +85°C
−65°C to +150°C
300°C
1 When used with external resistor divider.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 12. Thermal Resistance
Package Type
64-Lead LQFP
θJA
60
θJC Unit
20.5 °C/W
ESD CAUTION
Rev. C | Page 15 of 152


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
COM3/FP27 1
COM2/FP28 2
COM1 3
COM0 4
P1.2/FP25 5
P1.3/T2EX/FP24 6
P1.4/T2/FP23 7
P1.5/FP22 8
P1.6/FP21 9
P1.7/FP20 10
P0.1/FP19 11
P2.0/FP18 12
P2.1/FP17 13
P2.2/FP16 14
LCDVC 15
LCDVP2 16
ADE7566/ADE7569
TOP VIEW
(Not to Scale)
48 INT0
47 XTAL1
46 XTAL2
45 BCTRL/INT1/P0.0
44 SDEN/P2.3
43 P0.2/CF1/RTCCAL
42 P0.3/CF2
41 P0.4/MOSI/SDATA
40 P0.5/MISO
39 P0.6/SCLK/T0
38 P0.7/SS/T1
37 P1.0/RxD
36 P1.1/TxD
35 FP0
34 FP1
33 FP2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 9. Pin Configuration for the ADE7566/ADE7569
Table 13. Pin Function Descriptions
Pin No. Mnemonic
Description
1
COM3/FP27
Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.
2
COM2/FP28
Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.
3 COM1
Common Output 1. COM1 is used for the LCD backplane.
4 COM0
Common Output 0. COM0 is used for the LCD backplane.
5 P1.2/FP25
General-Purpose Digital I/O Port 1.2/LCD Segment Output 25.
6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.
7
P1.4/T2/FP23
General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.
8 P1.5/FP22
General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.
9 P1.6/FP21
General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.
10 P1.7/FP20
General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.
11 P0.1/FP19
General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.
12 P2.0/FP18
General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.
13 P2.1/FP17
General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.
14 P2.2/FP16
General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.
15 LCDVC
This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when
the LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF
capacitor. When this pin is an analog input, it is internally connected to VDD. A resistor should be connected
between this pin and LCDVB to generate the two highest voltages for the LCD waveforms (see the LCD
Driver section).
16 LCDVP2
This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the
LCD charge pump is enabled. When this pin is an analog output, a 100 nF capacitor should be connected between
this pin and LCDVP1. When this pin is an analog input, it is internally connected to LCDVP1 (see the LCD
Driver section).
17 LCDVB
This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the
LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF capacitor.
When this pin is an analog input, a resistor should be connected between this pin and LCDVC to generate an
intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this
pin and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVB and LCDVA are internally
connected (see the LCD Driver section).
Rev. C | Page 16 of 152


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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Pin No.
18
19
20 to 35
36
37
38
39
40
41
42
43
44
45
46
47
48
49, 50
51
52, 53
54
55
56
57
58
59
Mnemonic
LCDVA
LCDVP1
FP15 to FP0
P1.1/TxD
P1.0/RxD
P0.7/SS/T1
P0.6/SCLK/T0
P0.5/MISO
P0.4/MOSI/SDATA
P0.3/CF2
P0.2/CF1/RTCCAL
SDEN/P2.3
BCTRL/INT1/P0.0
XTAL2
XTAL1
INT0
VP, VN
EA
IP, IN
AGND
FP26
RESET
REFIN/OUT
VBAT
VINTA
Description
This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the
LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF capacitor.
When this pin is an analog input, a resistor should be connected between this pin and LCDVP1 to generate
an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between
this pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are
internally connected (see the LCD Driver section).
This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the
LCD charge pump is enabled. When this pin is an analog output, a 100 nF capacitor should be connected between
this pin and LCDVP2. When this pin is an analog input, a resistor should be connected between this pin and
LCDVA to generate an intermediate voltage for the LCD driver. Another resistor must be connected between
LCDVP1 and DGND to generate another intermediate voltage (see the LCD Driver section).
LCD Segment Output 15 to LCD Segment Output 0.
General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous).
General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input.
General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input.
General-Purpose Digital I/O Port 0.5/Data Input for SPI Port.
General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.
General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, Irms, or apparent power information.
General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic
Output. The CF1 logic output gives instantaneous active, reactive, Irms, or apparent information. The RTCCAL
logic output gives access to the calibrated RTC output.
Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial download
mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an
input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily
goes high and then user code is executed. If the pin is pulled down on reset, the embedded serial download/
debug kernel executes, and this pin remains low during the internal program execution. After reset, this pin
can be used as a digital output port pin (P2.3).
Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between VDD or VBAT and VSWOUT is selected internally.
A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7566/ADE7569.
The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator
circuit. An internal 6 pF capacitor is connected to this pin.
An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source for the ADE7566/ADE7569. The clock frequency for specified
operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.
External Interrupt Input 0.
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum differential
level of ±400 mV for specified operation. This channel also has an internal PGA.
This pin is used as an input for emulation. When held high, this input enables the device to fetch code from
internal program memory locations. The ADE7566/ADE7569 do not support external code memory. This pin
should not be left floating.
Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential
level of ±400 mV for specified operation. This channel also has an internal PGA.
This pin provides the ground reference for the analog circuitry.
LCD Segment Output 26.
Reset Input, Active Low.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1 µF
capacitor in parallel with a ceramic 100 nF capacitor.
Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when
the battery is selected as the power supply for the ADE7566/ADE7569.
This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
Rev. C | Page 17 of 152


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
Pin No. Mnemonic
60 VDD
61 VSWOUT
62 VINTD
63 DGND
64 VDCIN
Description
3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is
selected as the power supply for the ADE7566/ADE7569. This pin should be decoupled with a 10 µF capacitor in
parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the
ADE7566/ADE7569. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF
capacitor.
This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
Ground Reference for Digital Circuitry.
Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
Rev. C | Page 18 of 152


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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
COM3/FP27 1
COM2/FP28 2
COM1 3
COM0 4
P1.2/FP25 5
P1.3/T2EX/FP24 6
P1.4/T2/FP23 7
P1.5/FP22 8
P1.6/FP21 9
P1.7/FP20 10
P0.1/FP19 11
P2.0/FP18 12
P2.1/FP17 13
P2.2/FP16 14
LCDVC 15
LCDVP2 16
ADE7116/ADE7166/ADE7169
TOP VIEW
(Not to Scale)
48 INT0
47 XTAL1
46 XTAL2
45 BCTRL/INT1/P0.0
44 SDEN/P2.3
43 P0.2/CF1/RTCCAL
42 P0.3/CF2
41 P0.4/MOSI/SDATA
40 P0.5/MISO
39 P0.6/SCLK/T0
38 P0.7/SS/T1
37 P1.0/RxD
36 P1.1/TxD
35 FP0
34 FP1
33 FP2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 10. Pin Configuration for the ADE7116/ADE7166/ADE7169
Table 14. Pin Function Descriptions
Pin No. Mnemonic
Description
1
COM3/FP27
Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.
2
COM2/FP28
Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.
3 COM1
Common Output 1. COM1 is used for the LCD backplane.
4 COM0
Common Output 0. COM0 is used for the LCD backplane.
5 P1.2/FP25
General-Purpose Digital I/O Port 1.2/LCD Segment Output 25.
6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.
7
P1.4/T2/FP23
General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.
8 P1.5/FP22
General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.
9 P1.6/FP21
General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.
10 P1.7/FP20
General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.
11 P0.1/FP19
General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.
12 P2.0/FP18
General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.
13 P2.1/FP17
General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.
14 P2.2/FP16
General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.
15 LCDVC
In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116, this pin is always an analog input.
When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an
analog input, it is internally connected to VDD. A resistor should be connected between this pin and LCDVB to
generate the two highest voltages for the LCD waveforms (see the LCD Driver section).
16 LCDVP2
In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116, this pin is always an analog input.
When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP1. When
this pin is an analog input, it is internally connected to LCDVP1 (see the LCD Driver section).
17 LCDVB
In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116, this pin is always an analog input.
When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog
input, a resistor should be connected between this pin and LCDVC to generate an intermediate voltage for
the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVA to
generate another intermediate voltage. In 1/2 bias LCD mode, LCDVB and LCDVA are internally connected
(see the LCD Driver section).
Rev. C | Page 19 of 152


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
Pin No.
18
19
20 to 35
36
37
38
39
40
41
42
43
44
45
46
47
48
49, 50
51
52, 53
54
55
56
57
58
Mnemonic
LCDVA
LCDVP1
FP15 to FP0
P1.1/TxD
P1.0/RxD
P0.7/SS/T1
P0.6/SCLK/T0
P0.5/MISO
P0.4/MOSI/SDATA
P0.3/CF2
P0.2/CF1/RTCCAL
SDEN/P2.3
BCTRL/INT1/P0.0
XTAL2
XTAL1
INT0
VP, VN
EA
IPA, IN
AGND
IPB
RESET
REFIN/OUT
VBAT
Description
In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116, this pin is always an analog input.
When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog
input, a resistor should be connected between this pin and LCDVP1 to generate an intermediate voltage for the
LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVB to generate
another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are internally connected (see the
LCD Driver section).
In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or
an analog output when the LCD charge pump is enabled. In the ADE7116, this pin is always an analog input.
When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP2.
When this pin is an analog input, a resistor should be connected between this pin and LCDVA to generate an
intermediate voltage for the LCD driver. Another resistor must be connected between LCDVP1 and DGND to
generate another intermediate voltage (see the LCD Driver section).
LCD Segment Output 0 to LCD Segment Output 15.
General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous).
General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input.
General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input.
General-Purpose Digital I/O Port 0.5/Data Input for SPI Port.
General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.
General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, Irms, or apparent power information.
General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic
Output. The CF1 logic output gives instantaneous active, reactive, Irms, or apparent power information. The
RTCCAL logic output gives access to the calibrated RTC output.
Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial
download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily
becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin
momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded
serial download/debug kernel executes, and this pin remains low during the internal program execution.
After reset, this pin can be used as a digital output port pin (P2.3).
Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between VDD or VBAT and VSWOUT is selected internally.
A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7116/ADE7166/
ADE7169. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the
gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.
An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source for the ADE7116/ADE7166/ADE7169. The clock frequency
for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.
External Interrupt Input 0.
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
This pin is used as an input for emulation. When held high, this input enables the device to fetch code from
internal program memory locations. The ADE7116/ADE7166/ADE7169 do not support external code
memory. This pin should not be left floating.
Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
This pin provides the ground reference for the analog circuitry.
Analog Input for Second Current Channel (IPB). This input is fully differential with a maximum differential
level of ±400 mV, referred to IN for specified operation. This channel also has an internal PGA.
Reset Input, Active Low.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a
1 µF capacitor in parallel with a ceramic 100 nF capacitor.
Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when
the battery is selected as the power supply for the ADE7116/ADE7166/ADE7169.
Rev. C | Page 20 of 152


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Data Sheet
Pin No. Mnemonic
59 VINTA
60 VDD
61 VSWOUT
62 VINTD
63 DGND
64 VDCIN
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Description
This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is
selected as the power supply for the ADE7116/ADE7166/ADE7169. This pin should be decoupled with a 10 µF
capacitor in parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the
ADE7116/ADE7166/ADE7169. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic
100 nF capacitor.
This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
Ground Reference for Digital Circuitry.
Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
Rev. C | Page 21 of 152


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
GAIN = 1
1.5 INTEGRATOR OFF
INTERNAL REFERENCE
MID CLASS C
1.0
0.5 +25°C; PF = 1
0
–0.5
+85°C; PF = 1
–40°C; PF = 1
–1.0
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 11. Active Energy Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
1.5
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
0.5
+25°C; PF = 1
+85°C; PF = 1
–40°C; PF = 1
0
–0.5
+25°C; PF = 0.5
+85°C; PF = 0.5
–40°C; PF = 0.5
MID CLASS C
MID CLASS C
–1.0
–1.5
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 12. Active Energy Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
2.0
GAIN = 1
INTEGRATOR OFF
1.5 INTERNAL REFERENCE
1.0
0.5
0
+85°C; PF = 0
–0.5
+25°C; PF = 0
–40°C; PF = 0
–1.0
–1.5
–2.0
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
2.0
GAIN = 1
INTEGRATOR OFF
1.5 INTERNAL REFERENCE
1.0
0.5
0
–0.5
–1.0
+85°C; PF = 0.866
+25°C; PF = 0.866
–40°C; PF = 0.866
+85°C; PF = 0
+25°C; PF = 0
–40°C; PF = 0
–1.5
–2.0
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
2.0
GAIN = 1
1.5 INTEGRATOR OFF
INTERNAL REFERENCE
1.0
MID CLASS C
0.5 +85°C; PF = 1
+25°C; PF = 1
0
–0.5 –40°C; PF = 1
–1.0
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 15. Current RMS Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
2.0
GAIN = 1
1.5 INTEGRATOR OFF
INTERNAL REFERENCE
MID CLASS C
1.0
+25°C; PF = 1
+85°C; PF = 1
0.5
+25°C; PF = 0.5
+85°C; PF = 0.5
0
–0.5 –40°C; PF = 1
–40°C; PF = 0.5
–1.0
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 16. Current RMS Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
Rev. C | Page 22 of 152


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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
0.5
GAIN = 1
0.4
INTEGRATOR OFF
INTERNAL REFERENCE
0.3
0.2
Irms; 3.3V
0.1 Irms; 3.43V
0
Vrms; 3.3V
Vrms; 3.43V
Vrms; 3.13V
–0.1
–0.2
Irms; 3.13V
–0.3
–0.4
–0.5
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 17. Voltage and Current RMS Error as a Percentage of Reading (Gain = 1)
over Power Supply with Internal Reference, Integrator Off
1.0
GAIN = 1
INTEGRATOR OFF
0.8 INTERNAL REFERENCE
0.6
0.4
0.2
0
–0.2
MID CLASS B
PF = 1
PF = 0.5
MID CLASS B
–0.4
–0.6
–0.8
–1.0
40 45 50 55 60 65 70
LINE FREQUENCY (Hz)
Figure 18. Active Energy Error as a Percentage of Reading (Gain = 1)
over Frequency with Internal Reference, Integrator Off
0.5
GAIN = 1
0.4
INTEGRATOR OFF
INTERNAL REFERENCE
0.3
0.2 VAR; 3.43V
0.1 VAR; 3.3V
W; 3.3V
0
–0.1 VAR; 3.13V
W; 3.13V
–0.2
W; 3.43V
–0.3
–0.4
–0.5
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 19. Active and Reactive Energy Error as a Percentage of Reading
(Gain = 1) over Power Supply with Internal Reference, Integrator Off
1.5
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
0.5
PF = 1
0
–0.5
PF = –0.5
PF = +0.5
–1.0
MID CLASS C
MID CLASS C
–1.5
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 20. Active Energy Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
1.0
GAIN = 8
0.8
INTEGRATOR OFF
INTERNAL REFERENCE
0.6
0.4
PF = 1
0.2 PF = +0.5
0
–0.2
PF = –0.5
–0.4
–0.6
–0.8
–1.0
0.1
1
10 100
CURRENT CHANNEL (% of Full Scale)
Figure 21. Reactive Energy Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
1.5
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
0.5
PF = 1
0
PF = +0.5
MID CLASS C
PF = –0.5
–0.5
MID CLASS C
–1.0
–1.5
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 22. Current RMS Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
Rev. C | Page 23 of 152


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
2.0
GAIN = 16
1.5 INTEGRATOR OFF
INTERNAL REFERENCE
1.0
MID CLASS C
0.5
+25°C; PF = 1
0
–0.5 –40°C; PF = 1
+85°C; PF = 1
–1.0
–1.5
–2.0
0.1
MID CLASS C
1 10 100
CURRENT CHANNEL (% of Full Scale)
Figure 23. Active Energy Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
2.0
GAIN = 16
1.5
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
0.5
0
–0.5
–1.0
+85°C; PF = 0.5
+25°C; PF = 1
+25°C; PF = 0.5
+85°C; PF = 1
–40°C; PF = 1
–40°C; PF = 0.5
MID CLASS C
–1.5
–2.0
0.1
MID CLASS C
1 10 100
CURRENT CHANNEL (% of Full Scale)
Figure 24. Active Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
1.0
GAIN = 16
0.8
INTEGRATOR OFF
INTERNAL REFERENCE
0.6
0.4 +85°C; PF = 0
0.2
–40°C; PF = 0
0
–0.2
+25°C; PF = 0
–0.4
–0.6
–0.8
–1.0
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 25. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
1.0
GAIN = 16
0.8
INTEGRATOR OFF
INTERNAL REFERENCE
0.6
0.4
0.2
–40°C; PF = 0
+85°C; PF = 0
+85°C; PF = 0.866
–40°C; PF = 0.866
0
+25°C; PF = 0.866
–0.2 +25°C; PF = 0
–0.4
–0.6
–0.8
–1.0
0.1 1 10 100
CURRENT CHANNEL (% of Full Scale)
Figure 26. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
2.0
GAIN = 16
1.5
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
MID CLASS C
0.5 –40°C; PF = 1
0
–0.5
–1.0
+25°C; PF = 1
+85°C; PF = 1
–1.5
–2.0
0.1
MID CLASS C
1 10 100
CURRENT CHANNEL (% of Full Scale)
Figure 27. Current RMS Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
2.0
GAIN = 16
1.5
INTEGRATOR OFF
INTERNAL REFERENCE
MID CLASS C
1.0
–40°C; PF = 1
0.5
+25°C; PF = 1
–40°C; PF = 0.5
0
–0.5
+85°C; PF = 0.5
+25°C; PF = 0.5
+85°C; PF = 1
–1.0
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 28. Current RMS Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
Rev. C | Page 24 of 152


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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY
2.0
GAIN = 16
1.5
INTEGRATOR ON
INTERNAL REFERENCE
MID CLASS C
2.0
GAIN = 16
1.5
INTEGRATOR ON
INTERNAL REFERENCE
1.0
0.5
0
–0.5
–1.0
–40°C; PF = 1
+85°C; PF = 0.5
+25°C; PF = 0.5
–40°C; PF = 0.5
+25°C; PF = 1
+85°C; PF = 1
1.0
0.5
0
–0.5
–1.0
+25°C; PF = 1
+25°C; PF = 0.5
+85°C; PF = 0.5
+85°C; PF = 1
–40°C; PF = 0.5
–40°C; PF = 1
MID CLASS C
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 29. Active Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
1.0
GAIN = 16
0.8
INTEGRATOR ON
INTERNAL REFERENCE
0.6
0.4
+25°C; PF = 0
0.2
+85°C; PF = 0.866
–40°C; PF = 0
+25°C; PF = 0.866
0
–0.2
+85°C; PF = 0
–0.4 –40°C; PF = 0.866
–0.6
–0.8
–1.0
0.1
1
10 100
CURRENT CHANNEL (% of Full Scale)
Figure 30. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 31. Current RMS Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
Rev. C | Page 25 of 152


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569 is defined
by the following formula:
Percentage Error =

Energy
Register True
True Energy
Energy
 ×100%
(1)
Phase Error Between Channels
The digital integrator and the high-pass filter (HPF) in the
current channel have a nonideal phase response. To offset this
phase response and equalize the phase response between channels,
two phase correction networks are placed in the current channel:
one for the digital integrator and the other for the HPF. The
phase correction networks correct the phase response of the
corresponding component and ensure a phase match between
current channel and voltage channel to within ±0.1° over a range of
45 Hz to 65 Hz with the digital integrator off. With the digital
integrator on, the phase is corrected to within ±0.4° over a range of
45 Hz to 65 Hz.
Power Supply Rejection (PSR)
PSR quantifies the ADE7116/ADE7166/ADE7169/ADE7566/
ADE7569 measurement error as a percentage of reading when
the power supplies are varied. For the ac PSR measurement, a
reading at nominal supplies (3.3 V) is taken. A second reading
is obtained with the same input signal levels when an ac (100 mV
rms/120 Hz) signal is introduced onto the supplies. Any error
introduced by this ac signal is expressed as a percentage of reading
(see the Measurement Error definition).
For the dc PSR measurement, a reading at nominal supplies
(3.3 V) is taken. A second reading is obtained with the same
input signal levels when the supplies are varied ±5%. Any error
introduced is again expressed as a percentage of the reading.
ADC Offset Error
ADC offset error is the dc offset associated with the analog inputs
to the ADCs. It means that, with the analog inputs connected to
AGND, the ADCs still see a dc analog input signal. The magnitude
of the offset depends on the gain and input range selection (see
the Typical Performance Characteristics section). However, when
HPF1 is switched on, the offset is removed from the current
channel, and the power calculation is not affected by this offset.
The offsets can be removed by performing an offset calibration
(see the Analog Inputs section).
Gain Error
Gain error is the difference between the measured ADC output
code (minus the offset) and the ideal output code (see the Current
Channel ADC section and Voltage Channel ADC section). It is
measured for each of the gain settings on the current channel
(1, 2, 4, 8, and 16). The difference is expressed as a percentage
of the ideal code.
Rev. C | Page 26 of 152


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Data Sheet
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
SPECIAL FUNCTION REGISTER (SFR) MAPPING
Table 15
Mnemonic
INTPR
SCRATCH4
SCRATCH3
SCRATCH2
SCRATCH1
BATVTH
STRBPER
IPSMF
TEMPCAL
RTCCOMP
BATPR
PERIPH
DIFFPROG
B
VDCINADC
LCDSEGE2
IPSME
SPISTAT
SPI2CSTAT
SPIMOD2
I2CADR
SPIMOD1
I2CMOD
WAV2H
WAV2M
WAV2L
WAV1H
WAV1M
WAV1L
ACC
BATADC
MIRQSTH
MIRQSTM
MIRQSTL
MIRQENH
MIRQENM
MIRQENL
ADCGO
TEMPADC
IRMSH
IRMSM
IRMSL
VRMSH
VRMSM
VRMSL
PSW
TH2
TL2
RCAP2H
RCAP2L
Address
0xFF
0xFE
0xFD
0xFC
0xFB
0xFA
0xF9
0xF8
0xF7
0xF6
0xF5
0xF4
0xF3
0xF0
0xEF
0xED
0xEC
0xEA
0xEA
0xE9
0xE9
0xE8
0xE8
0xE7
0xE6
0xE5
0xE4
0xE3
0xE2
0xE0
0xDF
0xDE
0xDD
0xDC
0xDB
0xDA
0xD9
0xD8
0xD7
0xD6
0xD5
0xD4
0xD3
0xD2
0xD1
0xD0
0xCD
0xCC
0xCB
0xCA
Description
Interrupt pins configuration (see Table 17).
Scratch Pad 4 (see Table 25).
Scratch Pad 3 (see Table 24).
Scratch Pad 2 (see Table 23).
Scratch Pad 1 (see Table 22).
Battery detection threshold (see Table 52).
Peripheral ADC strobe period (see Table 49).
Power management interrupt flag (see Table 18).
RTC temperature compensation (see Table 135).
RTC nominal compensation (see Table 134).
Battery switchover configuration (see Table 19).
Peripheral configuration (see Table 20).
Temperature and supply delta (see Table 50).
Auxiliary math (see Table 56).
VDCIN ADC value (see Table 53).
LCD Segment Enable 2 (see Table 98).
Power management interrupt enable (see Table 21).
SPI interrupt status (see Table 150).
I2C interrupt status (see Table 154).
SPI Configuration SFR 2 (see Table 149).
I2C slave address (see Table 153).
SPI Configuration SFR 1 (see Table 148).
I2C mode (see Table 152).
Selection 2 sample MSB (see Table 31).
Selection 2 sample middle byte (see Table 31).
Selection 2 sample LSB (see Table 31).
Selection 1 sample MSB (see Table 31).
Selection 1 sample middle byte (see Table 31).
Selection 1 sample LSB (see Table 31).
Accumulator (see Table 56).
Battery ADC value (see Table 54).
Interrupt Status 3 (see Table 42).
Interrupt Status 2 (see Table 41).
Interrupt Status 1 (see Table 40).
Interrupt Enable 3 (see Table 45).
Interrupt Enable 2 (see Table 44).
Interrupt Enable 1 (see Table 43).
Start ADC measurement (see Table 51).
Temperature ADC value (see Table 55).
Irms measurement MSB (see Table 31).
Irms measurement middle byte (see Table 31).
Irms measurement LSB (see Table 31).
Vrms measurement MSB (see Table 31).
Vrms measurement middle byte (see Table 31).
Vrms measurement LSB (see Table 31).
Program status word (see Table 57).
Timer 2 high byte (see Table 120).
Timer 2 low byte (see Table 121).
Timer 2 reload/capture high byte (see Table 122).
Timer 2 reload/capture low byte (see Table 123).
Rev. C | Page 27 of 152


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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
Mnemonic
T2CON
EADRH
EADRL
POWCON
KYREG
WDCON
PROTR
PROTB1
PROTB0
EDATA
PROTKY
FLSHKY
ECON
IP
PINMAP2
PINMAP1
PINMAP0
LCDCONY
CFG
LCDDAT
LCDPTR
IEIP2
IE
DPCON
INTVAL
HOUR
MIN
SEC
HTHSEC
TIMECON
P2
EPCFG
SBAUDT
SBAUDF
LCDCONX
SPI2CRx
SPI2CTx
SBUF
SCON
LCDSEGE
LCDCLK
LCDCON
MDATH
MDATM
MDATL
MADDPT
P1
TH1
TH0
TL1
TL0
TMOD
TCON
Address
0xC8
0xC7
0xC6
0xC5
0xC1
0xC0
0xBF
0xBE
0xBD
0xBC
0xBB
0xBA
0xB9
0xB8
0xB4
0xB3
0xB2
0xB1
0xAF
0xAE
0xAC
0xA9
0xA8
0xA7
0xA6
0xA5
0xA4
0xA3
0xA2
0xA1
0xA0
0x9F
0x9E
0x9D
0x9C
0x9B
0x9A
0x99
0x98
0x97
0x96
0x95
0x94
0x93
0x92
0x91
0x90
0x8D
0x8C
0x8B
0x8A
0x89
0x88
Description
Timer/Counter 2 control (see Table 115).
Flash high byte address (see Table 110).
Flash low byte address (see Table 109).
Power control (see Table 26).
Key (see Table 126).
Watchdog timer (see Table 85).
Flash read protection (see Table 108).
Flash Write/Erase Protection 1 (see Table 107).
Flash Write/Erase Protection 0 (see Table 106).
Flash data (see Table 105).
Flash protection key (see Table 104).
Flash key (see Table 103).
Flash control (see Table 102).
Interrupt priority (see Table 79).
Port 2 weak pull-up enable (see Table 159).
Port 1 weak pull-up enable (see Table 158).
Port 0 weak pull-up enable (see Table 157).
LCD Configuration Y (see Table 91).
Configuration (see Table 63).
LCD data (see Table 97).
LCD pointer (see Table 96).
Interrupt Enable and Priority 2 (see Table 80).
Interrupt enable (see Table 78).
Data pointer control (see Table 76).
RTC alarm interval (see Table 133).
RTC hours counter (see Table 132).
RTC minutes counter (see Table 131).
RTC seconds counter (see Table 130).
RTC hundredths of a second counter (see Table 129).
RTC configuration (see Table 128).
Port 2 (see Table 162).
Extended port configuration (see Table 156).
Enhanced serial baud rate control (see Table 142).
UART timer fractional divider (see Table 143).
LCD Configuration X (see Table 89).
SPI/I2C receive buffer (see Table 147).
SPI/I2C transmit buffer (see Table 146).
Serial port buffer (see Table 141).
Serial communications control (see Table 140).
LCD segment enable (see Table 95).
LCD clock (see Table 92).
LCD configuration (see Table 88).
Energy measurement pointer data MSB (see Table 31).
Energy measurement pointer data middle byte (see Table 31).
Energy measurement pointer data LSB (see Table 31).
Energy measurement pointer address (see Table 30).
Port 1 (see Table 161).
Timer 1 high byte (see Table 118).
Timer 0 high byte (see Table 116).
Timer 1 low byte (see Table 119).
Timer 0 low byte (see Table 117).
Timer/Counter 0 and Timer/Counter 1 mode (see Table 113).
Timer/Counter 0 and Timer/Counter 1 control (see Table 114).
Rev. C | Page 28 of 152


ADE7569 (Analog Devices)
Single-Phase Energy Measurement IC

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Data Sheet
Mnemonic
PCON
DPH
DPL
SP
P0
Address
0x87
0x83
0x82
0x81
0x80
ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Description
Program control (see Table 58).
Data pointer high (see Table 60).
Data pointer low (see Table 59).
Stack pointer (see Table 62).
Port 0 (see Table 160).
Rev. C | Page 29 of 152


ADE7569 (Analog Devices)
Single-Phase Energy Measurement IC

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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
Data Sheet
POWER MANAGEMENT
The ADE7116/ADE7166/ADE7169/ADE7566/ADE7569
have elaborate power management circuitry that manages the
switchover from regular power supply to battery and manages
power supply failures. The power management functionalities
can be accessed directly through the 8052 SFRs (see Table 16).
Table 16. Power Management SFRs
SFR Address
R/W Mnemonic
0xEC
R/W IPSME
0xF5 R/W BATPR
0xF8 R/W IPSMF
0xFF R/W INTPR
0xF4 R/W PERIPH
0xC5
R/W POWCON
0xFB
R/W SCRATCH1
0xFC
R/W SCRATCH2
0xFD
R/W SCRATCH3
0xFE R/W SCRATCH4
Description
Power management interrupt enable (see Table 21).
Battery switchover configuration (see Table 19).
Power management interrupt flag (see Table 18).
Interrupt pins configuration (see Table 17).
Peripheral configuration (see Table 20).
Power control (see Table 26).
Scratch Pad 1 (see Table 22).
Scratch Pad 2 (see Table 23).
Scratch Pad 3 (see Table 24).
Scratch Pad 4 (see Table 25).
POWER MANAGEMENT REGISTER DETAILS
Table 17. Interrupt Pins Configuration SFR (INTPR, Address 0xFF)
Bit Mnemonic Default
Description
7
RTCCAL
0
Controls RTC calibration output. When set, the RTC calibration frequency selected by the
FSEL bits is output on the P0.2/CF1/RTCCAL pin.
[6:5] FSEL
00
Sets RTC calibration output frequency and calibration window.
FSEL
Result (Calibration Window, Frequency)
00 30.5 sec, 1 Hz
01 30.5 sec, 512 Hz
10 0.244 sec, 500 Hz
11 0.244 sec, 16 kHz
4 Reserved Not applicable Not applicable
[3:1] INT1PRG
000
Controls the function of INT1.
INT1PRG Result
X00 GPIO enabled
X01 BCTRL enabled
01X INT1 input disabled
11X INT1 input enabled
0
INT0PRG
0
Controls the function of INT0.
INT0PRG Result
0 INT0 input disabled
1 INT0 input enabled
Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF)
To protect the RTC from runaway code, a key must be written to the key SFR (KYREG, Address 0xC1) to obtain write access to INTPR.
KYREG (see Table 126) should be set to 0xEA to unlock this SFR and reset to 0 after a timekeeping register is written to. The RTC
registers can be written using the following 8052 assembly code:
MOV KYREG, #0EAh
MOV INTPR, #080h
Rev. C | Page 30 of 152




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