Analog Devices Semiconductor Electronic Components Datasheet



ADE7569 (Analog Devices)
(ADE7xxx) Single-Phase Energy Measurement IC

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Single-Phase Energy Measurement IC with
8052 MCU, RTC, and LCD Driver
ADE7566/ADE7569/ADE7166/ADE7169
GENERAL FEATURES
Wide supply voltage operation: 2.4 V to 3.7 V
Internal bipolar switch between regulated and battery inputs
Ultralow power operation with power-saving modes (PSM)
Full operation: 4 mA to 1.6 mA (PLL clock dependent)
Battery mode: 3.2 mA to 400 μA (PLL clock dependent)
Sleep mode
www.DataSheet4U.cRoemal-time clock (RTC) mode: 1.5 μA
RTC and LCD mode: 27 μA (LCD charge pump enabled)
Reference: 1.2 V ± 0.1% (10 ppm/°C drift)
64-lead RoHS package options
Lead frame chip scale package (LFCSP)
Low profile quad flat package (LQFP)
Operating temperature range: −40°C to +85°C
ENERGY MEASUREMENT FEATURES
Proprietary analog-to-digital converters (ADCs) and digital
signal processing (DSP) provide high accuracy active
(Watt), reactive (VAR), and apparent energy (VA)
measurement
Less than 0.1% error on active energy over a dynamic
range of 1000 to 1 @ 25°C
Less than 0.5% error on reactive energy over a dynamic
range of 1000 to 1 @ 25°C (ADE7569 and ADE7169 only)
Less than 0.5% error on root mean square (rms)
measurements over a dynamic range of 500 to 1 for
current (Irms) and 100 to 1 for voltage (Vrms) @ 25°C
Supports IEC 62053-21, IEC 62053-22, IEC 62053-23,
EN 50470-3 Class A, Class B, and Class C, and ANSI C12-16
Differential input with programmable gain amplifiers (PGAs)
supports shunts, current transformers, and di/dt current
sensors (ADE7569 and ADE7169 only)
Two current inputs for antitamper detection in the
ADE7166/ADE7169
High frequency outputs proportional to Irms, active, reactive,
or apparent power (AP)
Table 1.
Part No.
ADE7566
ADE7569
ADE7166
ADE7169
Anti-
Tamper
No
No
Yes
Yes
Watt, VA,
Irms, Vrms
Yes
Yes
Yes
Yes
VAR
No
Yes
No
Yes
di/dt Sensor
No
Yes
No
Yes
MICROPROCESSOR FEATURES
8052-based core
Single-cycle 4 MIPS 8052 core
8052-compatible instruction set
32.768 kHz external crystal with on-chip PLL
Two external interrupt sources
External reset pin
Low power battery mode
Wake-up from I/O, temperature change, alarm, and
universal asynchronous receiver/transmitter (UART)
LCD driver operation
Temperature measurement
Real-time clock
Counter for seconds, minutes, and hours
Automatic battery switchover for RTC backup
Operation down to 2.4 V
Ultralow battery supply current: 1.5 μA
Selectable output frequency: 1 Hz to 16.384 kHz
Embedded digital crystal frequency compensation for
calibration and temperature variation 2 ppm resolution
Integrated LCD driver
108-segment driver for the ADE7566/ADE7569 and
104-segment driver for the ADE7166/ADE7169
2×, 3×, or 4× multiplexing
LCD voltages generated internally or with external resistors
Internal adjustable drive voltages up to 5 V independent
of power supply level
On-chip peripherals
UART, SPI or I2C, and watchdog timer
Power supply monitoring with user-selectable levels
Memory: 16 kB flash memory, 512 bytes RAM
Development tools
Single-pin emulation
IDE-based assembly and C-source debugging
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices.Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2007 Analog Devices, Inc. All rights reserved.


ADE7569 (Analog Devices)
(ADE7xxx) Single-Phase Energy Measurement IC

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ADE7566/ADE7569/ADE7166/ADE7169
TABLE OF CONTENTS
General Features ............................................................................... 1
Energy Measurement Features........................................................ 1
Microprocessor Features.................................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Functional Block Diagrams............................................................. 4
Specifications..................................................................................... 6
Energy Metering ........................................................................... 6
www.DataShAeenta4lUog.coPmeripherals ....................................................................... 7
Digital Interface ............................................................................ 8
Timing Specifications ................................................................ 10
Absolute Maximum Ratings.......................................................... 15
Thermal Resistance .................................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
Typical Performance Characteristics ........................................... 18
Terminology .................................................................................... 22
SFR Mapping ................................................................................... 23
Power Management........................................................................ 25
Power Management Register Details ....................................... 25
Power Supply Architecture........................................................ 28
Battery Switchover...................................................................... 28
Power Supply Monitor Interrupt (PSM).................................. 29
Using the Power Supply Features ............................................. 31
Operating Modes ............................................................................ 33
PSM0 (Normal Mode) ............................................................... 33
PSM1 (Battery Mode) ................................................................ 33
PSM2 (Sleep Mode).................................................................... 33
3.3 V Peripherals and Wake-Up Events................................... 34
Transitioning Between Operating Modes ............................... 35
Using the Power Management Features .................................. 35
Energy Measurement ..................................................................... 37
Access to Energy Measurement SFRs ...................................... 37
Access to Internal Energy Measurement Registers................ 37
Energy Measurement Registers ................................................ 40
Energy Measurement Internal Registers Details.................... 41
Interrupt Status/Enable SFRs .................................................... 44
Analog Inputs.............................................................................. 46
Analog-to-Digital Conversion.................................................. 47
Fault Detection ........................................................................... 50
di/dt Current Sensor and Digital Integrator for the
ADE7569/ADE7169................................................................... 51
Power Quality Measurements................................................... 53
Phase Compensation ................................................................. 55
RMS Calculation ........................................................................ 55
Active Power Calculation .......................................................... 58
Active Energy Calculation ........................................................ 60
Reactive Power Calculation for the ADE7569/ADE7169..... 63
Reactive Energy Calculation for the ADE7569/ADE7169 ... 64
Apparent Power Calculation..................................................... 68
Apparent Energy Calculation ................................................... 69
Ampere-Hour Accumulation ................................................... 70
Energy-to-Frequency Conversion............................................ 71
Energy Register Scaling ............................................................. 72
Energy Measurement Interrupts .............................................. 72
Temperature, Battery, and Supply Voltage Measurements........ 73
Temperature Measurement ....................................................... 75
Battery Measurement................................................................. 75
External Voltage Measurement ................................................ 76
8052 MCU CORE Architecture.................................................... 78
MCU Registers............................................................................ 78
Basic 8052 Registers ................................................................... 80
Standard 8052 SFRs.................................................................... 81
Memory Overview ..................................................................... 81
Addressing Modes...................................................................... 82
Instruction Set ............................................................................ 84
Read-Modify-Write Instructions ............................................. 86
Instructions That Affect Flags .................................................. 86
Dual Data Pointers ......................................................................... 88
Interrupt System ............................................................................. 89
Standard 8052 Interrupt Architecture ..................................... 89
Interrupt Architecture ............................................................... 89
Interrupt Registers...................................................................... 89
Interrupt Priority........................................................................ 90
Interrupt Flags ............................................................................ 91
Interrupt Vectors ........................................................................ 93
Interrupt Latency........................................................................ 93
Context Saving............................................................................ 93
Watchdog Timer ............................................................................. 94
LCD Driver...................................................................................... 96
Rev. A | Page 2 of 144


ADE7569 (Analog Devices)
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LCD Registers ..............................................................................96
LCD Setup ....................................................................................99
LCD Timing and Waveforms ....................................................99
Blink Mode................................................................................ 100
Display Element Control......................................................... 100
Voltage Generation .................................................................. 101
LCD External Circuitry........................................................... 101
LCD Function in PSM2........................................................... 101
Flash Memory ............................................................................... 103
www.DataSheet4UO.vceormview ................................................................................... 103
Flash Memory Organization................................................... 104
Using the Flash Memory ......................................................... 104
Protecting the Flash Memory ................................................. 107
In-Circuit Programming ......................................................... 108
Timers ............................................................................................ 109
Timer Registers......................................................................... 109
Timer 0 and Timer 1................................................................ 111
Timer 2 ...................................................................................... 112
PLL ................................................................................................. 114
PLL Registers ............................................................................ 114
Real-Time Clock........................................................................... 116
RTC Registers ........................................................................... 116
Read and Write Operations .................................................... 119
RTC Modes ............................................................................... 119
RTC Interrupts ......................................................................... 119
RTC Calibration ....................................................................... 120
REVISION HISTORY
Revision History: ADE7566/ADE7569/ADE7166/ADE7169
12/07—Revision A: Initial Combined Version
Revision History: ADE7566/ADE7569
12/07—Rev. 0 to Rev. A
Added ADE7166/ADE7169 .............................................. Universal
Changes to Table 1 ............................................................................1
Changes to Ordering Guide.........................................................144
11/07—Revision 0: Initial Version
ADE7566/ADE7569/ADE7166/ADE7169
UART Serial Interface...................................................................121
UART Registers .........................................................................121
UART Operation Modes ..........................................................124
UART Baud Rate Generation ..................................................125
UART Additional Features ......................................................127
Serial Peripheral Interface (SPI)..................................................128
SPI Registers ..............................................................................128
SPI Pins.......................................................................................131
SPI Master Operating Modes ..................................................132
SPI Interrupt and Status Flags .................................................133
I2C Compatible Interface..............................................................134
Serial Clock Generation ...........................................................134
Slave Addresses..........................................................................134
I2C Registers...............................................................................134
Read and Write Operations .....................................................135
I2C Receive and Transmit FIFOs.............................................136
I/O Ports .........................................................................................137
Parallel I/O.................................................................................137
I/O Registers ..............................................................................138
Port 0...........................................................................................141
Port 1...........................................................................................141
Port 2...........................................................................................141
Determining the Version of the ADE7566/ADE7569..............142
Outline Dimensions......................................................................143
Ordering Guide .........................................................................144
Rev. A | Page 3 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
GENERAL DESCRIPTION
The ADE7566/ADE7569/ADE7166/ADE71691 integrate Analog
Devices, Inc., energy (ADE) metering IC analog front end and
fixed function DSP solution with an enhanced 8052 MCU core,
an RTC, an LCD driver, and all the peripherals to make an
electronic energy meter with an LCD display in a single part.
The ADE measurement core includes active, reactive, and apparent
energy calculations, as well as voltage and current rms measure-
ments. This information is ready to use for energy billing by using
built-in energy scalars. Many power line supervisory features
1 Patents pending.
www.DataSheet4U.com
such as SAG, peak, and zero crossing are included in the energy
measurement DSP to simplify energy meter design.
The microprocessor functionality includes a single-cycle 8052 core,
a real-time clock with a power supply backup pin, a UART, and an
SPI or I2C® interface. The ready-to-use information from the
ADE core reduces the program memory size requirement, making
it easy to integrate complicated design into 16 kB of flash
memory.
The ADE7566/ADE7569/ADE7166/ADE7169 also include a
108-/104-segment LCD driver. This driver generates voltages
capable of driving LCDs up to 5 V.
FUNCTIONAL BLOCK DIAGRAMS
IP 52
IN 53
VP 49
VN 50
DGND 63
AGND 54
VBAT 58
57 43 42
38 39 40 41 39 38 7 6
45 11 43 42 41 40 39 38 37 36 5 6 7 8 9 10
1.20V
REF
SPI/I2C
SERIAL
INTERFACE
3 × 16-BIT
COUNTER
TIMERS
ADE7566/ADE7569
+
PGA1
+
P–GA2
ADC
ADC
ENERGY
MEASUREMENT
DSP
TEMP
SENSOR
TEMP
ADC
BATTERY
ADC
POWER SUPPLY
CONTROL AND
MONITORING
PROGRAM MEMORY
16kB FLASH
USER RAM
256 BYTES
USER XRAM
256 BYTES
VDCIN
ADC
LDO
POR
LDO
3V/5V LCD
CHARGE PUMP
SINGLE
CYCLE
8052
MCU
WATCHDOG
TIMER
108-SEGMENT
LCD DRIVER
DOWNLOADER
DEBUGGER
UART
TIMER
UART
SERIAL
PORT
PLL
RTC OSC
64 60
61 62 59 56 51 44
36 37
47 46 48
12 P2.0 (FP18)
13 P2.1 (FP17)
14 P2.2 (FP16)
44 P2.3 (SDEN)
19 LCDVP1
16 LCDVP2
18 LCDVA
17 LCDVB
15 LCDVC
4 COM0
...
1 COM3
35 FP0
...
20 FP15
14 FP16
13 FP17
12 FP18
11 FP19
10 FP20
9 FP21
8 FP22
7 FP23
6 FP24
5 FP25
55 FP26
45
Figure 1. ADE7566/ADE7569 Functional Block Diagram
Rev. A | Page 4 of 144


ADE7569 (Analog Devices)
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ADE7566/ADE7569/ADE7166/ADE7169
57 43 42
38 39 40 41 39 38 7 8
45 11 43 42 41 40 39 38 37 36 5 6 7 8 9 10
1.20V
REF
SPI/I2C
SERIAL
INTERFACE
3 × 16-BIT
COUNTER
TIMERS
ADE7166/ADE7169
www.DataSheet4U.com
IPA 52
IN 53
IPB 55
VP 49
VN 50
DGND 63
AGND 54
VBAT 58
+
P–GA1
ADC
PGA1
+
ADC
ENERGY
MEASUREMENT
DSP
+
PGA2
ADC
TEMP
SENSOR
TEMP
ADC
BATTERY
ADC
POWER SUPPLY
CONTROL AND
MONITORING
PROGRAM MEMORY
16kB FLASH
USER RAM
256 BYTES
USER XRAM
256 BYTES
VDCIN
ADC
LDO
POR
LDO
3V/5V LCD
CHARGE PUMP
SINGLE
CYCLE
8052
MCU
WATCHDOG
TIMER
108-SEGMENT
LCD DRIVER
DOWNLOADER
DEBUGGER
UART
TIMER
UART
SERIAL
PORT
PLL
RTC OSC
12 P2.0 (FP18)
13 P2.1 (FP17)
14 P2.2 (FP16)
44 P2.3 (SDEN)
19 LCDVP1
16 LCDVP2
18 LCDVA
17 LCDVB
15 LCDVC
4 COM0
...
1 COM3
35 FP0
...
20 FP15
14 FP16
13 FP17
12 FP18
11 FP19
10 FP20
9 FP21
8 FP22
7 FP23
6 FP24
5 FP25
64 60
61 62 59 56 51 44
36 37
47 46 48 45
Figure 2. ADE7166/ADE7169 Functional Block Diagram
Rev. A | Page 5 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
SPECIFICATIONS
VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTAL = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
ENERGY METERING
Table 2.
Parameter
Min Typ
Max Unit
MEASUREMENT ACCURACY1
Phase Error Between Channels
PF = 0.8 Capacitive
±0.05
Degrees
PF = 0.5 Inductive
±0.05
Degrees
Active Energy Measurement Error2
www.DataSheeAt4CUP.coowmer Supply Rejection2
0.1 % of reading
Output Frequency Variation
0.01 %
DC Power Supply Rejection2
Output Frequency Variation
0.01 %
Active Energy Measurement Bandwidth1
8
kHz
Reactive Energy Measurement Error2, 3
0.5
% of reading
Vrms Measurement Error2
0.5 % of reading
Vrms Measurement Bandwidth1
3.9 kHz
Irms Measurement Error2
0.5 % of reading
Irms Measurement Bandwidth1
3.9 kHz
ANALOG INPUTS
Maximum Signal Levels
±400 mV peak
ADE7566/ADE7569
±400 mV peak
ADE7166/ADE7169
±250 mV peak
Input Impedance (DC)
770 kΩ
ADC Offset Error2
±10 mV
±1 mV
Gain Error2
Current Channel
−3 + 3 %
Voltage Channel
−3 + 3 %
Gain Error Match
±0.2 %
CF1 AND CF2 PULSE OUTPUT
Maximum Output Frequency
13.5 kHz
Duty Cycle
Active High Pulse Width
FAULT DETECTION4
Fault Detection Threshold
Inactive Input ≠ Active Input
Input Swap Threshold
Inactive Input > Active Input
Accuracy Fault Mode Operation
IPA Active, IPB = AGND
IPB Active, IPA = AGND
Fault Detection Delay
Swap Delay
50 %
90 ms
6.25 %, of active
6.25 % of active
0.1 % of reading
0.1 % of reading
3 Seconds
3 Seconds
Test Conditions/Comments
Phase lead 37°
Phase lag 60°
Over a dynamic range of 1000 to 1 @ 25°C
VDD = 3.3 V + 100 mV rms/120 Hz
IPx = VP = ±100 mV rms
VDD = 3.3 V ± 117 mV dc
Over a dynamic range of 1000 to 1 @ 25°C
Over a dynamic range of 100 to 1 @ 25°C
Over a dynamic range of 500 to 1 @ 25°C
VP − VN differential input
IP − IN differential input
IPA − IN and IPB − IN differential inputs
PGA1 = PGA2 = 1
PGA1 = 16
IPA = IPB = 0.4 V dc or IP = 0.4 dc
Voltage channel = 0.4 V dc
VP − VN = 400 mV peak; IPA − IN = 250 mV
PGA1 = 2 sine wave
If CF1 or CF2 frequency, >5.55 Hz
If CF1 or CF2 frequency, <5.55 Hz
IPA or IPB active
IPA or IPB active
Over a dynamic range of 500 to 1
Over a dynamic range of 500 to 1
1 These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
2 See the Terminology section for definition.
3 This function is not available in the ADE7566 and the ADE7166.
4 This function is not available in the ADE7566 and the ADE7569.
Rev. A | Page 6 of 144


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ANALOG PERIPHERALS
Table 3.
Parameter
INTERNAL ADCs (BATTERY, TEMPERATURE, VDCIN)
Power Supply Operating Range
No Missing Codes1
Conversion Delay2
ADC Gain
VDCIN Measurement
VBAT Measurement
Temperature Measurement
www.DataSheet4UA.DcoCmOffset
VDCIN Measurement at 3 V
VBAT Measurement at 3.7 V
Temperature Measurement at 25°C
VDCIN Analog Input
Maximum Signal Levels
Input Impedance (DC)
Low VDCIN Detection Threshold
POWER-ON RESET (POR)
VDD POR
Detection Threshold
POR Active Timeout Period
VSWOUT POR
Detection Threshold
POR Active Timeout Period
VINTD POR
Detection Threshold
POR Active Timeout Period
VINTA POR
Detection Threshold
POR Active Timeout Period
BATTERY SWITCH OVER
Voltage Operating Range (VSWOUT)
VDD to VBAT Switching
Switching Threshold (VDD)
Switching Delay
VBAT to VDD Switching
Switching Threshold (VDD)
Switching Delay
VSWOUT To VBAT Leakage Current
LCD, CHARGE PUMP ACTIVE
Charge Pump Capacitance Between
LCDVP1 and LCDVP2
LCDVA, LCDVB, LCDVC Decoupling Capacitance
LCDVA
LCDVB
LCDVC
V1 Segment Line Voltage
V2 Segment Line Voltage
V3 Segment Line Voltage
DC Voltage Across Segment and COM Pin
ADE7566/ADE7569/ADE7166/ADE7169
Min Typ Max Unit Test Conditions/Comments
2.4
3.7 V
Measured on VSWOUT
8 Bits
38 μs
15.3 mV/LSB
14.6 mV/LSB
0.78 °C/LSB
206 LSB
205 LSB
129 LSB
0 3.3 V
1 MΩ
1.09 1.2 1.27 V
2.5 2.95 V
33 ms
1.8 2.2 V
20 ms
2.03 2.22 V
16 ms
2.05 2.15 V
120 ms
2.4 3.7 V
2.5 2.95 V
10 ns
30 ms
2.5 2.95 V
30 ms
10 nA
100
470
0
0
0
LCDVA − 0.1
LCDVB − 0.1
LCDVC − 0.1
nF
1.75
3.5
5.3
LCDVA
LCDVB
LCDVC
50
nF
V
V
V
V
V
V
mV
Rev. A | Page 7 of 144
When VDD to VBAT switch activated by VDD
When VDD to VBAT switch activated by VDCIN
Based on VDD > 2.75 V
VBAT = 0 V, VSWOUT = 3.43 V, TA = 25°C
1/3 bias mode
1/3 bias mode
Current on segment line = −2 μA
Current on segment line = −2 μA
Current on segment line = −2 μA
LCDVC − LCDVB, LCDVC − LCDVA, or
LCDVB − LCDVA


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ADE7566/ADE7569/ADE7166/ADE7169
Parameter
LCD, RESISTOR LADDER ACTIVE
Leakage Current
V1 Segment Line Voltage
V2 Segment Line Voltage
V3 Segment Line Voltage
ON-CHIP REFERENCE
Reference Error
Power Supply Rejection
Temperature Coefficient1
Min Typ Max Unit Test Conditions/Comments
LCDVA − 0.1
LCDVB − 0.1
LCDVC − 0.1
±20
LCDVA
LCDVB
LCDVC
nA
V
V
V
1/2 and 1/3 bias modes, no load
Current on segment line = −2 μA
Current on segment line = −2 μA
Current on segment line = −2 μA
±0.9
80
10 50
mV
dB
ppm/°C
TA = 25°C
1 These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
2 Delay between ADC conversion request and interrupt set.
www.DataSheet4U.com
DIGITAL INTERFACE
Table 4.
Parameter
LOGIC INPUTS
All Inputs Except XTAL1, XTAL2, BCTRL,
INT0, INT1, RESET
Input High Voltage, VINH
Input Low Voltage, VINL
BCTRL, INT0, INT1, RESET
Input High Voltage, VINH
Input Low Voltage, VINL
Input Currents
RESET
Port 0, Port 1, Port 2
Input Capacitance
FLASH MEMORY
Endurance1
Data Retention2
CRYSTAL OSCILLATOR
Crystal Equivalent Series Resistance
Crystal Frequency
XTAL1 Input Capacitance
XTAL2 Output Capacitance
MCU CLOCK RATE (fCORE)
LOGIC OUTPUTS
Output High Voltage, VOH
ISOURCE
Output Low Voltage, VOL3
ISINK
START-UP TIME4
PSM0 Power-On Time
From Power Saving Mode 1 (PSM1)
PSM1 PSM0
From Power Saving Mode 2 (PSM2)
PSM2 PSM1
PSM2 PSM0
Min Typ Max Unit Test Conditions/Comments
2.0 V
0.4 V
1.3 V
0.4 V
−3.75
10
100
±100
−8.5
nA
nA
μA
pF
RESET = VSWOUT = 3.3 V
Internal pull-up disabled, input = 0 V or VSWOUT
Internal pull-up enabled, input = 0 V, VSWOUT = 3.3 V
All digital inputs
10,000
20
Cycles
Years TJ = 85°C
30 50 kΩ
32 32.768 33.5 kHz
12 pF
12 pF
4.096
MHz Crystal = 32.768 kHz and CD[2:0] = 0
32 kHz Crystal = 32.768 kHz and CD[2:0] = 0b111
2.4 V VDD = 3.3 V ± 5%
80 μA
0.4 V
VDD = 3.3 V ± 5%
2 mA
448 ms VDD at 2.75 V to PSM0 code execution
130 ms VDD at 2.75 V to PSM0 code execution
48 ms Wake-up event to PSM1 code execution
186 ms VDD at 2.75 V to PSM0 code execution
Rev. A | Page 8 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
Parameter
POWER SUPPLY INPUTS
VDD
VBAT
INTERNAL POWER SUPPLY SWITCH (VSWOUT)
VBAT to VSWOUT On Resistance
VDD to VSWOUT On Resistance
VBAT ←→ VDD Switching Open Time
BCTRL State Change and Switch Delay
VSWOUT Output Current Drive
POWER SUPPLY OUTPUTS
VINTA
www.DataSheet4UV.INcToDm
VINTA Power Supply Rejection
VINTD Power Supply Rejection
POWER SUPPLY CURRENTS
Current in Normal Mode (PSM0)
Current in PSM1
Current in PSM2
POWER SUPPLY CURRENTS
Current in Normal Mode (PSM0)
Min Typ Max Unit Test Conditions/Comments
3.13 3.3
2.4 3.3
3.46 V
3.7 V
22 Ω
VBAT = 2.4 V
10.2 Ω
VDD = 3.13 V
40 ns
18 μs
1 6 mA
2.25
2.3
60
50
2.75 V
2.70 V
dB
dB
4 5.3 mA fCORE = 4.096 MHz, LCD and meter active
2.1 mA fCORE = 1.024 MHz, LCD and meter active
1.6 mA fCORE = 32.768 kHz, LCD and meter active
3.2 4.25 mA fCORE = 4.096 MHz, meter DSP active, metering ADC
powered down
3 3.9 mA fCORE = 4.096 MHz, metering ADC and DSP powered
down
3.2 5.05 mA fCORE = 4.096 MHz, LCD active, VBAT = 3.7 V
880 μA fCORE = 1.024 MHz, LCD active
38 μA LCD active with charge pump at 3.3 V + RTC
1.5 μA RTC only, TA = 25°C, VBAT = 3.3 V
4 5.3 mA fCORE = 4.096 MHz, LCD and meter active
1 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
2 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
3 Test carried out with all the I/Os set to a low output level.
4 Delay between power supply valid and execution of first instruction by 8052 core.
Rev. A | Page 9 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
TIMING SPECIFICATIONS
AC inputs during testing were driven at VSWOUT − 0.5 V for Logic 1
and 0.45 V for Logic 0. Timing measurements were made at VIH
minimum for Logic 1 and VIL maximum for Logic 0, as shown in
Figure 3.
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded VOH/VOL level
occurs as shown in Figure 3.
CLOAD for all outputs = 80 pF, unless otherwise noted. VDD = 2.7 V
to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted.
VSWOUT – 0.5V
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0.45V
0.2VSWOUT + 0.9V
TEST POINTS
0.2VSWOUT – 0.1V
VLOAD – 0.1V
VLOAD
VLOAD + 0.1V
TIMING
REFERENCE
POINTS
Figure 3. Timing Waveform Characteristics
VLOAD – 0.1V
VLOAD
VLOAD – 0.1V
Table 5. Clock Input (External Clock Driven XTAL1) Parameter
Parameter
tCK
tCKL
tCKH
tCKR
tCKF
1/tCORE
Description
XTAL1 period
XTAL1 width low
XTAL1 width high
XTAL1 rise time
XTAL1 fall time
Core clock frequency1
Min
0.032768
32.768 kHz External Crystal
Typ Max
30.52
6.26
6.26
9
9
1.024
4.096
Unit
μs
μs
μs
ns
ns
MHz
1 The ADE7566/ADE7569/ADE7166/ADE7169 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz
internal clock for the system. The core can operate at this frequency or at a binary submultiple defined by the CD[2:0] bits, selected via the POWCON SFR (see Table 25).
Table 6. I2C-Compatible Interface Timing Parameters (400 kHz)
Parameter
Description
tBUF Bus-free time between stop condition and start condition
tL SCLK low pulse width
tH SCLK high pulse width
tSHD Start condition hold time
tDSU Data setup time
tDHD Data hold time
tRSU Setup time for repeated start
tPSU Stop condition setup time
tR Rise time of both SCLK and SDATA
tF Fall time of both SCLK and SDATA
tSUP1 Pulse width of spike suppressed
Typ
1.3
1.36
1.14
251.35
740
400
12.5
400
200
300
50
Unit
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
1 Input filtering on both the SCLK and SDATA inputs suppresses noise spikes less than 50 ns.
tBUF
tSUP
SDATA (I/O)
MSB
LSB
ACK
tPSU
SCLK (I)
tDSU
tSHD
1
PS
STOP
START
CONDITION CONDITION
tDHD
tDSU
tH
tDHD
tRSU
2 TO 7
tL
8
tSUP
9
Figure 4. I2C-Compatible Interface Timing
S(R)
REPEATED
START
tR
MSB
tF
tR
1
tF
Rev. A | Page 10 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters
Parameter
Description
tSL SCLK low pulse width
tSH SCLK high pulse width
tDAV Data output valid after SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
Min
2SPIR × tCORE1
2SPIR × tCORE1
0
tCORE1
www.DataShee1tt4CUOR.Ecdoempends on the clock divider or CD bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz.
Typ
19
19
19
19
Max
3 × tCORE1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
(SPICPOL = 0)
SCLK
(SPICPOL = 1)
MOSI
tSH
tDAV
tSL
tSR
tDF
MSB
tDR
BITS [6:1]
tSF
LSB
MISO
MSB IN
BITS [6:1]
tDSU
tDHD
Figure 5. SPI Master Mode Timing (SPICPHA = 1)
LSB IN
Rev. A | Page 11 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters
Parameter
Description
Min
tSL
tSH
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
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SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data output setup before SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
2SPIR × tCORE1
2SPIR × tCORE1
0
tCORE1
1 tCORE depends on the clock divider or CD bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz.
Typ
(SPIR + 1) × tCORE1
(SPIR + 1) × tCORE1
19
19
19
19
Max
3 × tCORE1
75
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
(SPICPOL = 0)
SCLK
(SPICPOL = 1)
MOSI
MISO
tSH tSL
tDOSU
tDAV
tDF
MSB
tDR
BITS [6:1]
tSR tSF
LSB
MSB IN
BITS [6:1]
LSB IN
tDSU tDHD
Figure 6. SPI Master Mode Timing (SPICPHA = 0)
Rev. A | Page 12 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters
Parameter
Description
tSS SS to SCLK edge
tSL SCLK low pulse width
tSH SCLK high pulse width
tDAV Data output valid after SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
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tSFS
SCLK fall time
SS high after SCLK edge
Min
145
6 × tCORE1
6 × tCORE1
0
2 × tCORE1 + 0.5 μs
0
1 tCORE depends on the clock divider or CD bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz.
Typ
19
19
19
19
Max
25
Unit
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
SS
SCLK
(SPICPOL = 0)
SCLK
(SPICPOL = 1)
tSS
tSH
tSL
tSFS
tSR tSF
MISO
MOSI
tDAV
tDF
MSB
tDR
BITS [6:1]
MSB IN
BITS [6:1]
tDSU
tDHD
Figure 7. SPI Slave Mode Timing (SPICPHA = 1)
LSB
LSB IN
Rev. A | Page 13 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters
Parameter
Description
tSS SS to SCLK edge
tSL SCLK low pulse width
tSH SCLK high pulse width
tDAV Data output valid after SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
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tDOSS
SCLK fall time
Data output valid after SS edge
tSFS SS high after SCLK edge
Min
145
6 × tCORE1
6 × tCORE1
0
2 × tCORE1+ 0.5 μs
0
0
1 tCORE depends on the clock divider or CD bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz.
Typ
19
19
19
19
SS
SCLK
(SPICPOL = 0)
SCLK
(SPICPOL = 1)
tSS
MISO
tDOSS
tSH tSL
tDAV
tDF
MSB
tDR
BITS [6:1]
tSFS
tSR tSF
LSB
Max Unit
ns
ns
ns
25 ns
ns
μs
ns
ns
ns
ns
ns
ns
MOSI
MSB IN
BITS [6:1]
LSB IN
tDSU
tDHD
Figure 8. SPI Slave Mode Timing (SPICPHA = 0)
Rev. A | Page 14 of 144


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ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 11.
Parameter
VDD to DGND
VBAT to DGND
VDCIN to DGND
Input LCD Voltage to AGND, LCDVA,
LCDVB, LCDVC1
Analog Input Voltage to AGND, VP, VN, IPA,
and IN
www.DataSheeDt4igUi.tcaolmInput Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range (Industrial)
Storage Temperature Range
64-Lead LQFP, Power Dissipation
Lead Temperature
Soldering
Time
1 When used with external resistor divider.
Rating
−0.3 V to +3.7 V
−0.3 V to +3.7 V
−0.3 V to VSWOUT + 0.3 V
−0.3 V to VSWOUT + 0.3 V
−2 V to +2 V
−0.3 V to VSWOUT + 0.3 V
−0.3 V to VSWOUT + 0.3 V
−40°C to +85°C
−65°C to +150°C
300°C
30 sec
ADE7566/ADE7569/ADE7166/ADE7169
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 12. Thermal Resistance
Package Type
θJA θJC Unit
64-Lead LQFP
60 20.5 °C/W
64-Lead LFCSP
27.1 2.3
°C/W
ESD CAUTION
Rev. A | Page 15 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
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64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
COM3/FP27 1
COM2/FP28 2
COM1 3
COM0 4
P1.2/FP25 5
P1.3/T2EX/FP24 6
P1.4/T2/FP23 7
P1.5/FP22 8
P1.6/FP21 9
P1.7/FP20 10
P0.1/FP19 11
P2.0/FP18 12
P2.1/FP17 13
P2.2/FP16 14
LCDVC 15
LCDVP2 16
PIN 1
ADE7566/ADE7569/ADE7166/ADE7169
TOP VIEW
(Not to Scale)
48 INT0
47 XTAL1
46 XTAL2
45 BCTRL/INT1/P0.0
44 SDEN/P2.3
43 P0.2/CF1/RTCCAL
42 P0.3/CF2
41 P0.4/MOSI/SDATA
40 P0.5/MISO
39 P0.6/SCLK/T0
38 P0.7/SS/T1
37 P1.0/RxD
36 P1.1/TxD
35 FP0
34 FP1
33 FP2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 9. Pin Configuration
Table 13. Pin Function Descriptions
Pin No. Mnemonic
Description
1
COM3/FP27
Common Output 3 or LCD Segment Output 27. COM3 is used for LCD backplane.
2
COM2/FP28
Common Output 2 or LCD Segment Output 28. COM2 is used for LCD backplane.
3 COM1
Common Output 1. COM1 is used for LCD backplane.
4 COM0
Common Output 0. COM0 is used for LCD backplane.
5 P1.2/FP25
General-Purpose Digital I/O Port 1.2 or LCD Segment Output 25.
6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3, Timer 2 Control Input, or LCD Segment Output 24.
7
P1.4/T2/FP23
General-Purpose Digital I/O Port 1.4, Timer 2 Input, or LCD Segment Output 23.
8 P1.5/FP22
General-Purpose Digital I/O Port 1.5 or LCD Segment Output 22.
9 P1.6/FP21
General-Purpose Digital I/O Port 1.6 or LCD Segment Output 21.
10 P1.7/FP20
General-Purpose Digital I/O Port 1.7 or LCD Segment Output 20.
11 P0.1/FP19
General-Purpose Digital I/O Port 0.1 or LCD Segment Output 19.
12 P2.0/FP18
General-Purpose Digital I/O Port 2.0 or LCD Segment Output 18.
13 P2.1/FP17
General-Purpose Digital I/O Port 2.1 or LCD Segment Output 17.
14 P2.2/FP16
General-Purpose Digital I/O Port 2.2 or LCD Segment Output 16.
15 LCDVC
Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor.
16 LCDVP2
Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP1 for the internal LCD
charge pump device.
17, 18 LCDVB, LCDVA
Output Port for LCD Levels. These pins should be decoupled with a 470 nF capacitor.
19 LCDVP1
Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP2 for the internal LCD
charge pump device.
35 to 20 FP0 to F15
LCD Segment Output 0 to LCD Segment Output 15.
36 P1.1/TxD
General-Purpose Digital I/O Port 1.1 or Transmitter Data Output (Asynchronous).
37 P1.0/RxD
General-Purpose Digital I/O Port 1.0 or Receiver Data Input (Asynchronous).
38 P0.7/SS/T1
General-Purpose Digital I/O Port 0.7, Slave Select when SPI is in Slave Mode or Timer 1 Input.
39
P0.6/SCLK/T0
General-Purpose Digital I/O Port 0.6, Clock Output for I2C or SPI Port, or Timer 0 Input.
40 P0.5/MISO
General-Purpose Digital I/O Port 0.5 or Data Input for SPI Port.
41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4, Data Line I2C-Compatible, or Data Output for SPI Port.
42 P0.3/CF2
General-Purpose Digital I/O Port 0.3 or Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, Irms, or apparent power information.
Rev. A | Page 16 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
Pin No. Mnemonic
43 P0.2/CF1/RTCCAL
44 SDEN/P2.3
45 BCTRL/INT1/P0.0
www.DataShee4t46U.com XTAL2
47 XTAL1
48
49, 50
51
INT0
VP, VN
EA
52, 53
54
55
IP or IPA, IN
AGND
FP26 or IPB
56 RESET
57 REFIN/OUT
58 VBAT
59 VINTA
60 VDD
61 VSWOUT
62 VINTD
63 DGND
64 VDCIN
Description
General-Purpose Digital I/O Port 0.2, Calibration Frequency Logic Output 1, or RTC Calibration Frequency
Logic Output. The CF1 logic output gives instantaneous active, reactive, Irms, or apparent power information.
The RTCCAL logic output gives access to the calibrated RTC output.
Serial Download Mode Enable or Digital Output Pin P2.3. This pin is used to enable serial download mode
through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input
and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high
and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug
kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be
used as a digital output port pin (P2.3).
Digital Input for Battery Control, External Interrupt Input 1, or General-Purpose Digital I/O Port 0.0. This logic
input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between VDD or VBAT and VSWOUT is selected internally.
A crystal can be connected across this pin and XTAL1 (see XTAL1 pin description) to provide a clock source
for the ADE7566/ADE7569/ADE7166/ADE7169. The XTAL2 pin can drive one CMOS load when an external
clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be
connected across XTAL1 and XTAL2 to provide a clock source for the ADE7566/ADE7569/ADE7166/ADE7169.
The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.
External Interrupt Input 0.
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
This pin is used as an input for emulation. When held high, this input enables the device to fetch code from
internal program memory locations. The ADE7566/ADE7569/ADE7166/ADE7169 do not support external
code memory. This pin should not be left floating.
Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
This pin provides the ground reference for the analog circuitry.
LCD Segment Output 26 (FP26) for ADE7566 and ADE7569 or Analog Inputs for Second Current Channel (IPB)
for ADE7166 and ADE7169. This input is fully differential with a maximum differential level of ±400 mV
referred to IN for specified operation. This channel also has an internal PGA.
Reset Input, Active Low.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
1.2 V ± 0.1% and a typical temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled
with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor.
Power Supply Input from the Battery with a 2.4 V to 2.7 V Range. This pin is connected internally to VDD when
the battery is selected as the power supply for the ADE7566/ADE7569/ADE7166/ADE7169.
This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Input from the Regulator. This pin is connected internally to VDD when the regulator is
selected as the power supply for the ADE7566/ADE7569/ADE7166/ADE7169. This pin should be decoupled
with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the
ADE7566/ADE7569/ADE7166/ADE7169. This pin should be decoupled with a 10 μF capacitor in parallel with
a ceramic 100 nF capacitor.
This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
This pin provides the ground reference for the digital circuitry.
Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
Rev. A | Page 17 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
GAIN = 1
1.5 INTEGRATOR OFF
INTERNAL REFERENCE
MID CLASS C
1.0
0.5 +25°C; PF = 1
0
–0.5
+85°C; PF = 1
–40°C; PF = 1
–1.0
www.DataSheet4U1.5.com
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 10. Active Energy Error as a Percentage of Reading (Gain = 1) over
Temperature with Internal Reference, Integrator Off
1.5
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
0.5
0
–0.5
+25°C; PF = 1
+85°C; PF = 1
–40°C; PF = 1
+25°C; PF = 0.5
+85°C; PF = 0.5
–40°C; PF = 0.5
MID CLASS C
MID CLASS C
–1.0
–1.5
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 11. Active Energy Error as a Percentage of Reading (Gain = 1) over
Power Factor with Internal Reference, Integrator Off
2.0
GAIN = 1
INTEGRATOR OFF
1.5 INTERNAL REFERENCE
1.0
0.5
0
–0.5
–1.0
+85°C; PF = 0
+25°C; PF = 0
–40°C; PF = 0
–1.5
–2.0
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 12. Reactive Energy Error as a Percentage of Reading (Gain = 1) over
Temperature with Internal Reference, Integrator Off
2.0
GAIN = 1
INTEGRATOR OFF
1.5 INTERNAL REFERENCE
1.0
+85°C; PF = 0.866
0.5
+25°C; PF = 0.866
–40°C; PF = 0.866
0
+85°C; PF = 0
–0.5 +25°C; PF = 0
–40°C; PF = 0
–1.0
–1.5
–2.0
0.1 1 10 100
CURRENT CHANNEL (% of Full Scale)
Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 1) over
Power Factor with Internal Reference, Integrator Off
2.0
GAIN = 1
1.5 INTEGRATOR OFF
INTERNAL REFERENCE
1.0
MID CLASS C
0.5 +25°C; PF = 1 +85°C; PF = 1
0
–0.5 –40°C; PF = 1
–1.0
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 14. Current RMS Error as a Percentage of Reading (Gain = 1) over
Temperature with Internal Reference, Integrator Off
2.0
GAIN = 1
1.5 INTEGRATOR OFF
INTERNAL REFERENCE
MID CLASS C
1.0
0.5
+25°C; PF = 1
+25°C; PF = 0.5
+85°C; PF = 1
+85°C; PF = 0.5
0
–0.5
–1.0
–40°C; PF = 1
–40°C; PF = 0.5
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 15. Current RMS Error as a Percentage of Reading (Gain = 1) over
Power Factor with Internal Reference, Integrator Off
Rev. A | Page 18 of 144


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0.5
GAIN = 1
0.4
INTEGRATOR OFF
INTERNAL REFERENCE
0.3
0.2 Irms; 3.3V
0.1 Irms; 3.43V
0
Vrms; 3.3V
–0.1
–0.2
Irms; 3.13V
Vrms; 3.43V
Vrms; 3.13V
–0.3
–0.4
www.DataSheet4U.com0.50.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 16. Voltage and Current RMS Error as a Percentage of Reading (Gain = 1)
over Power Supply with Internal Reference
1.0 GAIN = 1
0.8
INTEGRATOR OFF
INTERNAL REFERENCE
0.6
0.4
0.2
0
–0.2
MID CLASS B
PF = 1
PF = 0.5
MID CLASS B
–0.4
–0.6
–0.8
–1.0
40 45 50 55 60 65 70
LINE FREQUENCY (Hz)
Figure 17. Active Energy Error as a Percentage of Reading (Gain = 1) over
Frequency with Internal Reference, Integrator Off
0.5
GAIN = 1
0.4
INTEGRATOR OFF
INTERNAL REFERENCE
0.3
0.2 VAR; 3.43V
0.1 VAR; 3.3V
W; 3.3V
0
–0.1 VAR; 3.13V
W; 3.13V
–0.2
W; 3.43V
–0.3
–0.4
–0.5
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 18. Active and Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Power Supply with Internal Reference, Integrator Off
ADE7566/ADE7569/ADE7166/ADE7169
1.5
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
0.5
PF = 1
0
–0.5
PF = –0.5
PF = +0.5
–1.0
MID CLASS C
MID CLASS C
–1.5
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 19. Active Energy Error as a Percentage of Reading (Gain = 8) over
Power Factor with Internal Reference, Integrator Off
1.0
GAIN = 8
0.8
INTEGRATOR OFF
INTERNAL REFERENCE
0.6
0.4
PF = 1
0.2 PF = +0.5
0
–0.2
–0.4
PF = –0.5
–0.6
–0.8
–1.0
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 20. Reactive Energy Error as a Percentage of Reading (Gain = 8) over
Power Factor with Internal Reference, Integrator Off
1.5
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
0.5
PF = 1
0
PF = +0.5
MID CLASS C
–0.5 PF = –0.5
MID CLASS C
–1.0
–1.5
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 21. Current RMS Error as a Percentage of Reading (Gain = 8) over
Power Factor with Internal Reference, Integrator Off
Rev. A | Page 19 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
2.0
GAIN = 16
1.5
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
MID CLASS C
0.5 +25°C; PF = 1
0
–0.5 –40°C; PF = 1
+85°C; PF = 1
–1.0
–1.5
www.DataSheet4–2U.0.0c.1om
MID CLASS C
1 10 100
CURRENT CHANNEL (% of Full Scale)
Figure 22. Active Energy Error as a Percentage of Reading (Gain = 16) over
Temperature with Internal Reference, Integrator Off
2.0
GAIN = 16
1.5
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
+85°C; PF = 0.5
0.5
+25°C; PF = 1
+25°C; PF = 0.5
0
–0.5
–1.0
+85°C; PF = 1
–40°C; PF = 1
–40°C; PF = 0.5
MID CLASS C
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 23. Active Energy Error as a Percentage of Reading (Gain = 16) over
Power Factor with Internal Reference, Integrator Off
1.0 GAIN = 16
0.8
INTEGRATOR OFF
INTERNAL REFERENCE
0.6
0.4 +85°C; PF = 0
0.2
–40°C; PF = 0
0
–0.2
–0.4
+25°C; PF = 0
–0.6
–0.8
–1.0
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 24. Reactive Energy Error as a Percentage of Reading (Gain = 16) over
Temperature with Internal Reference, Integrator Off
1.0
GAIN = 16
0.8
INTEGRATOR OFF
INTERNAL REFERENCE
0.6
0.4
0.2
–40°C; PF = 0
+85°C; PF = 0
+85°C; PF = 0.866
–40°C; PF = 0.866
0
–0.2
+25°C; PF = 0.866
+25°C; PF = 0
–0.4
–0.6
–0.8
–1.0
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 25. Reactive Energy Error as a Percentage of Reading (Gain = 16) over
Power Factor with Internal Reference, Integrator Off
2.0
GAIN = 16
1.5
INTEGRATOR OFF
INTERNAL REFERENCE
1.0
MID CLASS C
0.5 –40°C; PF = 1
0
–0.5
–1.0
+25°C; PF = 1
+85°C; PF = 1
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 26. Current RMS Error as a Percentage of Reading (Gain = 16) over
Temperature with Internal Reference, Integrator Off
2.0
GAIN = 16
1.5
INTEGRATOR OFF
INTERNAL REFERENCE
MID CLASS C
1.0
–40°C; PF = 1
0.5
+25°C; PF = 1
–40°C; PF = 0.5
0
–0.5
–1.0
+85°C; PF = 0.5
+25°C; PF = 0.5
+85°C; PF = 1
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 27. Current RMS Error as a Percentage of Reading (Gain = 16) over
Power Factor with Internal Reference, Integrator Off
Rev. A | Page 20 of 144


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2.0
GAIN = 16
1.5
INTEGRATOR ON
INTERNAL REFERENCE
1.0 –40°C; PF = 1
+85°C; PF = 0.5
+25°C; PF = 0.5
0.5 –40°C; PF = 0.5
MID CLASS C
0
–0.5
+25°C; PF = 1
+85°C; PF = 1
–1.0
–1.5
www.DataSheet4U.com2.00.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 28. Active Energy Error as a Percentage of Reading (Gain = 16) over
Power Factor with Internal Reference, Integrator On
1.0 GAIN = 16
0.8
INTEGRATOR ON
INTERNAL REFERENCE
0.6
0.4 +25°C; PF = 0
0.2
+85°C; PF = 0.866
–40°C; PF = 0
+25°C; PF = 0.866
0
–0.2
+85°C; PF = 0
–0.4
–40°C; PF = 0.866
–0.6
–0.8
–1.0
0.1
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 29. Reactive Energy Error as a Percentage of Reading (Gain = 16) over
Power Factor with Internal Reference, Integrator On
ADE7566/ADE7569/ADE7166/ADE7169
2.0
GAIN = 16
1.5
INTEGRATOR ON
INTERNAL REFERENCE
1.0 +25°C; PF = 1
+25°C; PF = 0.5
0.5
+85°C; PF = 0.5
+85°C; PF = 1
–40°C; PF = 0.5
0
MID CLASS C
–0.5
–1.0
–40°C; PF = 1
–1.5
–2.0
0.1
MID CLASS C
1 10
CURRENT CHANNEL (% of Full Scale)
100
Figure 30. Current RMS Error as a Percentage of Reading (Gain = 16) over
Power Factor with Internal Reference, Integrator On
Rev. A | Page 21 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7566/ADE7569/ADE7166/ADE7169 is defined by the
following formula:
Percentage
Error
=
⎜⎜⎝⎛
Energy
Register True
True Energy
Energy
⎟⎟⎠⎞ ×100%
Phase Error Between Channels
The digital integrator and the high-pass filter (HPF) in the
current channel have a nonideal phase response. To offset this
www.DatapShhaeseet4rUes.cpoomnse and equalize the phase response between
channels, two phase correction networks are placed in the
current channel: one for the digital integrator and the other for
the HPF. The phase correction networks correct the phase
response of the corresponding component and ensure a phase
match between current channel and voltage channel to within
±0.1° over a range of 45 Hz to 65 Hz with the digital integrator
off. With the digital integrator on, the phase is corrected to
within ±0.4° over a range of 45 Hz to 65 Hz.
Power Supply Rejection (PSR)
PSR quantifies the ADE7566/ADE7569/ADE7166/ADE7169
measurement error as a percentage of reading when the power
supplies are varied. For the ac PSR measurement, a reading at
nominal supplies (3.3 V) is taken. A second reading is obtained
with the same input signal levels when an ac (100 mV rms/120 Hz)
signal is introduced onto the supplies. Any error introduced by
this ac signal is expressed as a percentage of reading (see the
Measurement Error definition).
For the dc PSR measurement, a reading at nominal supplies
(3.3 V) is taken. A second reading is obtained with the same
input signal levels when the supplies are varied ±5%. Any error
introduced is again expressed as a percentage of the reading.
ADC Offset Error
ADC offset error is the dc offset associated with the analog
inputs to the ADCs. It means that, with the analog inputs
connected to AGND, the ADCs still see a dc analog input
signal. The magnitude of the offset depends on the gain and
input range selection (see the Typical Performance
Characteristics section). However, when HPF1 is switched on,
the offset is removed from the current channel, and the power
calculation is not affected by this offset. The offsets can be
removed by performing an offset calibration (see the Analog
Inputs section).
Gain Error
Gain error is the difference between the measured ADC output
code (minus the offset) and the ideal output code (see the
Current Channel ADC section and the Voltage Channel ADC
section). It is measured for each of the gain settings on the
current channel (1, 2, 4, 8, and 16). The difference is expressed
as a percentage of the ideal code.
Rev. A | Page 22 of 144


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SFR MAPPING
Table 14.
Mnemonic
Address
Details
INTPR
0xFF Table 16
SCRATCH4
0xFE
Table 24
SCRATCH3
0xFD
Table 23
SCRATCH2
0xFC
Table 22
SCRATCH1
0xFB
Table 21
BATVTH
0xFA
Table 51
STRBPER
0xF9 Table 48
w w w . IPSDMFa t a S h 0exF8e t 4 U .Tabcle 1o7 m
TEMPCAL 0xF7 Table 127
RTCCOMP
0xF6
Table 126
BATPR
0xF5 Table 18
PERIPH
0xF4 Table 19
DIFFPROG
0xF3
Table 49
B 0xF0 Table 55
VDCINADC
0xEF
Table 52
LCDSEGE2
0xED
Table 88
IPSME
0xEC
Table 20
SPISTAT
0xEA
Table 142
SPI2CSTAT
0xEA
Table 147
SPIMOD2 0xE9 Table 141
I2CADR
0xE9 Table 146
SPIMOD1 0xE8 Table 140
I2CMOD
0xE8 Table 145
WAV2H
0xE7 Table 30
WAV2M
0xE6 Table 30
WAV2L
0xE5 Table 30
WAV1H
0xE4 Table 30
WAV1M
0xE3 Table 30
WAV1L
0xE2 Table 30
ACC 0xE0 Table 55
BATADC
0xDF
Table 53
MIRQSTH
0xDE
Table 41
MIRQSTM
0xDD
Table 40
MIRQSTL
0xDC
Table 39
MIRQENH
0xDB
Table 44
MIRQENM
0xDA
Table 43
MIRQENL
0xD9
Table 42
ADCGO
0xD8
Table 50
TEMPADC
0xD7
Table 54
IRMSH
0xD6
Table 30
IRMSM
0xD5
Table 30
IRMSL
0xD4
Table 30
VRMSH
0xD3
Table 30
VRMSM
0xD2
Table 30
VRMSL
0xD1
Table 30
ADE7566/ADE7569/ADE7166/ADE7169
Mnemonic
PSW
TH2
TL2
RCAP2H
RCAP2L
T2CON
EADRH
EADRL
POWCON
KYREG
WDCON
PROTR
PROTB1
PROTB0
EDATA
PROTKY
FLSHKY
ECON
IP
PINMAP2
PINMAP1
PINMAP0
LCDCONY
CFG
LCDDAT
LCDPTR
IEIP2
IE
DPCON
INTVAL
HOUR
MIN
SEC
HTHSEC
TIMECON
P2
EPCFG
SBAUDT
SBAUDF
LCDCONX
SPI2CRx
SPI2CTx
SBUF
SCON
LCDSEGE
Address
0xD0
0xCD
0xCC
0xCB
0xCA
0xC8
0xC7
0xC6
0xC5
0xC1
0xC0
0xBF
0xBE
0xBD
0xBC
0xBB
0xBA
0xB9
0xB8
0xB4
0xB3
0xB2
0xB1
0xAF
0xAE
0xAC
0xA9
0xA8
0xA7
0xA6
0xA5
0xA4
0xA3
0xA2
0xA1
0xA0
0x9F
0x9E
0x9D
0x9C
0x9B
0x9A
0x99
0x98
0x97
Details
Table 56
Table 110
Table 111
Table 112
Table 113
Table 105
Table 100
Table 99
Table 25
Table 116
Table 75
Table 98
Table 97
Table 96
Table 95
Table 94
Table 93
Table 92
Table 69
Table 152
Table 151
Table 150
Table 81
Table 62
Table 87
Table 86
Table 70
Table 68
Table 66
Table 125
Table 124
Table 123
Table 122
Table 121
Table 120
Table 155
Table 149
Table 134
Table 135
Table 79
Table 139
Table 138
Table 133
Table 132
Table 85
Rev. A | Page 23 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
Mnemonic
LCDCLK
LCDCON
MDATH
MDATM
MDATL
MADDPT
P1
TH1
TH0
Address
0x96
0x95
0x94
0x93
0x92
0x91
0x90
0x8D
0x8C
Details
Table 82
Table 78
Table 30
Table 30
Table 30
Table 30
Table 154
Table 108
Table 106
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Mnemonic
TL1
TL0
TMOD
TCON
PCON
DPH
DPL
SP
P0
Address
0x8B
0x8A
0x89
0x88
0x87
0x83
0x82
0x81
0x80
Details
Table 109
Table 107
Table 103
Table 104
Table 57
Table 59
Table 58
Table 61
Table 153
Rev. A | Page 24 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
POWER MANAGEMENT
The ADE7566/ADE7569/ADE7166/ADE7169 have elaborate
power management circuitry that manages the regular power
supply to battery switchover and power supply failures. The
power management functionalities can be accessed directly
through the 8052 SFRs (see Table 15).
Table 15. Power Management SFRs
SFR Address
R/W Mnemonic
0xEC
R/W IPSME
0xF5 R/W BATPR
0xF8 R/W IPSMF
0xFF R/W INTPR
www.DataShee0t4xUF4.com
0xC5
R/W PERIPH
R/W POWCON
0xFB
R/W SCRATCH1
0xFC
R/W SCRATCH2
0xFD
R/W SCRATCH3
0xFE R/W SCRATCH4
Description
Power Management Interrupt Enable. See Table 20.
Battery Switchover Configuration. See Table 18.
Power Management Interrupt Flag. See Table 17.
Interrupt Pins Configuration. See Table 16.
Peripheral Configuration SFR. See Table 19.
Power Control. See Table 25.
Scratch Pad 1. See Table 21.
Scratch Pad 2. See Table 22.
Scratch Pad 3. See Table 23.
Scratch Pad 4. See Table 24.
POWER MANAGEMENT REGISTER DETAILS
Table 16. Interrupt Pins Configuration SFR (INTPR, 0xFF)
Bit Mnemonic Default Description
7
RTCCAL
0
Controls RTC calibration output. When set, the RTC calibration frequency selected by FSEL[1:0] is
output on the P0.2/CF1/RTCCAL pin.
6 to 5 FSEL[1:0]
00
Sets RTC calibration output frequency and calibration window.
FSEL[1:0]
Result (Calibration window, frequency)
00 30.5 sec, 1 Hz
01 30.5 sec, 512 Hz
10 0.244 sec, 500 Hz
11 0.244 sec, 16.384 kHz
4 Reserved
3 to 1 INT1PRG[2:0] 000
Controls the function of INT1.
INT1PRG[2:0] Result
X00 GPIO enabled
X01 BCTRL enabled
01X INT1 input disabled
11X INT1 input enabled
0
INT0PRG
0
Controls the function of INT0.
INT0PRG
Result
0 INT0 input disabled
1 INT0 input enabled
Writing to the Interrupt Pins Configuration SFR (INTPR, 0xFF)
To protect the RTC from runaway code, a key must be written to the Key SFR (KYREG, 0xC1) to obtain write access to INTPR. KYREG
(see Table 116) should be set to 0xEA to unlock this SFR and reset to zero after a timekeeping register is written to. The RTC registers can
be written using the following 8052 assembly code:
MOV KYREG, #0EAh
MOV INTPR, #080h
Rev. A | Page 25 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
Table 17. Power Management Interrupt Flag SFR (IPSMF, 0xF8)
Bit Address Mnemonic Default Description
7 0xFF FPSR 0 Power Supply Restored Interrupt Flag. Set when the VDD power supply has been restored.
This occurs when the source of VSWOUT changes from VBAT to VDD.
6 0xFE FPSM 0
PSM Interrupt Flag. Set when an enabled PSM interrupt condition occurs.
5
0xFD
FSAG
0
Voltage SAG Interrupt Flag. Set when an ADE energy measurement SAG condition occurs.
4
0xFC
RESERVED 0
This bit must be kept cleared for proper operation.
3
0xFB
FVADC
0
VDCIN Monitor Interrupt Flag. Set when VDCIN changes by VDCIN_DIFF or when VDCIN
measurement is ready.
2
0xFA
FBAT
0
VBAT Monitor Interrupt Flag. Set when VBAT falls below BATVTH or when VBAT measurement is ready.
1
0xF9
FBSO
0
Battery Switchover Interrupt Flag. Set when VSWOUT switches from VDD to VBAT.
0 0xF8
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FVDCIN
0
VDCIN Monitor Interrupt Flag. Set when VDCIN falls below 1.2 V.
Table 18. Battery Switchover Configuration SFR (BATPR, 0xF5)
Bit
Mnemonic
Default
Description
7 to 2
Reserved
00
These bits must be kept to 0 for proper operation.
1 to 0
BATPRG[1:0]
00
Control Bits for Battery Switchover.
BATPRG[1:0] Result
00 Battery switchover enabled on low VDD
01 Battery switchover enabled on low VDD and low VDCIN
1X Battery switchover disabled
Table 19. Peripheral Configuration SFR (PERIPH, 0xF4)
Bit Mnemonic Default Description
7 RXFLAG
0
If set, indicates that an Rx edge event triggered wake-up from PSM2.
6 VSWSOURCE 1
Indicates the power supply that is internally connected to VSWOUT (0 VSWOUT = VBAT, 1 VSWOUT = VDD).
5 VDD_OK 1
If set, indicates that VDD power supply is ready for operation.
4 PLL_FLT
0
If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (see Table 50) in
the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the fault and clear the PLL_FLT bit.
3 REF_BAT_EN 0
Set this bit to enable internal voltage reference in PSM2 mode. This bit should be set if LCD is on in
PSM2 mode.
2 Reserved 0
This bit should be kept to zero.
1 to 0 RXPROG[1:0] 00
Controls the function of the P1.0/RxD pin.
RXPROG[1:0] Result
00 GPIO
01 RxD with wake-up disabled
11 RxD with wake-up enabled
Table 20. Power Management Interrupt Enable SFR (IPSME, 0xEC)
Bit
Interrupt Enable Bit
Default Description
7 EPSR
0 Enables a PSM interrupt when the power supply restored flag (FPSR) is set.
6 RESERVED
0 Reserved.
5 ESAG
0 Enables a PSM interrupt when the voltage SAG flag (FSAG) is set.
4 RESERVED
0 This bit must be kept cleared for proper operation.
3 EVADC
0 Enables a PSM interrupt when the VADC monitor flag (FVADC) is set.
2 EBAT
0 Enables a PSM interrupt when the VBAT monitor flag (FBAT) is set.
1 EBSO
0 Enables a PSM interrupt when the battery switchover flag (FBSO) is set.
0 EVDCIN
0 Enables a PSM interrupt when the VDCIN monitor flag (FVDCIN) is set.
Table 21. Scratch Pad 1 SFR (SCRATCH1, 0xFB)
Bit Mnemonic Default Description
7 to 0 SCRATCH1 0
Value can be written/read in this register. This value is maintained in all the power saving modes.
Rev. A | Page 26 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
Table 22. Scratch Pad 2 SFR (SCRATCH2, 0xFC)
Bit Mnemonic Default Description
7 to 0 SCRATCH2 0
Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 23. Scratch Pad 3 SFR (SCRATCH3, 0xFD)
Bit Mnemonic Default Description
7 to 0 SCRATCH3 0
Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 24. Scratch Pad 4 SFR (SCRATCH4, 0xFE)
Bit Mnemonic Default Description
7 to 0 SCRATCH4 0
Value can be written/read in this register. This value is maintained in all the power saving modes.
www.DataSheeCt4lUea.croimng the Scratch Pad Registers (SCRATCH1, 0xFB to SCRATCH4, 0xFE)
Note that these scratch pad registers are only cleared when the part loses VDD and VBAT. They are not cleared by software, watchdog, or
PLL reset and, therefore, need to be set correctly in these situations.
Table 25. Power Control SFR (POWCON, 0xC5)
Bit
Mnemonic
Default
Description
7
RESERVED
1
Reserved.
6
METER_OFF
0
Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0.
5
RESERVED
0
This bit should be kept at 0 for proper operation.
4
COREOFF
0
Set this bit to shut down the core and enter PSM2 if in the PSM1 operating mode.
3
RESERVED
0
Reserved.
2 to 0
CD[2:0]
010 Controls the core clock frequency, fCORE. fCORE = 4.096 MHz/2CD.
CD[2:0]
Result (fCORE in MHz)
000 4.096
001 2.048
010 1.024
011 0.512
100 0.256
101 0.128
110 0.064
111 0.032
Writing to the Power Control SFR (POWCON, 0xC5)
Writing data to the POWCON SFR involves writing 0xA7 into the Key SFR (KYREG, 0xC1), which is described in Table 116, followed by
a write to the POWCON SFR. For example:
MOV KYREG,#0A7h
;Write KYREG to 0xA7 to get write access to the POWCON SFR
MOV POWCON,#10h
;Shutdown the core
Rev. A | Page 27 of 144


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ADE7566/ADE7569/ADE7166/ADE7169
POWER SUPPLY ARCHITECTURE
Each ADE7566/ADE7569/ADE7166/ADE7169 has two power
supply inputs, VDD and VBAT, and require only a single 3.3 V
power supply at VDD for full operation. A battery backup, or
secondary power supply, with a maximum of 3.7 V can be
connected to the VBAT input. Internally, the ADE7566/ADE7569/
ADE7166/ADE7169 connect VDD or VBAT to VSWOUT, which is used
to derive power for the ADE7566/ADE7569/ ADE7166/ADE7169
circuitry. The VSWOUT output pin reflects the voltage at the
internal power supply (VSWOUT) and has a maximum output
current of 6 mA. This pin can also be used to power a limited
number of peripheral components. The 2.5 V analog supply (VINTA)
www.DataaSnhdeetht4eU2.c.5omV supply for the core logic (VINTD) are derived by on-
chip linear regulators from VSWOUT. Figure 31 shows the power
supply architecture of ADE7566/ADE7569/ADE7166/ADE7169.
The ADE7566/ADE7569/ADE7166/ADE7169 provide
automatic battery switchover between VDD and VBAT based on
the voltage level detected at VDD or VDCIN. Additionally, the
BCTRL input can be used to trigger a battery switchover. The
conditions for switching VSWOUT from VDD to VBAT and back to
VDD are described in the Battery Switchover section. VDCIN is an
input pin that can be connected to a 0 V to 3.3 V dc signal. This
input is intended for power supply supervisory purposes and
does not provide power to the ADE7566/ADE7569/ADE7166/
ADE7169 circuitry (see the Battery Switchover section).
VDCIN VDD VBAT
VSWOUT
ADC
BCTRL
POWER SUPPLY
MANAGEMENT
VSW
LDO VINTD
LDO VINTA
MCU
ADE
ADC
SCRATCHPAD
LCD
RTC
TEMPERATURE ADC
3.3V
Figure 31. Power Supply Architecture
SPI/I2C
UART
2.5V
BATTERY SWITCHOVER
The ADE7566/ADE7569/ADE7166/ADE7169 monitor VDD, VBAT,
and VDCIN. Automatic battery switchover from VDD to VBAT can be
configured based on the status of VDD, VDCIN, or the BCTRL pin.
Battery switchover is enabled by default. Setting Bit 1 in the
Battery Switchover Configuration SFR (BATPR, 0xF5) disables
battery switchover so that VDD is always connected to VSWOUT
(see Table 18). The source of VSWOUT is indicated by Bit 6 in the
Peripheral Configuration SFR (PERIPH, 0xF4), which is
described in Table 19. Bit 6 is set when VSWOUT is connected to
VDD and cleared when VSWOUT is connected to VBAT.
The battery switchover functionality provided by the
ADE7566/ADE7569/ADE7166/ADE7169 allows a seamless
transition from VDD to VBAT. An automatic battery switchover
option ensures a stable power supply to the ADE7566/
ADE7569/ADE7166/ADE7169, as long as the external battery
voltage is above 2.75 V. It allows continuous code execution
even while the internal power supply is switching from VDD to
VBAT and back. Note that the energy metering ADCs are not
available when VBAT is being used for VSWOUT.
Power supply monitor (PSM) interrupts can be enabled to
indicate when battery switchover occurs and when the VDD
power supply is restored (see the Power Supply Monitor
Interrupt (PSM) section.)
VDD to VBAT
The following three events switch the internal power supply
(VSWOUT) from VDD to VBAT:
VDCIN < 1.2 V. When VDCIN falls below 1.2 V, VSWOUT switches
from VDD to VBAT. This event is enabled when the
BATPRG[1:0] bits in the Battery Switchover Configuration
SFR (BATPR, 0xF5) = 0b01. Setting these bits disables
switchover based on VDCIN. Battery switchover on low VDCIN is
disabled by default.
VDD < 2.75 V. When VDD falls below 2.75 V, VSWOUT switches
from VDD to VBAT. This event is enabled when BATPRG[1:0] in
the BATPR SRF are cleared.
Falling edge on BCTRL. When the battery control pin,
BCTRL, goes low, VSWOUT switches from VDD to VBAT. This
external switchover signal can trigger a switchover to VBAT
at any time. Setting bits INT1PRG[4:2] to 0bx01 in the
Interrupt Pins Configuration SFR (INTPR, 0xFF) enables
the battery control pin (see Table 16).
Switching from VBAT to VDD
To switch VSWOUT from VBAT to VDD, all of the following events
that are enabled to force battery switchover must be false:
VDCIN < 1.2 V and VDD < 2.75 V enabled. If the low VDCIN
condition is enabled, VSWOUT switches to VDD after VDCIN
remains above 1.2 V and VDD remains above 2.75 V.
VDD < 2.75 V enabled. VSWOUT switches back to VDD after
VDD remains above 2.75 V.
BCTRL enabled. VSWOUT switches back to VDD after BCTRL
is high, and the first or second bullet point is satisfied.
Rev. A | Page 28 of 144


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POWER SUPPLY MONITOR INTERRUPT (PSM)
The power supply monitor interrupt (PSM) alerts the 8052 core
of power supply events. The PSM interrupt is disabled by default.
Setting the EPSM bit in the Interrupt Enable and Priority 2 SFR
(IEIP2, 0xA9) enables the PSM interrupt (see Table 70).
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EPSR
FPSR
ESAG
FSAG
EVADC
FVADC
EBAT
FBAT
EBSO
FBSO
EVDCIN
FVDCIN
FPSM
EPSM
ADE7566/ADE7569/ADE7166/ADE7169
The Power Management Interrupt Enable SFR (IPSME, 0xEC)
controls the events that result in a PSM interrupt (see Table 20).
Figure 32 is a diagram illustrating how the PSM interrupt vector
is shared among the PSM interrupt sources. The PSM interrupt
flags are latched and must be cleared by writing to the IPSMF flag
register (see Table 17).
TRUE?
PENDING PSM
INTERRUPT
IPSME ADDR. 0xEC
EPSR
RESERVED
ESAG
RESERVED
EVADC
IPSMF ADDR. 0xF8
FPSR
FPSM
FSAG
RESERVED
FVADC
IEIP2 ADDR. 0xA9 RESERVED PTI RESERVED PSI
EADE
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN
Figure 32. PSM Interrupt Sources
EBAT
FBAT
ETI
EBSO
FBSO
EPSM
EVDCIN
FVDCIN
ESI
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ADE7566/ADE7569/ADE7166/ADE7169
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE7566/ADE7569/ADE7166/ADE7169 can be
configured to generate a PSM interrupt when the source of
VSWOUT changes from VDD to VBAT, indicating battery switchover.
Setting the EBSO bit in the Power Management Interrupt
Enable SFR (IPSME, 0xEC) enables this event to generate a
PSM interrupt (see Table 20).
The ADE7566/ADE7569/ADE7166/ADE7169 can also be
configured to generate an interrupt when the source of VSWOUT
changes from VBAT to VDD, indicating that the VDD power supply
has been restored. Setting the EPSR bit in the Power Management
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Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate
a PSM interrupt.
The flags in the IPSME SFR for these interrupts, FBSO and
FPSR, are set regardless of whether the respective enable bits
have been set. The battery switchover and power supply restore
event flags, FBSO and FPSR, are latched. These events must be
cleared by writing a 0 to these bits. Bit 6 in the Peripheral
Configuration SFR (PERIPH, 0xF4), VSWSOURCE, tracks the
source of VSWOUT. The bit is set when VSWOUT is connected to VDD
and cleared when VSWOUT is connected to VBAT.
VDCIN ADC PSM Interrupt
The ADE7566/ADE7569/ADE7166/ADE7169 can be
configured to generate a PSM interrupt when VDCIN changes
magnitude by more than a configurable threshold. This threshold
is set in the Temperature and Supply Delta SFR (DIFFPROG,
0xF3), which is described in Table 49. See the External Voltage
Measurement section for more information. Setting the
EVDCIN bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
The VDCIN voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to check
the change in VDCIN. Conversions can also be initiated by writing to
the Start ADC Measurement SFR (ADCGO, 0xD8) described in
Table 50. The FVDCIN flag indicates when a VDCIN measurement
is ready. See the External Voltage Measurement section for
details on how VDCIN is measured.
VBAT Monitor PSM Interrupt
The VBAT voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to
check the change in VBAT. The FBAT bit is set when the battery
level is lower than the threshold set in the Battery Detection
Threshold SFR (BATVTH, 0xFA), described in Table 51, or
when a new measurement is ready in the Battery ADC Value
SFR (BATADC, 0xDF), described in Table 53. See the Battery
Measurement section for more information. Setting the EBAT
bit in the Power Management Interrupt Enable SFR (IPSME,
0xEC) enables this event to generate a PSM interrupt.
VDCIN Monitor PSM Interrupt
The VDCIN voltage is monitored by a comparator. The FVDCIN
bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8)
Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set
when the VDCIN input level is lower than 1.2 V. Setting the
EVDCIN bit in the IPSME SFR enables this event to generate a
PSM interrupt. This event, which is associated with the SAG
monitoring, can be used to detect a power supply (VDD) being
compromised and to trigger further actions prior to deciding a
switch of VDD to VBAT.
SAG Monitor PSM Interrupt
The ADE7566/ADE7569/ADE7166/ADE7169 energy
measurement DSP monitors the ac voltage input at the VP and
VN input pins. The SAGLVL register is used to set the threshold
for a line voltage SAG event. The FSAG bit in the Power
Management Interrupt Flag SFR (IPSMF, 0xF8) is set if the line
voltage stays below the level set in the SAGLVL register for the
number of line cycles set in the SAGCYC register. See the Line
Voltage SAG Detection section for more information. Setting
the ESAG bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
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