LFXP (Lattice Semiconductor)
LatticeXP Family

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www.DataSheeLt4Ua.ctotmiceXP Family Data Sheet
DS1001 Version 05.1, November 2007


LFXP (Lattice Semiconductor)
LatticeXP Family

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LatticeXP Family Data Sheet
Introduction
July 2007
Features
Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• No external configuration memory
• Excellent design security, no bit stream to
intercept
• Reconfigure SRAM based logic in milliseconds
www.DataSheet4U.comSRAM and non-volatile memory programmable
through system configuration and JTAG ports
Sleep Mode
• Allows up to 1000x static current reduction
TransFR™ Reconfiguration (TFR)
• In-field logic update while system operates
Extensive Density and Package Options
• 3.1K to 19.7K LUT4s
• 62 to 340 I/Os
• Density migration supported
Embedded and Distributed Memory
• 54 Kbits to 396 Kbits sysMEM™ Embedded
Block RAM
• Up to 79 Kbits distributed RAM
• Flexible memory resources:
Distributed and block memory
Data Sheet DS1001
Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
– SSTL 18 Class I
SSTL 3/2 Class I, II
– HSTL15 Class I, III
HSTL 18 Class I, II, III
PCI
LVDS, Bus-LVDS, LVPECL, RSDS
Dedicated DDR Memory Support
• Implements interface up to DDR333 (166MHz)
sysCLOCK™ PLLs
• Up to 4 analog PLLs per device
• Clock multiply, divide and phase shifting
System Level Support
• IEEE Standard 1149.1 Boundary Scan, plus
ispTRACY™ internal logic analyzer capability
• Onboard oscillator for configuration
• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
Table 1-1. LatticeXP Family Selection Guide
Device
LFXP3
LFXP6
PFU/PFF Rows
16 24
PFU/PFF Columns
24 30
PFU/PFF (Total)
384 720
LUTs (K)
36
Distributed RAM (KBits)
12
23
EBR SRAM (KBits)
54 72
EBR SRAM Blocks
68
VCC Voltage
PLLs
1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V
22
Max. I/O
136 188
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
62
144-pin TQFP (20 x 20 mm)
100
100
208-pin PQFP (28 x 28 mm)
136
142
256-ball fpBGA (17 x 17 mm)
188
388-ball fpBGA (23 x 23 mm)
484-ball fpBGA (23 x 23 mm)
LFXP10
32
38
1216
10
39
216
24
1.2/1.8/2.5/3.3V
4
244
188
244
LFXP15
40
48
1932
15
61
324
36
1.2/1.8/2.5/3.3V
4
300
188
268
300
LFXP20
44
56
2464
20
79
396
44
1.2/1.8/2.5/3.3V
4
340
188
268
340
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1 DS1001 Introduction_01.5a July 6, 2007 3:01 p.m.


LFXP (Lattice Semiconductor)
LatticeXP Family

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Lattice Semiconductor
Introduction
LatticeXP Family Data Sheet
Introduction
The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/Os in a
single architecture that is both non-volatile and infinitely reconfigurable to support cost-effective system designs.
The re-programmable non-volatile technology used in the LatticeXP family is the next generation ispXP™ technol-
ogy. With this technology, expensive external configuration memories are not required and designs are secured
from unauthorized read-back. In addition, instant-on capability allows for easy interfacing in many applications.
The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the Lat-
ticeXP family of FPGA devices. Synthesis library support for LatticeXP is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and back-
www.DataSheeat4nUn.cootamtes it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeXP family.
By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
1-2


LFXP (Lattice Semiconductor)
LatticeXP Family

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LatticeXP Family Data Sheet
Architecture
July 2007
Data Sheet DS1001
Architecture Overview
The LatticeXP architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) as shown in Figure 2-
1.
On the left and right sides of the PFU array, there are Non-volatile Memory Blocks. In configuration mode this non-
volatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™ peripheral port. On power up,
www.DataSheetth4eU.ccoomnfiguration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this
technology, expensive external configuration memories are not required and designs are secured from unautho-
rized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in
microseconds, providing an “instant-on” capability that allows easy interfacing in many applications.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and
right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be configured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeXP architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG
port which allows for serial or parallel device configuration. The LatticeXP devices are available for operation from
3.3V, 2.5V, 1.8V and 1.2V power supplies, providing easy integration into the overall system.
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1 DS1001 Architecture_02.0 July 6, 2007 3:03 p.m.


LFXP (Lattice Semiconductor)
LatticeXP Family

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Lattice Semiconductor
Figure 2-1. LatticeXP Top Level Block Diagram
Programmable I/O Cell
(PIC) includes sysIO
Interface
Non-volatile Memory
www.DataSheet4U.com
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
Architecture
LatticeXP Family Data Sheet
sysMEM Embedded
Block RAM (EBR)
JTAG Port
PFF (PFU without
RAM)
sysCLOCK PLL
Programmable
Functional Unit (PFU)
PFU and PFF Blocks
The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-2. PFU Diagram
From
Routing
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
LUT4 &
CARRY
LUT4 &
CARRY
Slice 1
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
LUT4 &
CARRY
LUT4 &
CARRY
Slice 3
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
To
Routing
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LFXP (Lattice Semiconductor)
LatticeXP Family

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Lattice Semiconductor
Architecture
LatticeXP Family Data Sheet
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice.
The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
with each slice.
Figure 2-3. Slice Diagram
www.DataSheet4U.com
To / From
Different slice / PFU Fast Carry In (FCI)
A1
B1
C1
D1
From
Routing
M1
M0
A0
B0
C0
D0
CO
LUT4 &
CARRY
F
SUM
CI
Slice
D
FF/
Latch
CO
LUT
Expansion
Mux
LUT4 &
CARRY
CI
F
SUM
OFX0
D
FF/
Latch
OFX1
F1
Q1
To
Routing
OFX0
F0
Q0
Control Signals
selected and
inverted per
slice in routing
CE
CLK
LSR
Note: Some interslice signals
are not shown.
To / From
Different slice / PFU Fast Carry Out (FCO)
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LatticeXP Family

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Lattice Semiconductor
Architecture
LatticeXP Family Data Sheet
Table 2-1. Slice Signal Descriptions
Function
Type
Signal Names
Description
Input
Data signal
A0, B0, C0, D0 Inputs to LUT4
Input
Data signal
A1, B1, C1, D1 Inputs to LUT4
Input
Multi-purpose
M0 Multipurpose Input
Input
Multi-purpose
M1 Multipurpose Input
Input
Control signal
CE Clock Enable
Input
Control signal
LSR Local Set/Reset
Input
Control signal
CLK System Clock
Input
Inter-PFU signal
FCIN
Fast Carry In1
www.DataSheet4U.com Output
Output
Data signals
Data signals
F0, F1
Q0, Q1
LUT4 output register bypass signals
Register Outputs
Output
Data signals
OFX0
Output of a LUT5 MUX
Output
Data signals
OFX1
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
Output Inter-PFU signal
FCO
For the right most PFU the fast carry chain output1
1. See Figure 2-2 for connection details.
2. Requires two PFUs.
Modes of Operation
Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of
all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.
Table 2-2. Slice Modes
PFU Slice
PFF Slice
Logic
LUT 4x2 or LUT 5x1
LUT 4x2 or LUT 5x1
Ripple
2-bit Arithmetic Unit
2-bit Arithmetic Unit
RAM
SP 16x2
N/A
ROM
ROM 16x1 x 2
ROM 16x1 x 2
Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables. A LUT4
can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this
lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup
tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices.
Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the fol-
lowing functions can be implemented by each Slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/Subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Ripple mode multiplier building block
• Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating Slices.
RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory.
Through the combination of LUTs and Slices, a variety of different memories can be constructed.
2-4


LFXP (Lattice Semiconductor)
LatticeXP Family

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Lattice Semiconductor
Architecture
LatticeXP Family Data Sheet
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of Slices required to implement different distributed RAM primitives. Figure 2-4 shows the dis-
tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions
as the read-write port. The other companion Slice supports the read-only port. For more information on RAM mode
in LatticeXP devices, please see details of additional technical documentation at the end of this data sheet.
Table 2-3. Number of Slices Required for Implementing Distributed RAM
SPR16x2 DPR16x2
Number of Slices
12
Note: SPR = Single Port RAM, DPR = Dual Port RAM
www.DataSheet4U.com
Figure 2-4. Distributed Memory Primitives
SPR16x2
DPR16x2
AD0
AD1
AD2
AD3
DI0
DI1
WRE
CK
DO0
DO1
WAD0
WAD1
WAD2
WAD3
DI0
DI1
WCK
WRE
RAD0
RAD1
RAD2
RAD3
RDO0
RDO1
WDO0
WDO1
ROM16x1
AD0
AD1
AD2 DO0
AD3
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
2-5


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LatticeXP Family

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Lattice Semiconductor
Architecture
LatticeXP Family Data Sheet
Table 2-4. PFU Modes of Operation
Logic
Ripple
LUT 4x8 or
MUX 2x1 x 8
2-bit Add x 4
LUT 5x4 or
MUX 4x1 x 4
2-bit Sub x 4
LUT 6x 2 or
MUX 8x1 x 2
2-bit Counter x 4
LUT 7x1 or
MUX 16x1 x 1
2-bit Comp x 4
1. These modes are not available in PFF blocks
RAM1
SPR16x2 x 4
DPR16x2 x 2
SPR16x4 x 2
DPR16x4 x 1
SPR16x8 x 1
ROM
ROM16x1 x 8
ROM16x2 x 4
ROM16x4 x 2
ROM16x8 x 1
www.DataSheeRt4Uo.ucotming
There are many resources provided in the LatticeXP devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal directions. The
x2 and x6 resources are buffered allowing both short and long connections routing between PFUs.
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock Distribution Network
The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed
through the chip via a clock distribution system.
Primary Clock Sources
LatticeXP devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing. Lat-
ticeXP devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There are four
dedicated clock inputs, one on each side of the device. Figure 2-5 shows the 20 primary clock sources.
2-6


LFXP (Lattice Semiconductor)
LatticeXP Family

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Lattice Semiconductor
Figure 2-5. Primary Clock Sources
From Routing
Architecture
LatticeXP Family Data Sheet
Clock Input
From Routing
PLL Input
PLL
PLL PLL Input
www.DataSheet4U.com
Clock Input
20 Primary Clock Sources
To Quadrant Clock Selection
Clock Input
PLL Input
PLL
PLL PLL Input
From Routing
Clock Input
Note: Smaller devices have two PLLs.
From Routing
Secondary Clock Sources
LatticeXP devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at
every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary
clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-6.
2-7


LFXP (Lattice Semiconductor)
LatticeXP Family

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Lattice Semiconductor
Figure 2-6. Secondary Clock Sources
From
Routing
From
Routing
Clock
Input
Architecture
LatticeXP Family Data Sheet
From
Routing
From
Routing
www.DataSheet4U.com
From Routing
From Routing
Clock Input
From Routing
From Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From Routing
From Routing
Clock Input
From Routing
From Routing
From
Routing
From
Routing
Clock
Input
From
Routing
From
Routing
Clock Routing
The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-
work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this
clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-
8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-
9.
Figure 2-7. Per Quadrant Primary Clock Selection
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1
DCS2
DCS2
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
1. Smaller devices have fewer PLL related lines.
2. Dynamic clock select.
2-8


LFXP (Lattice Semiconductor)
LatticeXP Family

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Figure 2-8. Per Quadrant Secondary Clock Selection
Architecture
LatticeXP Family Data Sheet
20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
www.DataSheet4U.com
4 Secondary Clocks per Quadrant
Figure 2-9. Slice Clock Selection
Primary Clock
Secondary Clock
Routing
GND
Clock to Each Slice
sysCLOCK Phase Locked Loops (PLLs)
The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
nals to the feedback divider: from CLKOP (PLL internal), from clock net (CLKOP or CLKOS) or from a user clock
(PIN or logic). There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-10
shows the sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block
allows the user to adjust the phase and duty cycle of the CLKOS output.
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider
is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post
scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-
quency range. The secondary divider is used to derive lower frequency outputs.
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Lattice Semiconductor
Architecture
LatticeXP Family Data Sheet
Figure 2-10. PLL Diagram
Dynamic Delay Adjustment
RST
CLKI
(from routing or
external pin)
Input Clock
Divider
(CLKI)
Delay
Adjust
Voltage
ConVtCroOlled
Oscillator
Post Scalar
Divider
(CLKOP)
www.DataSheet4U.com
CLKFB
from CLKOP
(PLL internal),
from clock net
(CLKOP) or
from a user
clock (PIN or logic)
Feedback
Divider
(CLKFB)
Phase/Duty
Select
LOCK
CLKOS
Secondary
Clock
Divider
(CLKOK)
CLKOP
CLKOK
Figure 2-11 shows the available macros for the PLL. Table 2-11 provides signal description of the PLL Block.
Figure 2-11. PLL Primitive
CLKI
CLKFB
EPLLB
CLKOP
LOCK
RST
CLKI
CLKFB
DDA MODE
DDAIZR
DDAILAG
DDAIDEL[2:0]
EHXPLLB
CLKOP
CLKOS
CLKOK
LOCK
DDAOZR
DDAOLAG
DDAODEL[2:0]
Table 2-5. PLL Signal Descriptions
Signal
CLKI
CLKFB
RST
CLKOS
CLKOP
CLKOK
LOCK
DDAMODE
DDAIZR
DDAILAG
DDAIDEL[2:0]
DDAOZR
DDAOLAG
DDAODEL[2:0]
I/O Description
I Clock input from external pin or routing
I PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
I “1” to reset input clock divider
O PLL output clock to clock tree (phase shifted/duty cycle changed)
O PLL output clock to clock tree (No phase shift)
O PLL output to clock tree through secondary clock divider
O “1” indicates PLL LOCK to CLKI
I Dynamic Delay Enable. “1” Pin control (dynamic), “0”: Fuse Control (static)
I Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
I Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead
I Dynamic Delay Input
O Dynamic Delay Zero Output
O Dynamic Delay Lag/Lead Output
O Dynamic Delay Output
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LatticeXP Family

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Lattice Semiconductor
Architecture
LatticeXP Family Data Sheet
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-12 illustrates
the DCS Block Macro.
Figure 2-12. DCS Block Primitive
www.DataSheet4U.com
CLK0
CLK1
SEL
DCS
DCSOUT
Figure 2-13 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information on the DCS, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-13. DCS Waveforms
CLK0
CLK1
SEL
DCSOUT
sysMEM Memory
The LatticeXP family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of a
9-Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6.
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LatticeXP Family

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Lattice Semiconductor
Architecture
LatticeXP Family Data Sheet
Table 2-6. sysMEM Block Configurations
Memory Mode
Single Port
www.DataSheet4U.com
True Dual Port
Pseudo Dual Port
Configurations
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual and Pseudo-Dual Port Modes
Figure 2-14 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM
modes the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the output.
2-12


LFXP (Lattice Semiconductor)
LatticeXP Family

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Lattice Semiconductor
Architecture
LatticeXP Family Data Sheet
Figure 2-14. sysMEM Memory Primitives
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AD[12:0]
DI[35:0]
CLK
CE
RST
WE
CS[2:0]
EBR
ADA[12:0]
DIA[17:0]
CLKA
DO[35:0]
CEA
RSTA
WEA
CSA[2:0]
DOA[17:0]
EBR
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
Single Port RAM
True Dual Port RAM
AD[12:0]
CLK
CE
RST
CS[2:0]
EBR
ADW[12:0]
DI[35:0]
CLKW
DO[35:0] CEW
WE
RST
CS[2:0]
EBR
ADR[12:0]
DO[35:0]
CER
CLKR
ROM
Pseudo-Dual Port RAM
The EBR memory supports three forms of write behavior for single port or dual port operation:
1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through - a copy of the input data appears at the output of the same port during a write cycle. This
mode is supported for all data widths.
3. Read-Before-Write – when new data is being written, the old content of the address appears at the output.
This mode is supported for x9, x18 and x36 data widths.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respec-
tively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both
ports are as shown in Figure 2-15.
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Figure 2-15. Memory Core Reset
Architecture
LatticeXP Family Data Sheet
Memory Core
QD SET
LCLR
Port A[17:0]
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RSTA
RSTB
GSRN
Output Data
Latches
QD SET
LCLR
Port B[17:0]
Programmable Disable
For further information on sysMEM EBR block, see the details of additional technical documentation at the end of
this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-16. The GSR input to the
EBR is always asynchronous.
Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram
Reset
Clock
Clock
Enable
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
Programmable I/O Cells (PICs)
Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as
shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO
buffer, and receives input from the buffer.
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Figure 2-17. PIC Diagram
TD
OPOS1
ONEG1
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OPOS0
ONEG0
INCK
INDD
INFF
IPOS0
IPOS1
CLK
CE
LSR
GSRN
DQS
DDRCLKPOL
Control
Muxes
CLKO
CEO
LSR
GSR
CLKI
CEI
Architecture
LatticeXP Family Data Sheet
PIO A
TD
D0
D1
DDRCLK
IOLT0
Tristate DO
Register Block
(2 Flip Flops)
D0
D1
DDRCLK
IOLD0
Output
Register Block
(2 Flip Flops)
INCK
INDD
INFF
IPOS0
IPOS1
DI
Input
Register Block
(5 Flip Flops)
PADA
"T"
sysIO
Buffer
PIO B
PADB “C”
In the LatticeXP family, seven PIOs or four (3.5) PICs are grouped together to provide two LVDS differential pairs,
one PIC pair and one single I/O, as shown in Figure 2-18.
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”). The PAD Labels “T” and
“C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device can be configured as
LVDS transmit/receive pairs.
One of every 14 PIOs (a group of 8 PICs) contains a delay element to facilitate the generation of DQS signals as
shown in Figure 2-19. The DQS signal feeds the DQS bus which spans the set of 13 PIOs (8 PICs). The DQS sig-
nal from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is
designed for memories that support one DQS strobe per eight bits of data.
The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-
tional detail is provided in the Signal Descriptions table in this data sheet.
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Figure 2-18. Group of Seven PIOs
Four PICs
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Figure 2-19. DQS Routing
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
Architecture
LatticeXP Family Data Sheet
PADA “T”
LVDS Pair
PADB “C”
PADA “T”
PADB “C”
PADA “T”
LVDS Pair
PADB “C”
PADA “T”
One PIO Pair
PADA “T”
LVDS Pair
PADB “C”
PADA “T”
PADB “C”
PADA “T”
LVDS Pair
PADB “C”
PADA “T”
DQS
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PADB “C”
sysIO
Buffer
Delay
Assigned DQS Pin
PADA “T”
LVDS Pair
PADB “C”
PADA “T”
PADB “C”
PADA “T”
LVDS Pair
PADB “C”
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-20 shows the diagram of the input register block.
Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
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Lattice Semiconductor
Architecture
LatticeXP Family Data Sheet
in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first
passes through an optional delay block. This delay, if selected, ensures no positive input-register hold-time require-
ment when using a global clock.
The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the
registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used
to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.
These two data streams are synchronized with the system clock before entering the core. Further discussion on
this topic is in the DDR Memory section of this data sheet.
Figure 2-21 shows the input register waveforms for DDR operation and Figure 2-22 shows the design tool primi-
tives. The SDR/SYNC registers have reset and clock enable available.
www.DataSheeTt4hUe.cosmignal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to the system clock domain. For further discussion of this topic,
see the DDR memory section of this data sheet.
Figure 2-20. Input Register Diagram
DI
(From sysIO
Buffer)
Delay Block
INCK
INDD
Fixed Delay
DDR Registers
DQ
D-Type
SDR & Sync
Registers
D0
DQ
D-Type
/LATCH
To Routing
IPOS0
DQS Delayed
(From DQS
Bus)
CLK0
(From Routing)
DDRCLKPOL
(From DDR Polarity
Control Bus)
D2
D Q D1 D Q
D-Type
D-Type
DQ
D-Type
/LATCH
IPOS1
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Figure 2-21. Input Register DDR Waveforms
DI
(In DDR Mode)
AB
DQS
DQS
Delayed
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D0
D2
Architecture
LatticeXP Family Data Sheet
C DE
F
BD
AC
Figure 2-22. INDDRXB Primitive
D
ECLK
LSR
SCLK
CE
DDRCLKPOL
IDDRXB
QA
QB
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-23 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-
type or as a latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-24 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
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Figure 2-23. Output Register Block
Architecture
LatticeXP Family Data Sheet
ONEG0
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From
Routing
OPOS0
CLK1
DQ
D-Type
/LATCH
DQ
LATCH
LE*
OUTDDN
0 DO
0
1
1 To sysIO
Buffer
*Latch is transparent when input is low.
Figure 2-24. ODDRXB Primitive
Programmed
Control
DA
DB
CLK
LSR
ODDRXB
Q
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-25 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
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Figure 2-25. Tristate Register Block
Architecture
LatticeXP Family Data Sheet
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TD
ONEG1
From
Routing
OPOS1
CLK1
DQ
D-Type
/LATCH
DQ
LATCH
LE*
OUTDDN
0 TO
0
1
1 To sysIO
Buffer
*Latch is transparent when input is low.
Programmed
Control
Control Logic Block
The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is
selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from
the programmable DQS pin. The clock can optionally be inverted.
The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate
signal is passed through this block.
DDR Memory Support
Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input
(for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the LatticeXP
devices provide this capability. In addition to these registers, the LatticeXP devices contain two elements to simplify
the design of input structures for read operations: the DQS delay block and polarity control logic.
DLL Calibrated DQS Delay Block
Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment, however in DDR memories the clock
(referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS rout-
ing resource. The DQS signal also feeds the polarity control logic which controls the polarity of the clock to the sync
registers in the input register blocks. Figures 2-26 and 2-27 show how the polarity control logic are routed to the
PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
(6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of
the device as shown in Figure 2-27. The DLL loop is compensated for temperature, voltage and process variations
by the system clock and feedback loop.
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Figure 2-26. DQS Local Bus
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Delay
Control
Bus
Polarity
Control
Bus
DQS
Bus
DQS
GSR
CLKI
CEI
DQS
PIO
Input
Register Block
( 5 Flip Flops)
To Sync.
Reg.
To DDR
Reg.
Architecture
LatticeXP Family Data Sheet
sysIO
Buffer
DDR
Datain
PAD
DI
DQS
PIO
Polarity Control
Logic
DQSDEL
Calibration Bus
from DLL
sysIO
Buffer
DQS
Strobe
PAD
DI
Figure 2-27. DLL Calibration Bus and DQS/DQS Transition Distribution
Delay Control Bus
Polarity Control Signal Bus
DQS Signal Bus
DLL
DLL
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Architecture
LatticeXP Family Data Sheet
Polarity Control Logic
In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the
internal system Clock (during the READ cycle) is unknown.
The LatticeXP family contains dedicated circuits to transfer data between these domains. To prevent setup and
hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is
used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of the each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
sysIOwww.DataSheet4U.com Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in eight groups referred to as Banks. The sysIO buffers allow users to implement the wide
variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LatticeXP devices have eight sysIO buffer banks; each is capable of supporting multiple I/O standards. Each sysIO
bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and VREF2 resources allowing each
bank to be completely independent from each other. Figure 2-28 shows the eight banks and their associated sup-
plies.
In the LatticeXP devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-X) are
powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as a fixed threshold input
independent of VCCIO. In addition to the bank VCCIO supplies, the LatticeXP devices have a VCC core logic power sup-
ply, and a VCCAUX supply that power all differential and referenced buffers.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-
enced input buffers. In the LatticeXP devices, a dedicated pin in a bank can be configured to be a reference voltage
supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages.
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Figure 2-28. LatticeXP Banks
Architecture
LatticeXP Family Data Sheet
VCCIO7
VREF1(7)
VREF2(7)
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GND
VCCIO6
V REF1(6)
V REF2(6)
GND
1
1
Bank 0 N
1 Bank 1 N
1
MM
11
MM
Bank 5
Bank 4
1 N1 N
VCCIO2
VREF1(2)
VREF2(2)
GND
VCCIO3
VREF1(3)
VREF2(3)
GND
Note: N and M are the maximum number of I/Os per bank.
LatticeXP devices contain two types of sysIO buffer pairs.
1. Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only)
The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be
configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have PCI clamps. Note that the PCI clamp is enabled after VCC,
VCCAUX and VCCIO are at valid operating levels and the device has been configured.
2. Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs)
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be configured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Select I/Os in the left and right banks have LVDS differential output drivers. Refer to the Logic Signal Connec-
tions tables for more information.
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Architecture
LatticeXP Family Data Sheet
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels.
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the
I/O banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state
with a weak pull-up to VCCIO. The I/O pins will not take on the user configuration until VCC, VCCAUX and VCCIO
have reached satisfactory levels at which time the I/Os will take on the user-configured settings.
The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buff-
ers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered up before or
together with the VCC and VCCAUX supplies.
www.DataSheeSt4uUp.cpoomrted Standards
The LatticeXP sysIO buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2, 1.5,
1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for
drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other sin-
gle-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, BLVDS,
LVPECL, differential SSTL and differential HSTL. Tables 2-7 and 2-8 show the I/O standards (together with their
supply and reference voltages) supported by the LatticeXP devices. For further information on utilizing the sysIO
buffer to support a variety of standards please see the details of additional technical documentation at the end of
this data sheet.
Table 2-7. Supported Input Standards
Input Standard
Single Ended Interfaces
VREF (Nom.)
LVTTL
LVCMOS332
LVCMOS252
LVCMOS18
LVCMOS15
LVCMOS122
PCI —
HSTL18 Class I, II
0.9
HSTL18 Class III
1.08
HSTL15 Class I
0.75
HSTL15 Class III
0.9
SSTL3 Class I, II
1.5
SSTL2 Class I, II
1.25
SSTL18 Class I
0.9
Differential Interfaces
Differential SSTL18 Class I
Differential SSTL2 Class I, II
Differential SSTL3 Class I, II
Differential HSTL15 Class I, III
Differential HSTL18 Class I, II, III
LVDS, LVPECL
BLVDS
1. When not specified VCCIO can be set anywhere in the valid operating range.
2. JTAG inputs do not have a fixed threshold option and always follow VCCJ.
VCCIO1 (Nom.)
1.8
1.5
3.3
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Architecture
LatticeXP Family Data Sheet
Table 2-8. Supported Output Standards
Output Standard
Single-ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33, Open Drain
www.DataSheet4U.comLVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
HSTL18 Class I, II, III
HSTL15 Class I, III
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I
Differential Interfaces
Differential SSTL3, Class I, II
Differential SSTL2, Class I, II
Differential SSTL18, Class I
Differential HSTL18, Class I, II, III
Differential HSTL15, Class I, III
LVDS
BLVDS1
LVPECL1
1. Emulated with external resistors.
Drive
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA
4mA, 8mA
2mA, 6mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA
4mA, 8mA
2mA. 6mA
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VCCIO (Nom.)
3.3
3.3
2.5
1.8
1.5
1.2
3.3
1.8
1.5
3.3
2.5
1.8
3.3
2.5
1.8
1.8
1.5
2.5
2.5
3.3
Hot Socketing
The LatticeXP devices have been carefully designed to ensure predictable behavior during power-up and power-
down. Power supplies can be sequenced in any order. During power up and power-down sequences, the I/Os
remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage
into I/O pins is controlled to within specified limits, which allows easy integration with the rest of the system.
These capabilities make the LatticeXP ideal for many multiple power supply and hot-swap applications.
Sleep Mode
The LatticeXP “C” devices (VCC = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced by up
to three orders of magnitude during periods of system inactivity. Entry and exit to Sleep Mode is controlled by the
SLEEPN pin.
During Sleep Mode, the FPGA logic is non-operational, registers and EBR contents are not maintained and I/Os
are tri-stated. Do not enter Sleep Mode during device programming or configuration operation. In Sleep Mode,
power supplies can be maintained in their normal operating range, eliminating the need for external switching of
power supplies. Table 2-9 compares the characteristics of Normal, Off and Sleep Modes.
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Architecture
LatticeXP Family Data Sheet
Table 2-9. Characteristics of Normal, Off and Sleep Modes
Characteristic
Normal
Off
Sleep
SLEEPN Pin
High
Low
Static Icc
Typical <100mA
0
Typical <100uA
I/O Leakage
<10µA
<1mA
<10µA
Power Supplies VCC/VCCIO/VCCAUX
Normal Range
Off
Normal Range
Logic Operation
User Defined
Non Operational
Non operational
I/O Operation
User Defined
Tri-state
Tri-state
JTAG and Programming circuitry
Operational
Non-operational
Non-operational
EBR Contents and Registers
Maintained
Non-maintained
Non-maintained
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SLEEPN Pin Characteristics
The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the
device. This pin also has a weak pull-up typically in the order of 10µA along with a Schmidt trigger and glitch filter to
prevent false triggering. An external pull-up to VCC is recommended when Sleep Mode is not used to ensure the
device stays in normal operation mode. Typically the device enters Sleep Mode several hundred ns after SLEEPN
is held at a valid low and restarts normal operation as specified in the Sleep Mode Timing table. The AC and DC
specifications portion of this data sheet show a detailed timing diagram.
Configuration and Testing
The following section describes the configuration and testing features of the LatticeXP family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeXP devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can
operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeXP devices contain two possible ports that can be used for device configuration and programming. The
test access port (TAP), which supports serial configuration, and the sysCONFIG port that supports both byte-wide
and serial configuration.
The non-volatile memory in the LatticeXP can be configured in three different modes:
• In sysCONFIG mode via the sysCONFIG port. Note this can also be done in background mode.
• In 1532 mode via the 1149.1 port.
• In background mode via the 1149.1 port. This allows the device to be operated while reprogramming takes
place.
The SRAM configuration memory can be configured in three different ways:
• At power-up via the on-chip non-volatile memory.
• In 1532 mode via the 1149.1 port SRAM direct configuration.
• In sysCONFIG mode via the sysCONFIG port SRAM direct configuration.
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LatticeXP Family

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Lattice Semiconductor
Architecture
LatticeXP Family Data Sheet
Figure 2-29 provides a pictorial representation of the different programming ports and modes available in the Lat-
ticeXP devices.
On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial
mode can be activated any time after power-up by sending the appropriate command through the TAP port.
Leave Alone I/O
When using 1532 mode for non-volatile memory programming, users may specify I/Os as high, low, tristated or
held at current value. This provides excellent flexibility for implementing systems where reprogramming occurs on-
the-fly.
TransFR (Transparent Field Reconfiguration)
TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting
www.DataSheest4yUs.tceomm operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Inter-
ruption During Configuration Using TransFR Technology, for details.
Security
The LatticeXP devices contain security bits that, when set, prevent the readback of the SRAM configuration and
non-volatile memory spaces. Once set, the only way to clear security bits is to erase the memory space.
For more information on device configuration, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-29. ispXP Block Diagram
ISP 1149.1 TAP Port
Port
sysCONFIG Peripherial Port
BACKGND
1532
sysCONFIG
Mode
Program in seconds
Memory Space
Memory Space
Power-up
Refresh
Download in microseconds
Configure in milliseconds
SRAM
Memory Space
Internal Logic Analyzer Capability (ispTRACY)
All LatticeXP devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabil-
ities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace mem-
ory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile
time.
For more information on ispTRACY, please see information regarding additional technical documentation at the
end of this data sheet.
Oscillator
Every LatticeXP device has an internal CMOS oscillator which is used to derive a master serial clock for configura-
tion. The oscillator and the master serial clock run continuously in the configuration mode. The default value of the
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