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v4.0.1
ACT2 Family FPGAs
Features
Up to 8000 Gate Array Gates
(20,000 PLD equivalent gates)
Replaces up to 200 TTL Packages
Replaces up to eighty 20-Pin PAL® Packages
Design Library with over 500 Macro Functions
Single-Module Sequential Functions
Wide-Input Combinatorial Functions
Up to 1232 Programmable Logic Modules
Up to 998 Flip-Flops
Datapath Performance at 105 MHz
16-Bit Accumulator Performance to 39 MHz
Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
Two High-Speed, Low-Skew Clock Networks
I/O Drive to 10 mA
Nonvolatile, User Programmable
Logic Fully Tested Prior to Shipment
1.0-micron CMOS Technology
Product Family Profile
Device
A1225A
A1240A
A1280A
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
2,500
6,250
63
25
4,000
10,000
100
40
8,000
20,000
200
80
Logic Modules
S-Modules
C-Modules
451 684 1,232
231 348 624
220 336 608
Flip-Flops (maximum)
382 568 998
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
36
15
250,000
36
15
400,000
36
15
750,000
User I/Os (maximum)
Packages1
Performance2
16-Bit Prescaled Counters
16-Bit Loadable Counters
16-Bit Accumulators
83
100 CPGA
100 PQFP
100 VQFP
84 PLCC
105 MHz
70 MHz
39 MHz
104
132 CPGA
144 PQFP
176 TQFP
84 PLCC
100 MHz
69 MHz
38 MHz
140
176 CPGA
160 PQFP
176 TQFP
84 PLCC
172 CQFP
85 MHz
67 MHz
36 MHz
Notes:
1. See the “Product Plan” on page 3 for package availability.
2. Performance is based on ‘–2’ speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2,
dated 3-28-93, any analysis is not endorsed by PREP.
December 2000
© 2000 Actel Corporation
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ACT2 Family FPGAs
Description
The ACT2 family represents Actels second generation of
field programmable gate arrays (FPGAs). The ACT 2 family
presents a two-module architecture, consisting of C-modules
and S-modules. These modules are optimized for both
combinatorial and sequential designs. Based on Actels
patented channeled array architecture, the ACT 2 family
provides significant enhancements to gate density and
performance while maintaining downward compatibility
with the ACT 1 design environment and upward
compatibility with the ACT 3 design environment. The
devices are implemented in silicon gate, 1.0-µm, two-level
metal CMOS, and employ Actels PLICE® antifuse
technology. This revolutionary architecture offers gate array
design flexibility, high performance, and fast
time-to-production with user programming. The ACT 2
family is supported by the Designer and Designer Advantage
Systems, which offers automatic pin assignment, validation
of electrical and design rules, automatic placement and
routing, timing analysis, user programming, and diagnostic
probe capabilities. The systems are supported on the
following platforms: 386/486PC, Sun, and HP
workstations. The systems provide CAE interfaces to the
following design environments: Cadence, Viewlogic®,
Mentor Graphics®, and OrCAD.
Ordering Information
A1280 A – 1
PG 176
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
CQ = Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Die Revision
A = 1.0-µm CMOS process
Part Number
A1225 = 2500 Gates
A1240 = 4000 Gates
A1280 = 8000 Gates
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Product Plan
Speed Grade*
Application
Std –1
2
CI
MB
A1225A Device
100-pin Ceramic Pin Grid Array (PG)
✔✔✔
100-pin Plastic Quad Flat Pack (PQ)
✔✔✔
100-pin Very Thin (1.0 mm) Quad Flat Pack (VQ) ✔ ✔ ✔
84-pin Plastic Leaded Chip Carrier (PL)
✔✔✔
A1240A Device
———
✔ ✔ ——
———
✔ ✔ ——
132-pin Ceramic Pin Grid Array (PG)
✔✔✔
176-pin Thin (1.4 mm) Quad Flat Pack (TQ)
144-pin Plastic Quad Flat Pack (PQ)
✔✔✔
84-pin Plastic Leaded Chip Carrier (PL)
✔✔✔
A1280A Device
✔ ✔
———
✔ ✔ ——
✔ ✔ ——
176-pin Ceramic Pin Grid Array (PG)
✔✔✔
176-pin Thin (1.4 mm) Quad Flat Pack (TQ)
160-pin Plastic Quad Flat Pack (PQ)
✔✔✔
172-pin Ceramic Quad Flat Pack (CQ)
✔✔✔
Contact your Actel sales representatives for product availability.
Applications: C = Commercial Availability: = Available *Speed Grade:
I = Industrial
P = Planned
M = Military
= Not Planned
B = MIL-STD-883
✔ ✔
———
✔ ✔ ——
✔ ✔
1 = Approx. 15% faster than Standard
2 = Approx. 25% faster than Standard
Device Resources
User I/Os
CPGA
PQFP
PLCC CQFP TQFP VQFP
Device Logic
Series Modules Gates 176-pin 132-pin 100-pin 160-pin 144-pin 100-pin 84-pin 172-pin 176-pin 100-pin
A1225A 451 2500 — — 83 — — 83
A1240A 684 4000 104
104
A1280A 1232 8000 140
125
72 — —
72 104
72 140 140
83
.
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ACT2 Family FPGAs
Operating Conditions
Absolute Maximum Ratings1
Free air temperature range
Symbol
Parameter
Limits
Units
VCC DC Supply Voltage
VI Input Voltage
VO Output Voltage
IIO
I/O Source/Sink
Current2
0.5 to +7.0
0.5 to VCC +0.5
0.5 to VCC +0.5
±20
V
V
V
mA
TSTG Storage Temperature 65 to +150
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum
Ratingsmay cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be
operated outside the Recommended Operating Conditions.
2. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than VCC + 0.5 V or less than GND 0.5 V, the internal
protection diode will be forward biased and can draw excessive
current.
Recommended Operating Conditions
Commercia Industria
Parameter
l
l Military Units
Temperature
Range1
0 to +70
40 to
+85
55 to
+125
°C
Power
Supply
±5 ±10 ±10 %VCC
Tolerance
Note:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
Electrical Specifications
Commercial
Industrial
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
VOH1
(IOH = 10 mA) 2
(IOH = 6 mA)
VOL1
(IOH = 4 mA)
(IOL = 10 mA) 2
(IOL = 6 mA)
VIL
VIH
Input Transition Time tR, tF2
CIO I/O Capacitance2, 3
Standby Current, ICC4 (typical = 1 mA)
Leakage Current5
2.4
3.84
3.7 3.7
0.5
0.33 0.40 0.40
0.3 0.8 0.3 0.8 0.3 0.8
2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3
500 500 500
10 10 10
2 10 20
10 10 10 10 10 10
Notes:
1. Only one output tested at a time. VCC = min.
2. Not tested, for information only.
3. Includes worst-case 176 CPGA package capacitance. VOUT = 0 V, f = 1 MHz.
4. All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal operation.
5. VOUT , VIN = VCC or GND.
Units
V
V
V
V
V
V
V
ns
pF
mA
µA
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w w w . ADC Tat 2aF aSmhil ye FePGt A4s U . c o m
Package Thermal Characteristics
The device junction to case thermal characteristic is θjc,
and the junction to ambient air characteristic is θja. The
thermal characteristics for θja are shown with two different
air flow rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a PQFP 160-pin package at
commercial temperature is as follows:
M------a--x----.---j-u---n---c---t-i--o---n-----t-e---m-----p---.---(--°--C----)----–----M-----a---x---.---c---o---m----m-----e---r--c--i--a---l----t--e---m-----p--.
θja (°C/W)
=
1---5----0--°---C-----–-----7---0---°--C---
33°C/W
=
2.4 W
Package Type
Pin Count
θjc
θja
Still Air
θja
300 ft/min
Ceramic Pin Grid Array
100 5
132 5
176 8
35 17
30 15
23 12
Ceramic Quad Flat Pack
172 8
25 15
Plastic Quad Flat Pack1
100 13 48 40
144 15 40 32
160 15 38 30
Plastic Leaded Chip Carrier2
84 12 37 28
Very Thin Quad Flat Pack3
100 12 43 35
Thin Quad Flat Pack4
176 15 32 25
Notes:(Maximum Power in Still Air)
1. Maximum Power Dissipation for PQFP packages are 1.9 Watts (100-pin), 2.3 Watts (144-pin), and 2.4 Watts (160-pin).
2. Maximum Power Dissipation for PLCC packages is 2.7 Watts.
3. Maximum Power Dissipation for VQFP packages is 2.3 Watts.
4. Maximum Power Dissipation for TQFP packages is 3.1 Watts.
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Power Dissipation
P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N +
IOH * (VCC VOH) * M
Where:
ICC standby is the current flowing when no inputs or outputs
are changing.
ICC active is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to VOL.
M equals the number of outputs driving TTL loads to VOH.
An accurate determination of N and M is problematical
because their values depend on the family type, design
details, and on the system I/O. The power can be divided
into two components: static and active.
Static Power Component
Actel FPGAs have small static power components that
result in lower power dissipation than PALs or PLDs. By
integrating multiple PALs/PLDs into one FPGA, an even
greater reduction in board-level power dissipation can be
achieved.
The power due to standby current is typically a small
component of the overall power. Standby power is
calculated below for commercial, worst case conditions.
ICC
2 mA
VCC
5.25V
Power
10.5 mW
The static power dissipated by TTL loads depends on the
number of outputs driving high or low and the DC load
current. Again, this value is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with
all outputs driving low, and 140 mW with all outputs driving
high. The actual dissipation will average somewhere
between as I/Os switch states with time.
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
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ACT2 Family FPGAs
and load device inputs. An additional component of the
active power dissipation is the totem-pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
Power (µW) = CEQ * VCC2 * F
(1)
Where:
CEQ is the equivalent capacitance expressed in pF.
VCC is the power supply in volts.
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring ICC
active at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over
a range of frequencies at a fixed value of VCC. Equivalent
capacitance is frequency independent so that the results
may be used over a wide range of operating conditions.
Equivalent capacitance values are shown below.
CEQ Values for Actel FPGAs
Modules (CEQM)
5.8
Input Buffers (CEQI)
12.9
Output Buffers (CEQO)
23.8
Routed Array Clock Buffer Loads (CEQCR)
3.9
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic
must be known. Equation 2 shows a piece-wise linear
summation over all components.
Power = VCC2 * [(m * CEQM* fm)modules +(n * CEQI* fn)inputs
+ (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR *
fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR *
fq2)routed_Clk2
+ (r2 * fq2)routed_Clk2]
(2)
Where:
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
p = Number of output buffers switching at fp
q1 = Number of clock loads on the first routed array
clock
q2 = Number of clock loads on the second routed
array clock
r1 = Fixed capacitance due to first routed array
clock
r2 = Fixed capacitance due to second routed array
clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in
pF
CL = Output lead capacitance in pF
fm = Average logic module switching rate in MHz
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
fq1 = Average first routed array clock rate in MHz
fq2 = Average second routed array clock rate in MHz
Fixed Capacitance Values for Actel FPGAs
(pF)
r1 r2
Device Type
routed_Clk1 routed_Clk2
A1225A
A1240A
A1280A
106
134
168
106.0
134.2
167.8
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to
the circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
Logic Modules (m)
80% of modules
Inputs switching (n)
# inputs/4
Outputs switching (p)
# outputs/4
First routed array clock loads (q1)
40%of
sequential
modules
Second routed array clock loads (q2)
40%of
sequential
modules
Load capacitance (CL)
35 pF
Average logic module switching rate (fm) F/10
Average input switching rate (fn)
F/5
Average output switching rate (fp)
F/10
Average first routed array clock rate (fq1) F
Average second routed array clock rate F/2
(fq2)
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ACT 2 Timing Model*
Input Delays
Internal Delays
I/O Module
tINYL = 2.6 ns
Combinatorial
Logic Module
tIRD2 = 4.8 ns
Predicted
Routing
Delays
Output Delays
I/O Module
DQ
G
tINH = 2.0 ns
tINSU = 4.0 ns
tINGL = 4.7 ns
ARRAY
CLOCKS
tCKH = 11.8 ns
FMAX = 100 MHz
FO = 256
tPD = 3.8 ns
tRD1 = 1.4 ns
tRD2 = 1.7 ns
tRD4 = 3.1 ns
tRD8 = 4.7 ns
Sequential
Logic Module
tDLH = 8.0 ns
I/O Module
tDLH = 8.0 ns
Combin-
atorial
Logic
included
in tSUD
tSUD = 0.4 ns
tHD = 0.0 ns
DQ
tRD1 = 1.4 ns
DQ
G
tENHZ = 7.1 ns
tCO = 3.8 ns
tOUTH = 0.0 ns
tOUTSU = 0.4 ns
tGLH = 9.0 ns
*Values shown for A1240A-2 at worst-case commercial conditions.
Input Module Predicted Routing Delay
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ACT2 Family FPGAs
Parameter Measurement
Output Buffer Delays
E
D
TRIBUFF
PAD To AC test loads (shown below)
In
PAD
VOL
VCC
50% 50%
VOH
1.5 V
GND
1.5 V
tDLH
tDHL
E
PAD
VCC
50% 50%
VCC
1.5 V
VOL
GND
10%
tENZL
tENLZ
E
PAD
GND
VCC
50% 50%
VOH
1.5 V
GND
90%
tENZH
tENHZ
AC Test Loads
Load 1
(Used to measure propagation delay)
To the output under test
Load 2
(Used to measure rising/falling edges)
VCC GND
50 pF
To the output under test
R to VCC for tPLZ/tPZL
R to GND for tPHZ/tPZH
R = 1 k
50 pF
Input Buffer Delays
PAD
INBUF
Y
PAD
Y
GND
3V
1.5 V 1.5 V
VCC
50%
0V
50%
tINYH
tINYL
Module Delays
S
AY
B
S, A or B
Y
GND
Y
VCC
50% 50%
VCC
50%
GND
50%
tPLH
50%
tPHL
tPHL
GND
tPLH
VCC
50%
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Sequential Module Timing Characteristics
Flip-Flops and Latches
D
E
CLK
PRE
CLR
Y
(Positive edge triggered)
D1
G, CLK
E
Q
PRE, CLR
tSUD
tHD
tWCLKA
tSUENA
tHENA
tWCLKI
tCO
tRS
tWASYN
Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.
tA
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Sequential Timing Characteristics (continued)
Input Buffer Latches
ACT2 Family FPGAs
DATA
PAD
G
CLK PAD
CLKBUF
IBDL
DATA
G
CLK
Output Buffer Latches
tINSU
tSUEXT
tINH
tHEXT
D PAD
OBDLHS
G
D
tOUTSU
G
tOUTH
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Timing Derating Factor (Temperature and Voltage)
(Commercial Minimum/Maximum Specification) x
Industrial
Min. Max.
0.69 1.11
Military
Min. Max.
0.67 1.23
Timing Derating Factor for Designs at Typical Temperature (TJ = 25°C) and
Voltage (5.0 V)
(Commercial Maximum Specification) x
0.85
Temperature and Voltage Derating Factors
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
55 40
0
25 70
4.50 0.75 0.79 0.86 0.92 1.06
4.75 0.71 0.75 0.82 0.87 1.00
5.00 0.69 0.72 0.80 0.85 0.97
5.25 0.68 0.69 0.77 0.82 0.95
5.50 0.67 0.69 0.76 0.81 0.93
Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial, TJ = 4.75V, 70°C)
85
1.11
1.05
1.02
0.98
0.97
125
1.23
1.16
1.13
1.09
1.08
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
4.50
4.75
5.00
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
5.25
125˚C
85˚C
70˚C
25˚C
0˚C
–40˚C
–55˚C
5.50
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ACT2 Family FPGAs
A1225A Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Logic Module Propagation Delays1
‘–2Speed
‘–1Speed
StdSpeed
Parameter Description
Min. Max. Min. Max. Min. Max. Units
tPD1 Single Module
tCO Sequential Clk to Q
tGO Latch G to Q
tRS Flip-Flop (Latch) Reset to Q
Predicted Routing Delays2
3.8 4.3 5.0 ns
3.8 4.3 5.0 ns
3.8 4.3 5.0 ns
3.8 4.3 5.0 ns
tRD1 FO=1 Routing Delay
tRD2 FO=2 Routing Delay
tRD3 FO=3 Routing Delay
tRD4 FO=4 Routing Delay
tRD8 FO=8 Routing Delay
Sequential Timing Characteristics3,4
1.1 1.2 1.4 ns
1.7 1.9 2.2 ns
2.3 2.6 3.0 ns
2.8 3.1 3.7 ns
4.4 4.9 5.8 ns
tSUD
Flip-Flop (Latch) Data Input
Setup
0.4
0.4
0.5
ns
tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 ns
tSUENA
Flip-Flop (Latch) Enable Setup
0.8
0.9
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.5
5.0
6.0
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.5
5.0
6.0
ns
tA
tINH
tINSU
tOUTH
tOUTSU
fMAX
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock
Frequency
9.4 11.0 13.0 ns
0.0 0.0 0.0 ns
0.4 0.4 0.5 ns
0.0 0.0 0.0 ns
0.4 0.4 0.5 ns
105.0
90.0
75.0 MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
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A1225A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
‘–2Speed
‘–1Speed
StdSpeed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Unit
Max.
s
tINYH
Pad to Y High
tINYL
Pad to Y Low
tINGH
G to Y High
tINGL
G to Y Low
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Global Clock Network
2.9 3.3 3.8 ns
2.6 3.0 3.5 ns
5.0 5.7 6.6 ns
4.7 5.4 6.3 ns
4.1 4.6 5.4 ns
4.6 5.2 6.1 ns
5.3 6.0 7.1 ns
5.7 6.4 7.6 ns
7.4 8.3 9.8 ns
tCKH
Input Low to High
FO = 32
FO = 256
10.2
11.8
11.0
13.0
12.8
15.7
ns
tCKL
Input High to Low
FO = 32
FO = 256
10.2
12.0
11.0
13.2
12.8
15.9
ns
tPWH
Minimum Pulse Width
High
FO = 32
FO = 256
3.4
3.8
4.1
4.5
4.5
5.0
ns
tPWL
Minimum Pulse Width
Low
FO = 32
FO = 256
3.4
3.8
4.1
4.5
4.5
5.0
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
0.7
3.5
0.7
3.5
0.7
3.5
ns
tSUEXT
Input Latch External
Setup
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
ns
tHEXT
Input Latch External
Hold
FO = 32
FO = 256
7.0
11.2
7.0
11.2
7.0
11.2
ns
tP
Minimum Period
FO = 32
FO = 256
7.7
8.1
8.3
8.8
9.1
10.0
ns
fMAX
Maximum Frequency
FO = 32
FO = 256
130.0
125.0
120.0
115.0
110.0
100.0
MHz
Note:
1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.
Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to
determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device
prior to shipment.
v4.0
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ACT2 Family FPGAs
A1225A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing
‘–2Speed
‘–1Speed
StdSpeed
Parameter Description
Min. Max. Min. Max.
TTL Output Module Timing1
tDLH Data to Pad High
tDHL Data to Pad Low
tENZH
Enable Pad Z to High
tENZL
Enable Pad Z to Low
tENHZ
Enable Pad High to Z
tENLZ
Enable Pad Low to Z
tGLH
G to Pad High
tGHL
G to Pad Low
dTLH
Delta Low to High
dTHL
Delta High to Low
CMOS Output Module Timing1
8.0 9.0
10.1 11.4
8.9 10.0
11.6 13.2
7.1 8.0
8.3 9.5
8.9 10.2
11.2 12.7
0.07 0.08
0.12 0.13
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
dTLH
dTHL
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
G to Pad Low
Delta Low to High
Delta High to Low
10.1 11.5
8.4 9.6
8.9 10.0
11.6 13.2
7.1 8.0
8.3 9.5
8.9 10.2
11.2 12.7
0.12 0.13
0.09 0.10
Note:
1. Delays based on 50 pF loading.
2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board.
Min.
Max.
10.6
13.4
11.8
15.5
9.4
11.1
11.9
14.9
0.09
0.16
13.5
11.2
11.8
15.5
9.4
11.1
11.9
14.9
0.16
0.12
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
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A1240A Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Logic Module Propagation Delays1
‘–2Speed
‘–1Speed
StdSpeed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max. Units
tPD1 Single Module
tCO Sequential Clk to Q
tGO Latch G to Q
tRS Flip-Flop (Latch) Reset to Q
Predicted Routing Delays2
3.8 4.3 5.0 ns
3.8 4.3 5.0 ns
3.8 4.3 5.0 ns
3.8 4.3 5.0 ns
tRD1 FO=1 Routing Delay
tRD2 FO=2 Routing Delay
tRD3 FO=3 Routing Delay
tRD4 FO=4 Routing Delay
tRD8 FO=8 Routing Delay
Sequential Timing Characteristics3, 4
1.4 1.5 1.8 ns
1.7 2.0 2.3 ns
2.3 2.6 3.0 ns
3.1 3.5 4.1 ns
4.7 5.4 6.3 ns
tSUD
Flip-Flop (Latch) Data Input
Setup
0.4
0.4
0.5 ns
tHD
Flip-Flop (Latch) Data Input
Hold
0.0
0.0
0.0 ns
tSUENA
Flip-Flop (Latch) Enable Setup
0.8
0.9
1.0 ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0 ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.5
6.0
6.5 ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.5
6.0
6.5 ns
tA
tINH
tINSU
tOUTH
tOUTSU
fMAX
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock
Frequency
9.8 12.0 15.0 ns
0.0 0.0 0.0 ns
0.4 0.4 0.5 ns
0.0 0.0 0.0 ns
0.4 0.4 0.5 ns
100.0
80.0
66.0 MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
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ACT2 Family FPGAs
A1240A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
‘–2Speed
‘–1Speed
StdSpeed
Parameter Description
Min. Max. Min. Max. Min. Max. Units
tINYH
Pad to Y High
tINYL
Pad to Y Low
tINGH
G to Y High
tINGL
G to Y Low
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Global Clock Network
2.9 3.3 3.8 ns
2.6 3.0 3.5 ns
5.0 5.7 6.6 ns
4.7 5.4 6.3 ns
4.2 4.8 5.6 ns
4.8 5.4 6.4 ns
5.4 6.1 7.2 ns
5.9 6.7 7.9 ns
7.9 8.9 10.5 ns
tCKH
Input Low to High
FO = 32
FO = 256
10.2
11.8
11.0
13.0
12.8
15.7
ns
tCKL Input High to Low
FO = 32
FO = 256
10.2
12.0
11.0
13.2
12.8
15.9
ns
tPWH
Minimum Pulse Width
High
FO = 32
FO = 256
3.8
4.1
4.5
5.0
5.5
5.8
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 256
3.8
4.1
4.5
5.0
5.5
5.8
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
0.5
2.5
0.5
2.5
0.5
2.5
ns
tSUEXT
Input Latch External Setup
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 256
7.0
11.2
7.0
11.2
7.0
11.2
ns
tP
Minimum Period
FO = 32
FO = 256
8.1
8.8
9.1 11.1
10.0 11.7
ns
fMAX
Maximum Frequency
FO = 32
FO = 256
125.0
115.0
110.0
100.0
90.0
85.0
MHz
Note:
These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing
delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual
worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
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A1240A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing
‘–2Speed
‘–1Speed
StdSpeed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
TTL Output Module Timing1
tDLH Data to Pad High
tDHL Data to Pad Low
tENZH
Enable Pad Z to High
tENZL
Enable Pad Z to Low
tENHZ
Enable Pad High to Z
tENLZ
Enable Pad Low to Z
tGLH
G to Pad High
tGHL
G to Pad Low
dTLH
Delta Low to High
dTHL
Delta High to Low
CMOS Output Module Timing1
8.0 9.0
10.1 11.4
8.9 10.0
11.7 13.2
7.1 8.0
8.4 9.5
9.0 10.2
11.2 12.7
0.07 0.08
0.12 0.13
tDLH
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
tGHL
dTLH
dTHL
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
G to Pad Low
Delta Low to High
Delta High to Low
10.2 11.5
8.4 9.6
8.9 10.0
11.7 13.2
7.1 8.0
8.4 9.5
9.0 10.2
11.2 12.7
0.12 0.13
0.09 0.10
Note:
1. Delays based on 50 pF loading.
2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board.
Max.
10.6
13.4
11.8
15.5
9.4
11.1
11.9
14.9
0.09
0.16
13.5
11.2
11.8
15.5
9.4
11.1
11.9
14.9
0.16
0.12
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
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ACT2 Family FPGAs
A1280A Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Logic Module Propagation Delays1
‘–2Speed
‘–1Speed
StdSpeed
Parameter Description
Min. Max. Min. Max. Min. Max. Units
tPD1 Single Module
3.8 4.3 5.0 ns
tCO Sequential Clk to Q
3.8 4.3 5.0 ns
tGO Latch G to Q
3.8 4.3 5.0 ns
tRS Flip-Flop (Latch) Reset to Q
Predicted Routing Delays2
3.8 4.3 5.0 ns
tRD1 FO=1 Routing Delay
1.7 2.0 2.3 ns
tRD2 FO=2 Routing Delay
2.5 2.8 3.3 ns
tRD3 FO=3 Routing Delay
tRD4 FO=4 Routing Delay
tRD8 FO=8 Routing Delay
Sequential Timing Characteristics3,4
3.0 3.4 4.0 ns
3.7 4.2 4.9 ns
6.7 7.5 8.8 ns
tSUD
Flip-Flop (Latch) Data Input
Setup
0.4
0.4
0.5
ns
tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 ns
tSUENA
Flip-Flop (Latch) Enable Setup
0.8
0.9
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
5.5
6.0
7.0
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
5.5
6.0
7.0
ns
tA
Flip-Flop Clock Input Period
11.7
13.3
18.0
ns
tINH
tINSU
tOUTH
tOUTSU
fMAX
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock
Frequency
0.0 0.0 0.0 ns
0.4 0.4 0.5 ns
0.0 0.0 0.0 ns
0.4 0.4 0.5 ns
85.0 75.0 50.0 MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
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A1280A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
‘–2Speed
‘–1Speed
StdSpeed
Parameter Description
Min. Max. Min. Max. Min. Max. Units
tINYH
Pad to Y High
tINYL
Pad to Y Low
tINGH
G to Y High
tINGL
G to Y Low
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Global Clock Network
2.9 3.3 3.8 ns
2.7 3.0 3.5 ns
5.0 5.7 6.6 ns
4.8 5.4 6.3 ns
4.6 5.1 6.0 ns
5.2 5.9 6.9 ns
5.6 6.3 7.4 ns
6.5 7.3 8.6 ns
9.4 10.5 12.4 ns
tCKH
Input Low to High
FO = 32
FO = 384
10.2
13.1
11.0
14.6
12.8
17.2
ns
tCKL Input High to Low
FO = 32
FO = 384
10.2
13.3
11.0
14.9
12.8
17.5
ns
tPWH
Minimum Pulse Width
High
FO = 32
FO = 384
5.0
5.8
5.5
6.4
6.6
7.6
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 384
5.0
5.8
5.5
6.4
6.6
7.6
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
0.5
2.5
0.5
2.5
0.5
2.5
ns
tSUEXT
Input Latch External Setup
FO = 32
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 384
7.0
11.2
7.0
11.2
7.0
11.2
ns
tP Minimum Period
FO = 32
FO = 384
9.6
10.6
11.2
12.6
13.3
15.3
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
105.0
95.0
90.0
80.0
75.0
65.0
MHz
Note:
These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing
delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual
worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
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ACT2 Family FPGAs
A1280A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing
‘–2Speed
‘–1Speed
StdSpeed
Parameter Description
Min.
Max. Min.
Max. Min.
TTL Output Module Timing1
tDLH Data to Pad High
tDHL Data to Pad Low
tENZH
Enable Pad Z to High
tENZL
Enable Pad Z to Low
tENHZ
Enable Pad High to Z
tENLZ
Enable Pad Low to Z
tGLH
G to Pad High
tGHL
G to Pad Low
dTLH
Delta Low to High
dTHL
Delta High to Low
CMOS Output Module Timing1
8.1 9.0
10.2 11.4
9.0 10.0
11.8 13.2
7.1 8.0
8.4 9.5
9.0 10.2
11.3 12.7
0.07 0.08
0.12 0.13
tDLH Data to Pad High
10.3 11.5
tDHL Data to Pad Low
8.5 9.6
tENZH
Enable Pad Z to High
9.0 10.0
tENZL
Enable Pad Z to Low
11.8 13.2
tENHZ
Enable Pad High to Z
7.1 8.0
tENLZ
Enable Pad Low to Z
8.4 9.5
tGLH
G to Pad High
9.0 10.2
tGHL
G to Pad Low
11.3 12.7
dTLH
Delta Low to High
0.12 0.13
dTHL
Delta High to Low
0.09 0.10
Note:
1. Delays based on 50 pF loading.
2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board.
Max.
10.6
13.4
11.8
15.5
9.4
11.1
11.9
14.9
0.09
0.16
13.5
11.2
11.8
15.5
9.4
11.1
11.9
14.9
0.16
0.12
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
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Pin Description
CLKA
Clock A (Input)
TTL Clock input for clock distribution networks. The Clock
input is buffered prior to clocking the logic modules. This
pin can also be used as an I/O.
CLKB
Clock B (Input)
TTL Clock input for clock distribution networks. The Clock
input is buffered prior to clocking the logic modules. This
pin can also be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground
LOW supply voltage.
I/O Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O
pins are automatically driven LOW by the ALS software.
MODE
Mode (Input)
The MODE pin controls the use of multifunction pins
(DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the
special functions are active. When the MODE pin is LOW,
the pins function as I/Os. To provide Actionprobe capability,
the MODE pin should be terminated to GND through a 10K
resistor so that the MODE pin can be pulled high when
required.
NC No Connection
This pin is not connected to circuitry within the device.
PRA
Probe A (Output)
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin is used in conjunction with the
Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when debugging has been completed.
The pins probe capabilities can be permanently disabled to
protect programmed design confidentiality. PRA is active
when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.
PRB
Probe B (Output)
The Probe B pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin is used in conjunction with the
Probe A pin to allow real-time diagnostic output of any
signal path within the device. The Probe B pin can be used
as a user-defined I/O when debugging has been completed.
The pins probe capabilities can be permanently disabled to
protect programmed design confidentiality. PRB is active
when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
VCC
5.0V Supply Voltage
HIGH supply voltage.
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Package Pin Assignments
84-Pin PLCC
1 84
ACT2 Family FPGAs
84-Pin
PLCC
Signal
A1225A Function
A1240A Function
A1280A Function
2 CLKB, I/O
CLKB, I/O
CLKB, I/O
4 PRB, I/O
PRB, I/O
PRB, I/O
6 GND
GND
GND
10 DCLK, I/O
DCLK, I/O
DCLK, I/O
12 MODE
MODE
MODE
22 VCC
VCC
VCC
23 VCC
VCC
VCC
28 GND
GND
GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
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Package Pin Assignments
84-Pin PLCC
1 84
84-Pin
PLCC
Signal
A1225A Function
A1240A Function
A1280A Function
43 VCC
VCC
VCC
49 GND
GND
GND
63 GND
GND
GND
64 VCC
VCC
VCC
65 VCC
VCC
VCC
70 GND
GND
GND
76 SDI, I/O
SDI, I/O
SDI, I/O
81 PRA, I/O
PRA, I/O
PRA, I/O
83 CLKA, I/O
CLKA, I/O
CLKA, I/O
84 VCC
VCC
VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
v4.0
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FPGAs

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Package Pin Assignments (continued)
100-Pin PQFP
ACT2 Family FPGAs
100-Pin
PQFP
100
1
Pin Number
A1225A Function
Pin Number
A1225A Function
2 DCLK, I/O
66 VCC
4 MODE
67 VCC
9 GND
72 GND
16 VCC
79 SDI, I/O
17 VCC
84 GND
22 GND
87 PRA, I/O
34 GND
89 CLKA, I/O
40 VCC
90 VCC
46 GND
92 CLKB, I/O
57 GND
94 PRB, I/O
64 GND
96 GND
65 VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
24 v4.0


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FPGAs

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Package Pin Assignments (continued)
144-Pin PQFP
1
144
144-Pin
PQFP
v4.0
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FPGAs

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ACT2 Family FPGAs
144-Pin PQFP
Pin Number
A1240A Function
Pin Number
A1240A Function
2 MODE
9 GND
10 GND
11 GND
18 VCC
19 VCC
20 VCC
21 VCC
89 VCC
90 VCC
91 VCC
92 VCC
93 VCC
100 GND
101 GND
102 GND
28 GND
110 SDI, I/O
29 GND
116 GND
30 GND
117 GND
44 GND
118 GND
45 GND
123 PRA, I/O
46 GND
125 CLKA, I/O
54 VCC
126 VCC
55 VCC
127 VCC
56 VCC
128 VCC
64 GND
130 CLKB, I/O
65 GND
132 PRB, I/O
79 GND
136 GND
80 GND
137 GND
81 GND
138 GND
88 GND
144 DCLK, I/O
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
26 v4.0


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FPGAs

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Package Pin Assignments (continued)
160-Pin PQFP
160
1
160-Pin
PQFP
v4.0
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FPGAs

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ACT2 Family FPGAs
160-Pin PQFP
Pin Number
A1280A Function
Pin Number
A1280A Function
2 DCLK, I/O
6 VCC
11 GND
16 PRB, I/O
18 CLKB, I/O
20 VCC
21 CLKA, I/O
23 PRA, I/O
69 GND
80 GND
86 VCC
89 GND
98 VCC
99 GND
109 GND
114 VCC
30 GND
120 GND
35 VCC
125 GND
38 SDI, I/O
130 GND
40 GND
135 VCC
44 GND
138 VCC
49 GND
139 VCC
54 VCC
140 GND
57 VCC
145 GND
58 VCC
150 VCC
59 GND
155 GND
60 VCC
159 MODE
61 GND
160 GND
64 GND
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
28 v4.0


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FPGAs

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Package Pin Assignments (continued)
100-Pin VQFP
100
1
100-Pin
VQFP
100-Pin VQFP
Pin Number
A1225A Function
Pin Number
A1225A Function
2 MODE
65 VCC
7 GND
70 GND
14 VCC
77 SDI, I/O
15 VCC
82 GND
20 GND
85 PRA, I/O
32 GND
87 CLKA, I/O
38 VCC
88 VCC
44 GND
90 CLKB, I/O
55 GND
92 PRB, I/O
62 GND
94 GND
63 VCC
100 DCLK, I/O
64 VCC
Notes:
1. All unlisted pin numbers are user I/Os.
2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND.
v4.0
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FPGAs

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Package Pin Assignments (continued)
176-Pin TQFP
176
1
ACT2 Family FPGAs
176-Pin
TQFP
30 v4.0




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