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Freescale Semiconductor
Data Sheet
MCF5213EC
Rev. 0, 05/2005
MCF5213 Microcontroller Family
Hardware Specification
The MCF5213 is a member of the ColdFire® family of
reduced instruction set computing (RISC)
microprocessors. This hardware specification provides
an overview of the 32-bit MCF5213 microcontroller,
focusing on its highly integrated and diverse feature set.
Freescale reserves the right to change or discontinue this
product without notice. Specifications and information
herein are subject to change without notice.
This 32-bit device is based on the Version 2 ColdFire
core operating at a frequency up to 80 MHz, offering
high performance and low power consumption. On-chip
memories connected tightly to the processor core include
256 Kbytes of Flash and 32 Kbytes of static random
access memory (SRAM). On-chip modules include the
following:
• V2 ColdFire core delivering 76 MIPS
(Dhrystone 2.1) at 80 MHz running from
internal Flash with Multiply Accumulate (MAC)
Unit and hardware divider
• FlexCAN controller area network (CAN)
module
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
Table of Contents
1 MCF5213 Family Configurations .........................2
1.1 Block Diagram ...................................................3
1.2 Features.............................................................4
1.3 Part Numbers and Packaging..........................14
1.4 Package Pinouts..............................................15
1.5 Reset Signals ..................................................20
1.6 PLL and Clock Signals ....................................20
1.7 Mode Selection................................................21
1.8 External Interrupt Signals ................................21
1.9 Queued Serial Peripheral Interface (QSPI) .....22
1.10 I2C I/O Signals.................................................22
1.11 UART Module Signals .....................................22
1.12 DMA Timer Signals..........................................23
1.15 Pulse Width Modulator Signals........................24
1.16 Debug Support Signals....................................24
1.17 EzPort Signal Descriptions ..............................26
1.18 Power and Ground Pins...................................26
2 Preliminary Electrical Characteristics................26
3 Mechanical Outline Drawings ............................42
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.


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MCF5213 Family Configurations
• Inter-integrated circuit (I2C™) bus controller
• Queued serial peripheral interface (QSPI) module
• Eight-channel 12-bit fast analog-to-digital converter (ADC)
• Four-channel direct memory access (DMA) controller
• Four 32-bit input capture/output compare timers with DMA support (DTIM)
• Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width
modulation (PWM), and pulse accumulation
• Eight-channel/Four-channel, 8-bit/16-bit pulse width modulation timer
• Two 16-bit periodic interrupt timers (PITs)
• Programmable software watchdog timer
• Interrupt controller capable of handling 63 selectable-priority interrupt sources
• Clock module with 8 MHz on-chip relaxation oscillator and integrated phase locked loop (PLL)
• Test access/debug port (JTAG, BDM)
1 MCF5213 Family Configurations
Table 1. MCF5213 Family Configurations
Module
ColdFire Version 2 Core with MAC (Multiply-Accumulate
Unit)
System Clock
Performance (Dhrystone 2.1 MIPS)
Flash / Static RAM (SRAM)
Interrupt Controller (INTC)
Fast Analog-to-Digital Converter (ADC)
FlexCAN 2.0B Module
Four-channel Direct-Memory Access (DMA)
Software Watchdog Timer (WDT)
Programmable Interrupt Timer
Four-Channel General Purpose Timer
32-bit DMA Timers
QSPI
UART(s)
I2C
Eight/Four-channel 8/16-bit PWM Timer
General Purpose I/O Module (GPIO)
5211
x
66 MHz
63
128/16 Kbytes
x
x
-
x
x
2
x
4
x
3
x
x
x
5212
x
5213
x
66, 80 MHz
up to 76
256/32 Kbytes
xx
xx
-x
xx
xx
22
xx
44
xx
33
xx
xx
xx
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MCF5213 Family Configurations
Table 1. MCF5213 Family Configurations (continued)
Module
5211
5212
5213
Chip Configuration and Reset Controller Module
x xx
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port1
x xx
x xx
Package
64-pin LQFP
64-pin LQFP 81-ball MAPBGA
81-ball MAPBGA 81-ball MAPBGA 100-Lead LQFP
N1 OTTEhSe:full debug/trace interface is available only on the 100-pin packages. A reduced debug
interface is bonded on smaller packages.
1.1 Block Diagram
The MCF5213 comes in a 100-pin low-profile quad flat pack (LQFP) and operates in single-chip mode
only. Figure 1 shows a top-level block diagram of the MCF5213. Other members of this family can have
different package options, which are described later in this document.
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MCF5213 Family Configurations
EzPort
EzPCS
Arbiter
Interrupt
Controller
4 CH DMA
To/From PADI
JTAG_EN MUX
AN[7:0]
JTAG
TAP
ADC
VRH VRL
UART UART UART
012
I2C
QSPI
DTIM DTIM DTIM DTIM
0123
V2 ColdFire CPU
IFP
OEP
MAC
32 Kbytes
SRAM
(4Kx16)x4
VSTBY
256 Kbytes
Flash
(32Kx16)x4
PORTS
(GPIO)
GPTn
QSPI_DIN,
QSPI_DOUT
QSPI_CLK,
QSPI_CSn
SDA
SCL
UTXDn
URXDn
URTSn
UCTSn
DTINn/DTOUTn
CANRX
CANTX
PWMn
IRQn
PMM
RSTI
CIM
RSTO
FlexCAN
Edge
Port
PLL OCO
CLKGEN
PIT0
PIT1
GPT
PWM
EXTAL XTAL CLKOUT
CLKMOD0 CLKMOD1
To/From Interrupt Controller
Figure 1. MCF5213 Block Diagram
1.2 Features
This document contains information on a new product under development. Freescale reserves the right to
change or discontinue this product without notice. Specifications and information herein are subject to
change without notice.
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MCF5213 Family Configurations
1.2.1 Feature Overview
• Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register, and
four new instructions for improved bit processing
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16 × 16 32 or
32 × 32 32 operations
— Illegal instruction decode that allows for 68K emulation support
• System debug support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can
be configured into a 1- or 2-level trigger
• On-chip memories
— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with
standby power supply support
— 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
• Power management
— Fully static operation with processor sleep and whole chip stop modes
— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
• FlexCAN 2.0B Module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard Data and Remote Frames (up to 109 bits long)
– Extended Data and Remote Frames (up to 127 bits long)
– 0-8 bytes data length
– Programmable bit rate up to 1 Mbit/sec
— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length
each, configurable as Rx or Tx, all supporting standard and extended messages
— Unused MB space can be used as general purpose RAM space
— Listen only mode capability
— Content-related addressing
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MCF5213 Family Configurations
— No read/write semaphores
— Three programmable mask registers: global for MBs 0-13, special for MB14, and special for
MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— “Time stamp” based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Maskable interrupts
• Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
• I2C Module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
• Queued Serial Peripheral Interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
• Fast Analog-to-Digital Converter (ADC)
— Eight analog input channels
— 12-bit resolution ± 2.5 counts accuracy
— Minimum 2.25 µs conversion time
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over
low/high limit
— Unused analog channels can be used as digital I/O
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MCF5213 Family Configurations
• Four 32-bit DMA Timers
— 12.5-ns resolution at 80 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input capture capability with programmable trigger edge on input pin
— Output compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or output compare
— DMA trigger capability on input capture or output compare
• Four-channel General Purpose Timers
— 16-bit architecture
— Programmable prescaler
— Output pulse widths variable from microseconds to seconds
— Single 16-bit input pulse accumulator
— Toggle-on-overflow feature for pulse-width modulator (PWM) generation
— One dual-mode pulse accumulation channel
• Pulse-Width Modulation Timer
— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution
— Programmable period and duty cycle
— Programmable enable/disable for each channel
— Software selectable polarity for each channel
— Period and duty cycle are double buffered. Change takes effect when the end of the current
period is reached (PWM counter reaches zero) or when the channel is disabled.
— Programmable center or left aligned outputs on individual channels
— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
— Emergency shutdown
• Two Periodic Interrupt Timers (PITs)
— 16-bit counter
— Selectable as free running or count down
• Software Watchdog Timer
— 16-bit counter
— Low power mode support
• Clock Generation Features
— 1 to 16 MHz crystal, 8 MHz on-chip relaxation oscillator, or external oscillator reference
options
— Relaxation oscillator NVM-trimmed to 2% accuracy
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— 2 to 10 MHz reference frequency for normal PLL mode
— System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator
— Low power modes supported
— 2n (n 0 15) low-power divider for extremely low frequency operation
• Interrupt Controller
— Support for up to 56 interrupt sources organized as follows:
– 49 fully-programmable interrupt sources
– 7 fixed-level interrupt sources
— Seven external interrupt signals
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
• DMA Controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for
16-byte (4 x 32-bit) burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)
• Reset
— Separate reset in and reset out signals
— Seven sources of reset:
– Power-on reset (POR)
– External
– Software
– Watchdog (resets the CPU without affecting the peripheral modules)
– Loss of clock
– Loss of lock
– Low-voltage detection (LVD)
— Status flag indication of source of last reset
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• Chip Integration Module (CIM)
— System configuration during reset
— Selects one of six clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
• General Purpose I/O interface
— Up to 56 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Programmable drive strengths of 2mA or 10mA per pin
— Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing
MCF5213 Family Configurations
1.2.2 V2 Core Overview
The Version 2 ColdFire processor core is comprised of two separate pipelines that are decoupled by an
instruction buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address
generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds
prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includes
two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support for a
separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the
MCF5213 core includes the multiply-accumulate (MAC) unit for improved signal processing capabilities.
The MAC implements a three-stage arithmetic pipeline, optimized for 16 x 16 bit operations, with support
for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers,
signed fractional operands, and a complete set of instructions to process these data types. The MAC
provides support for execution of DSP operations within the context of a single processor at a minimal
hardware cost.
1.2.3 Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface users can access
debug information, and on 100-lead packages real-time tracing capability is provided. This allows the
processor and system to be debugged at full speed without the need for costly in-circuit emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address register
and an address mask register, a data register and a data mask register, and four PC registers plus one PC
mask register. These registers can be accessed through the dedicated debug serial communication channel
or from the processor’s supervisor mode programming model. The breakpoint registers can be configured
to generate triggers by combining the address, data, and PC conditions in a variety of single- or dual-level
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definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt
exception.
The MCF5213’s interrupt servicing options during emulator mode allow real-time critical interrupt service
routines to be serviced while processing a debug interrupt event, thereby ensuring that the system
continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data
(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand
data, and branch target addresses defining processor activity at the CPU’s clock rate. The full debug/trace
interface is available only on the 100-pin packages. However, every product features the dedicated debug
serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
The MCF5213 includes a new debug signal, ALLPST. This signal is the logical ‘AND’ of the processor
status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] =
1111).
1.2.4 JTAG
The MCF5213 supports circuit board test strategies based on the Test Technology Committee of IEEE and
the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state
controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan
register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register.
Test logic, implemented using static logic design, is independent of the device system logic.
The MCF5213 implementation can do the following:
• Perform boundary-scan operations to test circuit board electrical continuity
• Sample MCF5213 system pins during operation and transparently shift out the result in the
boundary scan register
• Bypass the MCF5213 for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
1.2.5 On-Chip Memories
1.2.5.1 SRAM
The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access
in a single cycle. The location of the memory block can be set to any 32-Kbyte boundary within the
4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the
system stack. Because the SRAM module is physically connected to the processor's high-speed local bus,
it can quickly service core-initiated accesses or memory-referencing commands from the debug module.
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The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal
for implementing applications with double-buffer schemes, where the processor and a DMA device
operate in alternate regions of the SRAM to maximize system performance.
1.2.5.2 Flash
The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) module that connects to the
processor’s high-speed local bus. The CFM is constructed with four banks of 32K x 16-bit Flash arrays to
generate 256 Kbytes of 32-bit Flash memory. These arrays serve as electrically erasable and
programmable, non-volatile program and data memory. The Flash memory is ideal for program and data
storage for single-chip applications, allowing for field reprogramming without requiring an external high
voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory
controller which supports interleaved accesses from the 2-cycle Flash arrays. A backdoor mapping of the
Flash memory is used for all program, erase, and verify operations, as well as providing a read datapath
for the DMA. Flash memory may also be programmed via the EzPort, which is a serial Flash programming
interface that allows the Flash to be read, erased and programmed by an external controller in a format
compatible with most SPI bus Flash memory chips.
1.2.6 Power Management
The MCF5213 incorporates several low power modes of operation which are entered under program
control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors
the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD)
monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the
LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip
falls below the standby battery voltage.
1.2.7 FlexCAN
The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts
A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific
requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of
FlexCAN has 16 message buffers.
1.2.8 UARTs
The MCF5213 has three full-duplex UARTs that function independently. The three UARTs can be clocked
by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third
UART is multiplexed with other digital I/O functions.
1.2.9 I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange
and minimizes the interconnection between devices. This bus is suitable for applications requiring
occasional communications over a short distance between many devices.
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1.2.10 QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with
queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU
intervention between transfers.
1.2.11 Fast ADC
The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold
(S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible
buffers for further processing.
The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or
perform a programmed scan sequence repeatedly until manually stopped.
The ADC can be configured for either sequential or simultaneous conversion. When configured for
sequential conversions, up to eight channels can be sampled and stored in any order specified by the
channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same
time. This configuration requires that a single channel may not be sampled by both S/H circuits
simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures
below the low threshold limit or above the high threshold limit set in the limit registers) or at several
different zero crossing conditions.
1.2.12 DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3)
on the MCF5213. Each module incorporates a 32-bit timer with a separate register set for configuration
and control. The timers can be configured to operate from the system clock or from an external clock
source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The
input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter
register (TCRn). Each of these timers can be configured for input capture or reference (output) compare
mode. Timer events may optionally cause interrupt requests or DMA transfers.
1.2.13 General Purpose Timer (GPT)
The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable
counter driven by a 7-stage programmable prescaler. Each of the four channels can be configured for input
capture or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse
accumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit
range of the counter. The input capture and output compare functions allow simultaneous input waveform
measurements and output waveform generation. The input capture function can capture the time of a
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MCF5213 Family Configurations
selected transition edge. The output compare function can generate output waveforms and timer software
delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.
1.2.14 Periodic Interrupt Timers (PIT0 and PIT1)
The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular
intervals with minimal processor intervention. Each timer can either count down from the value written in
its PIT modulus register, or it can be a free-running down-counter.
1.2.15 Pulse Width Modulation Timers
The MCF5213 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty
cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms
with software-selectable duty rates from 0% to 100%. The PWM outputs have programmable polarity, and
can be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycle
resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a
single 16-bit channel. The module can thus be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit
channels.
1.2.16 Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter
is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must
periodically restart the countdown.
1.2.17 Phase Locked Loop (PLL)
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked
loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control
logic. In order to improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their
own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply
pins, VDD and VSS.
1.2.18 Interrupt Controller (INTC)
The MCF5213 has a single interrupt controller that supports up to 56 interrupt sources, organized as seven
levels with nine sources per level. Each interrupt source has a unique interrupt vector, and 49 of the 56
sources have a programmable level [1-7] and priority within the level. One source on each level has a fixed
middle priority and is assigned to the IRQ pin corresponding to that level.
1.2.19 DMA Controller
The direct memory access (DMA) controller provides an efficient way to move blocks of data with
minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line
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MCF5213 Family Configurations
transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the
occurrence of certain UART or DMA timer events.
1.2.20 Reset
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and
keeps track of what caused the last reset. There are seven sources of reset:
• External reset input
• Power-on reset (POR)
• Watchdog timer
• Phase locked-loop (PLL) loss of lock
• PLL loss of clock
• Software
• Low-voltage detector (LVD)
Control of the LVD and its associated reset and interrupt are handled by the reset controller. Other registers
provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO
pin.
1.2.21 GPIO
Nearly all pins on the MCF5213 have general purpose I/O capability and are grouped into 8-bit ports.
Some ports do not use all 8 bits. Each port has registers that configure, monitor, and control the port pins.
1.3 Part Numbers and Packaging
Table 2. Part Number Summary
Part Number
MCF5211
MCF5212
MCF5213
Flash / SRAM
128 Kbytes / 16 Kbytes
256 Kbytes / 32 Kbytes
256 Kbytes / 32 Kbytes
Key Features
3 UARTs, I2C, QSPI, A/D
16-/32-bit/PWM Timers
3 UARTs, I2C, QSPI, A/D
16-/32-bit/PWM Timers
3 UARTs, I2C, QSPI, A/D
16-/32-bit/PWM Timers, CAN
Package
64-pin LQFP
81-ball MAPBGA
64-pin LQFP
81-ball MAPBGA
81-ball MAPBGA
100-Lead LQFP
Speed
66 MHz
66, 80 MHz
66 MHz
66, 80 MHz
66, 80 MHz
66, 80 MHz
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1.4 Package Pinouts
Figure 2 shows the pinout configuration for the 100-Lead LQFP.
MCF5213 Family Configurations
VDD
VDD
VSS
URTS1
TEST
UCTS0
URXD0
UTXD0
URTS0
SCL
SDA
QSPI_CS3
QSPI_CS2
VDD
VSS
QSPI-DIN
QSPI_DOUT
QSPI_CLK
QSPI_CS1
QSPI_CS0
RCON
VDD
VDD
VSS
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 LQFP
75 VSS
74 VDDPLL
73 EXTAL
72 XTAL
71 VSSPLL
70 PST3
69 PST2
68 VDD
67 VSS
66 PST1
65 PST0
64 PSTCLK
63 PWM7
62 GPT3
61 GPT2
60 PWM5
59 GPT1
58 GPT0
57 VDD
56 VSS
55 VSTBY
54 AN4
53 AN5
52 AN6
51 AN7
Figure 2. 100-Lead LQFP Pin Assignments
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MCF5213 Family Configurations
Figure 3 shows the pinout configuration for the 81-Lead MAPBGA.
123456789
A VSS
UTXD1
RSTI
IRQ5
IRQ3
ALLPST
TDO
TMS
VSS
B URTS1
URXD1
RSTO
IRQ6
IRQ2
TRST
TDI
VDDPLL
EXTAL
C UCTS0
TEST
UCTS1
IRQ7
IRQ4
IRQ1
TCLK
VSSPLL
XTAL
D URXD0
UTXD0
URTS0
VSS
VDD
VSS
PWM7
GPT3
GPT2
E SCL
SDA
VDD
VDD
VDD
VDD
VDD
PWM5
GPT1
F QSPI_CS3 QSPI_CS2 QSPI_DIN
VSS
VDD
VSS
GPT0
VSTBY
AN4
G QSPI_DOUT
SCK
RCON
DTIN1
CLKMOD0
AN2
AN3
AN5
AN6
H QSPI_CS0 QSPI_CS1
DTIN3
DTIN0
CLKMOD1
AN1
VSSA
VDDA
AN7
J VSS
JTAG_EN
DTIN2
PWM3
PWM1
AN0
VRL
Figure 3. 81-Lead MAPBGA Pin Assignments
VRH
VSSA
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Figure 4 shows the pinout configuration for the 64-Lead LQFP.
MCF5213 Family Configurations
VDD
URTS1
TEST
UCTS0
URXD0
UTXD0
URTS0
SCL
SDA
VDD
VSS
QSPI_DIN
QSPI_DOUT
QSPI_CLK
QSPI_CS0
RCON
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 LQFP
48 VDDPLL
47 EXTAL
46 XTAL
45 VSSPLL
44 PSTCLK
43 GPT3
42 GPT2
41 GPT1
40 IGPT0
39 VDD
38 VSS
37 VSTBY
36 AN4
35 AN5
34 AN6
33 AN7
Figure 4. 64-Lead LQFP Pin Assignments
Table 3 shows the pin functions by primary and alternate purpose, and illustrates which packages contain
each pin.
Table 3. Primary and Alternate Pin Functions by Package
Pin
Group
ADC
Clock
Generation
Primary
Function
AN[7:0]
VDDA
VSSA
VRH
VRL
EXTAL
XTAL
VDDPLL
VSSPLL
Secondary
Function
Tertiary
Function
Quaternary
Function
Bonded Bonded
on on 81
100 LQFP MAPBGA
Bonded
on 64
LQFP
GPIO
1
1
1
— 111
— 111
— 111
— 111
— 111
— 111
— 111
— 111
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MCF5213 Family Configurations
Table 3. Primary and Alternate Pin Functions by Package (continued)
Pin
Group
Primary
Function
Secondary
Function
Debug Data ALLPST
DDATA[3:0]
PST[3:0]
I2C SCL
SDA
Interrupts
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
JTAG/BDM JTAG_EN
TCLK/PSTCL
K
TDI/DSI
TDO/DSO
TMS
/BKPT
TRST
/DSCLK
Mode
Selection
CLKMOD0
CLKMOD1
RCON/
EZPCS
PWM
PWM7
PWM5
PWM3
PWM1
CANTX1
CANRX1
SYNCA
CLKOUT
Tertiary
Function
UTXD2
URXD2
PWM1
Quaternary
Function
Bonded Bonded
on on 81
100 LQFP MAPBGA
Bonded
on 64
LQFP
— 111
GPIO
4
0
0
GPIO
4
0
0
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
0
GPIO
1
1
0
GPIO
1
1
1
GPIO
1
1
0
GPIO
1
1
0
GPIO
1
1
1
— 111
— 111
— 111
— 111
— 111
— 111
— 111
— 111
— 111
GPIO
1
1
0
GPIO
1
1
0
GPIO
1
1
0
GPIO
1
1
0
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MCF5213 Family Configurations
Table 3. Primary and Alternate Pin Functions by Package (continued)
Pin
Group
Primary
Function
Secondary
Function
QSPI
QSPI_DIN/
EZPD
QSPI_DOUT/
EZPQ
QSPI_SCK/
EZPCK
QSPI_CS3
QSPI_CS2
QSPI_CS1
QSPI_CS0
Reset
RSTI
RSTO
Test TEST
Timers, 16-bit GPT3
GPT2
GPT1
GPT0
Timers, 32-bit DTIN3
DTIN2
DTIN1
DTIN0
UART 0
URXD0
UTXD0
UCTS0
URTS0
UART 1
UCTS1
URTS1
URXD1
UTXD1
CANRX1
CANTX1
SCL
SYNCA
SDA
DTOUT3
DTOUT2
DTOUT1
DTOUT0
CANRX
CANTX
SYNCA
SYNCB
Tertiary
Function
RXD1
TXD1
RTS1
SYNCB
CTS1
PWM7
PWM5
PWM3
PWM1
PWM6
PWM4
PWM2
PWM0
URXD2
UTXD2
Quaternary
Function
Bonded Bonded
on on 81
100 LQFP MAPBGA
Bonded
on 64
LQFP
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
0
GPIO
1
1
0
GPIO
1
1
0
GPIO
1
1
1
— 111
— 111
— 111
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
GPIO
1
1
1
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MCF5213 Family Configurations
Table 3. Primary and Alternate Pin Functions by Package (continued)
Pin
Group
Primary
Function
Secondary
Function
Tertiary
Function
Quaternary
Function
Bonded Bonded
on on 81
100 LQFP MAPBGA
Bonded
on 64
LQFP
UART 2
UCTS2
— GPIO 1
0
URTS2
— GPIO 1
0
URXD2
— GPIO 1
0
UTXD2
— GPIO 1
0
VSTBY
VSTBY
11
VDD
VDD
86
VSS
VSS
86
NOTES:
1 The multiplexed CANTX and CANRX signals are not available on the MCF5211 or MCF5212
0
0
0
0
1
5
5
1.5 Reset Signals
Table 4 describes signals that are used to either reset the chip or as a reset indication.
Table 4. Reset Signals
Signal Name
Reset In
Reset Out
Abbreviation
Function
I/O
RSTI
RSTO
Primary reset input to the device. Asserting RSTI immediately resets
the CPU and peripherals.
Driven low for 512 CPU clocks after the reset source has deasserted.
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1.6 PLL and Clock Signals
Table 5 describes signals that are used to support the on-chip clock generation circuitry.
Table 5. PLL and Clock Signals
Signal Name
External Clock In
Crystal
Clock Out
Abbreviation
Function
I/O
EXTAL
XTAL
CLKOUT
Crystal oscillator or external clock input except when the on-chip
relaxation oscillator is used.
Crystal oscillator output except when CLKMOD1=1, then sampled as
part of the clockmode selection mechanism.
This output signal reflects the internal system clock.
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MCF5213 Family Configurations
1.7 Mode Selection
Table 6 describes signals used in mode selection, Table 7 describes particular clocking modes.
Table 6. Mode Selection Signals
Signal Name
Abbreviation
Function
I/O
Clock Mode Selection
Reset Configuration
Test
CLKMOD[1:0] Selects the clock boot mode.
RCON
The Serial Flash Programming mode is entered by asserting the
RCON pin (with the TEST pin negated) as the chip comes out of
reset. During this mode, the EzPort has access to the Flash memory
which can be programmed from an external device.
TEST
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of
test functions.
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CLKMOD[1:0]
00
00
01
10
10
11
XTAL
0
1
N/A
0
1
N/A
Table 7. Clocking Modes
Configure the clock mode.
PLL disabled, clock driven by external oscillator
PLL disabled, clock driven by on-chip oscillator
PLL disabled, clock driven by crystal
PLL in normal mode, clock driven by external oscillator
PLL in normal mode, clock driven by on-chip oscillator
PLL in normal mode, clock driven by crystal
1.8 External Interrupt Signals
Table 8 describes the external interrupt signals.
Table 8. External Interrupt Signals
Signal Name
External Interrupts
Abbreviation
Function
IRQ[7:1] External interrupt sources.
I/O
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MCF5213 Family Configurations
1.9 Queued Serial Peripheral Interface (QSPI)
Table 9 describes QSPI signals.
Table 9. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name
Abbreviation
Function
I/O
QSPI Synchronous QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be
Serial Output
driven on the rising or falling edge of QSPI_CLK.
QSPI Synchronous
Serial Data Input
QSPI_DIN Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK.
QSPI Serial Clock
QSPI_CLK Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable.
Synchronous Peripheral QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active
Chip Selects
high or low.
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1.10 I2C I/O Signals
Table 10 describes the I2C serial interface module signals.
Table 10. I2C I/O Signals
Signal Name
Serial Clock
Serial Data
Abbreviation
Function
SCL
SDA
Open-drain clock signal for the for the I2C interface. Either it is driven
by the I2C module when the bus is in master mode or it becomes the
clock input when the I2C is in slave mode.
Open-drain signal that serves as the data input/output for the I2C
interface.
I/O
I/O
I/O
1.11 UART Module Signals
Table 11 describes the UART module signals.
Table 11. UART Module Signals
Signal Name
Transmit Serial Data
Output
Receive Serial Data
Input
Clear-to-Send
Request-to-Send
Abbreviation
Function
I/O
UTXDn
URXDn
UCTSn
URTSn
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, LSB first, on this pin at
the falling edge of the serial clock source.
Receiver serial data inputs for the UART modules. Data is received on
this pin LSB first. When the UART clock is stopped for power-down
mode, any transition on this pin restarts it.
Indicate to the UART modules that they can begin data transmission.
Automatic request-to-send outputs from the UART modules. This
signal can also be configured to be asserted and negated as a
function of the RxFIFO level.
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MCF5213 Family Configurations
1.12 DMA Timer Signals
Table 12 describes the signals of the four DMA timer modules.
Table 12. DMA Timer Signals
Signal Name
DMA Timer Input
DMA Timer Output
Abbreviation
Function
DTIN
DTOUT
Event input to the DMA timer modules.
Programmable output from the DMA timer modules.
I/O
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1.13 ADC Signals
Table 13 describes the signals of the Analog-to-Digital Converter.
Signal Name
Analog Inputs
Analog Reference
Analog Supply
Table 13. ADC Signals
Abbreviation
Function
AN[7:0]
VRH
VRL
VDDA
VSSA
Inputs to the A-to-D converter.
Reference voltage high and low inputs.
Isolate the ADC circuitry from power supply noise
I/O
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MCF5213 Family Configurations
1.14 General Purpose Timer Signals
Table 14 describes the General Purpose Timer Signals.
Table 14. GPT Signals
Signal Name
General Purpose Timer
Input/Output
Abbreviation
Function
GPT[3:0] Inputs to or outputs from the general purpose timer module
I/O
I/O
1.15 Pulse Width Modulator Signals
Table 15 describes the PWM signals.
Table 15. PWM Signals
Signal Name
Abbreviation
PWM Output Channels PWM[7:0]
Function
Pulse width modulated output for PWM channels
I/O
O
1.16 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM
logic.
Table 16. Debug Support Signals
Signal Name
Abbreviation
Function
I/O
JTAG Enable
Test Reset
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Development Serial
Clock
JTAG_EN
TRST
TCLK
TMS
TDI
TDO
DSCLK
Select between debug module and JTAG signals at reset
This active-low signal is used to initialize the JTAG logic
asynchronously.
Used to synchronize the JTAG logic.
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
Development Serial Clock-Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
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Signal Name
Breakpoint
MCF5213 Family Configurations
Table 16. Debug Support Signals (continued)
Abbreviation
Function
I/O
BKPT
Breakpoint - Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor
status/debug data signals (PSTDDATA[7:0]) as the value 0xF. If
CSR[BKD] is set (disabling normal BKPT functionality), asserting
BKPT generates a debug interrupt exception in the processor.
I
Development Serial
Input
DSI Development Serial Input -Internally synchronized input that provides
data input for the serial communication port to the debug module,
once the DSCLK has been seen as high (logic 1).
Development Serial
Output
DSO
Development Serial Output -Provides serial output communication for
debug module responses. DSO is registered internally. The output is
delayed from the validation of DSCLK high.
Debug Data
DDATA[3:0] Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
Processor Status Clock
PSTCLK
Processor Status Clock - Delayed version of the processor clock. Its
rising edge appears in the center of valid PST and DDATA output.
PSTCLK indicates when the development system should sample PST
and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and
PST and DDATA outputs from toggling without disabling triggers.
Non-quiescent operation can be reenabled by clearing CSR[PCD],
although the external development systems must resynchronize with
the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC,
0xD, or 0xF) occurs during system reset exception processing.
Processor Status
Outputs
PST[3:0]
Indicate core status. Debug mode timing is synchronous with the
processor clock; status is unrelated to the current bus transfer. The
CLKOUT signal can be used by the development system to know
when to sample PST[3:0].
All Processor Status
Outputs
ALLPST Logical “AND” of PST[3.0]
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Preliminary Electrical Characteristics
1.17 EzPort Signal Descriptions
Table 17 contains a list of EzPort external signals
Table 17. EzPort Signal Descriptions
Signal Name
EzPort Clock
EzPort Chip Select
EzPort Serial Data In
EzPort Serial Data Out
Abbreviation
EZPCK
EZPCS
EZPD
EZPQ
Function
Shift clock for EzPort transfers
Chip select for signalling the start and end
of serial transfers
EZPD is sampled on the rising edge of
EZPCK
EZPQ transitions on the falling edge of
EZPCK
I/O
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1.18 Power and Ground Pins
The pins described in Table 18 provide system power and ground to the chip. Multiple pins are provided
for adequate current capability. All power supply pins must have adequate bypass capacitance for
high-frequency noise suppression.
Table 18. Power and Ground Pins
Signal Name
PLL Analog Supply
Positive Supply
Ground
Abbreviation
Function
VDDPLL,
VSSPLL
VDD
VSS
Dedicated power supply signals to isolate the sensitive PLL analog
circuitry from the normal levels of noise present on the digital power
supply.
These pins supply positive power to the core logic.
This pin is the negative supply (ground) to the chip.
I/O
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2 Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the MCF5213
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5213.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however
for production silicon these specifications will be met. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this appendix supersede any values found in the
module specifications.
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Preliminary Electrical Characteristics
2.1
Maximum Ratings
Table 19. Absolute Maximum Ratings1, 2
Rating
Symbol
Value
Unit
Supply Voltage
Clock Synthesizer Supply Voltage
RAM Memory Standby Supply Voltage
Digital Input Voltage 3
EXTAL pin voltage
XTAL pin voltage
Instantaneous Maximum Current
Single pin limit (applies to all pins) 4, 5
VDD
VDDPLL
VSTBY
VIN
VEXTAL
VXTAL
IDD
– 0.3 to +4.0
– 0.3 to +4.0
– 0.3 to + 4.0
– 0.3 to + 4.0
0 to 3.3
0 to 3.3
25
V
V
V
V
V
V
mA
Operating Temperature Range (Packaged)
TA
(TL - TH)
– 40 to 85
°C
Storage Temperature Range
Tstg – 65 to 150
°C
NOTES:
1 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum
Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress
beyond those listed may affect device reliability or cause permanent damage to the device.
2 This device contains circuitry protecting against damage due to high static voltage or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD).
3 Input must be current limited to the IDD value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then
use the larger of the two values.
4 All functional non-supply pins are internally clamped to VSS and VDD.
5 Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD,
the injection current may flow out of VDD and could result in external power supply going out of
regulation. Insure external VDD load will shunt current greater than maximum injection current. This
will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must
maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions.
2.2
Power Consumption
Table 20. Low Power Stop Mode Power Consumption1
MODE
Typical2
Peak3
Units
Stop Mode 3 (Stop 11)
0.13
0.13 mA
Stop Mode 2 (Stop 10)
2.29
2.29
NOTES:
1 all values are measured with a 3.30V power supply
2 CLKOUT and all peripheral clocks except UART0 and CFM off before entering
low power mode. CLKOUT is disabled. All code executed from FLASH. Code run
from SRAM reduces power consumption further.
3 CLKOUT and all peripheral clocks on before entering low power mode. All code
is executed from FLASH. All code is executed at 80MHz clock.
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Preliminary Electrical Characteristics
Table 21. Low Power Mode Operation Power Consumption1
MODE
8MHz(Typ)2 16MHz(Typ)2 64MHz(Typ)2 80MHz (Typ)2
80MHz
(Peak)3
Units
Stop Mode 1 (Stop 01)4
2.80 3.08 4.76
5.38
5.38 mA
Stop Mode - 0 (Stop 00)
2.80 3.08 4.76 5.39 15.59
Wait / Doze
11.12
20.23
30.17
33.36
57.50
Run
12.40
22.74
39.92
45.47
69.39
NOTES:
1 all values are measured with a 3.30V power supply
2 CLKOUT and all peripheral clocks except UART0 and CFM off before entering low power mode. CLKOUT is disabled. All
code executed from FLASH. Code run from SRAM reduces power consumption further.
3 CLKOUT and all peripheral clocks on before entering low power mode. All code is executed from FLASH. All code is
executed at 80MHz clock.
4 Results are identical to STOP 00 for typical values since they only differ by CLKOUT power consumption. CLKOUT is
already disabled in this instance prior to entering low power mode.
Typical Low-Power Consumption
50.00
45.00
40.00
35.00
30.00
25.00
20.00
15.00
10.00
5.00
0.00
0
8 16 24 32 40 48 56 64 72 80
System Clock (MHz)
Stop 0 - Flash
Stop 1 - Flash
Stop 2 - Flash
Stop 3 - Flash
Wait/Doze - Flash
Run - Flash
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Preliminary Electrical Characteristics
Table 22. Power Consumption Specifications
Characteristic
Symbol
Typical
Active
(SRAM)
Typical
Active
(Flash)
Peak1
• 1 MHz core & I/O
• 8 MHz core & I/O
• 16 MHz core & I/O
• 64 MHz core & I/O
• 80 MHz core & I/O
RAM Memory Standby Supply Current
Normal Operation: VDD > VSTBY - 0.3 V
Transient Condition: VSTBY - 0.3 V > VDD >
VSS + 0.5 V
Standby Operation: VDD < VSS + 0.5 V
Analog Supply Current
Normal Operation
Low-Power Stop
IDD
ISTBY
IDDA
TBD
7.28
12.08
40.14
49.2
0
TBD
TBD
3.48
13.37
25.08
54.62
64.09
0
TBD
TBD
TBD
19.02
35.66
85.01
100.03
TBD
TBD
TBD
TBD
TBD
NOTES:
1 Peak current measured with all modules active, and default drive strength with matching load.
Unit
mA
µA
mA
µA
mA
µA
Freescale Semiconductor
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Preliminary Electrical Characteristics
2.3 Thermal Characteristics
Table 23 lists thermal resistance values
Table 23. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Junction to ambient, natural convection
100 LQFP
Four layer board (2s2p)
θJMA
531,2
°C/W
Junction to ambient (@200 ft/min)
100 LQFP
Four layer board (2s2p)
θJMA
46 °C/W
Junction to board
Junction to case
Junction to top of package
Maximum operating junction temperature
100 LQFP
100 LQFP
Natural convection
100 LQFP
θJB 273 °C/W
θJC 124 °C/W
Ψjt 25 °C/W
Tj 105 oC
NOTES:
1 θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of θJmA and power dissipation specifications in the system design to prevent
device junction temperatures from exceeding the rated specification. System designers should be aware that
device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in the
customer’s system using the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD
Standard 51-2.
2 Per JEDEC JESD51-6 with the board horizontal.
3 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
5 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written in conformance with Psi-JT.
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