34921 (Freescale Semiconductor)
Configurable Motor Driver IC

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Technical Data
Configurable Motor Driver IC
with Power Supplies
MC34921
Rev 5.0, 07/2005
34921
The 34921 power IC integrates multiple motor drivers, multiple
power regulators, and most other analog functions a small consumer
motion-enabled product needs. The 34921’s circuitry is fully protected
with current limiting, short-circuit shutdown, over-temperature, over-
voltage, and under-voltage detection. Supervisory functions can be
read and programmed through a 8-MHz Serial Interface.
A 5.0 V dual-mode (linear or switching) voltage regulator, 3.3 V
switching buck regulator, and a voltage-selectable (1.5 V, 1.8 V, 2.5 V)
linear regulator provide power management. Two H-Bridges and a
configurable motor driver are provided for controlling two dc motors
and one unipolar stepper motor.
The highly integrated 34921 brings together sensing,
communication, power management, system protection, and motor
control in one device.
Features
• Two Functionally Identical Pulse-Width Modulated (PWM) DC Motor
Drivers
• One Switching, One Linear, and One Dual-Mode Regulator
• Dual Mode Switching/Linear 5.0 V Regulator
• Supervisory Functions (Power-ON Reset and Error Reset Circuitry)
• 8-Channel, 8-Bit Analog-to-Digital Converter (ADC)
• Charge Pump for High-Side MOSFET Drive
• Complete Support for
• Analog Quadrature Encoder
• Pb-Free package is designated by suffix AE
H-BRIDGE MOTOR DRIVER
AND POWER SUPPLY
AE SUFFIX (Pb-Free)
98ARH98426A
64-LEAD LQFP-EP
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC34921AE/R2
0°C to 70°C
64 LQFP-EP
5.0 V / 3.3 V
B+
34921
Serial MISO
MCU MOSI
SCLK
Ports CE
A/D
AN0
B+
GATEOUT
5.0 V
3.3 V
VCORE
High-Side
MOSFET
ADCMA
AN3
Inputs
A
B+
APWM
B+ SA/CDCMA
B SB/LSOUT1 ADCMB
Step
Motor
C
B
A
CPWMA
CPWMB
SB/LSOUT2
SA/CDCMB
DGND
BDCMA
BPWM
BDCMB
GND
DC
Motor
A
DC
Motor
B
Figure 1. 34921 Simplified Application Diagram
*This document contains information on a product under development.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.


34921 (Freescale Semiconductor)
Configurable Motor Driver IC

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INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
B+
CP1 CP2
VBOOST
5 V SELECT
5 V SWITCH
5 V SUPPLY
5V
3.3 V SWITCH
3.3 V
VCORE SUPPLY
VCORE
VCORE SELECT
ENC_FILTB
ENC_FILTA
5.0 V
Dual Mode
Regulator
B+
3.3 V Switching
Regulator
VCORE
Linear
Regulator
I/V
Converter
Charge Pump
Gate Voltage
Generator
Thermal
Shutdown
B+
Oscillator
Motor Driver B
B+
BPWM
BDCMA
BDCMB
APWM
ADCMA
AN3/ANALOGIN_B
AN2/ANALOGIN_A
AN1/ANALOGOUT_B
AN0/ANALOGOUT_A
MISO
MOSI
SCLK
CE
GATEOUT
A /D
Converter
and
Multiplexer
Motor Driver A
Serial I/O
Gate Driver
Active Clamp
Step
Motor Driver
SS DC Motor Driver
RST
Supervisor
Circuitry
DGND
GND
Figure 2. 34921 Simplified Internal Block Diagram
ADCMB
SA /CDCMA
SA /CDCMB
SB/LSOUT1
SB/LSOUT2
CPWMA /CDCPWM
CPWMB
CDCMA /HSOUT1
CDCMB /HSOUT2
34921
2
Analog Integrated Circuit Device Data
Freescale Semiconductor


34921 (Freescale Semiconductor)
Configurable Motor Driver IC

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TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
GND
VCORE SELECT
SA/CDCMA
SA/CDCMB
SB/LSOUT1
SB/LSOUT2
B+
NC
NC
3.3V SWITCH
3.3 V
VCORE SUPPLY
VCORE
ADCMA
ADCMA
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48 GND
47 ENC_FILTA
46 ENC_FILTB
45 AN3/ANALOGIN_B
44 AN2/ANALOGIN_A
43 AN1/ANALOGOUT_B
42 AN0/ANALOGOUT_A
41 GND
40 NC
39 5 V
38 5 V SUPPLY
37 5 V SWITCH
36 5 V SELECT
35 BDCMA
34 BDCMA
33 GND
Figure 3. Terminal Function Description
Table 1. Terminal Function Description
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18
Terminal
Terminal Name
Formal Name
Definition
1, 16, 17, 24,
32, 33, 41,
48, 49, 64
2
3
4
5
6
7, 20, 21, 28,
29, 62
8, 9, 25,
40, 57
GND
VCORE SELECT
SA / CDCMA
SA / CDCMB
SB / LSOUT1
SB / LSOUT2
B+
NC
Ground
Ground.
Core Voltage Output Core voltage regulator output voltage select.
Select
Unipolar Step A/ Step Motor Output A or DC Motor C Output A.
DC Motor C Output A
Unipolar Step A/ Step Motor Output A or DC Motor C Output B.
DC Motor C Output B
Unipolar Step B/
Low-Side 1
Step Motor Output B or Low-Side Output 1.
Unipolar Step B/
Low-Side 2
Step Motor Output B or Low-Side Output 2.
Power Supply Input Motor and regulator input voltage.
No Connect
No internal connection to this terminal.
Analog Integrated Circuit Device Data
Freescale Semiconductor
34921
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TERMINAL CONNECTIONS
Table 1. Terminal Function Description (continued)
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18
Terminal
Terminal Name
Formal Name
Definition
10
11
12
13
14, 15
18, 19
22
23
26
27
30, 31
34, 35
36
37
38
39
42
43
44
45
46
47
50
51
52
53
3.3 V SWITCH
3.3 V Switching
Regulator Switch
Output
3.3 V regulator switching output.
3.3 V
3.3 V Regulator
Feedback
Feedback terminal for 3.3 V switching regulator and internal logic supply.
VCORE SUPPLY
Core Voltage
Regulator Input
Core regulator input supply.
VCORE
Core Voltage
Regulator Output
Core regulator output voltage.
ADCMA
DC Motor A Output A DC motor driver A output A.
ADCMB
DC Motor A Output B DC motor driver A output B.
VBOOST
Boost Voltage
Boost voltage storage node.
CP2 Switching Capacitor 2 Charge pump capacitor connection 2.
CP1 Switching Capacitor 1 Charge pump capacitor connection 1.
GATEOUT
High-Side MOSFET Gate driver for external N-channel switch.
Gate Driver
BDCMB
DC Motor B Output B DC motor driver B output B.
BDCMA
DC Motor B Output A DC motor driver B output A.
5 V SELECT
5.0 V Regulator Mode 5.0 V regulator operating mode select.
Select
5 V SWITCH
5.0 V Switching
Regulator Switch
Output
5.0 V switching regulator switching output.
5 V SUPPLY
5.0 V Regulator Input 5.0 V regulator input voltage.
Supply
5V
5.0 V Regulator
5.0 V regulator feedback.
Feedback
AN0/ANALOGOUT_A AN0/Analogout_A A/D input 0 or analog encoder output A.
AN1/ANALOGOUT_B AN1/Analogout_B A/D input 1 or analog encoder output B.
AN2/ANALOGIN_A
AN2/Analogin_A A/D input 2 or analog encoder input A.
AN3/ANALOGIN_B
AN3/Analogin_B A/D input 3 or analog encoder input B.
ENC_FILTB
Analog Encoder
Channel B Filter
I/V amplifier channel B filter.
ENC_FILTA
Analog Encoder
Channel A Filter
I/V amplifier channel A filter.
RST
Reset
Reset input and output.
MISO
Master In Slave Out Serial data out to MCU.
MOSI
Master Out Slave In Serial data in from MCU.
SCLK
Serial Clock
Serial data clock.
34921
4
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34921 (Freescale Semiconductor)
Configurable Motor Driver IC

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TERMINAL CONNECTIONS
Table 1. Terminal Function Description (continued)
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 18
Terminal
Terminal Name
Formal Name
Definition
54
CE
Chip Enable
Serial data strobe.
55 CPWMA/CDCPWM Motor Driver C PWM Step motor driver Phase A PWM or DC motor driver PWM.
Input A
56
DGND
Digital Ground
Digital ground.
58
CPWMB
Motor Driver C PWM Step motor driver Phase B PWM.
Input B
59
APWM
Motor Driver A PWM PWM input for DC motor driver A.
Input
60
BPWM
Motor Driver B PWM PWM input for DC motor driver B.
Input
61
CDCMB / HSOUT2
Motor Driver C DC Step motor driver C output or high-side output 2.
Motor Output or High-
Side Output 2
63
CDCMA / HSOUT1
Motor Driver C DC Step motor driver C output or high-side output 1.
Motor Output or High-
Side Output 1
Analog Integrated Circuit Device Data
Freescale Semiconductor
34921
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MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating
Symbol
Max
Unit
ELECTRICAL Ratings
Input Power Supply Voltage
IB+ = 0.0 A
Logic Input Voltage
Boost Supply Voltage
Input Power Supply Ripple Voltage
Ripple Voltage Measured at < 20 MHz
Motor Drivers A & B Maximum Output Voltage
5.0 V Linear Regulator Maximum Output Voltage
Startup
5.0 V Switching Regulator Maximum Output Voltage
Startup
3.3 V Switching Regulator Maximum Output Voltage
Startup
VCORE Linear Regulator Maximum Output Voltage
ICORE = 0.0 A
Motor Drivers A, B, and C (Motor Driver C Configured as Step Motor Driver)(1)
Motor Driver A Sink or Source Current
Motor Driver B Sink or Source Current
Motor Driver C Sink or Source Current
Motor Driver C in Step Mode Step Motor Output Current
Output x or x On
Motor Driver C in Step Mode Standoff Voltage
Output Off, IDSS = 10 mA
ESD Voltage(2)
Non-Operating, Unbiased, Human Body Model
Machine Model
Charge Device Model
B+
VIN
VBOOST
VRIPPLE B
VOUTMAX
V5.0
V5.0
V3.3
VCORE
I PWM(A)
I PWM(B)
I PWM(C)
I STEP
V BVDS
VESD
-0.3 to 38
-0.3 to V5.0+0.3
B+ +15
400
40
5.4
5.4
3.6
VCORE_NOM +10%
±4.5
±4.5
±1.5
2.0
60
± 2000
± 200
± 250
V
V
V
mVPP
V
V
V
V
V
A
A
V
V
Notes
1. B+ = 34 V, Motor Stalled and Saturated
2. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (CZAP = 200
pF, RZAP = 0 ), and the Charge Device Model.
34921
6
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MAXIMUM RATINGS
Table 2. Maximum Ratings(continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating
Symbol
Max
Unit
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Storage Temperature
Thermal Resistance
Junction to Ambient(3)
Junction to Board(4)
Junction to Case
TA
TJ
TSTG
RθJA
RθJB
RθJC
0.0 to 70
150
-55 to 150
40
14
<1.0
°C
°C
°C/W
Peak Package Reflow Temperature During Solder Mounting (5)
TSOLDER
245
°C
THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS
Power Dissipation (TA = 25° C) (6)
PD 2.0 W
Notes
3. 1s PCB test board JESD51-2 and SEMI G38-87.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured at the package
center lead foot. 2s2p test board, exposed pad soldered to PCB.
5. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
6. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used.
Analog Integrated Circuit Device Data
Freescale Semiconductor
34921
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STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 16 V B+ 34 V, 0°C TA 70°C, and 0°C TJ 100°C unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
Serial Interfaces (MISO, MOSI, SCLK, CE)
Input Low Voltage from MCU
V5.0 = 5.0 V, V3.3 = 3.3 V, IIN <200 µA, VIN Falling
Input High Voltage
V5.0 = 5.0 V, V3.3 = 3.3 V, IIN <200 µA, VIN Rising
Input Hysteresis
V5.0 = 5.0 V, V3.3 = 3.3 V
Output High-Level, MISO (V5.0 = 5.0 V, V3.3 = 3.3 V)
IOUT = 150 µA
IOUT = 20 µA
Output Low-Level, MISO (V5.0 = 5.0 V, V3.3 = 3.3 V)
IOUT < 20 µA
IOUT < 150 µA
Input Pulldown Current
V5.0 = 5.0 V, V3.3 = 3.3 V, VIN = 5.0 V, Includes RST
MISO High-Impedance Current
MISO = 3.3 V or GND
VIL
VIH
VHYS
VOH (MISO)
VOL (MISO)
IPULLDOWN
I HI-Z
1.1
1.1
0.4
2.4
V3.3 -0.1
0.0
0.0
50
-100
1.35
2.00
0.6
V3.3 -25
mV
V3.3 -10
mV
10
25
120
0.1
2.2
2.2
1.5
V3.3
V3.3
100
400
175
100
V
V
V
V
mV
µA
µA
5.0 V Linear Regulator
Logic Supply Voltage
IV5.0 = 10 mA to 50 mA, 16 V < B+ < 20 V, REXT = 140
Load Regulation
ILOAD = 10 mA to 50 mA
Current Limit Threshold
REXT = 0
V5.0 to Turn On/Off V3.3 Regulator (7)
Hysteresis for V5_3.3t (7)
Notes
7. See Figure 10, Power-Up Sequencing, page 22.
V5.0
VILOAD
I LIMIT
V5_3.3 t
V5_3.3 t_hys
4.8
75
5.0 5.2
V
mV
±100
mA
135 600
2.2 –
V
175 – mV
34921
8
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Configurable Motor Driver IC

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STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 16 V B+ 34 V, 0°C TA 70°C, and 0°C TJ 100°C unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
5.0 V Switching Regulator
Vreg Threshold
Cycle-by-Cycle Current Limit Threshold
V5.0 = 2.0 V to Max
V5.0 1.0 V
V5.0 to Turn On/Off V3.3 Regulator (8)
Hysteresis for V5_3.3t (8)
3.3 V Switching Regulator
V5.0
I LIMIT
4.8 5.0 5.2
0.75 1.2 2.25
– 1.0 –
V
A
V5_3.3 t – 2.2 –
V
V5_3.3 t_hys
175
mV
Vreg Threshold
Cycle-by-Cycle Current Limit Threshold
V3.3 = 2.0 V to Max
V3.3 1.0 V
V3.3
I LIMIT
3.15
2.75
3.28
3.6
3.5
3.45
5.5
V
A
VCORE 3.3V Linear Regulator
Voltage Tolerance
ICORE = 0.02 A to 0.3 A, VNOM = 2.5 V
ICORE = 0.02 A to 0.3 A, VNOM = 1.8 V
ICORE 0 0.02 A to 0.3 A, VNOM = 1.5 V
Load Regulation
ILOAD = 20 mA to 300 mA
Current Limit Threshold
Motor Drivers in DC Mode
Motor Driver A High- or Low-Side Switch Voltage Drop
IPWM = 1.7 A, GND or B+ to Output
Motor Driver A Output Current Limit
Motor Driver B High- or Low-Side Switch Voltage Drop
IPWM = 2.0 A, GND or B+ to Output
Motor Driver B Output Current Limit
Motor Driver C High- or Low-Side Switch Voltage Drop
IPWM = 0.375 A, GND or B+ to Output
Motor Driver C Current Limit—Top Side
Motor Driver C Current Limit—Bottom Side
Notes
8. See Figure 10, Power-Up Sequencing, page 22.
VCORE_TOL
VILOAD
I LIMIT
2.35
1.675
1.4
400
VDROP(A)
I LIMIT(A)
VDROP(B)
I LIMIT(B)
VDROP(C)
I LIMIT1(C)
I LIMIT2(C)
3.6
2.8
0.75
1.0
2.49
1.78
1.49
2.66
1.925
1.6
±10 ±100
750 1200
.65 1.5
4.9 7.2
.70 1.4
4.9 7.2
.75 1.5
1.2 1.5
1.65 2.0
V
mV
mA
V
A
V
A
V
A
A
Analog Integrated Circuit Device Data
Freescale Semiconductor
34921
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STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 16 V B+ 34 V, 0°C TA 70°C, and 0°C TJ 100°C unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
Motor Drivers in DC Mode (cont)
Output MOSFET Leakage Current
VGS = 0.0 V, VO = 0.0 V or 20 V
Current Limit Maximum Duty Cycle(9)
Current Limit Pulse Width(9)
Motor Driver C in Step Mode
Switch Voltage Drop, Output to Ground
ISTEP = 0.375 A, GND to Output
Step Motor Current Limit
B+ = 20 V
Voltage at Which Internal Clamp Activates
IDSS = 1.0 mA, B+ = 20 V
Tested Maximum High-Voltage Leakage Current
VS = VCLAMP +4.0
Any Step Driver Output Leakage Current to Ground
B+ = 20 V, VS = 20 V
Current Limit Maximum Duty Cycle
Current Limit Pulse Width
Vb Charge Pump
Boost Voltage
IB = 0.5 mA
I DSS
µA
– 0.1 ±40
IDCLIMIT
1.0
2.0
4.0
%
I LIMITPW
0.5
1.5
6.0
µs
VSDROP
V
– 1.5
I STEP(LIMIT)
1.0 – 2.0
VCLAMP
44 51 59
A
V
I BREAKDOWN
0.5 40
µA
I LEAKAGE
0.1 40
µA
tdILIMIT 5.0 11 15 %
I LIMITPW
5
10 20 µs
Vb V
B+ + 10
B+ + 11.5
B+ +15
External N-FET Gate Drive Output
GATEOUT High Output
IOH = 4.0 mA
IOH = 200 µA
VOH2
Vb - 6.0
Vb - 0.3
Vb - 2.5
Vb - .1
Vb
Vb
V
GATEOUT Low Output
IOL = -200 µA
VOL V
– 0.1 0.3
Notes
9. Motor driver A, B, C Top Side only. For C Bottom Side, see Motor Driver C in Step Mode: Current Limit Maximum Duty Cycle and Current
Limit Pulse Width
34921
10
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STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 16 V B+ 34 V, 0°C TA 70°C, and 0°C TJ 100°C unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
Supervisor Circuitry
Minimum Function B+ for Charge Pump, Oscillator Up
Reset/Fault Registers Valid (10)
B+ V
9.0 –
Minimum Function V5.0 for RST Operational
RST VOL 0.05 V @ 1.0 mA (10)
Minimum Function V3.3 for RST Operational
RST VOL 0.05 V @ 1.0 mA (10)
RST Low Voltage (11)
IRST 5.0 mA
RST V5.0 Threshold
V5.0 Rising
V5.0 Falling
RST Hysteresis for V5.0
RST V3.3 Threshold
V3.3 Rising
V3.3 Falling
RST Hysteresis for V3.3
RST VCORE Threshold
VCORE Falling
RST Hysteresis for VCORE
Overtemperature Junction Temperature(12)
TJ Rising
Overtemperature Hysteresis(12)
TJ Falling
Thermal Warning (12)
B+ Undervoltage Threshold to Assert RST
V5.0 = +5.0 V, B+ Falling
B+ Undervoltage Threshold Hysteresis(13)
Minimum B+ Necessary to Clear B+ Fault
V5.0 = +5.0 V, B+ Rising
V5.0 RST
V3.3 RST
VOL
2.0
2.0
V5.0 t+
V5.0 t
VHYSV5.0
4.5
10
V3.3 t+
V3.3 t
VHYS_3.3
2.8
10
VCORE
VHYS CORE
TJ (OVER)
TJ (HYS)
TW
B+(FAULT)
B+FAULT (HYS)
B+ RECOVERY
85
140
10
TJ -30
12
1.0
0.1
4.65
4.6
50
2.9
2.9
15
86
10
12.75
1.5
0.25
4.75
4.70
3.15
3.0
90
30
TJ -20
13.5
2.0
15.25
V
V
V
V
mV
V
mV
% VCORE_
NOM
mV
°C
°C
°C
V
V
V
Notes
10. If any of these conditions for this not is true, then RST is activated until all operating conditions are met.
11. The RST terminal uses an external pull-up, which may be to 5.0 V or 3.3 V.
12. Guaranteed by design.
13. Alternately, the minimum B+ fault threshold voltage must not be lower than 12 V, and the B+ fault clear voltage must not be higher than
15.25 V. The hysteresis may be greater than 2.0 V if this requirement is met.
Analog Integrated Circuit Device Data
Freescale Semiconductor
34921
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STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 16 V B+ 34 V, 0°C TA 70°C, and 0°C TJ 100°C unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
Analog Encoder Interface Current-to-Voltage Conversion Stage
Minimum Offset Current
Midpoint Offset Current
Maximum Offset Current
Offset Step Size (1 LSB)
Analog-to-Digital Converter
I OFFSET_MIN
I OFFSET_MID
I OFFSET_MAX
I OFFSTEP
- 6.0
- 0.5
6.0
0.25
- 8.0
0.0
8.0
0.5
-10
0.5
10
0.75
µA
µA
µA
µA
Resolution, No Missing Codes
ADC
– – 8.0 Bits
Measurement Range for Correct Conversion
Linearity Error (16)
Over Input Voltage Range of 4% to 96% Ideal Measurement Range
(IMR) max. Over Time and Temperature (14), (15)
VIN = -0.5 to 5.5 V (17)
Input Leakage Current (ANx)
V5.0 = 5.0 V, TJ = 25°C, VANx = 5.0 V, ANALOG_TEST MODE = 0,
Channel Not Selected
IMR
INL
I LEAKAGE
0.0
– 5.0 V
0.4 ±1.0 LSB
µA
0.1 10
Notes
14. Errors include effects of multiplexer and sample and hold circuitry, including droop.
15. The Linearity Error is the worst case error caused by the differential and integral nonlinearity.
16. An LSB (least significant bit) is defined as follows:
LSB = IMR Volts
2#BITS -1
Where:
IMR is the Ideal Measurement Range.
#BITS is the resolution of the ADC.
17. The ADC will read full scale at VIN = 5.0 V. If VIN on one input exceeds this value, the value of other inputs may become unreadable.
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STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 16 V B+ 34 V, 0°C TA 70°C, and 0°C TJ 100°C unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
Analog-to-Digital Converter (cont)
Zero Error (18), (19)
Zero Error Drift
Over Time and Temperature (18)
EZ
± 1.0
± 8.0
LSB(20)
EZD LSB
– ±4.0 –
Full Scale Error (18), (19), (21)
EFS
± 2.0
± 8.0
LSB
Notes
18. Errors include effects of multiplexer and sample and hold circuitry, including droop.
19. The Zero Error is defined as the number of LSB values away from the ideal value of 1/2 LSB that the ADC output count will transition
from 0 to 1 when the input is swept through the range of interest. The transition must occur within the specified range.
111 Zero Error
110 Ideal Transfer
101 Characteristic
100
011
Actual Transfer
010 Characteristic
001
000
01234567
Input Voltage
111 Full Scale Error
110 Ideal Transfer
101 Characteristic
100
011
Actual Transfer
010 Characteristic
001
000
01234567
Input Voltage
Differential
111 Nonlinearity
Integral
111 Nonlinearity
110 110
101 101
100 100
011 011
010 010
001 001
000
01234567
Input Voltage
000
01234567
Input Voltage
20. An LSB is defined as follows:
LSB = IMR Volts
2#BITS -1
Where:
IMR is the Ideal Measurement Range.
#BITS is the resolution of the ADC.
21. The Full Scale Error is defined as the number of LSB values away from the ideal value of -1/2 LSB from Full Scale that the ADC output
count actually transitions from -1 LSB count to Full Scale count when the input voltage is swept through the voltage range of interest.
The transition must occur within the specified range.
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DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 16 V B+ 34 V, 0°C TA 70°C, and 0°C TJ 100°C unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
Serial Interface Timing(22)
Setup Time for CE to rising edge of SCLK (CL = 50 pF)
Hold Time for CE after rising edge of SCLK (CL = 50 pF)
Setup Time for MOSI to rising edge of SCLK (CL = 50 pF)
Hold Time for MOSI after rising edge of SCLK (CL = 50 pF)
Delay for MISO valid after rising edge of SCLK (CL = 50 pF)
Period for SCLK (CL = 50 pF)
Duty Cycle of SCLK
5.0 V Switching Regulator
t setup (CE)
15
– ns
t hold (CE)
15
– ns
t setup (MOSI)
15
– ns
t hold ( MOSI)
15
– ns
t delay (MISO)
35 55 ns
t period (SCLK)
125
750 ns
tduty (SCLK)
45
55 %
Switching Rise and Fall Time
Load Resistance = 100 , B+ = 18 V
tr, tf ns
10 30 50
3.3 V Switching Regulator
Switching Rise and Fall Time
Load Resistance = 100 , B+ = 18 V
tr, tf ns
10 16 50
Motor Drivers
Motor Drivers A and B Output Waveform Rise Time
R = 7.0 , VDCX = (5.0 V) to (0.90 x B+), B+ = 18 V
tr ns
100 175 300
Motor Driver C Output Waveform Rise Time
R = 25 , VDCX = (5.0 V) to (0.90 x B+), B+ = 18 V
tr ns
100 175 300
Output Waveform Fall Time
VDCX = (0.90 x B+) to 5.0 V, R = 7.0 , B+ = 18 V
Crossover Dead Time (23)
Motor Driver C in Step Mode
tf
t dead
ns
100 – 300
15
600 2000
ns
Output Rise Time
VXPHASE = 5.0 V to 0.90 x B+, Rw = 20 , B+ = 18 V
tr ns
100 175 350
Output Fall Time
VXPHASE = 0.90 x B+ to 5.0 V, Rw = 20 , B+ = 18 V
tf ns
100 155 350
Delay from Phase Turn-Off to Counterphase Turn-On
Rw = 20 , 0.90 x B+ Rising to 0.90 x B+ Falling, B+ = 18 V Falling
tdelay (C)
0.0
300 400
ns
Notes
22. See Figure 4, Serial Interface Timing, page 16.
23. This parameter is guaranteed by design but not production tested.
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DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 16 V B+ 34 V, 0°C TA 70°C, and 0°C TJ 100°C unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
Supervisor Circuitry
RST Delay
V5.0 = +4.9 V (24)
tdelay (RST)
RST Filter Time
V5.0 = 5.0 V
t filter
RST Fall Time
V5.0 = 5.0 V, CL = 100 pF, IPULLUP = 0.75 mA(external), 90% to 10% of
V5.0
tf
External Input Low to RST Pulled Low
V5.0 = 5.0 V (25)
t slpl
128
3.25
7.0
26
tSCLK
128
µs
ns
20
ns
60
Analog Encoder Interface Variable Gain Stage
Adjustable Gain (Ideal)
Settings S = 0 to 15, Default 0
Settings S = 16 to 31, Default 0
Gain
Setting = 0
Setting = 31
Gain Step Factor Tolerance
Gain Step Size Gs/G(s-1) S = 1 to 31
Analog Encoder Interface Digital Signal Conversion Stage
Operating Frequency
Comparator Filter Time(24)
Filter Configuration Bit Set to 0
Filter Configuration Bit Set to 1
ADC
Sample and Hold Acquisition Time
A/D Speed Bit = 0
A/D Speed Bit = 1
Conversion Time (Return Word Clocked Out Immediately Following tc )
A/D Speed Bit = 0
A/D Speed Bit = 1
Master Oscillator
Operating Frequency
B+ 12 V
Notes
24. Guaranteed by design.
25. See Figure 6, RST Timing, page 17.
G (Ideal)
G
GSF
(1.0+0.1 * S)
(1.0+0.1 * [S-16]) / 0.375
V/V
0.8 1.0 1.2
6.0 6.6 7.2
V/V
1.01 1.02
1.2
f OP(MAX)
0
– 15 kHz
t filter
SCLK
3.0 – 4.0 Cycles
6.0 – 7.0
tsh tSCLK
15 – 16
31 32
tc tSCLK
– – 48
– – 96
fOP kHz
150 200 250
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TIMING DIAGRAMS
TIMING DIAGRAMS
90% B+
90% B+
Figure 4. Serial Interface Timing
tdelay (C)
A or B Output
Figure 5. Step Motor Crossover Delay Timing
A or B Output
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External
RST
Input
VIH
VIL
34921
RST
VIH
VIL
t slpl
tdelay (RST)
Figure 6. RST Timing
TIMING DIAGRAMS
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FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The serial interface of the MC34921 is a three input, one
output interface similar to a Serial Peripheral Interface (SPI)
port in general form, but different in specific clocking
requirements due to the fact that an A/D converter cannot
reliably run without a continuous clock. The 34921 serial
interface communicates to a microcontroller unit (MCU) at up
to 16 MHz. The serial signals are SCLK, CE, MOSI, and
MISO. The SCLK signal pin requires a free-running clock (up
to 16 MHz) which is provided by the MCU. This signal is
required to ensure proper operation of both the ADC and the
reset timer circuitry. The serial data transfers between the
MCU and the 34921 via the MOSI and MISO terminals. The
serial data from the MCU is handled in the MC34921 via two
input registers -- the NORMAL input register contains bits
controlling the motor drivers as well as the A/D converter, and
the CONFIG register contains bits relating to the general
configuration setup of the device. The MC34921 also has two
output registers -- the NORMAL output register reports A/D
conversion data as well as digital encoder data, and the IREQ
output register reports under voltage, temperature, and other
device status data.
FUNCTIONAL TERMINAL DESCRIPTION
GROUND (GND)
Main ground. It is used for the B+ filters and motor filter
grounds, as well as the ground return for external
components which are used with the linear and switching
regulators.
COVER VOLTAGE OUTPUT SELECT (VCORE
SELECT)
This terminal is used to select the output voltage provided
by the VCORE linear regulator. The VCORE Select potential
is latched in during the MC34921's power-on sequence. The
MC34921 will not respond to changes in VCORE Select after
power up.
UNIPOLAR STEP A/DC MOTOR C OUTPUT A (SA/
CDCMA)
A low-side driver output is configurable for either stepper
motor control (SA) or C DC motor (as CDCMA, which
requires an external hardwire to pin 63) via the serial I/O. The
driver is PWM controlled via the CPWMA/CDCPWM pin, and
direction controlled via the Serial I/O. It includes an active
voltage clamp, current limit, and thermal shutdown
protection.
UNIPOLAR STEP A/DC MOTOR C OUTPUT B (SA/
CDCMB)
A low-side driver output is configurable for either stepper
motor control (SA) or C DC motor (as CDCMB, it requires
external hardwire to pin 61) via the serial I/O. The driver is
PWM controlled via the CPWMA/CDCPWM pin, and
direction controlled via the Serial I/O. It includes active
voltage clamp, current limit, and thermal shutdown
protection.
UNIPOLAR STEP B/LOW-SIDE 1 (SB/LSOUT1)
A low-side driver output is configurable for either stepper
motor control (SB) or as a general purpose low-side driver
(LSOUT1) via the serial I/O. The SB is PWM controlled via
the CPWMB pin. The direction and LSOUT1 are controlled
via the serial I/O. It includes active voltage clamp, current
limit and thermal shutdown protection.
UNIPOLAR STEP B/LOW-SIDE 2 (SB/LSOUT2)
A low-side driver output is configurable for either stepper
motor control (SB) or as a general purpose low-side driver
(LSOUT2) via the serial I/O. The SB is PWM controlled via
the CPWMB pin. The direction and LSOUT2 are controlled
via the serial I/O. It includes active voltage clamp, current
limit and thermal shutdown protection.
POWER SUPPLY INPUT (B+)
This is the main power supply input for the regulators and
DC motor drivers.
3.3 V SWITCHING REGULATOR SWITCH OUTPUT
(3.3 V SWITCH)
The high-side driver output is used for the 3.3v switching
regulator. It uses the internal 200KHZ clock.
3.3 V REGULATOR FEEDBACK (3.3 V)
This terminal is the error amp feedback for the 3.3v
switching regulator. It is also the output point for the 3.3v
switching supply.
CORE VOLTAGE REGULATOR INPUT (VCORE
SUPPLY)
The input voltage terminal for the VCORE linear supply,
which is usually provided by externally hardwiring the 3.3v
switching regulator output.
CORE VOLTAGE REGULATOR OUTPUT (VCORE)
The output terminal of the VCORE linear regulator.
Voltage options of 1.5v, 1.8v, or 2.5v are set by the potential
of the VCORE Select pin at power up. It features current limit
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FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
and thermal shutdown protection. It is typically used to supply
a micro processor core or embedded DRAM.
DC MOTOR A OUTPUT A (ADCMA)
A high-side and low-side driver output terminal, which
when combined with ADCMB forms the A H-bridge DC motor
driver. The driver is PWM controlled via the APWM input, and
direction controlled via the Serial I/O. It features current limit
and thermal shutdown protection.
DC MOTOR A OUTPUT B (ADCMB)
A high-side and low-side driver output terminal, which
when combined with ADCMA forms the A H-bridge DC motor
driver. The driver is PWM controlled via the APWM input and
direction controlled via the Serial I/O. It features current limit
and thermal shutdown protection.
BOOST VOLTAGE (VBOOST)
This is the boost voltage storage node for the charge pump
circuit. It provides the gate drive voltage for the high-side
FETS in the DC motor drivers, switch mode controllers, and
Gateout pin.
SWTICHING CAPACITOR (CP1 AND CP2)
These are the connections for the charge pump flying
capacitor.
HIGH-SIDE MOSFET GATE DRIVER (GATEOUT)
The output terminal for an external N-channel high-side
driver. Enabled via the Serial I/O, it provides gate drive
control for an external N-channel MOSFET high-side switch.
DC MOTOR B OUTPUT B (BDCMB)
A high-side and low-side driver output terminal, which
when combined with BDCMB, forms the B H-bridge DC motor
driver. The drivers are PWM controlled via the BPWM input,
and direction controlled via the Serial I/O. It features current
limit and thermal shutdown protection.
DC MOTOR B OUTPUT A (BDCMA)
A high-side and low-side driver output terminal, which
when combined with BDCMA, forms the B H-bridge DC motor
driver. The drivers are PWM controlled via the BPWM input,
and direction controlled via the Serial I/O. It features current
limit and thermal shutdown protection.
5.0 V REGULATOR MODE SELECT (5 V SELECT)
This terminal is used to set the 5v regulator to operate in
either linear or switching mode. Ground this terminal to
operate in switching mode, or float to operate in linear mode.
5.0 V REGULATOR SWITCH OUTPUT (5 V SWITCH)
This terminal is the high-side driver output used for the 5v
switching regulator. It uses the internal 200KHZ clock.
5.0 V REGULATOR INPUT SUPPLY (5 V SUPPLY)
The input voltage terminal for the 5v regulator. Limit it to
20v in linear mode. An additional series resistor is
recommended to dissipate power off-chip.
5.0 V REGULATOR FEEDBACK (5 V)
This is the 5v feedback input terminal and output voltage
point for the 5v regulator when in the switch configuration,
and the output pin when tied to 5v SWITCH in linear
configuration. It is also the power supply terminal for the
MC34921AE on board logic.
AN0/ANALOGOUT_A (AN0/ANALOGOUT_A)
Mux input 0 for the A/D converter, which is also available
in Freescale test mode as an output for the AN2 I/V
converter.
AN1/ANALOGOUT_B (AN1/ANALOGOUT_B)
Mux input 1 for the A/D converter, which is also available
in Freescale test mode as an output for the AN3 I/V
converter.
AN2/ANALOGIN_A (AN2/ANALOGIN_A)
Mux input 2 for the A/D converter incorporating an I/V
converter with offset and gain calibration via the Serial I/O.
AN3/ANALOGIN_B (AN3/ANALOGIN_B)
Mux input 3 for the A/D converter incorporating an I/V
converter with offset and gain calibration via the Serial I/O.
ANALOG ENCODER CHANNEL B FILTER
(ENC_FILTB)
Input to the AN3 I/V converter stage for feedback
components used with the I/V converter op amp.
ANALOG ENCODER CHANNEL A FILTER
(ENC_FILTA)
Input to the AN2 I/V converter stage for feedback
components used with the I/V converter op amp.
RESET (RST)
Supervisory function I/O, incorporating a comparator input
and an open drain output, and typically connected to the RST
of a microprocessor. As an input, RST resets internal
registers to default states, turns step motor outputs off, forces
DC motor drive low-side drives on, and sets MISO to a high
Z state. As an output, RST is set during B+ UVLO, all
regulators UVLO, current limit, and thermal shutdown events.
MASTER IN SLAVE OUT (MISO)
This is the master-in-slave-out terminal; the serial output
port of the Serial I/O, which typically connects to the MISO of
a microprocessor. MISO reports two data frames: NORMAL
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FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
- A/D conversion and analog encoder signals, and INFO -
Fault data and analog encoder signals.
The output data is loaded into the output shift register on
each rising edge of SCLK, while CE is held in a logic high
state. This means the MISO pin shows the status of the most
significant bit (bit 15) of the output frame until the first rising
edge of SCLK after the CE pin is taken to a logic low state.
The shift register will then shift data out on the MISO pin on
each subsequent rising edge of SCLK while CE is held in the
logic low state. During transfers, the most significant bit
(MSB) is transferred first. After all 16 bits have been
transferred, if any additional clocks are given while CE is in a
logic low state, the data is undefined and should be ignored.
MASTER OUT SLAVE IN (MOSI)
This is the master-out-slave-in terminal; the serial input
port of the Serial I/O, which typically connects to the MOSI of
a microprocessor. It has two frames of operation - NORMAL
and CONFIG, which are set by a bit in the NORMAL
frame.The MOSI pin is used for serial instruction data input.
MOSI information is clocked into the input shift register on the
rising edge of SCLK. A logic high state present on MOSI will
program a register bit on. The specific bit will turn on with the
16th rising edge of SCLK after placing the CE pin in a logic
low state. Conversely, a logic low state present on the MOSI
pin will program the register bit off. The specific bit will turn off
with the 16th rising edge of SCLK after placing the CE pin in
a logic low state. For each rising edge of the SCLK while CE
is logic low, a data bit instruction (on or off) is loaded into the
shift register per the data bit MOSI state. The last bit clocked
in (bit 0) is the CONFIG bit. If this bit is in a logic high state at
the 16th rising edge of SCLK after lowering the CE pin, the
bits in the shift register will be loaded into the CONFIG
register. If the bit is in a low logic state, the bits will be loaded
into the NORMAL register. Care should be taken to keep the
MOSI pin in a logic low state when it is not being used for
transfers to avoid erroneous data. During transfers, the most
significant bit (MSB) is clocked in first.
SERIAL CLOCK (SCLK)
As the serial clock terminal, the SCLK pin clocks the
internal shift registers of the MC34921. The serial data input
(MOSI) pin data is latched into the input shift register on the
rising edge of the 16th clock after the falling edge of the chip
select (CE) pin. The serial data output (MISO) pin shifts data
out of the shift register on the rising edge of the SCLK signal.
False clocking of the shift register must be avoided to ensure
validity of data. It is essential that one rising edge of SCLK
occur while CE is in a logic high state to ensure the correct
output data is latched into the output shift register. Clocking
the SCLK pin for more than one clock period while CE is in a
logic high state is not recommended and may have undesired
effects. For this reason, it is recommended that the SCLK pin
be clocked only once while CE is in a logic high state. The
MC34921 is designed such that SCLK should be a
continuous clock. This ensures that A/D sample rates are
held as constant as possible.
CHIP ENABLE (CE)
The chip enable port of the Serial I/O, typically connects to
the CE of a microprocessor. The logic state of the CE pin
activates clocking in and shifting out of data in and out of the
MC34921. While the CE pin is in the logic high state, the
output data in the NORMAL registers and the INFO registers
are latched (depending on the state of the IREQ bit in the
previous communication frame) in on each rising edge of the
clock such that the state of the MSB (bit 15) is readable on
the serial data output (MISO) pin. When CE is in a low logic
state both the input shift register and output shift register shift
data at the rising edge of SCLK.
MOTOR DRIVER C PWM INPUT A (CPWMA /
CDCPWM)
This is the PWM logic input for the SA/SA/CDCM motor
drivers. The motor driver outputs follow this signal.
MOTOR DRIVER C PWM INPUT B (CPWMB)
This is the PWM logic input for the SB/SB motor drivers.
The motor driver outputs follow this signal.
DIGITAL GROUND (DGND)
This terminal is used for the Serial I/O and A/D converter
logic grounds, and should be kept isolated from the Analog
ground on the application PCB.
MOTOR DRIVER A PWM INPUT (APWM)
The PWM logic input terminal for the ADCM motor drivers.
The motor driver outputs follow this signal.
MOTOR DRIVER B PWM INPUT (BPWM)
The PWM logic input terminal for the BDCM motor drivers.
The motor driver outputs follow this signal.
MOTOR DRIVER C STEP MOTOR OUTPUT OR
HIGH-SIDE OUTPUT 2 (CDCMB / HSOUT2)
The high-side driver output is configurable for either C DC
motor control (as CDCMB, it requires external hardwire to pin
4), or as a general purpose high-side driver (HSOUT2) via the
serial I/O. The CDCMB is PWM controlled via the CPWMA/
CDCPWM pin. The direction and HSOUT2 are controlled via
the serial I/O. It includes current limit and thermal shutdown
protection.
MOTOR DRIVER C STEP MOTOR OUTPUT OR
HIGH-SIDE OUTPUT 1 (CDCMA / HSOUT1)
The high-side driver output is configurable for either C DC
motor control (as CDCMA, it requires external hardwire to pin
4), or as a general purpose high-side driver (HSOUT1) via the
serial I/O. The CDCMA is PWM controlled via the CPWMA/
CDCPWM pin. The direction and HSOUT1 are controlled via
the serial I/O. It includes current limit and thermal shutdown
protection.
34921
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FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
3.3 V Regulator
Switching
DC Motor
Drivers
5.0 V Regulator
Switching and
Linear
Step
Motor Driver
V Core
Linear Regulator
Charge
Pump
Supervisory
RST Function
A/D
Convertor
Timing
Logic
Figure 7. Internal Block Diagram
5.0 V AND 3.3 V REGULATORS
The 34921 5.0 V regulators have two operating modes—
switching and linear—that share a dedicated input terminal,
as illustrated in Figure 8 and Figure 9. The 5.0 V switching
regulator operates off B+ directly. The 5.0 V linear regulator
is only used when B+ < 20 V, and the dedicated input
terminal is connected to B+ through an external power
resistor to dissipate some power off-chip. The regulator that
is used depends on the power requirement and B+NOM of the
application. The designer is able to trade off power versus
overall system cost for each particular application. The linear
regulator mode is a low-current mode and has much less
external component cost.
34921
5V SUPPLY
B+
5V
5V SWITCH
5V SELECT
34921
5V SUPPLY
5V
B+
R
5V SWITCH
5V SELECT
B+ - 9.0 V
R=
IOUT
Figure 9. 5.0 V Linear Regulator Mode
The 5V SELECT terminal must be tied to ground for
switching regulator mode. An internal pull-up is incorporated
in the 34921 sufficient to avoid any problems owing to
switching noise on this terminal.
The 5.0 V switching and linear regulators may supply
external logic components of the overall assembly,
depending on the application. For the 5.0 V linear regulator,
an external capacitor on the output should be used for
filtering.
Figure 8. 5.0 V Switching Regulator Mode
5.0 V AND 3.3 V SWITCHING REGULATORS
The 5.0 V and 3.3 V switching regulators are implemented
as constant ripple buck regulators. These regulators operate
in both discontinuous and continuous mode. The clock
source is the on-board 200 kHz master oscillator. The actual
frequency of the switch terminal can vary owing to cycle
skipping. The switch MOSFET is internal to the 34921 IC, but
the remaining components—recovery diode, inductor, and
output capacitor—must be externally supplied. The input
voltage to the regulators is B+, and the regulators perform
within specifications over the range of I5.0 0.6 A for the
5.0 V switching regulator and I3.3 2.5 A for the 3.3 V
switching regulator. Each has cycle-by-cycle current limiting.
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FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The power up sequence of the 5.0 V and 3.3 V switching
regulators is controlled such that -1.0v <= V5 - V3.3 <= 2.6v.
Figure 10 depicts the power-up sequence for the 5.0 V and
3.3 V regulators.
V5.0 < V5_3.3t
V5.0 V5_3.3t
3.3 V Positive
Threshold
3.3 V Start
3.3 V Reg ON
Ref = 2.5 V
5.0 V Reg ON
3.3 V Positive
Threshold
Power-Up
5.0 V Reg ON
Ref = 2.5 V
3.3 V Reg OFF
5.0 V 3.3 V
Undervoltage (UV)
5.0 V Fault
5.0 V Reg ON
3.3 V Reg OFF
V5.0 V5_3.3t
& 3.3 V > 3.3 V UV
Full Start
Ref = 5.0 V
3.3 V Reg ON
5.0 V Reg ON
V5.0 V5_3.3t
Figure 10. Power-Up Sequencing
VCORE LINEAR REGULATOR
The output voltage of the VCORE linear regulator is
selectable for different applications. The output is selected
with an external pull-up or pull-down, which instructs internal
logic to select the appropriate regulator set-point (refer to
Table 5). The VCORE linear regulator is available whenever
the 3.3 V supply is in stable operation.
Current limiting is implemented to provide short circuit
protection. The VCORE linear regulator is shut off by the local
thermal shutdown sensor, thus protecting the 34921 IC from
an over-temperature condition resulting from a VCORE short
circuit, but otherwise allowing VCORE to follow the 3.3 V
switching regulator.
The VCORE SUPPLY terminal is the drain or collector of
the linear regulator transistor and must be tied to the 3.3V
terminal to use the internal regulator. This allows the option
of using an external regulator if the internal 3.3 V regulator
cannot supply enough current for a particular application.
Use of an external regulator requires leaving this terminal
open, thus disabling the internal regulator. The output of the
external regulator is then connected to the VCORE terminal
for under-voltage monitoring.
Table 5. VCORE Regulator Output Voltage Select
VCORE SELECT
VCORE_NOM
(Volts)
Tied to Ground terminal
Tied to 3.3V terminal
Floating
1.5
1.8
2.5
DC MOTOR DRIVERS
There are two DC motor drivers on the 34921 IC: if used in
a printer application, for example, they might be the carriage
motor driver and the paper motor driver. A third drive, Motor
Driver C, can be configured as a DC motor driver or, when
B+NOM = 18 V, as a step motor driver (refer to succeeding
paragraph Step Motor Driver). Configuration bit 13
determines the mode: 0 = step mode, 1 = DC mode. A step
motor driver can only be used in B+ = 12 V to 20 V
applications. Step motor outputs are suppressed by the
internal supervisor for B+ > 20 V. The ability to use the low-
side MOSFETs for general purpose low-side outputs is
included when the system is in DC motor mode (LSOUTx).
Alternatively, the ability to use the high-side MOSFETs for
general purpose high-side outputs (HSOUTx) has been
included when the system is in step mode. (Refer to
Table 20, page 31, and Table 21, page 32.)
The DC motor drivers are pulse width modulated (PWM’d)
via inputs from the digital subsystem on the APWM and
BPWM terminals, respectively. This signal is approximately
20 kHz to 40 kHz. The DC motor driver bridge direction may
be reversed while there is significant current flowing in the
motor. The purpose of this action is to brake the motor by
rapidly lowering the current. There are pull-downs on the
PWM input terminals so that, in the event of a connection
failure, the driver will default to a safe condition.
The DC motor drivers provide high-side and low-side
current limiting. The current limits have a 0.5 µs to 6.0 µs
deglitch filter, followed by an off-timer. The off-timer shuts off
the bridge long enough to meet the 4% duty cycle goal. The
motor drivers also have thermal shutdown protection.
STEP MOTOR DRIVER C
Step motor driver C can be configured as a DC motor
driver or, when B+NOM = 18 V, as a step motor driver (refer to
succeeding paragraph Step Motor Driver). Configuration
bit 13 determines the mode: 0 = step mode, 1 = DC mode.
The ability to use the low-side MOSFETs for general purpose
low-side outputs is included when the system is in DC motor
mode (LSOUTx). Alternatively, the ability to use the high-side
MOSFETs for general purpose high-side outputs (HSOUTx)
has been included when the system is in step mode. (Refer
to Table 20, page 31, and Table 21, page 32.)
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FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Step motor driver C is PWM’d via an input from the digital
subsystem on the CPWMA/CDCPWM terminal. This signal is
approximately 20 kHz to 40 kHz. There are pull-downs on the
PWM input terminals so that DC motor drive C will default to
a safe condition in the event of a connection failure.
STEP MOTOR DRIVER
A step motor driver can be configured as a DC motor driver
(refer to preceding paragraph DC Motor Drivers) or, when
B+NOM 20 V, as a unipolar step driver. Serial input
configuration frame bit 4 determines the mode: 0 = step
mode, 1 = DC mode. A step motor driver will only be used in
B+ = 12 V to 20 V applications.
Note It is possible to use the step motor driver with
B+ > 20 V if the step motor is driven from a separate supply
that is 20 V.
The step motor driver on the 34921 is a unipolar, voltage-
mode wave drive circuit employing synchronous rectification.
The centertap of each phase-counterphase pair is connected
to B+.
Two PWM signals are sent directly from the digital
subsystem. The CPWMA/CDCPWM terminal provides the
PWM signal for the A and A outputs. The CPWMB terminal
provides the PWM signal for the B and B outputs. The step
motor driver employs synchronous rectification to control
substrate currents. In synchronous rectification, when an
output is turned off, the counterphase output MOSFET is
turned on to maintain current continuity. In order to avoid a
large shoot-through current, there is a dead time delay
(tdelay) between phase off and counterphase on. Refer to
Figure 5, Step Motor Crossover Delay Timing, page 16.
VBOOST CHARGE PUMP
The high-side MOSFETs in the DC motor H-bridges and
the external GATEOUT switch need a gate voltage in excess
of B+, which is provided by the VBOOST supply. The
VBOOST regulator is a charge pump, switching directly off
the B+ supply and operating at 200 kHz.
EXTERNAL N-FET GATE DRIVE OUTPUT
The GATEOUT terminal is an output for a high-side
N-channel MOSFET gate drive. The output will be used to
drive an external high-side MOSFET switch (see figure
below). When enabled, GATEOUT will be connected to the
Vb supply. The edge rates when switching the transistors
must be controlled so that shoot-through current does not
affect B+.
GATEOUT
Bit
Vb
GATEOUT
RS B+
CS
Figure 11. External N-FET Gate Drive Circuit
CLOCKING SCHEMES
There are two basic clocking schemes that can be used
while clocking data into the MC34921 IC. One has 16 rising
edges of SCLK while CE is in a logic low state and the other
has 15 rising edges of SCLK. In the 15 SCLK clocking
scheme, the input data and output data are latched on the
same clock edge. In the timing diagram on page 16, the
numbers on the MOSI line are the bits that will be clocked into
the input shift register at the rising edge of SCLK. They are
drawn occurring before SCLK to account for the required
setup time (minimum 15ns). The numbers on the MISO line
are the bits that will be clocked out at the rising edge of SCLK.
They are drawn occurring after SCLK to account for the
output delay from the rising edge of SCLK (maximum 40ns).
The numbers on the SCLK line are for reference only.
Note: when using the 15 bit clocking method with exactly
one rising edge of SCLK when CE is in a logic high state, the
output data to be sent out is latched at the same time the
IREQ bit is latched in. The next frame following the assertion
of the IREQ bit is the IREQ data. I.e., the frame after the
sending of the IREQ bit will have the data from the IREQ
register rather than skipping one frame. Note: regarding the
reporting of the DONE bit after the completion of an A/D
conversion: the DONE bit is sent out every time a conversion
completes. This requires the user to hold the MOSI pin in a
low state when it is not being used to transmit data. Refer to
Figure 4, Serial Interface Timing and Figure 5, Step Motor
Crossover Delay Timing
SUPERVISORY (RST) FUNCTION
Supervisory Circuitry
The supervisor circuitry provides control of the RST line, an
open drain signal, based on system operating conditions
monitored by the 34921 IC. V 5.0, V3.3, VCORE, B+, and
thermal shutdown detectors in various parts of the chip are
monitored for error conditions. Because other devices in the
system may trigger a reset, the RST line itself is also
monitored, but the supervisor circuitry controls all reset
timing, including externally generated resets. Driving the RST
line low causes the system to be held in the reset state. V5.0,
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V3.3, VCORE, B+, and TSD have both positive- and negative-
going thresholds.
Static Operating Specifications
The state of RST is guaranteed as long as the minimum
supervisor operating conditions of B+ 9.0 V and V5.0
2.0 V and V3.3 1.5 V and VCORE are met. Once all these
conditions are met, RST is dependent on system operating
conditions. During initial power-up, RST is held low if any one
of the following error conditions is present: +5.0 V(low),
VCORE(low), +3.3 V(low), B+(low), or TSD. Once all voltages
reach their positive-going threshold, RST is set high after the
appropriate timing.
Dynamic Operating Specifications
The RST is a bidirectional signal with an open drain output
driver and a CMOS digital input gate (see Figure 12). This I/
O structure allows wired OR connection to the CPU’s RST I/
O terminal, as well as allowing the CPU to initiate a reset
cycle by driving its RST terminal low. When responding to a
CPU request for a reset cycle, the 34921 IC must respond
rapidly enough to prevent a glitch. Figure 6, RST Timing,
page 17, shows the timing parameters for responding to an
externally applied RST signal.
To Internal
Registers
From
Internal
Reset
Circuits
RST
CLOAD
Optional
Figure 12. RST Terminal Interface
The rise time with the open drain circuit may be relatively
slow, and the internal RST input gate must operate reliably
(no oscillations during the transition) under these conditions;
i.e., the RST input can be inhibited for up to tphsl (max). Error
conditions must be present for a minimum time, tfilter, before
the 34921 responds to them. Once all error conditions are
cleared, RST is held low for an additional time of tdelay,
128 SCLK periods. If any monitored item falls below its
negative-going threshold for t filter, 1.5 µs to 5.0 µs, the tdelay
count is restarted when system operating conditions are met,
regardless of whether the tdelay count has been completed.
The trigger for the tdelay retriggerable one shot is
([+5.0 V(low) + 3.3 V(low) + VCORE (low) + B+(low) + TSD]
and tfilter), where tfilter is the 1.5 µs to 5.0 µs delay.
RST and Thermal Shutdown State (TSD) Definition
There are seven registers in the INFO output word where
the trigger for the reset is recorded. This includes externally
generated resets as well as all the fault conditions listed in the
Supervisory Functions section of this datasheet. These
registers will remain valid as long as B+ 9.0 V. The fault
registers will only be cleared upon an externally generated
RST and will not be guaranteed for B+ < 9.0 V; i.e., initial
power-up or a serious B+ fault. The EXT bit will only be set
upon an externally generated reset.
Whenever RST is asserted and TSD is not set, the MISO
terminal will enter a high-impedance state, all the step motor
outputs will be off, and all the DC motor low-side drives will
be on. In addition, all internal data registers excepting the
RST fault registers in the INFO output word will be set to their
default values.
The thermal shutdown circuitry will monitor the chip’s
internal temperature at various points. The overtemperature
circuitry will disable all circuitry on the 34921 IC with the
exception of the RST output. RST will be asserted when the
temperature exceeds 140°C. This condition will be
maintained (regulators shut down in accordance with
Table 6, page 24) until the die temperature falls by the
thermal hysteresis amount, at which time the 5.0 V and 3.3 V
regulators will restart and the supervisor circuit will issue a full
length reset pulse. The system will then perform a normal
restart. The purpose of this circuitry is to prevent damage to
the 34921 owing to inadvertent high dissipation in the motor
drivers.
Table 6. Regulator Shutdown Schedule
Condition
XDCMA(26) XDCMB(26) SX
SX 5.0 V VCORE 3.3 V
Fault Registers
RST 0 0 OFF OFF ON ON ON Updated at falling RST
TSD and RST
Z
Z OFF OFF OFF ON OFF Updated at falling RST
TSDCore and RST
Z
Z OFF OFF OFF OFF OFF Updated at falling RST
Notes
26. XDCMA and XDCMB: 0 means low-side ON, 1 means high-side ON, Z means both OFF.
Other Data
Registers
Default value
Default value
Default value
ANALOG ENCODER INTERFACE
Introduction
The analog encoder interface is intended to provide a
complete interface for an analog quadrature encoder, such
as an Agilent Technologies HEDS-9710/HEDS-9711 series
of analog output small optical encoder modules.
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FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The Agilent HEDS-9710/HEDS-9711 incremental analog
quadrature encoder is a 200 lpi encoder that outputs a
quadrature analog current reflecting the position of the
encoder codewheel/codestrip within the encoder. The analog
encoder interface must provide six functions to support this
encoder: force a bias point of 1.3 V, current-to-voltage
conversion, offset current nulling, output amplitude adjust
(variable gain), channel inversion, and digital phase
generation (see Figure 13).
Note: Freescale does not assume liability, endorse, or
warrant components from external manufacturers that are
referenced in this document. While Freescale offers
component recommendations, it is the customer’s
responsibility to validate their application.
AN2/ANALOGIN_A
ENC_FILTA
A
Variable Gain
Amplifier
1.3 V
A
-1
AN3/ANALOGIN_B
Variable Gain
Amplifier
ENC_FILTB
B
B
-1
Figure 13. Analog Encoder Interface Block Diagram
A
To ADC
A
DENCA
DENCB
To Serial
Interface
B
B To ADC
I/V Conversion Stage
The I/V conversion stage is carried out by a
transimpedance amplifier using an external resistor. There is
a resistor to ground at the ANALOGIN_x input to allow offset
current trim and force the proper bias point on the encoder.
The feedback resistor should be sized to accommodate
±2.5 V output voltage swing for the full encoder current
waveform. For example, if the encoder produces a ±50 µA
signal, the feedback resistor needs to be 50 k.
The resistor to ground must have a specific relationship to
the feedback resistor. It needs to be 1.17 times the feedback
resistor, or 58.5 kfor the example above. This ensures that
the encoder is biased at 1.35 V, and that the output of the
transimpedance amplifier is 2.5 V.
The I/V conversion stage can trim an encoder offset
current of up to ±8.0 µA in the encoder output.
Variable Gain Amplifier
The I/V conversion stage is followed by a variable gain
amplifier that can compensate for variations in the encoder
output. This is designed to accommodate manufacturing
variations in the encoder, as well as aging and other effects.
The gain can be changed over the serial interface at any time.
The output of the variable gain amplifiers can be routed to
the ANALOGOUT_x terminals for engineering evaluation.
Otherwise, these terminals are general purpose A/D inputs.
Channel Inversion and Digital Phase Generation
The A and B channels are inverted by applying the
function CHANNELx = 2.5 V - CHANNELx. This results in four
signals: A, B, A, and B. These signals are used produce the
digital encoder signals DENCA and DENCB, which are
converted by the ADC to provide the analog position
information. The value of the DENCA and DENCB signals
determine which signal—A, B, A, or B—is converted. Refer to
Table 7, page 26, for more information.
Position Information
The entire position information is produced by
concatenating the value of the a quadrature counter, driven
by DENCA and DENCB bits, and the 8 bits of “fractional”
information from the ADC.
Calibration of the Encoder
It is necessary to adjust the gain and offset of the I/V circuit
initially and periodically to compensate for encoder-to-
encoder variation, aging, and other effects. The ADC “double
conversion” function allows this by continuously sampling the
A and B signals, allowing a map of the encoder output to be
built up. The user will need to provide the necessary
algorithm to use the waveform map to produce gain and
offset calibration values for both channels.
ANALOG-TO-DIGITAL CONVERTER
Introduction
There is an 8-bit analog-to-digital converter (ADC) on the
34921 IC that uses the on-board voltage reference and
derives all the necessary timing signals from the SCLK input.
The ADC is referenced to the same ground as the system
ground (GND).
ADC Input Selection
The ADC has an 8-channel analog multiplexer so that all
inputs share one ADC. The input(s) to be converted are
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FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
determined by the A/Da[2:0] bits in the serial normal input
frame (refer to Table 11, page 28).
Three different types of conversion can occur (refer to
Table 7):
Single Conversion 00X does a single conversion of
inputs AN0/ANALOGOUT_A or AN1/ANALOGOUT_B.
Double Conversion 1XX does a double conversion of
channels A and B, A and A, B and B, or
AN2/ANALOGIN_A and AN3/ANALOGIN_B,
respectively.
Auto-Select Conversion 011 does a single
conversion of one of the outputs from the analog
encoder interface, as selected by the digital outputs of
the analog encoder interface, DENCA and DENCB.
Table 7. A/D Input Conversion Channel Addressing
NORMAL
Input
Frame
Bit 2
NORMAL
Input
Frame
Bit 3
NORMAL
Input
Frame
Bit 4
NORMAL
Output
Frame
Bit 2(27)
NORMAL
Output
Frame
Bit 3(27)
Input(s) Selected
A/Da0
0
1
1
1
1
1
1
0
0
1
A/Da1
0
0
1
1
1
1
0
0
1
1
A/Da2
0
0
0
0
0
0
1
1
1
1
DENCA
X
X
1
0
1
0
X
X
X
X
DENCB
X
X
0
1
1
0
X
X
X
X
AN0/ANALOGOUT_A terminal
AN1/ANALOGOUT_B terminal
Analog encoder interface output A
Analog encoder interface output A
Analog encoder interface output B
Analog encoder interface output B
Analog encoder interface outputs A and A with S/H (28)
Analog encoder interface outputs A and B with S/H (28)
Analog encoder interface outputs B and B with S/H (28)
AN2/ANALOGIN_A and AN3/ANALOGIN_B terminals (direct input) with
S/H (28)
Notes
Notes
27. DENCA and DENCB values are captured at the output of the 3 or 6 Edge filter on SCLK rising edge, then immediately
shifted out in the MISO data when CE is high.
28. Inputs are listed in order of conversion.
A/D Conversion Flow
There is a START conversion bit in the serial channel. The
presence of this bit begins a conversion cycle on the input(s)
selected in that frame. If the ADC is converting when a
subsequent START bit arrives, this start request will be
ignored. Figure 14, A/D Converter Input Structure, page 27,
shows how this process works. The current conversion
completes during the frame prior to the data being returned.
If there is a START bit in that input frame, another conversion
is begun as the previous conversion’s data is being shifted
out. If there is no START bit in the input frame, then another
conversion is begun the frame following receipt of the start
bit. The single conversion rate is paced at four frames for
configuration bit 3 =0 or eight frames (or less) for
configuration bit 3 =1, including sampling time (refer to
Table 13, CONFIG Input Frame Bit Allocation, page 29). In
order to simplify implementation of the 34921, the user must
ensure that no A/D conversions are in progress when an
INFO word is requested. For input pairs, the inputs are listed
in the order of conversion in Table 7.
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FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Start
Idle
Start
A2Ddone1 = 0
A2Ddone2 = 0
A/Da=Last Address
Convert
A/Dd = Last
Conversion
A2Ddone1 = 0
A2Ddone2 = 0
A/Da = Current
Address
A/Dd = Last
Conversion
Start
Start Send Data2
A2Ddone1 = 0
Conversion
Done
Start
Send Data
Start
A2Ddone2 = 1
A/Da = Current
Address
A/Dd = Current
Conversion
A2Ddone1 = 0
A2Ddone2 = 0
A2Da = Current
Address
A2Dd = Current
Conversion
A/Da = 1
Conversion
Done
Convert2
A2Ddone1 = 0
A2Ddone2 = 0
A/Da = Current
Address
A/Dd = Last
Conversion
Note “Start” is bit 1 of the serial input normal frame.
A/D Converter Input Structure
The input impedance of a selected channel is an RC
circuit. As shown in Figure 14, the input impedance of the
selected channel is a resistor connected to the sample and
hold (S/H) capacitor. The sample and hold time is 15 * tSCLK,
or a minimum of 0.9285 µs. The tolerances of the internal S/
H components are such that a time constant is about 93.6 ns.
Therefore to achieve a proper level on the S/H capacitor
(5*93.6 ns) = 0.468 µs, minimum, is required to satisfy
internal component time constants. This only allows 460 ns
for external time constants. Therefore, the maximum source
impedance of the circuit driving the selected A/D channel is
7.8 kwhen the SCLK speed matches the speed
configuration bit.
SCLK
Channel Select Logic
AN0/ANALOGOUT_A
AN1/ANALOGOUT_B
C < 11.7 pF
hold
AN2/ANALOGIN_A
S/ H
AN3/ANALOGIN_B
A I/V
A
B I/V
B
Multiplexer RDS(on) < 8.0 k
Figure 14. A/D Converter Input Structure
ADC Output Addressing
The return word to the digital subsystem also contains two
conversion done bits, A/Ddone1 and A/Ddone2 (refer to
Table 8). The A/Ddone1 bit is used for single conversions
and the first conversion when input pairs are selected. The
A/Ddone2 bit is used for the second conversion when input
pairs are selected. A zero to one transition of these bits on
successive return words indicates that a conversion cycle is
complete and the data sent in that return word is valid for that
conversion. The conversion done bits will only be asserted for
one serial frame, although the data may be valid for multiple
frames. The A/Dr bits indicate which A/D input is being
reported when data is valid (refer to Table 9).
Table 8. A/D Done Bits
A/Ddone1 A/Ddone2
Return Data and A/Dr Value
Rising
0 Valid for single or first conversion
0
Rising
Valid for second conversion
00
Don’t care
Table 9. A/D Channel of Current A/D Data
NORMAL
Output
Frame
Bit 4
NORMAL
Output
Frame
Bit 5
NORMAL
Output
Frame
Bit 6
A/D Value Reported
A /Dr0
A /Dr1
A /Dr2
001
A
101
B
011
A
111
B
0 0 0 AN0/ANALOGOUT_A
1 0 0 AN1/ANALOGOUT_B
0 1 0 AN2/ANALOGIN_A
(direct input)
1 1 0 AN3/ANALOGIN_B
(direct input)
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
NORMAL MODE:
Normal mode is the normal operating mode of the IC (as opposed to the Configuration mode or Information Request mode).
Table 10. NORMAL Mode Input Frame Programming Model
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OUT2 OUT1 B
B A/Cdcb A/Cdca Adcb Adca Bdcb Bdca GATE A/Da2 A/Da1 A/Da0 start config
OUT
Table 11. NORMAL Input Frame Bit Allocation (29)
Bit Bit Name
Bit Description
15– 14
13– 10
OUT2, OUT1
B, B, A, A
(31)
High-side or low-side output control. Bit 4 of the configuration mode input frame determines which output is
controlled. Output turns on when corresponding bit is asserted. Refer to Table 20 and Table 21 Truth Tables,
page 31 and page 32, respectively, for operation.
Step motor outputs, inverting. Corresponding output on when bit asserted. Refer to Table 22 Truth Table,
page 32, for operation.
11– 10
A/Cdca, A/Cdcb Motor driver C direction bits. Outputs follow these bits, regardless of PWM value, when they are equal; i.e., 00
(30) or 11. Refer to Table 19 Truth Table, page 31, for operation.
9– 8 Adcb, Adca Motor driver A direction bits. Outputs follow these bits, regardless of PWM value, when the are equal; i.e., 00
or 11. Refer to Table 19 Truth Table, page 31, for operation.
7– 6 Bdcb, Bdca Motor driver B direction bits. Outputs follow these bits, regardless of PWM value, when the are equal; i.e., 00
or 11. Refer to Table 19 Truth Table, page 31, for operation.
5 GATEOUT Assertion puts Vb on the GATEOUT terminal. Deassertion connects the GATEOUT terminal to ground.
4–2
A/Da[2:0]
A/D conversion target channel. These bits determine which input(s) to the ADC are to be converted.
1 start A/D conversion start bit. This bit causes the ADC to sample the input(s) specified by bits A/Da[2:0] (bits [4:2])
and begin an analog-to-digital conversion. This bit is ignored if a conversion is already in progress.
0
config
The input frame can be either a configuration frame or a normal frame. Bit 0 determines the type of frame being
received. Bit 0 = 0 is a normal mode input frame.
Notes
29. All defaults = 0 at power up.
30. When in DC motor mode.
31. When in step motor mode, outputs are A, A, B, and B; when in DC motor mode, outputs B and B have no function.
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CONFIG MODE:
Configuration mode is the mode in which the IC is programmed or configured by the external digital subsystem via the serial
interface (i.e., MOSI, MISO, SCLK, CE).
Table 12. CONFIG Mode Input Frame Programming Model
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Mtest1 Mtest0 cal4 cal3 cal2 cal1 cal0 ANALOG caladdr caladdr Filter DC SS A/D sleep
(MSB)
(LSB)
_TEST
MODE
1
0
Speed
Bit 1
IREQ
Bit 0
config
Table 13. CONFIG Input Frame Bit Allocation (32)
Bit Bit Name
Bit Description
15 – 14
13 – 9
8
7–6
Mtest[1:0]
cal[4:0]
ANALOG_TEST
MODE
caladdr[1:0]
Reserved for Freescale test. Set to [10].
Data for various calibration registers.
Routes A and B output of analog encoder interface to AN0 and AN1, respectively. Used only for user
development and verification. Do not use in normal operation.
Determines the calibration register, as identified in Table 14 below, the calibration data in the cal[4:0] (Bits
13–9) bits is latched in.
5
Filter
Determines the number of SCLK edges used to filter the DENCA and DENCB signals coming from the Digital
Signal Generation stage of the analog encoder interface. This digital filter filters the DENCA and DENCB
signals made available to the serial output frame.
4
DC SS
Determines if Motor Driver C operates in DC motor or step motor mode. Implicitly determines whether
HSOUTx or LSOUTx are available. In DC motor mode, LSOUTx are available; in step motor mode, HSOUTx
are available.
3 A/D Speed Determines how many SCLK edges are required for conversion. This allows the use of a faster SCLK but still
maintains A/D conversion accuracy.
2
sleep
When asserted, causes the 34921 to enter a power-down state, and minimize power consumption.
1
IREQ
Causes the next output frame sent to the host to contain internal information from the 34921.
0
config
The input frame can be either a configuration frame or a normal frame. Bit 0 determines the type of frame being
received. Bit 0 = 1 is a configuration mode input frame.
Notes
32. All defaults = 0 at power up.
Table 14. Calibration Register Addressing
caladdr0
caladdr1
0 0 Channel A gain
1 0 Channel A offset
0 1 Channel B gain
1 1 Channel B offset
Register
Analog Integrated Circuit Device Data
Freescale Semiconductor
34921
29


34921 (Freescale Semiconductor)
Configurable Motor Driver IC

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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 15. NORMAL Mode Output Frame Programming Model
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A/Dd7 A/Dd6 A/Dd5 A/Dd4 A/Dd3 A/Dd2 A/Dd1 A/Dd0 Info A/Dr2 A/Dr1 A/Dr0 DENCB DENCA A/Ddone2 A/Ddone1
Table 16. NORMAL Mode Output Frame Bit Allocation Model
Bit Bit Name
Bit Description
15 – 8
A/Dd[7:0] ADC data from last conversion.
7 Info Identifies the output frame as a normal or information frame. The type of output frame is determined by the IREQ
bit (Bit 1) in the Configuration mode input frame.
6–4 A/Dr[2:0] Report the input to the ADC that is represented in the A/Dd[7:0] (Bits 15–8).
3–2 DENCB, Analog encoder interface digital signals. These signals are used to drive a quadrature encoder on the MCU.
DENCA
1–0 A/Ddone2, Flag completion of the ADC for corresponding conversion. If ADC in single conversion mode, only A/Ddone1 is
A/Ddone1 asserted. If in double conversion mode, A/Ddone1 is asserted for first conversion and A/Ddone2 is asserted for
second conversion
NFO (IREQ) MODE:
NFO (IREQ) Mode is the mode in which the MC34921 IC reports status and error information via the serial interface.
Table 17. NFO (IREQ) Mode Output Frame Programming Model I
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
0 0 0 1 1 0 EXT B+UV Info
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
V5VUV 3.3UV CoreU DENC DENC
VBA
Bit 1
TSD
Bit 0
TW
Table 18. INFO (IREQ) Mode Output Frame Bit Allocation
Bit Bit Name
Bit Description
15 – 10
9
8
Reserved
EXT
B+UV
These bits will report [011000].
This flag will report if the last generated reset was due to an external signal driving RST.
Undervoltage flag for the B+ input voltage. If the input voltage drops below that necessary for the 34921 to
operate, this flag will be asserted.
7 Info Identifies the output frame as a normal or information frame. The type of output frame is determined by the IREQ
bit (Bit 1) in the Configuration mode input frame.
6
V5VUV
Undervoltage warning for the 5.0 V regulator. This will be asserted when a fault on the 5.0 V causes the voltage
to droop.
5
3.3UV
Undervoltage warning for the 3.3 V regulator. This will be asserted when a fault on the 3.3 V causes the voltage
to droop.
4
CoreUV
Undervoltage warning for the VCORE linear regulator. This will be asserted when a fault on the VCORE voltage
causes the voltage to droop.
3–2
DENCB,
Analog encoder interface digital signals. These signals are used to drive a quadrature encoder on the MCU.
DENCA
1
TSD
Thermal shutdown flag. This flag will report if the last generated reset was due to a TSD. Thermal shutdown
occurs when the junction temperature reaches approximately 140ºC.
0 TW Thermal warning flag. This bit is asserted when the junction temperature on the die reaches approximately
110ºC.
34921
30
Analog Integrated Circuit Device Data
Freescale Semiconductor




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