80C196MH (Intel Corporation)
INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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®
8XC196MH INDUSTRIAL MOTOR CONTROL
CHMOS MICROCONTROLLER
High Performance CHMOS 16-bit CPU
16 MHz Operating Frequency
32 Kbytes of On-chip OTPROM/ROM
744 Bytes of On-chip Register RAM
Register-to-register Architecture
16 Prioritized Interrupt Sources
Peripheral Transaction Server (PTS) with 15
Prioritized Sources
Up to 52 I/O Lines
3-phase Complementary Waveform Generator
8-channel 8- or 10-bit A/D with Sample and
Hold
2-channel UART
Event Processor Array (EPA) with 2 High-
speed Capture/Compare Modules and 4 High-
speed Compare-only Modules
Two Programmable 16-bit Timers with
Quadrature Counting Inputs
Two Pulse-width Modulator (PWM) Outputs
with High Drive Capability
Flexible 8- or 16-bit External Bus
1.75 µs 16 × 16 Multiply
3 µs 32/16 Divide
Extended Temperature Available
Idle and Powerdown Modes
Watchdog Timer
The 8XC196MH is a member of Intel’s family of 16-bit MCS® 96 microcontrollers. It is designed primarily to
control three-phase AC induction and DC brushless motors. It features an enhanced three-phase waveform
generator specifically designed for use in “inverter” motor-control applications. This peripheral provides pulse-
width modulation and three-phase sine wave generation with minimal CPU intervention. It generates three
complementary non-overlapping PWM pulses with resolutions of 0.125 µs (edge triggered) or 0.250 µs
(centered).
The 8XC196MH has two dedicated serial port peripherals, allowing less software overhead. The watchdog timer
can be programmed with one of four time options.
The 8XC196MH is available as the 80C196MH, which does not have on-chip ROM, the 87C196MH,
which contains 32 Kbytes of on-chip OTPROM* or factory programmed ROM, and the 83C196MH, which
contains 32 Kbytes of factory programmed MASK ROM. It is available in 84-lead PLCC, 80-lead Shrink EIAJ/QFP,
and 64-lead SDIP. The 64-lead package does not contain pins for the P5.1/INST and P6.7/PWM1 signals.
Operational characteristics are guaranteed over the temperature range of – 40°C to + 85°C.
*One-Time Programmable Read-Only Memory (OTPROM) is similar to EPROM but comes in an unwindowed package and
cannot be erased. It is user programmable.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 2004
August 2004
Order Number: 272543-003


80C196MH (Intel Corporation)
INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
®
CPU
8/10-Bit
A/D
Converter
744
Byte
Register
File
24 Bytes
CPU SFRs
S/H
RALU
Microcode
Engine
16
Interrupt
Controller
32K
On-chip
ROM/
OTPROM
8
Peripheral
Transaction
Server
Memory
Controller
Queue
8
8 Watchdog
Timer
Port 5
Control
Signals
Port 3
AD7:0
Port 4
AD15:8
Mux
8
A/D
Port 0
Port 0
Baud
Rate
Generator
SIO 0
SIO 1
Timer 1
Timer 2
Event
Processor
Array
4
2
Port 1
6
Port 2
3-Phase
Waveform
Generator
PWM0
PWM1
62
Port 6
48
Port 1
Serial I/O
Port 2
SIO, EPA
2 Capture/Compare
4 Compare
EXTINT
8
Port 6
Waveform
Generator
A2542-01
Figure 1. 8XC196MH Block Diagram
2


80C196MH (Intel Corporation)
INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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® 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS IV
process. Additional process and reliability information
is available in Intel’s Components Quality and
Reliability Handbook (order number 210997).
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
will change depending on operating conditions and
the application. The Intel Packaging Handbook (order
number 240800) describes Intel’s thermal impedance
test methodology.
Table 1. Thermal Characteristics
Package Type
84-lead PLCC
80-lead QFP
64-lead SDIP
θJA
33°C/W
56°C/W
56°C/W
θJC
11°C/W
12°C/W
N/A
X XX 8 X C 196 XX XX
Device Speed:
Product Family:
No Mark = 16 MHz
Kx, Mx, Nx
CHMOS Technology
Program Memory Options:
0 = ROMless, 3 = ROM, 7 = OTPROM
Package - Type Options:
Temperature and Burn In Options:
x = SDIP, x = PLCC, x = QFP
x = –40˚C – +85˚C Ambient
with Intel Standard Burn-In
A2759-01
Figure 2. The 8XC196MH Family Nomenclature
NOTE: To address the fact that many of the package prefix variables have changed,
all package prefix variables in this document are now indicated with an "x".
3


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INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
®
Table 2. 8XC196MH Memory Map
Address
(1)
Description
Notes
0FFFFH
0A000H
External Memory
09FFFH
02080H
Internal ROM/OTPROM or External Memory
0207FH
0205EH
Reserved
1, 2
0205DH
02040H
PTS Vectors
0203FH
02030H
Interrupt Vectors (upper)
0202FH
02020H
ROM/OTPROM Security Key
0201FH
0201CH
Reserved
1, 2
0201BH Reserved (must contain 20H)
0201AH CCB1
02019H Reserved (must contain 20H)
02018H CCB0
02017H
02014H
Reserved
02013H
02000H
Interrupt Vectors (lower)
01FFFH
01F00H
Internal SFRs
1
1EFFH
300H
External Memory
2FFH
18H
Register RAM
3
17H
00H
CPU SFRs
1
NOTES:
1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.
2. WARNING: The contents and/or function of reserved locations may change with future revisions of the
device.
3. Code executed in locations 0000H to 02FFH will be forced external.
4


80C196MH (Intel Corporation)
INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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® 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 3. Signals Arranged by Functional Categories
Address & Data
Programming Control
Input/Output
Input/Output (Cont’d)
AD15:0
AINC#
P0.0/ACH0
P2.5/COMP1
CPVER
P0.1/ACH1
P2.6/COMP2
Bus Control & Status PACT#
P0.2/ACH2
P2.7/SCLK1#/BCLK1
ALE/ADV#
PALE#
P0.3/ACH3
P3.7:0
BHE#/WRH#
PBUS15:0
P0.4/ACH4
P4.7:0
BUSWIDTH
PMODE.3:0
P0.5/ACH5
P5.7:0
INST
PROG#
P0.6/ACH6/T1CLK
P6.0/WG1#
READY
PVER
P0.7/ACH7/T1DIR
P6.1/WG1
RD#
P1.0/TXD0
P6.2/WG2#
WR#/WRL#
Processor Control
P1.1/RXD0
P6.3/WG2
EA#
P1.2/TXD1
P6.4/WG3#
Power & Ground
EXTINT
P1.3/RXD1
P6.5/WG3
ANGND
NMI
P2.0/EPA0
P6.6/PWM0
VCC
VPP
VREF
VSS
NOTE:
ONCE#
P2.1/SCLK0#/BCLK0 P6.7/PWM1
RESET#
P2.2/EPA1
XTAL1
P2.3/COMP3
XTAL2
P2.4/COMP0
The following signals are not available in the 64-pin package: P5.1, P6.7, INST, and PWM1.
5


80C196MH (Intel Corporation)
INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
®
VSS
P5.0/ALE/ADV#
VPP
P5.3/RD#
P5.5/BHE#/WRH#
P5.2/WR#/WRL#
P5.7/BUSWIDTH
P4.6/AD14/PBUS.14
P4.5/AD13/PBUS.13
P4.7/AD15/PBUS.15
VCC
P4.4/AD12/PBUS.12
P4.3/AD11/PBUS.11
P4.2/AD10/PBUS.10
P4.1/AD9/PBUS.9
P4.0/AD8/PBUS.8
P3.7/AD7/PBUS.7
P3.6/AD6/PBUS.6
P3.5/AD5/PBUS.5
P3.4/AD4/PBUS.4
P3.3/AD3/PBUS.3
P3.2/AD2/PBUS.2
P3.1/AD1/PBUS.1
P3.0/AD0/PBUS.0
RESET#
NMI
EA#
VSS
VCC
P6.5/WG3
P6.4/WG3#
P6.3/WG2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
xx8XC196MH
TOP VIEW
(Looking down
on component side of
PC board)
64 P5.6/READY
63 P5.4/ONCE#
62 EXTINT
61 VSS
60 XTAL1
59 XTAL2
58 P6.6/PWM0
57 P2.7/SCLK1#/BCLK1
56 P2.6/COMP2/CPVER
55 P2.5/COMP1/PACT#
54 P2.4/COMP0/AINC#
53 P2.3/COMP3
52 P2.2/EPA1/PROG#
51 P2.1/SCLK0#/BCLK0/PALE#
50 P2.0/EPA0/PVER
49 P0.0/ACH0
48 P0.1/ACH1
47 P0.2/ACH2
46 P0.3/ACH3
45 P0.4/ACH4/PMODE.0
44 P0.5/ACH5/PMODE.1
43 VREF
42 ANGND
41 P0.6/ACH6/T1CLK/PMODE.2
40 P0.7/ACH7/T1DIR/PMODE.3
39 P1.0/TXD0
38 P1.1/RXD0
37 P1.2/TXD1
36 P1.3/RXD1
35 P6.0/WG1#
34 P6.1/WG1
33 P6.2/WG2#
Figure 3. 8XC196MH 64-lead Shrink DIP (SDIP) Package
A2572-01
6


80C196MH (Intel Corporation)
INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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Table 4. 64-lead Shrink DIP (SDIP) Pin Assignment
Pin Name
1 VSS
2 P5.0/ALE/ADV#
3 VPP
4 P5.3/RD#
5 P5.5/BHE#/WRH#
6 P5.2/WR#/WRL#
7 P5.7/BUSWIDTH
8 P4.6/AD14
/PBUS.14
9 P4.5/AD13
/PBUS.13
10 P4.7/AD15
/PBUS.15
11 VCC
12 P4.4/AD12
/PBUS.12
13 P4.3/AD11
/PBUS.11
14 P4.2/AD10
/PBUS.10
15 P4.1/AD9/PBUS.9
16 P4.0/AD8/PBUS.8
Pin Name
17 P3.7/AD7
/PBUS.7
18 P3.6/AD6
/PBUS.6
19 P3.5/AD5
/PBUS.5
20 P3.4/AD4
/PBUS.4
21 P3.3/AD3
/PBUS.3
22 P3.2/AD2
/PBUS.2
23 P3.1/AD1
/PBUS.1
24 P3.0/AD0
/PBUS.0
25 RESET#
26 NMI
27 EA#
28 VSS
29 VCC
30 P6.5/WG3
31 P6.4/WG3#
32 P6.3/WG2
Pin Name
33 P6.2/WG2#
Pin Name
49 P0.0/ACH0
34 P6.1/WG1
50 P2.0/EPA0/PVER
35 P6.0/WG1#
36 P1.3/RXD1
37 P1.2/TXD1
51 P2.1/SCLK0#
/BCLK0/PALE#
52 P2.2/EPA1
/PROG#
53 P2.3/COMP3
38 P1.1/RXD0
39 P1.0/TXD0
40 P0.7/ACH7/T1DIR
/PMODE.3
41 P0.6/ACH6
/T1CLK/PMODE.2
42 ANGND
54 P2.4/COMP0
/AINC#
55 P2.5/COMP1
/PACT#
56 P2.6/COMP2
/CPVER
57 P2.7/SCLK1#
/BCLK1
58 P6.6/PWM0
43 VREF
44 P0.5/ACH5
/PMODE.1
45 P0.4/ACH4
/PMODE.0
46 P0.3/ACH3
59 XTAL2
60 XTAL1
61 VSS
62 EXTINT
47 P0.2/ACH2
48 P0.1/ACH1
63 P5.4/ONCE#
64 P5.6/READY
7


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INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
®
P4.7/AD15/PBUS.15
P4.6/AD14/PBUS.14
VCC
P4.5/AD13/PBUS.13
NC
P4.4/AD12/PBUS.12
P4.3/AD11/PBUS.11
P4.2/AD10/PBUS.10
P4.1/AD9/PBUS.9
P4.0/AD8/PBUS.8
NC
NC
P3.7/AD7/PBUS.7
P3.6/AD6/PBUS.6
P3.5.AD5/PBUS.5
P3.4/AD4/PBUS.4
P3.3/AD3/PBUS.3
P3.2/AD2/PBUS.2
P3.1/AD1/PBUS.1
P3.0/AD0/PBUS.0
NC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
xx8XC196MH
TOP VIEW
(Looking down
on component side of
PC board)
74 P2.5/COMP1/PACT#
73 P2.4/COMP0/AINC#
72 NC
71 NC
70 P2.7/SCLK1#/BCLK1
69 P2.3/COMP3
68 P2.2/EPA1/PROG#
67 NC
66 NC
65 P2.1/SCLK0#/BCLK0/PALE#
64 P2.0/EPA0/PVER
63 NC
62 P0.0/ACH0
61 P0.1/ACH1
60 P0.2/ACH2
59 P0.3/ACH3
58 P0.4/ACH4/PMODE.0
57 P0.5/ACH5/PMODE.1
56 VREF
55 ANGND
54 P0.6/ACH6/T1CLK/PMODE.2
Figure 4. 8XC196MH 84-lead PLCC Package
A2573-02
8


80C196MH (Intel Corporation)
INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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® 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Pin Name
1 P5.4/ONCE#
2 P5.6/READY
3 P5.1/INST
4 VSS
5 P5.0/ALE/ADV#
6 VPP
7 P5.3/RD#
8 P5.5/BHE#/WRH#
9 NC
10 P5.2/WR#/WRL#
11 P5.7/BUSWIDTH
12 P4.7/AD15
/PBUS.15
13 P4.6/AD14
/PBUS.14
14 VCC
15 P4.5/AD13
/PBUS.13
16 NC
17 P4.4/AD12
/PBUS.12
18 P4.3/AD11
/PBUS.11
19 P4.2/AD10
/PBUS.10
20 P4.1/AD9/PBUS.9
21 P4.0/AD8/PBUS.8
Table 5. 84-lead PLCC Pin Assignment
Pin
22 NC
23 NC
Name
Pin Name
43 VSS
44 P6.2/WG2#
24 P3.7/AD7
/PBUS.7
25 P3.6/AD6
/PBUS.6
26 P3.5/AD5
/PBUS.5
27 P3.4/AD4
/PBUS.4
28 P3.3/AD3
/PBUS.3
29 P3.2/AD2
/PBUS.2
30 P3.1/AD1
/PBUS.1
31 P3.0/AD0
/PBUS.0
32 NC
33 RESET#
34 NMI
45 P6.1/WG1
46 P6.0/WG1#
47 P1.3/RXD1
48 P1.2/TXD1
49 NC
50 NC
51 P1.1/RXD0
52 P1.0/TXD0
53 P0.7/ACH7
/T1DIR/PMODE.3
54 P0.6/ACH6
/T1CLK/PMODE.2
55 ANGND
35 NC
36 EA#
37 VSS
38 NC
56 VREF
57 P0.5/ACH5
/PMODE.1
58 P0.4/ACH4
/PMODE.0
59 P0.3/ACH3
39 VCC
40 P6.5/WG3
60 P0.2/ACH2
61 P0.1/ACH1
41 P6.4/WG3#
42 P6.3/WG2
62 P0.0/ACH0
63 NC
Pin Name
64 P2.0/EPA0/PVER
65 P2.1/SCLK0#
/BCLK0/PALE#
66 NC
67 NC
68 P2.2/EPA1
/PROG#
69 P2.3/COMP3
70 P2.7/SCLK1#
/BCLK1
71 NC
72 NC
73 P2.4/COMP0
/AINC#
74 P2.5/COMP1
/PACT#
75 P2.6/COMP2
/CPVER
76 P6.7/PWM1
77 P6.6/PWM0
78 NC
79 NC
80 NC
81 XTAL2
82 XTAL1
83 VSS
84 EXTINT
9


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INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
®
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P5.2/WR#/WRL#
P5.7/BUSWIDTH
P4.7/AD15/PBUS.15
P4.6/AD14/PBUS.14
VCC
P4.5/AD13/PBUS.13
NC
P4.4/AD12/PBUS.12
P4.3/AD11/PBUS.11
P4.2/AD10/PBUS.10
P4.1/AD9/PBUS.9
P4.0/AD8/PBUS.8
P3.7/AD7/PBUS.7
P3.6/AD6/PBUS.6
P3.5/AD5/PBUS.5
P3.4/AD4/PBUS.4
P3.3/AD3/PBUS.3
P3.2/AD2/PBUS.2
P3.1/AD1/PBUS.1
P3.0/AD0/PBUS.0
NC
RESET#
NMI
EA#
1 64
2 63
3 62
4 61
5 60
6 59
7 58
8 57
9 56
10
xx8XC196MH
55
11 54
12 53
13
TOP VIEW
52
(Looking down
14
on component side of
51
15
PC board)
50
16 49
17 48
18 47
19 46
20 45
21 44
22 43
23 42
24 41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P6.7/PWM1
P2.6/COMP2/CPVER
P2.5/COMP1/PACT#
P2.4/COMP0/AINC#
NC
NC
P2.7/SCLK1#/BCLK1
P2.3/COMP3
P2.2/EPA1/PROG#
NC
NC
P2.1/SCLK0#/BCLK0/PALE#
P2.0/EPA0/PVER
NC
P0.0/ACH0
P0.1/ACH1
P0.2/ACH2
P0.3/ACH3
P0.4/ACH4/PMODE.0
P0.5/ACH5/PMODE.1
VREF
ANGND
P0.6/ACH6/T1CLK/PMODE.2
P0.7/ACH7/T1DIR/PMODE.3
Figure 5. 8XC196MH 80-lead Shrink EIAJ/QFP Package
A2574-01
10


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INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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® 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
Table 6. 80-lead Shrink EIAJ/QFP Pin Assignment
Pin Name
1 P5.2/WR#/WRL#
Pin Name
21 NC
2 P5.7/BUSWIDTH 22 RESET#
3 P4.7/AD15
/PBUS.15
4 P4.6/AD14
/PBUS.14
5 VCC
23 NMI
24 EA#
25 VSS
6 P4.5/AD13
/PBUS.13
7 NC
8 P4.4/AD12
/PBUS.12
9 P4.3/AD11
/PBUS.11
10 P4.2/AD10
/PBUS.10
11 P4.1/AD9/PBUS.9
12 P4.0/AD8/PBUS.8
13 P3.7/AD7/PBUS.7
26 NC
27 VCC
28 P6.5/WG3
29 P6.4/WG3#
30 P6.3/WG2
31 VSS
32 P6.2/WG2#
33 P6.1/WG1
14 P3.6/AD6/PBUS.6
15 P3.5/AD5/PBUS.5
16 P3.4/AD4/PBUS.4
34 P6.0/WG1#
35 P1.3/RXD1
36 P1.2/TXD1
17 P3.3/AD3/PBUS.3
18 P3.2/AD2/PBUS.2
37 NC
38 NC
19 P3.1/AD1/PBUS.1
20 P3.0/AD0/PBUS.0
39 P1.1/RXD0
40 P1.0/TXD0
Pin Name
41 P0.7/ACH7/T1DIR
/PMODE.3
42 P0.6/ACH6
/T1CLK/PMODE.2
43 ANGND
44 VREF
Pin Name
61 P2.4/COMP0
/AINC#
62 P2.5/COMP1
/PACT#
63 P2.6/COMP2
/CPVER
64 P6.7/PWM1
45 P0.5/ACH5
/PMODE.1
46 P0.4/ACH4
/PMODE.0
47 P0.3/ACH3
48 P0.2/ACH2
65 P6.6/PWM0
66 NC
67 NC
68 NC
49 P0.1/ACH1
69 XTAL2
50 P0.0/ACH0
70 XTAL1
51 NC
52 P2.0/EPA0/PVER
53 P2.1/SCLK0#
/BCLK0/PALE#
54 NC
55 NC
56 P2.2/EPA1
/PROG#
57 P2.3/COMP3
58 P2.7/SCLK1#
/BCLK1
59 NC
60 NC
71 VSS
72 EXTINT
73 P5.4/ONCE#
74 P5.6/READY
75 P5.1/INST
76 VSS
77 P5.0/ALE/ADV#
78 VPP
79 P5.3/RD#
80 P5.5/BHE#/WRH#
11


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INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER

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®
PIN DESCRIPTIONS
Table 7. Signal Descriptions
Signal
Name
ACH7
ACH6
ACH5
ACH4
ACH3:0
AD15:8
AD7:0
ADV#
AINC#
ALE
ANGND
BCLK1
BCLK0
Type
Description
Multiplexed
With
I
I/O
O
I
O
GND
I
Analog Channels. These pins are analog inputs to the A/D
converter.
These pins are multiplexed with the port 0 pins. While it is
possible for the pins to function simultaneously as analog and
digital inputs, this is not recommended because reading the
port while a conversion is in process can produce unreliable
conversion results.
The ANGND and VREF pins must be connected for the A/D
converter and the multiplexed port pins to function.
Address/Data Lines. These pins provide a multiplexed
address and data bus. During the address phase of the bus
cycle, address bits 0–15 are presented on the bus and can
be latched using ALE or ADV#. During the data phase, 8- or
16-bit data is transferred.
Address Valid. This active-low output signal is asserted only
during external memory accesses.
ADV# indicates that valid address information is available on
the system address/data bus. The signal remains low while a
valid bus cycle is in progress and is returned high as soon as
the bus cycle completes.
An external latch can use the ADV# signal to demultiplex the
address from the address/data bus. Used with a decoder,
ADV# can generate chip-selects for external memory.
Auto Increment. In slave programming mode, this active-low
input signal enables the autoincrement mode. Auto increment
allows reading from or writing to sequential OTPROM
locations without requiring address transactions across the
programming bus for each read or write.
Address Latch Enable. This active-high output signal is
asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates
that valid address information is available on the system
address/data bus. ALE differs from ADV# in that it is not
returned high until a new bus cycle is to begin.
An external latch can use ALE to demultiplex the address
from the address/data bus.
Analog Ground. Reference ground for the A/D converter
and the logic used to read port 0. ANGND must be held at
nominally the same potential as VSS.
Serial Communications Baud Clock 0 and 1. BCLK0 and 1
are alternate clock sources for the serial ports. The maximum
input frequency is FOSC/4.
P0.7/T1DIR/PMODE.3
P0.6/T1CLK/PMODE.2
P0.5/PMODE.1
P0.4/PMODE.0
P0.3:0
P4.7:0/PBUS.15:8
P3.7:0/PBUS.7:0
P5.0/ALE
P2.4/COMP0
P5.0/ADV#
P2.7/SCLK1#
P2.1/SCLK0#/PALE#
12


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Table 7. Signal Descriptions (Continued)
Signal
Name
Type
Description
Multiplexed
With
BHE#
O Byte High Enable. During 16-bit bus cycles, this active-low P5.5/WRH#
output signal is asserted for word reads and writes and for
high-byte reads and writes to external memory. BHE#
indicates that valid data is being transferred over the upper
half of the system address/data bus.
BHE#, in conjunction with A0, selects the memory byte to be
accessed:
BHE# A0 Byte(s) Accessed
0 0 both bytes
0 1 high byte only
1 0 low byte only
BUSWIDTH I Bus Width. When enabled in the chip configuration register, P5.7
this active-high input signal dynamically selects the bus width
of the bus cycle in progress. When BUSWIDTH is high, a 16-
bit bus cycle occurs; when BUSWIDTH is low, an 8-bit bus
cycle occurs. BUSWIDTH is active during a CCR fetch.
COMP3
COMP2
COMP1
COMP0
O Event Processor Array (EPA) Compare Pins. These
P2.3
signals are the output of the EPA compare modules. These P2.6/CPVER
pins are multiplexed with other signals and may be
P2.5/PACT#
configured as standard I/O.
P2.4/AINC#
CPVER
O Cumulative Program Verification. This active-high output P2.6/COMP2
signal indicates whether any verify errors have occurred
since the device entered programming mode. CPVER
remains high until a verify error occurs, at which time it is
driven low. Once an error occurs, CPVER remains low until
the device exits programming mode. When high, CPVER
indicates that all locations have programmed correctly since
the device entered programming mode.
EA#
I External Access. This active-low input signal directs
memory accesses to on-chip or off-chip memory. If EA# is
low, the memory access is off-chip. If EA# is high and the
memory address is within 2000H–2FFFH, the access is to
on-chip ROM or OTPROM. Otherwise, an access with EA#
high is to off-chip memory.
EA# is sampled only on the rising edge of RESET#.
If EA# = VEA on the rising edge of RESET#, the device enters
the programming mode selected by PMODE.3:0.
For devices without ROM, EA# must be tied low.
EPA1
EPA0
I/O Event Processor Array (EPA) Input/Output pins. These
are the high-speed input/output pins for the EPA
capture/compare modules. These pins are multiplexed with
other signals and may be configured as standard I/O.
P2.2/PROG#
P2.0/PVER
13


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Signal
Name
EXTINT
INST
NMI
ONCE#
Table 7. Signal Descriptions (Continued)
Type
Description
Multiplexed
With
I External Interrupt. This programmable interrupt is controlled —
by the WG_PROTECT register. This register controls
whether the interrupt is edge triggered or sampled and
whether a rising edge/high level or falling edge/low level
activates the interrupt. This interrupt vectors through memory
location 203CH. If the chip is in idle mode and if EXTINT is
enabled, a valid EXTINT interrupt brings the chip back to
normal operation, where the first action is to execute the
EXTINT service routine. After completion of the service
routine, execution resumes at the instruction following the
one that put the chip into idle mode.
In powerdown mode, a valid EXTINT interrupt causes the
chip to return to normal operating mode. If EXTINT is
enabled, the EXTINT service routine is executed. Otherwise,
execution continues at the instruction following the IDLPD
instruction that put the chip into powerdown mode.
O Instruction Fetch. This active-high output signal is valid only P5.1
during external memory bus cycles. When high, INST
indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle
of an external instruction fetch. INST is low for data
accesses, including interrupt vector fetches and chip configu-
ration byte reads. INST is low during internal memory
fetches.
I Nonmaskable Interrupt. In normal operating mode, a rising —
edge on NMI causes a vector through the NMI interrupt at
location 203EH. NMI must be asserted for greater than one
state time to guarantee that it is recognized.
In idle mode, a rising edge on NMI brings the chip back to
normal operation, where the first action is to execute the NMI
service routine. After completion of the service routine,
execution resumes at the instruction following the one that
put the chip into idle mode.
In powerdown mode, NMI causes a return to normal
operating mode only if it is tied to EXTINT.
I On-circuit Emulation. Holding this pin low while the
P5.4
RESET# signal transitions from a low to a high places the
device into on-circuit emulation (ONCE) mode. ONCE mode
isolates the device from other components in the system to
allow the use of a clip-on emulator for system debugging.
This mode puts all pins except XTAL1 and XTAL2 into a high-
impedance state. To exit ONCE mode, reset the device by
pulling the RESET# signal low.
14


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Signal
Name
P0.7
P0.6
P0.5
P0.4
P0.3:0
P1.3
P1.2
P1.1
P1.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P3.7:0
P4.7:0
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
Table 7. Signal Descriptions (Continued)
Type
Description
Multiplexed
With
I Port 0. This is a high-impedance, input-only port. Port 0 pins ACH7/T1DIR/PMODE.3
should not be left floating.
ACH6/T1CLK/PMODE.2
These pins may individually be used as analog inputs
ACH5/PMODE.1
(ACHx) or digital inputs (P0.x). While it is possible for the pins ACH4/PMODE.0
to function simultaneously as analog and digital inputs, this is ACH3:0
not recommended because reading port 0 while a conversion
is in process can produce unreliable conversion results.
ANGND and VREF must be connected for port 0 and the A/D
converter to function.
I Port 1. This is a 4-bit, bidirectional, standard I/O port that is RXD1
multiplexed with individually selectable special-function
TXD1
signals. (Used as PBUS.15:12 in Auto-programming Mode.) RXD0
TXD0
I/O Port 2. This is an 8-bit, bidirectional, standard I/O port that is SCLK1#/BCLK1
multiplexed with individually selectable special-function
COMP2/CPVER
signals. P2.6 is multiplexed with a special test mode function. COMP1/PACT#
To prevent accidental entry into test modes, always configure COMP0/AINC#
P2.6 as an output.
COMP3
EPA1/PROG#
SCLK0#/BCLK0/PALE#
EPA0/PVER
I/O Port 3. This is an 8-bit, bidirectional, memory-mapped I/O
port with open-drain outputs. The pins are shared with the
multiplexed address/data bus, which has complementary
drivers.
AD7:0/PBUS.7:0
In programming modes, port 3 serves as the low byte of the
programming bus (PBUS).
I/O Port 4. This is an 8-bit, bidirectional, memory-mapped I/O
port with open-drain outputs. The pins are shared with the
multiplexed address/data bus, which has complementary
drivers.
AD15:8/PBUS.15:8
In programming modes, port 4 serves as the high byte of the
programming bus (PBUS).
I/O Port 5. This is an 8-bit, bidirectional, standard I/O port that is BUSWIDTH
multiplexed with individually selectable control signals.
READY
Because P5.4 is multiplexed with the ONCE# function,
BHE#/WRH#
always configure it as an output to prevent accidental entry ONCE#
into ONCE mode.
RD#
WR#/WRL#
INST
ALE/ADV#
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Table 7. Signal Descriptions (Continued)
Signal
Name
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
PACT#
PALE#
PBUS.15:8
PBUS.7:0
PMODE.3
PMODE.2
PMODE.1
PMODE.0
PROG#
PVER
PWM1:0
RD#
Type
Description
Multiplexed
With
O Port 6. This is an 8-bit output port that is multiplexed with the PWM1
special functions of the waveform generator and PWM
PWM0
peripherals. The WG_OUT register configures the pins,
WG3
establishes the output polarity, and controls whether changes WG3#
to the outputs are synchronized with an event or take effect WG2
immediately.
WG2#
WG1
WG1#
O Programming Active. In auto-programming mode, PACT# P2.5/COMP1
low indicates that programming activity is occurring.
I Programming ALE. In slave programming mode, this active- P2.1/SCLK0#/BCLK0
low input indicates that ports 3 and 4 contain a
command/address. When PALE# is asserted, data and
commands on ports 3 and 4 are read into the device.
I/O Programming Bus. In programming modes, used as a
P4.7:0/AD15:8
bidirectional port with open-drain outputs to pass commands, P3.7:0/AD7:0
addresses, and data to or from the device. Used as a regular
system bus to access external memory during auto-
programming mode. When using slave programming mode,
the PBUS is used in open-drain I/O port mode (not as a
system bus). In slave programming mode, you must add
external pull-up resistors to read data from the device during
the dump word routine.
I Programming Mode Select. Determines the OTPROM
P0.7/ACH7/T1DIR
programming algorithm that is to be performed. PMODE is P0.6/ACH6/T1CLK
sampled after a device reset when EA# = VEA and must be
stable while the device is operating.
P0.5/ACH5
P0.4/ACH4
I Programming Start. This active-low input is valid only in
P2.2/EPA1
slave programming mode. The rising edge of PROG# latches
data on the PBUS and begins programming. The falling edge
of PROG# ends programming.
O Program Verification. In programming modes, this active-
high output signal is asserted to indicate that the word has
programmed correctly. (PVER low after the rising edge of
PROG# indicates an error.)
P2.0/EPA0
O Pulse Width Modulator Outputs. These are PWM output
pins with high-current drive capability. The duty cycle and
frequency-pulse-widths are programmable.
P6.7:6
O Read. Read-signal output to external memory. RD# is
asserted only during external memory reads.
P5.3
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Signal
Name
READY
RESET#
RXD1
RXD0
SCLK1#
SCLK0#
T1CLK
T1DIR
TXD1
TXD0
VCC
VPP
Table 7. Signal Descriptions (Continued)
Type
Description
Multiplexed
With
I
I/O
I/O
I/O
I
I
O
PWR
PWR
Ready Input. This active-high input signal is used to
lengthen external memory cycles for slow memory by
generating wait states.
When READY is high, CPU operation continues in a normal
manner. If READY is low, the memory controller inserts wait
states until the READY signal goes high or until the number
of wait states is equal to the number programmed into the
chip configuration register.
READY is ignored for all internal memory accesses.
Reset. Reset input to and open-drain output from the chip. A
falling edge on RESET# initiates the reset process. When
RESET# is first asserted, the chip turns on a pull-down
transistor connected to the RESET pin for 16 state times.
This function can also be activated by execution of the RST
instruction. In the powerdown and idle modes, asserting
RESET# causes the chip to reset and return to normal
operating mode. RESET# is a level-sensitive input.
Receive Serial Data 0 and 1. In modes 1, 2, and 3, RXD0
and 1 are used to receive serial port data. In mode 0, they
function as either inputs or open-drain outputs for data.
Synchronous Clock Pin 0 and 1. In mode 4, these are the
bidrectional, shift clock signals that synchronize the serial
data transfer. Data is transferred 8 bits at a time with the LSB
first. The DIR bit (SP_CONx.7) controls the direction of
SCLKx signal.
DIR = 0 The internal shift clock is output on SCLKx.
DIR = 1 An external shift clock is input on SCLKx.
External Clock. External clock for timer 1. Timer 1
increments (or decrements) on both rising and falling edges
of T1CLK. Also used in conjunction with T1DIR for
quadrature counting mode.
Timer 1 External Direction. External direction (up/down) for
timer 1. Timer 1 increments when T1DIR is high and
decrements when it is low. Also used in conjunction with
T1CLK for quadrature counting mode.
Transmit Serial Data 0 and 1. In serial I/O modes 1, 2, and
3, TXD0 and 1 are used to transmit serial port data. In mode
0, they are used as the serial clock output.
Digital Supply Voltage. Connect each VCC pin to the digital
supply voltage.
Programming Voltage. Set to 12.5 V when programming the
on-chip OTPROM. Also the timing pin for the “return from
power-down” circuit.
P5.6
P1.3
P1.1
P2.7/BCLK1
P2.1/BCLK0
P0.6/ACH6/PMODE.2
P0.7/ACH7/PMODE.3
P1.2
P1.0
17


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Signal
Name
VREF
VSS
WG3
WG2
WG1
WG3#
WG2#
WG1#
WR#
WRH#
WRL#
XTAL1
XTAL2
Table 7. Signal Descriptions (Continued)
Type
Description
Multiplexed
With
PWR
Reference Voltage for the A/D Converter. VREF is also the
supply voltage to the analog portion of the A/D converter and
the logic used to read Port 0. VREF must be connected for the
A/D and port 0 to function.
GND
O
Digital Circuit Ground (0 volts). Connect each VSS pin to
ground.
Waveform Generator Phase 13 Positive Outputs.
3-phase output signals used in motion-control applications.
O Waveform Generator Phase 13 Negative Outputs.
Complementary 3-phase output signals used in motion-
control applications.
O Write. This active-low output indicates that an external write
is occurring. This signal is asserted only during external
memory writes.
O Write High. During 16-bit bus cycles, this active-low output
signal is asserted for high-byte writes and word writes to
external memory.
During 8-bit bus cycles, WRH# is asserted for all write
operations.
O Write Low. During 16-bit bus cycles, this active-low output
signal is asserted for low-byte writes and word writes.
During 8-bit bus cycles, WRL# is asserted for all write
operations.
I Clock/Oscillator Input. Input to the on-chip oscillator
inverter and the internal clock generator. Also provides the
clock input for the serial I/O baud-rate generator, timers, and
PWM unit. If an external oscillator is used, connect the
external clock input signal to XTAL1 and ensure that the
XTAL1 VIH specification is met.
O Oscillator Output. Output of the on-chip oscillator inverter.
When using the on-chip oscillator, connect XTAL2 to an
external crystal or resonator. When using an external clock
source, let XTAL2 float.
P6.5
P6.3
P6.1
P6.4
P6.2
P6.0
P5.2/WRL#
P5.5/BHE#
P5.2/WR#
18


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ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature ................................ – 65°C to + 150°C
Ambient Temperature
under Bias.............................................. – 40°C to + 85°C
Voltage from VPP or EA# to
VSS or ANGND (Note 1) ...................... – 0.5 V to + 13.0 V
Voltage with respect to
VSS or ANGND (Note 1) ........................ – 0.5 V to + 7.0 V
(This includes VPP on ROM and CPU devices.)
Power Dissipation .......................................................... 1.5 W
(based on package heat transfer limitations, not device
power consumption)
NOTICE: This data sheet contains preliminary infor-
mation on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
*WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “Operating
Conditions” is not recommended and extended exposure
beyond the “Operating Conditions” may affect device reli-
ability.
OPERATING CONDITIONS*
TA (Ambient Temperature Under Bias) .........– 40°C to + 85°C
VCC (Digital Supply Voltage) .......................... 4.50 V to 5.50 V
VREF (Analog Supply Voltage) ....................... 4.50 V to 5.50 V
FOSC (Oscillator Frequency) (Note 2) ........... 8 MHz to 16 MHz
NOTES:
1. ANGND and VSS should be at nominally the same
potential.
2. Testing is performed down to 8 MHz, although
the device is static by design and will typically
operate below 1 Hz.
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DC CHARACTERISTICS
Table 8. DC Characteristics over Specified Operating Conditions
Symbol
Parameter
Min Typ (4) Max Units Test Conditions
VIL Input Low Voltage
(standard inputs (1))
– 0.5
0.3 VCC
V
VIL1 Input Low Voltage
– 0.5
(RESET#, ports 3, 4, and
5)
0.8 V
VIH Input High Voltage
0.7 VCC
(standard inputs (1))
VCC + 0.5 V
VIH1 Input High Voltage 0.2 VCC + 1.0
(RESET#, ports 3, 4, and
5)
VCC + 0.5 V
VOL
VOL1
Output Low Voltage
(RESET#, ports 1, 2, 5,
P6.6, P6.7, and XTAL2)
Output Low Voltage (ports
3, 4)
0.3
0.45
1.5
1.0
V IOL = 200 µA
V IOL = 3.2 mA
V IOL = 7.0 mA
V IOL = 7 mA
VOL2
Output Low Voltage
(P6.5:0)
0.45
V IOL = 10 mA
VOH Output High Voltage VCC – 0.3
(output pins and I/O
VCC – 0.7
configured as push/pull
VCC – 1.5
outputs)
V IOH = – 200 µA
V IOH = – 3.2 mA
V IOH = – 7.0 mA
VTH+ – VTHHysteresis voltage width
on RESET# pin
0.2
V
ILI Input Leakage Current
(standard inputs (1))
± 10
µA VSS < VIN < VCC – 0.3V
ILI1 Input Leakage Current
(port 0 – A/D inputs)
± 3 µA VSS < VIN < VREF
IIH Input High Current (NMI)
IIL Input Low Current (port 2,
except P2.6)
300
70
µA VIN = 0.7 VCC
µA VIN = 0.3 VCC
NOTES:
1. Standard input pins include XTAL1, EA#, and Ports 1 and 2 when configured as inputs.
2. Maximum current that an external device must sink to ensure test mode entry.
3. Violating these specifications during reset may cause the device to enter test modes.
4. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions
for typical values are room temperature and VREF = VCC = 5.5 V.
5. Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
6. All voltages are referenced relative to VSS. When used, VSS refers to the device pin.
7. Table 9 lists the total current limits during normal (non-transient conditions). The total current listed is the
sum of the pins listed for each specification value.
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Table 8. DC Characteristics over Specified Operating Conditions (Continued)
Symbol
Parameter
Min Typ (4) Max Units Test Conditions
IIL1 Input Low Current (P5.4
and P2.6 during reset) (2)
– 10
mA VIN = 0.8 V
IIL2 Input Low Current (ports 3,
4, and 5, except P5.4)
– 300
µA VIN = 0.8 V
IIL3 Input Low Current (port 1)
IOH
Output High Current (P5.4
– 0.2
and P2.6 during reset) (3)
– 300
µA VIN = 0.3 VCC
mA 0.7 VCC
IOH1 Output High Current
(P6.5:0 during reset)
–6
– 40
µA 0.7 VCC
ICC VCC Supply Current
IREF A/D Reference Supply
Current
50 70 mA XTAL1 = 16 MHz
VCC = 5.5 V
VPP = 5.5 V
VREF = 5.5 V
2 5 mA
IIDLE Idle Mode Current
IPD Powerdown Mode Current
(4)
15 30 mA
5 50 µA
RRST
Reset Pull-up Resistor
6
65 k
CS Pin Capacitance (any pin
to VSS)
10 pF FTEST = 1.0 MHz
NOTES:
1. Standard input pins include XTAL1, EA#, and Ports 1 and 2 when configured as inputs.
2. Maximum current that an external device must sink to ensure test mode entry.
3. Violating these specifications during reset may cause the device to enter test modes.
4. Typical values are based on a limited number of samples and are not guaranteed. Operating conditions
for typical values are room temperature and VREF = VCC = 5.5 V.
5. Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
6. All voltages are referenced relative to VSS. When used, VSS refers to the device pin.
7. Table 9 lists the total current limits during normal (non-transient conditions). The total current listed is the
sum of the pins listed for each specification value.
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70
60
50
ICC 40
(mA)
30
20
10
0
0
4 10
Frequency (MHz)
ICC Max
ICC Typ
IIDLE Max
IIDLE Typ
16
A2711-01
Table 9. Total Current Limits During Normal (Non-transient) Conditions
Signal Names
Port 1
Port 2, P6.6, P6.7
Port 3
Port 4
Port 5
P6.5:0
Maximum IOL Limits
25 mA
40 mA
40 mA
40 mA
40 mA
40 mA
Maximum IOH Limits
– 25 mA
– 40 mA
– 30 mA
– 30 mA
– 30 mA
– 30 mA
Figure 6. ICC, IIDLE versus Frequency
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EXPLANATION OF AC SYMBOLS
Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pair indicate a signal
and its condition, respectively. Symbols represent the time between the two signal/condition points. For example,
TRHDZ is the time between signal R (RD#) condition H (high) and signal D (Input Data) condition Z (floating). Table
10 defines the signal and condition codes.
Table 10. AC Timing Symbol Definitions
Signals
Conditions
A Address
P PROG#
H High
B BHE#
Q Data Out
L Low
D Data In
R RD#
V Valid
G BUSWIDTH
V PVER
X No Longer Valid
I T1DIR/AINC#
W WR#/WRH#/WRL# Z Floating
K T1CLK
X XTAL1
L ALE/ADV#/PALE# Y READY
AC CHARACTERISTICS (OVER SPECIFIED OPERATION CONDITIONS)
Table 11 defines the AC timing specifications that the external memory system must meet and those that the
8XC196MH will provide.
Table 11. AC Timing Definitions (1)
Symbol
Parameter
Min Max Units Notes
FOSC
TOSC
Frequency on XTAL1
8 16
1/FOSC
62.5 125
The External Memory System Must Meet These Specifications
MHz
ns
4
TAVYV
Address Valid to READY Setup
2TOSC – 75
ns
TLLYV
ALE/ADV# Low to READY Setup
TOSC – 70
ns
TYLYH
Non READY Time
No Upper Limit
ns
TLLYX
READY Hold after ALE/ADV# Low
TOSC – 15
2TOSC – 40
ns
2
TAVGV
Address Valid to BUSWIDTH Setup
2TOSC – 75
ns
TLLGV
ALE/ADV# Low to BUSWIDTH Setup
TOSC – 60
ns
NOTES:
1. Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FOSC = 16 MHz.
2. Exceeding the maximum specification causes additional wait states.
3. If wait states are used, add 2TOSC × n, where n = number of wait states.
4. Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
5. Assuming back-to-back bus cycles.
6. 8-bit bus only.
23


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®
Table 11. AC Timing Definitions (1) (Continued)
Symbol
Parameter
Min Max Units Notes
The External Memory System Must Meet These Specifications (Continued)
TLLGX
BUSWIDTH Hold after ALE/ADV# Low
TOSC
ns
TLHDV
ALE/ADV# High to Input Data Valid
3TOSC – 55
ns
TAVDV
Address Valid to Input Data Valid
3TOSC – 55 ns 3
TRLDV
RD# Active to Input Data Valid
TOSC – 30 ns 3
TRHDZ
End of RD# to Input Data Float
TOSC
ns
TRXDX
Data Hold after RD# Inactive
0
ns
The 8XC196MH will Meet These Specifications
TXHLH
XTAL1 Rising Edge to ALE Rising
20 110 ns
TXHLL
XTAL1 Rising Edge to ALE Falling
20 110 ns
TLHLH
ALE/ADV# Cycle Time
4TOSC
ns 3
TLHLL
ALE/ADV# High Period
TOSC – 10
TOSC + 10
ns
TAVLH
Address Valid to ALE/ADV# High
TOSC – 17
ns
TAVLL
Address Valid to ALE/ADV# Low
TOSC – 17
ns
TLLAX
Address Hold after ALE/ADV# Low
TOSC – 40
ns
TLLRL
ALE/ADV# Low to RD# Low
TOSC – 30
ns
TRLRH
RD# Low Period
TOSC – 5
TOSC + 25 ns 3
TRHLH
RD# High to ALE/ADV# High
TOSC
TOSC + 25 ns 5
TRLAZ
RD# Low to Address Float
5 ns
TLLWL
ALE/ADV# Low to WR# Low
TOSC – 10
ns
TQVWH
Data Valid before WR# High
TOSC – 23
ns
TWLWH
WR# Low Period
TOSC – 30
ns 3
TWHQX
Data Hold after WR# High
TOSC – 25
ns
TWHLH
WR# High to ALE/ADV# High
TOSC – 10
TOSC + 15 ns 5
TWHBX
BHE#, INST Hold after WR# High
TOSC – 10
ns
TWHAX
A15:8 Hold after WR# High
TOSC – 30
ns 6
TRHBX
BHE#, INST Hold after RD# High
TOSC – 10
ns
TRHAX
A15:8 Hold after RD# High
TOSC – 30
ns 6
NOTES:
1. Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FOSC = 16 MHz.
2. Exceeding the maximum specification causes additional wait states.
3. If wait states are used, add 2TOSC × n, where n = number of wait states.
4. Testing is performed down to 8 MHz, although the device is static by design and will typically operate
below 1 Hz.
5. Assuming back-to-back bus cycles.
6. 8-bit bus only.
24


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SYSTEM BUS TIMINGS
XTAL1
ALE
RD#
BUS
WR#
BUS
INST
A15:8
(8-bit Bus)
TXHLL
TOSC
TLHLH
TLHLL
TLHDV
TLLRL
TRLRH
TXHLH
TRHLH
TAVLH
TLLAX
TAVLL
TRLAZ
Address Out
TAVDV
TLLWL
TRLDV
TWLWH
TRHDZ
TRXDX
Data
TWHLH
TQVWH
TWHQX
Address Out
Valid
Address Out
Data Out
TRHBX
TWHBX
TRHAX
TWHAX
Figure 7. System Bus Timing Diagram
Address Out
A2543-01
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
READY TIMING (ONE WAIT STATE)
XTAL1
ALE
READY
RD#
Bus
WR#
Bus
TOSC
TLHLH + 2TOSC
TLLYX(Max)
TLLYX(Min)
TLLYV
16 MHz
8 MHz
TCLYX(Max)
TCLYX(Min)
TAVYV
TRLRH + 2TOSC
TRLDV + 2TOSC
TAVDV + 2TOSC
Address Out
TWLWH + 2TOSC
Data In
Address Out
TRLDV + 2TOSC
TQVWH + 2TOSC
Data Out
Address
®
Figure 8. READY Timing Diagram (One Wait State)
A2544-01
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BUSWIDTH TIMING
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
XTAL1
ALE
Bus
BUSWIDTH
TOSC
Address Out
TAVGV
TLLGV
TLLGX
Data In
EXTERNAL CLOCK DRIVE
Figure 9. BUSWIDTH Timing Diagram
Symbol
1/TXLXL
TXLXL
TXHXX
TXLXX
TXLXH
TXHXL
Table 12. External Clock Drive Timing
Parameter
Oscillator Frequency
Oscillator Period (TOSC)
High Time
Low Time
Rise Time
Fall Time
Min
8
62.5
22
22
Max
16
125
10
10
A2545-01
Units
MHz
ns
ns
ns
ns
ns
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®
0.7 VCC
XTAL1
TXHXX
0.7 VCC
TXLXH
0.8 V
TXLXX
0.8 V
0.7 VCC
TXLXL
Figure 10. External Clock Drive Waveforms
TXHXL
A2578-01
External
Clock Input
VCC
4.7k*
XTAL1
Clock Driver
No Connect
8XC196 Device
XTAL2
Note:
*Required if TTL driver is used. Not needed if CMOS driver is used.
Figure 11. External Clock Connections
A0274-01
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® 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
C1
VSS
XTAL1
8XC196 Device
XTAL2
C2
Quartz Crystal
Note:
Keep oscillator components close to the chip and use
short, direct traces to XTAL1, XTAL2, and Vss. When
using crystals, C1=C220pF. When using ceramic
resonators, consult the manufacturer for recommended
oscillator circuitry.
Figure 12. External Crystal Connections
3.5 V
0.45 V
2.0 V
0.8 V
Test Points
2.0 V
0.8 V
AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for
a logic "0". Timing measurements are made at 2.0 V for a logic
"1" and 0.8 V for a logic "0".
Figure 13. AC Testing Input, Output Waveforms
A0273-01
A2120-02
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8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
®
VLOAD + 0.1 V
VLOAD
VLOAD – 0.1 V
Timing Reference
Points
VOH – 0.1 V
VOL + 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading VOH/VOL level occurs
with IOL/IOH 15 mA.
Figure 14. Float Waveforms
A2579-01
AC CHARACTERISTICS — SERIAL PORT, SHIFT REGISTER MODE
Table 13. Serial Port Timing — Shift Register Mode (Mode 0)
Symbol
Parameter
Min
TXLXL
Serial Port Clock Period
(Baud-raten 8002H)
(Baud-raten = 8001H)
6TOSC
4TOSC
TXLXH
Serial Port Clock Low Period
(Baud-raten 8002H)
(Baud-raten = 8001H)
4TOSC – 50
2TOSC – 50
TQVXH
Output Data Setup to Clock High
2TOSC – 50
TXHQX
Output Data Hold after Clock High
2TOSC – 50
TXHQV
Next Output Data Valid after Clock High
TDVXH
Input Data Setup to Clock High
TOSC + 50
TXHDX
Input Data Hold after Clock High
0
TXHQZ
Last Clock High to Output Float
NOTES:
1. n for Baud-raten signifies Serial Port 0 or 1.
2. Maximum Serial Port Mode 0 reception is with Baud-raten 8002H.
Max
4TOSC + 50
2TOSC + 50
2TOSC + 50
TOSC
Units Notes
ns
ns 1, 2
ns
ns 1, 2
ns
ns
ns
ns
ns
ns
30




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