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8XC196KB 8XC196KB16
COMMERCIAL EXPRESS CHMOS MICROCONTROLLER
Y 8 Kbytes of On-Chip ROM OTP
Available
Y 232 Byte Register File
Y Register-to-Register Architecture
Y 28 Interrupt Sources 16 Vectors
Y 1 75 ms 16 x 16 Multiply (16 MHz)
Y 3 0 ms 32 16 Divide (16 MHz)
Y Powerdown and Idle Modes
Y Five 8-Bit I O Ports
Y 16-Bit Watchdog Timer
Y 12 MHz and 16 MHz Available
Y Dedicated 15-Bit Baud Rate Generator
Y Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y Full Duplex Serial Port
Y High Speed I O Subsystem
Y 16-Bit Timer
Y 16-Bit Up Down Counter with Capture
Y Pulse-Width-Modulated Output
Y Four 16-Bit Software Timers
Y 10-Bit A D Converter with Sample Hold
Y HOLD HLDA Bus Protocol
Y Extended Temperature Available
The 8XC196KB is a 16-bit microcontroller available in three different memory varieties ROMless (80C196KB)
8K ROM (83C196KB) and 8K OTP (One Time Programmable 87C196KB) The 8XC196KB is a high perform-
ance member of the MCS 96 microcontroller family The 8XC196KB has the same peripheral set as the
8096BH and has a true superset of the 8096BH instructions Intel’s CHMOS process provides a high perform-
ance processor along with low power consumption To further reduce power requirements the processor can
be placed into Idle or Powerdown Mode
Bit byte word and some 32-bit operations are available on the 80C196KB With a 16 MHz oscillator a 16-bit
addition takes 0 50 ms and the instruction times average 0 37 ms to 1 1 ms in typical applications
Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are
available for pulse or waveform generation The high-speed output can also generate four software timers or
start an A D conversion Events can be based on the timer or up down counter Also provided on-chip are an
A D converter serial port watchdog timer and a pulse-width-modulated output signal
The 8XC196KB has a maximum guaranteed frequency of 12 MHz The 8XC196KB16 has a maximum guaran-
teed frequency of 16 MHz All references to the 80C196KB also refer to the 80C196KB16 83C196KB Rxxx
87C196KB and 87C196KB16 unless otherwise noted The ROM device does not have a speed indicator at the
end of the device name Instead it has a ROM code number
With the commercial (standard) temperature option operational characteristics are guaranteed over the tem-
perature range of 0 C to a70 C With the extended temperature range option operational characteristics are
guaranteed over the temperature range of b40 C to a85 C
Package Designators N e 68-pin PLCC S e 80-pin QFP (commercial only) Prefix Designators T e Extend-
ed Temperature
Other brands and names are the property of their respective owners
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
July 1994
Order Number 270909-006


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Figure 1 8XC196KB Block Diagram
270909 – 1
2


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PROCESS INFORMATION
This device is manufactured on P629 0 and 629 1 a
CHMOS III-E process Additional process and reli-
ability information is available in Intel’s Components
Quality and Reliability Handbook Order Number
210997
270909 – 2
EXAMPLE N87C196KB16 is 68-Lead PLCC
OTPROM 16 MHz
For complete package dimensional data refer to the
Intel Packaging Handbook (Order Number 240800)
NOTE
1 EPROMs are available as One Time Programmable
(OTPROM) only
Figure 2 The 8XC196KB Nomenclature
Table 1 Thermal Characteristics
Package
Type
ija
ijc
PLCC
35 C W
13 C W
QFP
70 C W
4C W
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation Values will change
depending on operation conditions and application See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology
Table 2 8XC196KB Memory Map
Description
Address
External Memory or I O
0FFFFH
04000H
Internal ROM EPROM or External
Memory (Determined by EA)
3FFFH
2080H
Reserved Must contain FFH
(Note 5)
207FH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM EPROM Security Key
202FH
2020H
Reserved Must contain FFH
(Note 5)
201FH
201AH
Reserved Must Contain 20H
(Note 5)
2019H
CCB
2018H
Reserved Must contain FFH
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
Port 3 and Port 4
1FFFH
1FFEH
External Memory
1FFDH
0100H
232 Bytes Register RAM (Note 1)
00FFH
0018H
CPU SFR’s (Notes 1 3)
0017H
0000H
NOTES
1 Code executed in locations 0000H to 00FFH will be
forced external
2 Reserved memory locations must contain 0FFH unless
noted
3 Reserved SFR bit locations must contain 0
4 Refer to 8XC196KB quick reference for SFR descrip-
tions
5 WARNING Reserved memory locations must not be
written or read The contents and or function of these lo-
cations may change with future revisions of the device
Therefore a program that relies on one or more of these
locations may not function properly
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270909 – 3
Figure 3 68-Pin Package (PLCC Top View)
NOTE
The above pin out diagram applies to the OTP (87C196KB) device The OTP device uses all of the programming pins shown
above The ROM (83C196KB) device only uses programming pins AINC PALE PMODE n and PROG The ROMless
(80C196KB) doesn’t use any of the programming pins
4


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NOTE
N C means No Connect (do not connect these pins)
270909 – 4
Figure 4 80-Pin QFP Package
NOTE
The above pin out diagram applies to the OTP (87C196KB) device The OTP device uses all of the programming pins shown
above The ROM (83C196KB) device only uses programming pins AINC PALE PMODE n and PROG The ROMless
(80C196KB) doesn’t use any of the programming pins
5


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PIN DESCRIPTIONS
Symbol
Name and Function
VCC
VSS
VREF
Main supply voltage (5V)
Digital circuit ground (0V) There are multiple VSS pins all of them must be connected
Reference voltage for the A D converter (5V) VREF is also the supply voltage to the analog
portion of the A D converter and the logic used to read Port 0 Must be connected for A D
and Port 0 to function
ANGND
VPP
XTAL1
Reference ground for the A D converter Must be held at nominally the same potential as
VSS Connect VSS and ANGND at chip to avoid noise problems
Programming voltage Also timing pin for the return from power down circuit
Input of the oscillator inverter and of the internal clock generator
XTAL2
Output of the oscillator inverter
CLKOUT
Output of the internal clock generator The frequency of CLKOUT is the oscillator
frequency It has a 50% duty cycle
RESET
Reset input to and open-drain output from the chip Input low for at least 4 state times to reset
the chip The subsequent low-to-high transition re-synchronizes CLKOUT and commences a
10-state-time RESET sequence
BUSWIDTH Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus
cycle in progress If BUSWIDTH is a 1 a 16-bit bus cycle occurs If BUSWIDTH is a 0 an 8-bit
cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus
NMI A positive transition causes a vector through 203EH
INST
Output high during an external memory read indicates the read is an instruction fetch and
output low indicates a data fetch INST is valid throughout the bus cycle INST is activated
only during external memory accesses
EA Input for memory select (External Access) EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM OTPROM EA equal to a
TTL-low causes accesses to these locations to be directed to off-chip memory
ALE ADV
Address Latch Enable or Address Valid output as selected by CCR Both pin options provide
a latch to demultiplex the address from the address data bus When the pin is ADV it goes
inactive high at the end of the bus cycle ALE ADV is activated only during external memory
accesses
RD Read signal output to external memory RD is activated only during external memory reads
WR WRL
Write and Write Low output to external memory as selected by the CCR WR will go low for
every external write while WRL will go low only for external writes where an even byte is
being written WR WRL is activated only during external memory writes
BHE WRH
Bus High Enable or Write High output to external memory as selected by the CCR BHE will
go low for external writes to the high byte of the data bus WRH will go low for external writes
where an odd byte is being addressed BHE WRH is activated only during external memory
writes
READY
Ready input to lengthen external memory cycles If the pin is low prior to the falling edge of
CLKOUT the memory controller goes into a wait mode until the next positive transition in
CLKOUT occurs with READY high When the external memory is not being used READY has
no effect Internal control of the number of wait states inserted into a bus cycle (held not
ready) is available in the CCR
HSI Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 and HSI 3
Two of them (HSI 2 and HSI 3) are shared with the HSO Unit
HSO
Outputs from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1 HSO 2
HSO 3 HSO 4 and HSO 5 Two of them (HSO 4 and HSO 5) are shared with the HSI Unit
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PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
Port 0
8-bit high impedance input-only port Three pins can be used as digital inputs and or as
analog inputs to the on-chip A D converter
Port 1
8-bit quasi-bidirectional I O port These pins are shared with HOLD HLDA and BREQ
Port 2
8-bit multi-functional port All of its pins are shared with other functions in the 87C196KB
Pins P2 6 and P2 7 are quasi-bidirectional
Ports 3 and 4 8-bit bidirectional I O ports with open drain outputs These pins are shared with the
multiplexed address data bus which has strong internal pullups
HOLD
Bus Hold input requesting control of the bus Enabled by setting WSR 7
HLDA
Bus Hold acknowledge output indicating release of the bus Enabled by setting WSR 7
BREQ
Bus Request output activated when the bus controller has a pending external memory
cycle Enabled by setting WSR 7
TxD The TxD pin is used for serial port transmission in Modes 1 2 and 3 In Mode 0 the pin is
used as the serial clock output
RxD Serial Port Receive pin used for serial port reception In Mode 0 the pin functions as input or
output data
EXTINT
A rising edge on the EXTINT pin will generate an external interrupt
T2CLK
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input
T2RST
A rising edge on the T2RST pin will reset Timer2
PWM
The pulse width modulator output
T2UP-DN
The T2UPDN pin controls the direction of Timer2 as an up or down counter
T2CAPTURE A rising edge on P2 7 will capture the value of Timer2 in the T2CAPTURE register
PMODE
Programming Mode Select Determines the EPROM programming algorithm that is
performed PMODE is sampled after a chip reset and should be static while the part is
operating
SID Slave ID Number Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement
PALE
Programming ALE Input Accepted by the 87C196KB when it is in Slave Programming
Mode Used to indicate that Ports 3 and 4 contain a command address
PROG
Programming Falling edge indicates valid data on PBUS and the beginning of
programming Rising edge indicates end of programming
PACT
Programming Active Used in the Auto Programming Mode to indicate when programming
activity is complete
PVAL
Program Valid This signal indicates the success or failure of programming in the Auto
Programming Mode A zero indicates successful programming
PVER
Program Verification Used in Slave Programming and Auto CLB Programming Modes
Signal is low after rising edge of PROG if the programming was not successful
AINC
Auto Increment Active low signal indicates that the auto increment mode is enabled Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write
Ports 3
and 4
(Programming
Mode)
Address Command Data Bus Used to pass commands addresses and data to and from
slave mode 87C196KBs Used by chips in Auto Programming Mode to pass command
addresses and data to slaves Also used in the Auto Programming Mode as a regular
system bus to access external memory Should have pullups to VCC when used in slave
programming mode
7


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ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature
Under Bias
Storage Temperature
Voltage On Any Pin to VSS
Power Dissipation(1)
b55 C to a125 C
b65 C to a150 C
b0 5V to a7 0V
1 5W
NOTE
1 Power dissipation is based on package heat transfer lim-
itations not device power consumption
NOTICE This data sheet contains preliminary infor-
mation on new products in production The specifica-
tions are subject to change without notice Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design
WARNING Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted )
Symbol
Description
Min Max Units
TA
VCC
VREF
FOSC
FOSC
Ambient Temperature Under Bias
Digital Supply Voltage
Analog Supply Voltage
Oscillator Frequency 12 MHz
Oscillator Frequency 16 MHz
0
4 50
4 50
35
35
a70
5 50
5 50
12
16
C
V
V
MHz
MHz
NOTE
ANGND and VSS should be nominally at the same potential
DC CHARACTERISTICS
Symbol
Description
Min Max Units Test Conditions
VIL Input Low Voltage
b0 5
08 V
VIH Input High Voltage (All Pins except 0 2 VCC a 0 9 VCC a 0 5 V
XTAL1 and RESET)
VIH1
VIH2
VOL
Input High Voltage on XTAL 1
Input High Voltage on RESET
Output Low Voltage
VOH Output High Voltage
(Standard Outputs)(2)
VOH1
Output High Voltage
(Quasi-bidirectional Outputs)(1)
ILI Input Leakage Current
(Std Inputs)(3)
0 7 VCC
26
VCC b 0 3
VCC b 0 7
VCC b 1 5
VCC b 0 3
VCC b 0 7
VCC b 1 5
VCC a 0 5 V
VCC a 0 5 V
03
0 45
15
V IOL e 200 mA
V IOL e 3 2 mA
V IOL e 7 mA
V IOH e b200 mA
V IOH e b3 2 mA
V IOH e b7 mA
V IOH e b10 mA
V IOH e b30 mA
V IOH e b60 mA
g10
mA 0 k VIN k VCC b 0 3V
ILI1 Input Leakage Current (Port 0)
ITL 1 to 0 Transition Current
(QBD Pins)(1)
a3
b800
mA 0 k VIN k VREF
mA VIN e 2 0V
IIL Logical 0 Input Current (QBD Pins)(1)
b50
mA VIN e 0 45V
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DC CHARACTERISTICS (Continued)
Symbol
Description
Min Typ(7) Max Units
Test Conditions
IIL1 Logical 0 Input Current in Reset
BHE WR P2 0
b850 mA VIN e 0 45V
IIL2 Logical 0 Input Current in Reset
ALE RD INST
b7 mA VIN e 0 45V
IIH1 Logical 1 Input Current
on NMI Pin
100 mA VIN e 2 0V
Hyst
Hysteresis on RESET Pin
300
mV
ICC
IREF
IIDLE
IPD
RRST
CS
Active Mode Current in Reset
A D Converter Reference Current
Idle Mode Current
Powerdown Mode Current
Reset Pullup Resistor
Pin Capacitance (Any Pin to VSS)
6K
50
2
10
5
60 mA XTAL1 e 16 MHz
5 mA VCC e VPP e VREF e 5 5V
25 mA
30 mA VCC e VPP e VREF e 5 5V
50K X
10 pF FTEST e 1 0 MHz
NOTES (Notes apply to all specifications)
1 QBD (Quasi-bidirectional) pins include Port 1 P2 6 and P2 7
2 Standard Outputs include AD0–15 RD WR ALE BHE INST HSO pins PWM P2 5 CLKOUT RESET Ports 3 and 4
TXD P2 0 and RXD (in serial mode 0) The VOH specification is not valid for RESET Ports 3 and 4 are open-drain outputs
3 Standard Inputs include HSI pins EA READY BUSWIDTH NMI RXD P2 1 EXTINT P2 2 T2CLK P2 3 and T2RST
P2 4
4 Maximum current per pin must be externally limited to the following values if VOL is held above 0 45V or VOH is held
below VCC b 0 7V
IOL on Output pins 10 mA
IOH on quasi-bidirectional pins self limiting
IOH on Standard Output pins 10 mA
5 Maximum current per bus pin (data and control) during normal operation is g3 2 mA
6 During normal (non-transient) conditions the following total current limits apply
Port 1 P2 6
IOL 29 mA
IOH is self limiting
HSO P2 0 RXD RESET IOL 29 mA
IOH 26 mA
P2 5 P2 7 WR BHE
IOL 13 mA
IOH 11 mA
AD0 – AD15
IOL 52 mA
IOH 52 mA
RD ALE INST – CLKOUT IOL 13 mA
IOH 13 mA
7 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature
and VREF e VCC e 5V
ICC Max e 3 88 c FREQ a 8 43
IIDLE Max e 1 65 c FREQ a 2 2
Figure 6 ICC and IIDLE vs Frequency
270909 – 5
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AC CHARACTERISTICS
Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 12 16 MHz
The system must meet these specifications to work with the 87C196KB
Symbol
Description
Min Max
TAVYV
TYLYH
TCLYX
TLLYX
TAVGV
TCLGX
TAVDV
TRLDV
TCLDV
TRHDZ
TRXDX
Address Valid to READY Setup
NonREADY Time
READY Hold after CLKOUT Low
READY Hold after ALE Low
Address Valid to Buswidth Setup
Buswidth Hold after CLKOUT Low
Address Valid to Input Data Valid
RD Active to Input Data Valid
CLKOUT Low to Input Data Valid
End of RD to Input Data Float
Data Hold after RD Inactive
2 TOSC b 75
No upper limit
0
TOSC b 15
0
TOSC b 30
2 TOSC b 40
2 TOSC b 75
3 TOSC b 55
TOSC b 23
TOSC b 50
TOSC b 20
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(Note 1)
(Note 1)
(Note 2)
(Note 2)
NOTES
1 If max is exceeded additional wait states will occur
2 When using wait states add 2 TOSC c n where n e number of wait states
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AC CHARACTERISTICS (Continued)
Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 12 16 MHz
The 87C196KB will meet these specifications
Symbol
Description
FXTAL
FXTAL
TOSC
TOSC
TXHCH
TCLCL
TCHCL
TCLLH
TLLCH
TLHLH
TLHLL
TAVLL
TLLAX
TLLRL
TRLCL
TRLRH
TRHLH
TRLAZ
TLLWL
TCLWL
TQVWH
TCHWH
TWLWH
TWHQX
TWHLH
TWHBX
TRHBX
TWHAX
TRHAX
Frequency on XTAL1 12 MHz
Frequency on XTAL1 16 MHz
1 FXTAL 12 MHz
1 FXTAL 16 MHz
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
CLKOUT High Period
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
ALE High Period
Address Setup to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
RD Low to CLKOUT Falling Edge
RD Low Period
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
ALE Falling Edge to WR Falling Edge
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE INST HOLD after WR Rising Edge
BHE INST HOLD after RD Rising Edge
AD8–15 hold after WR Rising Edge
AD8–15 hold after RD Rising Edge
Min Max
3 5 12 0
3 5 16 0
83 3
286
62 5
286
a20
a110
2 TOSC
TOSC b 10 TOSCa10
b10
a10
b15
a15
4 TOSC
TOSC b 10 TOSCa10
TOSC b 20
TOSC b 40
TOSC b 35
a4 a25
TOSCb5
TOSC
TOSC a 25
TOSC a 25
a5
TOSC b 10
0
a25
TOSC b 23
b5
a15
TOSC b 15
TOSC b 15
TOSC b 15
TOSC b 15
TOSC b 10
TOSC b 30
TOSC b 25
TOSC a 5
TOSC a 10
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(Note 2)
(Note 2)
(Note 3)
(Note 3)
(Note 1)
(Note 3)
(Note 3)
(Note 1)
NOTES
1 Assuming back-to-back bus cycles
2 Testing performed at 3 5 MHz however the device is static by design and will typically operate below 1 Hz
3 When using wait states all 2 TOSCa n where n e number of wait states
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System Bus Timings
270909 – 6
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READY Timings (One Wait State)
8XC196KB 8XC196KB16
Buswidth Bus Timings
270909 – 7
270909 – 8
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HOLD HLDA Timings
Symbol
Description
THVCH
TCLHAL
TCLBRL
THALAZ
THALBZ
TCLHAH
TCLBRH
THAHAX
THAHAV
THAHBX
THAHBV
TCLLH
HOLD Setup
CLKOUT Low to HLDA Low
CLKOUT Low to BREQ Low
HLDA Low to Address Float
HLDA Low to BHE INST RD WR Float
CLKOUT Low to HLDA High
CLKOUT Low to BREQ High
HLDA High to Address No Longer Float
HLDA High to Address Valid
HLDA High to BHE INST RD WR No Longer Float
HLDA High to BHE INST RD WR Valid
CLKOUT Low to ALE High
NOTE
1 To guarantee recognition at next clock
Min
55
b15
b15
b15
0
b20
0
b5
Max
15
15
10
10
15
15
15
Maximum Hold Latency
Bus Cycle Type
Internal Access
16-Bit External Execution
8-Bit External
Latency
1 5 States
2 5 States
4 5 States
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(Note 1)
270909 – 9
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EXTERNAL CLOCK DRIVE
Symbol
Parameter
1 TXLXL
1 TXLXL
TXLXL
TXLXL
TXHXX
TXLXX
TXLXH
TXHXL
Oscillator Frequency 12 MHz
Oscillator Frequency 16 MHz
Oscillator Period 12 MHz
Oscillator Period 16 MHz
High Time
Low Time
Rise Time
Fall Time
EXTERNAL CLOCK DRIVE WAVEFORMS
8XC196KB 8XC196KB16
Min
Max
Units
35
12 0
MHz
3 5 16 MHz
83 3
286
ns
62 5
286
ns
21 25
ns
21 25
ns
10 ns
10 ns
270909 – 10
An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up This is due to
interaction between the amplifier and its feedback capacitance Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
270909 – 11
NOTE
Keep oscillator components close to chip and use
short direct traces to XTAL1 XTAL2 and VSS When
using crystals C1 e 20 pF C2 e 20 pF When using
ceramic resonators consult manufacturer for recom-
mended circuitry
AC TESTING INPUT OUTPUT WAVEFORMS
Required if open-collector TTL driver used
Not needed if CMOS driver is used
270909 – 12
FLOAT WAVEFORMS
270909 – 13
AC Testing inputs are driven at 2 4V for a Logic ‘‘1’’ and 0 45V for
a Logic ‘‘0’’ Timing measurements are made at 2 0V for a Logic
‘‘1’’ and 0 8V for a Logic ‘‘0’’
270909 – 14
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs and Begins to Float
when a 200 mV change from the Loaded VOH VOL Level occurs
IOL IOH e g15 mA
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EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’ for time The characters in a pair indicate a signal and its
condition respectively Symbols represent the time between the two signal condition points
Conditions
Signals
H - High
L - Low
V - Valid
X - No Longer Valid
Z - Floating
A - Address
B - BHE
BR - BREQ
C - CLKOUT
D - DATA IN
G - Buswidth
H - HOLD
HA - HLDA
L - ALE ADV
Q - DATA OUT
R - RD
W - WR WRH WRL
X - XTAL1
Y - READY
AC CHARACTERISTICS SERIAL PORT SHIFT REGISTER MODE
SERIAL PORT TIMING SHIFT REGISTER MODE (MODE 0)
Symbol
Parameter
Min
Max
Units
TXLXL
TXLXH
TXLXL
TXLXH
TQVXH
TXHQX
TXHQV
TDVXH
TXHDX
TXHQZ
Serial Port Clock Period (BRR t 8002H)
6 TOSC
Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) 4 TOSC b 50 4 TOSC a 50
Serial Port Clock Period (BRR e 8001H)
4 TOSC
Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) 2 TOSC b 50 2 TOSC a 50
Output Data Setup to Clock Rising Edge
2 TOSC b50
Output Data Hold after Clock Rising Edge
Next Output Data Valid after Clock Rising Edge
Input Data Setup to Clock Rising Edge
Input Data Hold after Clock Rising Edge
2 TOSC b50
TOSC a50
0
2 TOSC a50
Last Clock Rising to Output Float
2 TOSC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WAVEFORM SERIAL PORT SHIFT REGISTER MODE
SERIAL PORT WAVEFORM SHIFT REGISTER MODE (MODE 0)
270909 – 18
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10-BIT A D CHARACTERISTICS
State times are calculated as follows
At a clock speed of 6 MHz or less the clock prescal-
er should be disabled This is accomplished by set-
2
state time e
XTAL1
ting IOC2 4 e 1
The converter is ratiometric so the absolute accura-
At higher frequencies (greater than 6 MHz) the clock
prescaler should be enabled (IOC2 4 e 0) to allow
the comparator to settle
cy is directly dependent on the accuracy and stability
of VREF VREF must be close to VCC since it supplies
both the resistor ladder and the digital section of the
converter
The table below shows two different clock speeds
and their corresponding A D conversion and sample
times
See the MCS-96 A D Converter Quick Reference
for definition of A D terms
Example Sample and Conversion Times
A D Clock
Prescaler
xIOC2 4 e 0 ON
xIOC2 4 e 1 OFF
Clock Speed
(MHz)
16
6
Sample Time
(States)
15
8
Sample Time
at Clock
Speed
(ms)
1 875
2 667
Conversion
Time
(States)
156 5
89 5
Conversion
Time at
Clock Speed
(ms)
19 6
29 8
A D CONVERTER SPECIFICATIONS
Parameter
Typical(1)
Resolution
Absolute Error
Full Scale Error
Zero Offset Error
Non-Linearity Error
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
Temperature Coefficients
Offset
Full Scale
Differential Non-Linearity
Off Isolation
Feedthrough
VCC Power Supply Rejection
Input Series Resistance
DC Input Leakage
Sampling Capacitor
0 25 g0 50
0 25 g0 50
1 5 g2 5
g0 1
g0 25
0 009
0 009
0 009
b60
b60
3
Minimum
1024
10
0
0
lb1
0
b60
750
0
NOTES
An ‘‘LSB’’ as used here has a value of approximately 5 mV
1 Typical values are expected for most devices at 25 C
2 DC to 100 KHz
3 Multiplexer Break-Before-Make Guaranteed
4 Resistance from device pin through internal MUX to sample capacitor
Maximum
1024
10
g3
g3
a2
g1
1 2K
g3 0
Units
Levels
Bits
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSB C
LSB C
LSB C
dB
dB
dB
X
mA
pF
Notes
23
2
2
4
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OTPROM SPECIFICATIONS
OTPROM PROGRAMMING OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Units
TA
VCC VPD VREF(1)
VEA
VPP
VSS ANGND(3)
FOSC
FOSC
Ambient Temperature During Programming
Supply Voltages During Programming
Programming Mode Supply Voltage
EPROM Programming Supply Voltage
Digital and Analog Ground
Oscillator Frequency 12 MHz
Oscillator Frequency 16 MHz
20
45
12 50
12 50
0
60
60
30
55
13 0
13 0
0
12 0
16 0
C
V
V(2)
V(2)
V
MHz
MHz
NOTES
1 VCC VPD and VREF should nominally be at the same voltage during programming
2 VEA and VPP must never exceed the maximum voltage for any amount of time or the device may be damaged
3 VSS and ANGND should nominally be at the same voltage (0V) during programming
AC OTPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Min
TSHLL
TLLLH
TAVLL
TLLAX
TLLVL
TPLDV
TPHDX
TDVPL
TPLDX
TPLPH
TPHLL
TLHPL
TPHPL
TPHIL
TILIH
TILVH
TILPL
TPHVL
Reset High to First PALE Low
PALE Pulse Width
Address Setup Time
Address Hold Time
PALE Low to PVER Low
PROG Low to Word Dump Valid
Word Dump Data Hold
Data Setup Time
Data Hold Time
PROG Pulse Width
PROG High to Next PALE Low
PALE High to PROG Low
PROG High to Next PROG Low
PROG High to AINC Low
AINC Pulse Width
PVER Hold after AINC Low
AINC Low to PROG Low
PROG High to PVER Low
1100
40
0
50
0
50
40
120
220
120
0
40
50
170
Max
60
50
50
90
Units
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
TOSC
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DC OTPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Min Max Units
IPP VPP Supply Current (When Programming)
100 mA
NOTE
Do not apply VPP until VCC is stable and within specifications and the oscillator clock has stabilized or the device may be
damaged
OTPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
270909 – 15
SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT
270909 – 16
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SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT
270909 – 17
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FUNCTIONAL DEVIATIONS
Devices marked with an ‘‘E’’ ‘‘F’’ or ‘‘G’’ have the
following errata
1 Missed Interrupt on P0 7 EXTINT
Interrupts occurring on P0 7 could be missed since
the INT PEND EXTINT bit may not be set See
techbit MC0893
2 HSI MODE Divide-by-Eight
See Faxback 2192
REVISION HISTORY
This data sheet (270909-006) is valid for devices
with an ‘‘E’’ ‘‘F’’ or ‘‘G’’ at the end of the top side
tracking number Data sheets are changed as new
device information becomes available Verify with
your local Intel sales office that you have the latest
version before finalizing a design or ordering devic-
es
The following differences exist between this data
sheet (270909-006) and (270909-005)
1 Removed ‘‘Word Addressable Only’’ from Port 3
and 4 in Table 2
2 Removed ICC1 active mode current at 3 5 MHz
This specification is not longer required
3 Removed TLLYV and TLLGV from waveform dia-
grams
4 The HSI errata and CMPL with R0 were removed
as this is now considered normal operation
5 The HSI MODE divide-by-eight errata was add-
ed to the known errata section
The following differences exist between this data
sheet (270909-005) and (270909-004)
1 ITL MAX was b650 mA (270909-004) Now ITL
MAX is b800 mA (270909-005)
2 IIL2 was named IIL1 (270909-004) Now IIL2 is
correctly named (270909-005)
3 IIL1 was omitted (270909-004) IIL1 MAX was
added IIL1 MAX is b850 mA (270909-005)
4 TLLYV and TLLGV (270909-004) were removed
These timings are not required in high-speed sys-
tem designs
5 An errata was added to the known errata section
There is a possibility to miss an external interrupt
on P0 7 EXTINT
The following differences exist between this data
sheet (270909-004) and (270909-003)
1 The ROM (80C196KB) and ROMless
(83C196KB) were combined with this data sheet
resulting in no specification differences
2 The description of the prescalar bit for the A D
has been enhanced
3 THAHBVMIN was b15 ns (270909-003) Now
THAHBVMIN is b20 ns (270909-004)
4 TXHQZMAX was 1 TOSC (270909-003) Now
TXHQZMAX is 2 TOSC (270909-004) This should
have no impact on designs using synchronous
serial mode 0
5 The change indicators for the 80C196KB are
‘‘E’’ ‘‘F’’ and ‘‘G’’ Previously there was only one
change indicator ‘‘E’’ The change indicator is
used for tracking purposes The change indicator
is the last character in the FPO number The FPO
number is the second line on the top side of the
device
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The following differences exist between (-003) and
version (-002)
1 The 12 MHz and 16 MHz devices were com-
bined in this data sheet The 87C196KB 12 MHz
only data sheet (272035-001) is now obsolete
2 Changes were made to the format of the data
sheet and the SFR descriptions were removed
3 The -002 version of this data sheet was valid for
devices marked with a ‘‘B’’ or a ‘‘D’’ at the end
of the top side tracking number
4 The OSCILLATOR errata was removed
5 An errata was not documented in the -002 data
sheet for devices marked with a ‘‘B’’ or a ‘‘D’’
This is the DIVIDE DURING HOLD READY er-
rata When HOLD or READY is active and DIV
DIVB is the last instruction in the queue the di-
vide result may be incorrect
6 TXCH was changed from Min e 40 ns to Min e
20 ns
7 TRLCL was changed from Min e 5 ns to Min e
4 ns
9 IIL1 was changed from Max e b6 mA to Max e
b7 mA
10 THAHBV was changed from Min e b10 ns to
Min e b15 ns
Differences between the -002 and -001 data sheets
1 The -001 version of this data sheet was valid for
devices marked with a ‘‘C’’ at the end of the top
side tracking number
2 Added 64L SDIP and 80L QFP packages
3 Added IIH1
4 Changed TCHWH Min from b 10 ns to b 5 ns
5 Changed TCHWH Max from a 10 ns to a 15 ns
6 Changed TWLWH Min from TOSC b 20 ns to
TOSC b 15 ns
7 Changed TWHQX Min from TOSC b 10 ns to
TOSC b 15 ns
8 Changed TWHLH Min from TOSC b 10 ns to
TOSC b 15 ns
9 Changed TWHLH Max from TOSC a 15 ns to
TOSC a 10 ns
10 Changed TWHBX Min from TOSC b 10 ns to
TOSC b 15 ns
11 Changed THVCH Min from 85 ns to 55 ns
12 Remove THVCH Max
13 Changed TCLHAL Min from b 10 ns to b 15 ns
14 Changed TCLHAL Max from 20 ns to 15 ns
15 Changed TCLBRL Min from b 10 ns to b 15 ns
16 Changed TCLBRL Max from 20 ns to 15 ns
17 Changed THAHAX Min from b 10 ns to b 15 ns
18 Added HSI description to Functional Deviations
19 Added Oscillator description to Functional Devi-
ations
22




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