IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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ADVANCE INFORMATION
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION
589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51333
IDT72T51343
IDT72T51353
FEATURES:
Choose from among the following memory density options:
IDT72T51333 Total Available Memory = 589,824 bits
IDT72T51343 Total Available Memory = 1,179,648 bits
IDT72T51353 Total Available Memory = 2,359,296 bits
Configurable from 1 to 8 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 512 x 18 or 1,024 x 9
Independent Read and Write access per queue
User programmable via serial port
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
Default multi-queue device configurations
-IDT72T51333: 4,096 x 18 x 8Q
-IDT72T51343: 8,192 x 18 x 8Q
-IDT72T51353: 16,384 x 18 x 8Q
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
Individual, Active queue flags (OV, FF, PAE, PAF)
8 bit parallel flag status on both read and write ports
Provides continuous PAE and PAF status of up to 8 Queues
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
- x18in to x18out
- x9in to x18out
- x18in to x9out
- x9in to x9out
FWFT mode of operation on read port
Partial Reset, clears data in single Queue
Expansion of up to 8 multi-queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
WADEN
FSTR
WRADD
6
WEN
WCLK
Din
x9, x18
DATA IN
FF
PAF
PAFn
8
Q0
Q7
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RADEN
ESTR
RDADD
6 REN
RCLK
EREN
ERCLK
OE
Qout
x9, x18
DATA OUT
OV
PAE
PAEn
8
6113 drw01
NOVEMBER 2003
DSC-6113/2


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION
The IDT72T51333/72T51343/72T51353 multi-queue flow-control de-
vices are single chip within which anywhere between 1 and 8 discrete FIFO
queues can be setup. All queues within the device have a common data input
bus, (write port) and a common data output bus, (read port). Data written into
the write port is directed to a respective queue via an internal de-multiplex
operation, addressed by the user. Data read from the read port is accessed
from a respective queue via an internal multiplex operation, addressed by
the user. Data writes and reads can be performed at high speeds up to
200MHz, with access times of 3.6ns. Data write and read operations are totally
independent of each other, a queue maybe selected on the write port and
a different queue on the read port or both ports may select the same queue
simultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 8 bit programmable flag busses are available, providing status of all
queues, including queues not selected for write or read operations, these flag
busses provide an individual flag per queue.
Bus Matching is available on this device, either port can be 9 bits or 18 bits
wide. When Bus Matching is used the device ensures the logical transfer of
data throughput in a Little Endian manner.
The user has full flexibility configuring queues within the device, being able
to program the total number of queues between 1 and 8, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
Both Master Reset and Partial Reset pins are provided on this device. A Master
Reset latches in all configuration setup pins and must be performed before
programming of the device can take place. A Partial Reset will reset the read and
write pointers of an individual queue, provided that the queue is selected on both
the write port and read port at the time of partial reset.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the queue that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect toERENandERCLK,thisisveryusefulwhendataisbeingreadathigh
speed.
The multi-queue flow-control device has the capability of operating its IO in
either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected
via the IOSEL input. The core supply voltage (VCC) to the multi-queue is always
2.5V, however the output levels can be set independently via a separate supply,
VDDQ.
The devices also provide additional power savings via a Power Down Input.
This input disables the write port data inputs when no write operations are
required.
A JTAG test port is provided, here the multi-queue flow-control device has a
fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline
of the functional blocks within the device.
2


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WCLK WEN
Din
x9, x18
D0 - D17
INPUT
DEMUX
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WRADD
WADEN
6
FSTR
PAFn
FSYNC
FXO
FXI
FF
PAF
SI
SO
SCLK
SENI
SENO
8
FM
IW
OW
MAST
ID0
ID1
ID2
DF
DFM
PRS
MRS
IOSEL
Vref
PD
Write Control
Logic
Write Pointers
PAF
General Flag
Monitor
Active Q
Flags
Serial
Multi-Queue
Programming
Upto 8
FIFO
Queues
0.5 Mbit
1.1 Mbit
2.3 Mbit
Dual Port
Memory
Reset
Logic
Device ID
3 Bit
PAE/ PAF
Offset
OUTPUT
MUX
OUTPUT
REGISTER
IO Level Control
&
Power Down
OE Q0 - Q17
Qout x9, x18
JTAG
Logic
TMS
TDI
TDO
TCK
TRST
Active Q
Flags
PAE
General Flag
Monitor
Read Pointers
Read Control
Logic
OV
PAE
8
PAEn
ESTR
ESYNC
EXI
EXO
6
RDADD
RADEN
NULL-Q
REN
RCLK
EREN
ERCLK
6113 drw02
Figure 1. Multi-Queue Flow-Control Device Block Diagram
3


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PIN CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
A1 BALL PAD CORNER
A
D14 D13
D12
D10
D7 D4 D1 TCK TDO ID1
Q3
Q6
Q9
Q12 Q14
Q15
B
D15 D16
D11
D9
D6 D3
D0 TMS TDI
ID0
Q2
Q5
Q8 Q11 Q13 DNC
C
D17 GND
GND
D8
D5 D2 TRST IOSEL ID2 Q0 Q1
Q4
Q7
Q10 Q17
DNC
D
GND GND
GND
VDDQ VDDQ VDDQ VCC
E
GND GND
GND
VDDQ
VDDQ VCC
VCC
EF
GND GND
GND
VDDQ
VCC GND GND
C NG
NGND GND GND VCC VCC GND GND
A IOH
GND GND GND VCC GND GND GND
V TJ
GND NULL-Q GND
VCC GND GND GND
D AK
PD GND VREF
VCC
VCC GND GND
A ML
SI DFM
DF
VDDQ
VCC GND GND
RM
SENO SENI
SO
VDDQ
VDDQ VCC VCC
ON
FWRADD1 WRADD0 SCLK
VDDQ
VDDQ VDDQ VCC
INP
GND GND WRADD2 WADEN PAF3 PAF6 PAF7
VCC
GND
GND
GND
GND
GND
GND
GND
GND
VCC
FF
VCC
GND
GND
GND
GND
GND
GND
GND
GND
VCC
OV
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
PAE
VDDQ
VDDQ
VDDQ
Q16 DNC DNC
VCC
VDDQ
VDDQ
DNC DNC
DNC
GND
VCC
VDDQ
DNC DNC
DNC
GND
VCC
VCC DNC DNC DNC
GND
GND
VCC DNC DNC DNC
GND
GND
VCC GND DNC DNC
GND
VCC
VCC GND MAST FM
GND
VCC
VDDQ
GND IW
OW
VCC
VDDQ
VDDQ
OE RDADD0 RDADD1
VDDQ
VDDQ VDDQ RDADD2 GND GND
PAE7 PAE6
PAE3 RDADD3 RDADD4 RDADD5
R
WRADD4 WRADD3 FSYNC
FSTR
PAF2 PAF5 PAF4 PAF
DNC ERCLK EREN PAE5
PAE2 RADEN ESTR ESYNC
T
WRADD5 FXI
FXO
PAF0 PAF1 WEN WCLK PRS
MRS RCLK REN
PAE4 PAE1 PAE0 EXO EXI
12
3
NOTE:
1. DNC - Do Not Connect.
4 5 6 7 8 9 10 11 12 13 14 15 16
6113 drw03
PBGA (BB256-1, order code: BB)
TOP VIEW
4


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
single data output port with up to 8 FIFO queues in parallel buffering between
the two ports. The user can setup between 1 and 8 Queues within the device.
These queues can be configured to utilize the total available memory, providing
the user with full flexibility and ability to configure the queues to be various depths,
independent of one another.
MEMORY ORGANIZATION/ ALLOCATION
The memory is organized into what is known as “blocks”, each block being
512 x 18 or 1,024 x 9 bits. When the user is configuring the number of queues
and individual queue sizes the user must allocate the memory to respective
queues, in units of blocks, that is, a single queue can be made up from 0 to m
blocks, where m is the total number of blocks available within a device. Also the
total size of any given queue must be in increments of 512 x 18 or 1,024 x 9.
For the IDT72T51333, IDT72T51343 and IDT72T51353 the Total Available
Memory is 64, 128 and 256 blocks respectively (a block being 512 x 18 or 1,024
x 9). If any port is configured for x18 bus width, a block size is 512 x 18. If both
the write and read ports are configured for x9 bus width, a block size is 1,024
x 9. Queues can be built from these blocks to make any size queue desired and
any number of queues desired.
BUS WIDTHS
The input port is common to all queues within the device, as is the output port.
The device provides the user with Bus Matching options such that the input port
and output port can be either x9 or x18 bits wide, the read and write port widths
being set independently of one another. Because the ports are common to all
queues the width of the queues is not individually set, so that the input width of
all queues are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Data being written into the device via the input port is directed to a discrete
queue via the write queue select address inputs. Conversely, data being read
from the device read port is read from a queue selected via the read queue select
address inputs. Data can be simultaneously written into and read from the same
queue or different queues. Once a queue is selected for data writes or reads,
the writing and reading operation is performed in the same manner as
conventional IDT synchronous FIFO, utilizing clocks and enables, there is a
single clock and enable per port. When a specific queue is addressed on the
write port, data placed on the data inputs is written to that queue sequentially
based on the rising edge of a write clock provided setup and hold times are met.
Conversely, data is read on to the output port after an access time from a rising
edge on a read clock.
The operation of the write port is comparable to the function of a conventional
FIFO operating in standard IDT mode. Write operations can be performed on
the write port provided that the queue currently selected is not full, a full flag output
provides status of the selected queue. The operation of the read port is
comparable to the function of a conventional FIFO operating in FWFT mode.
When a queue is selected on the output port, the next word in that queue will
automatically fall through to the output register. All subsequent words from that
queue require an enabled read cycle. Data cannot be read from a selected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
when data read out is valid. If the user switches to a queue that is empty, the
last word from the previous queue will remain on the output register.
As mentioned, the write port has a full flag, providing full status of the selected
queue. Along with the full flag a dedicated almost full flag is provided, this almost
full flag is similar to the almost full flag of a conventional IDT FIFO. The device
provides a user programmable almost full flag for all 8 queues and when a
respective queue is selected on the write port, the almost full flag provides status
for that queue. Conversely, the read port has an output valid flag, providing
status of the data being read from the queue selected on the read port. As well
as the output valid flag the device provides a dedicated almost empty flag. This
almost empty flag is similar to the almost empty flag of a conventional IDT FIFO.
The device provides a user programmable almost empty flag for all 8 queues
and when a respective queue is selected on the read port, the almost empty flag
provides status for that queue.
PROGRAMMABLE FLAG BUSSES
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid & almost empty on the read port, there are two flag status busses. An almost
full flag status bus is provided, this bus is 8 bits wide. Also, an almost empty flag
status bus is provided, again this bus is 8 bits wide. The purpose of these flag
busses is to provide the user with a means by which to monitor the data levels
within queues that may not be selected on the write or read port. As mentioned,
the device provides almost full and almost empty registers (programmable by
the user) for each of the 8 queues in the device.
The4bitPAEnand4bit PAFnbussesprovideadiscretestatusoftheAlmost
Empty and Almost Full conditions of all 8 queue's. If the device is programmed
for less than 8 queue's, then there will be a corresponding number of active
outputs on the PAEn and PAFn busses.
The flag busses can provide a continuous status of all queues. If devices are
connected in expansion mode the individual flag busses can be left in a discrete
form, providing constant status of all queues, or the busses of individual devices
can be connected together to produce a single bus of 8 bits. The device can
then operate in a "Polled" or "Direct" mode.
When operating in polled mode the flag bus provides status of each device
sequentially, that is, on each rising edge of a clock the flag bus is updated to show
the status of each device in order. The rising edge of the write clock will update
the Almost Full bus and a rising edge on the read clock will update the Almost
Empty bus.
When operating in direct mode the device driving the flag bus is selected by
the user. The user addresses the device that will take control of a respective
flag bus, these PAFn and PAEn flag busses operating independently of one
another. Addressing of the Almost Full flag bus is done via the write port and
addressing of the Almost Empty flag bus is done via the read port.
EXPANSION
Expansion of multi-queue devices is also possible, up to 8 devices can be
connected in a parallel fashion providing the possibility of both depth expansion
or queue expansion. Depth Expansion means expanding the depths of
individual queues. Queue expansion means increasing the total number of
queues available. Depth expansion is possible by virtue of the fact that more
memory blocks within a multi-queue device can be allocated to increase the
depth of a queue. For example, depth expansion of 8 devices provides the
possibility of 8 queues of 32K x 18 deep within the IDT72T51333, 64K x 18 deep
within the IDT72T51343 and 128K x 18 deep within the IDT72T51353, each
queue being setup within a single device utilizing all memory blocks available
to produce a single queue. This is the deepest queue that can setup within a
device.
For queue expansion of the 8 queue device, a maximum number of 64 (8
x 8) queues may be setup, each queue being 16K x18 or 32K x 9 deep, if less
queues are setup, then more memory blocks will be available to increase queue
depths if desired. When connecting multi-queue devices in expansion mode all
respective input pins (data & control) and output pins (data & flags), should be
“connected” together between individual devices.
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(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol &
Name
I/O TYPE
Pin No.
D[17:0]
Data Input Bus HSTL-LVTTL
Din (See Pin
INPUT
table for details)
Description
These are the 18 data input pins. Data is written into the device via these input pins on the rising edge
of WCLK provided that WEN is LOW. Due to bus matching not all inputs may be used, any unused
inputs should be tied LOW.
DF(1)
Default Flag
LVTTL If the user requires default programming of the multi-queue device, this pin must be setup before Master
(L3) INPUT Resetandmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
DFM(1)
(L2)
Default Mode
LVTTL
INPUT
The multi-queue device requires programming after master reset. The user can do this serially via the
serial port, or the user can use the default method. If DFM is LOW at master reset then serial mode will be
selected, if HIGH then default mode is selected.
ERCLK
(R10)
RCLK Echo
HSTL-LVTTL ReadClockEchooutput,thisoutputgeneratesaclockbasedonthereadclockinput,thisisusedforSource
OUTPUT SynchronousclockingwherethereceivingdevicesutilizestheERCLKtoclockdataoutputfromthequeue.
EREN
(R11)
REN Echo
HSTL-LVTTL ReadEnableEchooutput,canbeusedinconjunctionwiththeERCLKoutputtoloaddataoutputfromthe
OUTPUT queue into the receiving device.
ESTR
(R15)
PAEn Flag Bus
Strobe
LVTTL
INPUT
If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK
and the RDADD bus to select a device for its queues to be placed onto the PAEn bus outputs. A device
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a PAEn flag bus
selection cannot be made, (ESTR must NOT go active) until programming of the part has been completed
and SENO has gone LOW.
ESYNC
(R16)
PAEn Bus Sync HSTL-LVTTL
OUTPUT
ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAEn bus
during Polled operation of the PAEn bus. During Polled operation each device's queue status flags are
loaded on to the PAEn bus outputs sequentially based on RCLK. The first RCLK rising edge loads
device 1 on to PAEn, the second RCLK rising edge loads device 2 and so on. During the RCLK cycle
that a selected device is placed on to the PAEn bus, the ESYNC output will be HIGH.
EXI
(T16)
PAEn Bus
Expansion In
LVTTL
INPUT
The EXI input is used when multi-queue devices are connected in expansion mode and Polled PAEn
bus operation has been selected . EXI of device ‘N’ connects directly to EXO of device ‘N-1’. The EXI
receives a token from the previous device in a chain. In single device mode the EXI input must be tied
LOW if the PAEn bus is operated in direct mode. If thePAEn bus is operated in polled mode the EXI input
must be connected to the EXO output of the same device. In expansion mode the EXI of the first device
should be tied LOW, when direct mode is selected.
EXO
(T15)
PAEn Bus
Expansion Out
LVTTL
OUTPUT
EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
PAEn bus operation has been selected . EXO of device ‘N’ connects directly to EXI of device ‘N+1’. This
pin pulses HIGH when device N places its PAE status onto the PAEn bus with respect to RCLK. This
pulse (token) is then passed onto the next device in the chain ‘N+1’ and on the next RCLK rising edge
device N+1 will be loaded on to the PAEn bus. This continues through the chain and EXO of the last device
is then looped back to EXI of the first device. The ESYNC output of each device in the chain provides
synchronization to the user of this looping event.
FF
Full Flag
HSTL-LVTTL This pin provides the full flag output for the active queue, that is, the queue selected on the input port for
(P8) OUTPUT write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a queue
selection, this flag will show the status of the newly selected queue. Data can be written to this queue on
the next cycle provided FF is HIGH. This flag has High-Impedance capability, this is important during
expansion of devices, when the FF flag output of up to 8 devices may be connected together on a common
line. The device with a queue selected takes control of theFF bus, all other devices place their FF output
into High-Impedance. When a queue selection is made on the write port this output will switch from
High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK.
FM(1)
(K16)
Flag Mode
HSTL-LVTTL This pin is setup before a master reset and must not toggle during any device operation. The state of the
INPUT FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbussesoperateineitherPolled
or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.
FSTR
(R4)
PAFn Flag Bus
Strobe
LVTTL
INPUT
If direct operation of the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK
and the WRADD bus to select a device for its queues to be placed onto the PAFn bus outputs. A device
6


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
FSTR
(Continued)
(R4)
FSYNC
(R3)
Name
PAFn Flag Bus
Strobe
PAFn Bus Sync
I/O TYPE
LVTTL
INPUT
LVTTL
OUTPUT
Description
addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If
Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a PAFn flag bus
selection cannot be made, (FSTR must NOT go active) until programming of the part has been completed
and SENO has gone LOW.
FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAFn bus
during Polled operation of the PAFn bus. During Polled operation each device's queue status flags is
loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads
device 1 on to PAFn, the second WCLK rising edge loads device 2 and so on. During the WCLK cycle
that selected device is placed on to the PAFn bus, the FSYNC output will be HIGH.
FXI
PAFn Bus
LVTTL The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn
(T2)
Expansion In
INPUT bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receives a token from the previous device in a chain. In single device mode the FXI input must be tied
LOW if the PAFn bus is operated in direct mode. If thePAFn bus is operated in polled mode the FXI input
must be connected to the FXO output of the same device. In expansion mode the FXI of the first device
should be tied LOW, when direct mode is selected.
FXO
PAFn Bus
LVTTL FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
(T3) ExpansionOut OUTPUT PAFn bus operation has been selected . FXO of device ‘N’ connects directly to FXI of device ‘N+1’. This
pin pulses when device N places its PAE onto the PAFn bus with respect to WCLK. This pulse (token) is
then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising edge the first quadrant
of device N+1 will be loaded on to the PAFn bus. This continues through the chain and FXO of the last
device is then looped back to FXI of the first device. The FSYNC output of each device in the chain provides
synchronization to the user of this looping event.
ID[2:0](1)
ID2-C9
ID1-A10
ID0-B10
Device ID Pins
HSTL-LVTTL
INPUT
For the 8Q multi-queue device the WRADD and RDADD address busses are 6 bits wide. When a queue
selection takes place the 3 MSb’s of this 8 bit address bus are used to address the specific device (the
3 LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s
of the addressarecomparedtothedeviceIDpins.Thefirstdeviceinachainofmulti-queue’s(connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which
is ‘111’, however the ID does not have to match the device order. In single device mode these pins should
be setup as ‘000’ and the 3 MSb’s of the WRADD and RDADD address busses should be tied LOW. The
ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
IOSEL
(C8)
IO Select
LVTTL
INPUT
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
required then IOSEL should be tied HIGH. If LVTTL I/O are required then it should be tied LOW.
IW(1)
Input Width
LVTTL IW selects the bus width for the data input bus. If IW is LOW during a Master Reset then the bus width
(L15) INPUT is x18, if HIGH then it is x9.
MAST(1)
(K15)
Master Device
HSTL-LVTTL ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices), isthe
INPUT Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The
master device is the first to take control of all outputs after a master reset, all slave devices go to High-
Impedance, preventing bus contention. If a multi-queue device is being used in single device mode, this
pin must be set HIGH.
MRS MasterReset HSTL-LVTTL Amasterresetisperformedbytaking MRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired
(T9) INPUT aftermasterreset.
NULL-Q
(J2)
OE
(M14)
Null Queue
Select
Output Enable
HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD
INPUT and RADEN address bus to address the Null-Q.
HSTL-LVTTL TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontrolofthemulti-queue
INPUT data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will
be in a Low Impedance condition if the OE input is LOW. If OE is HIGH then the Qout data outputs will be
in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be
in High Impedance until that device has been selected on the Read Port, at which point OE provides three-
state of that respective device.
7


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(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
OV
(P9)
Name
Output Valid
Flag
I/O TYPE
Description
HSTL-LVTTL Thisoutputflagprovidesoutputvalidstatusforthedatawordpresentonthemulti-queueflow-controldevice
OUTPUT data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That
is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time theOV flag
represents the data in that respective queue. When a selected queue on the read port is read to empty,
the OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has High-
Impedance capability, required when multiple devices are used and the OV flags are tied together.
OW(1)
(L16)
PAE
(P10)
PAEn
(PAE7-P11
PAE6-P12
PAE5-R12
PAE4-T12
PAE3-P13
PAE2-R13
PAE1-T13
PAE0-T14)
PAF
(R8)
PAFn
(PAF7-P7
PAF6-P6
PAF5-R6
PAF4-R7
PAF3-P5
PAF2-R5
PAF1-T5
PAF0-T4)
OutputWidth
LVTTL
INPUT
OW selects the bus width for the data output bus. If OW is LOW during a Master Reset then the bus width
is x18, if HIGH then it is x9.
Programmable
Almost-Empty
Flag
HSTL-LVTTL
OUTPUT
This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is
synchronized to RCLK.
Programmable
Almost-Empty
Flag Bus
HSTL-LVTTL
OUTPUT
On the 8Q device the PAEn bus is 8 bits wide. During a Master Reset this bus is setup for Almost Empty
mode. This output bus provides PAE status of all 8 queues within a selected device. During queue
read/write operations these outputs provide programmable empty flag status, in either direct or polled
mode. The mode of flag operation is determined during master reset via the state of the FM input. This
flag bus is capable of High-Impedance state, this is important during expansion of multi-queue devices.
During direct operation the PAEn bus is updated to show the PAE status of queues within a selected
device. Selection is made using RCLK, ESTR and RDADD. During Polled operation the PAEn bus is
loaded with the PAE status of multi-queue flow-control devices sequentially based on the rising edge
of RCLK.
Programmable HSTL-LVTTL
Almost-FullFlag OUTPUT
This pin provides the Almost-Full flag status for the queue that has been selected on the input port for
write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected
queue is almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is
synchronized to WCLK.
Programmable HSTL-LVTTL
Almost-FullFlag OUTPUT
Bus
On the 8Q device the PAFn bus is 8 bits wide. At any one time this output bus provides PAF status
of all 8 queues within a selected device. During queue read/write operations these outputs provide
programmable full flag status, in either direct or polled mode. The mode of flag operation is determined
during master reset via the state of the FM input. This flag bus is capable of High-Impedance state,
this is important during expansion of multi-queue devices. During direct operation the PAFn bus is
updated to show the PAF status of a quadrant of queues within a selected device. Selection is made
using WCLK, FSTR, WRADD and WADEN. During Polled operation the PAFn bus is loaded with the
PAF status of multi-queue flow-control device sequentially based on the rising edge of WCLK.
PD
Power Down
HSTL This input is used to provide additional power savings. When the device I/O is setup for HSTL/eHSTL
(K1) INPUT mode a HIGH on the PD input disables the data inputs on the write port only, providing significant power
savings. In LVTTL mode this pin has no operation
PRS PartialReset HSTL-LVTTL APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial
(T8) INPUT Reset can be performed on a queue, that queue must be selected on both the write port and read port
2 clock cycles before the reset is performed. A Partial Reset is then performed by taking PRS LOW for
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
the first memory location, none of the devices configuration will be changed.
Q[17:0]
DataOutputBus HSTL-LVTTL These are the 18 data output pins. Data is read out of the device via these output pins on the rising edge
Qout (See Pin
OUTPUT of RCLK provided that REN is LOW, OE is LOW and the queue is selected. Due to bus matching not
table for details)
all outputs may be used, any unused outputs should not be connected.
RADEN
(R14)
Read Address
Enable
HSTL-LVTTL
INPUT
The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,
that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the part
has been completed and SENO has gone LOW.
8


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(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
RCLK
(T10)
Name
Read Clock
I/O TYPE
Description
HSTL-LVTTL
INPUT
When enabled by REN, the rising edge of RCLK reads data from the selected queue via the output
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the
PAEn flag quadrant to be placed on the PAEn bus during direct flag operation. During polled flag operation
the PAEn bus is cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. ThePAE
and OV outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals are
based on RCLK. RCLK must be continuous and free-running.
RDADD
Read Address
[5:0] Bus
(RDADD5-P16
RDADD4-P15
RDADD3-P14
RDADD2-N14
RDADD1-M16
RDADD0-M15)
HSTL-LVTTL
INPUT
For the 8Q device the RDADD bus is 6 bits. The RDADD bus is a dual purpose address bus. The first
function of RDADD is to select a queue to be read from. The least significant 3 bits of the bus, RDADD[2:0]
are used to address 1 of 8 possible queues within a multi-queue device. The most significant 3 bits,
RDADD[5:3] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that data
can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge). On the
next rising RCLK edge after a read queue select, a data word from the previous queue will be placed onto
the outputs, Qout, regardless of theRENinput. Two RCLK rising edges after read queue select, data will
be placed on to the Qout outputs from the newly selected queue, regardless ofREN due to the first word
fall through effect.
The second function of the RDADD bus is to select the device of queues to be loaded on to the PAEn bus
during strobed flag mode. The most significant 3 bits, RDADD[5:3] are again used to select 1 of 8
possiblemulti-queuedevices that may be connected in expansion mode. Address bits RDADD[2:0] are
don’t care during quadrant selection. The quadrant address present on the RDADD bus will be selected
on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout
bus, read from the previously selected queue on this RCLK edge). Please refer to Table 2 for details
on RDADD bus.
REN
(T11)
Read Enable
HSTL-LVTTL
INPUT
The REN input enables read operations from a selected queue based on a rising edge of RCLK. A
queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless
of the state of REN. Data from a newly selected queue will be available on the Qout output bus on the second
RCLK cycle after queue selection regardless of REN due to the FWFT operation. A read enable is not
required to cycle the PAEn bus (in polled mode) or to select the device, (in direct mode).
SCLK
(N3)
Serial Clock
HSTL-LVTTL
INPUT
If serial programming of the multi-queue device has been selected during master reset, the SCLK input
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed
the SCLK of all devices should be connected to the same source.
SENI Serial Input HSTL-LVTTL During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
(M2) Enable
INPUT part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are
cascaded,theSENIinputshouldbeconnectedtothe SENOoutputofthepreviousdevice.Sowhenserial
loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain
to be programmed (SENO will followSENI of a given device once that device is programmed). TheSENI
input of the master device (or single device), should be controlled by the user.
SENO
(M1)
Serial Output
Enable
HSTL-LVTTL This output is used to indicate that serial programming or default programming of the multi-queue device
OUTPUT has been completed.SENOfollowsSENI once programming of a device is complete. Therefore,SENO
will go LOW after programming providedSENI is LOW, once SENI is taken HIGH again, SENO will also
go HIGH. When theSENOoutput goes LOW, the device is ready to begin normal read/write operations.
If multiple devices are cascaded and serial programming of the devices will be used, the SENO output
should be connected to the SENI input of the next device in the chain. When serial programming of the
first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the SENO output
essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
SI
Serial In
HSTL-LVTTL Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.
(L1) INPUT Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
9


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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
SI
(L1)
(Continued)
Name
Serial In
I/O TYPE
Description
HSTL-LVTTL modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO
INPUT hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
SO
Serial Out
HSTL-LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain
(M3) OUTPUT to complete programming of all devices. The SI of a device connects to SO of the previous device in the
chain. The SO of the final device in a chain should not be connected.
TCK(2)
(A8)
JTAG Clock
LVTTL
INPUT
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising
edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal
needs to be tied to GND.
TDI(2) JTAG Test Data LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
(B9) Input
INPUT operation,testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,
ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(2)
(A9)
JTAG Test Data LVTTL
Output
OUTPUT
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while
in SHIFT-DR and SHIFT-IR controller states.
TMS(2)
(B8)
TRST(2)
(C7)
JTAG Mode
Select
JTAG Reset
LVTTL
INPUT
LVTTL
INPUT
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMSdirects the
device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK
cycles. If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the
JTAGfunctionisusedbuttheuserdoesnotwanttouseTRST,thenTRSTcanbetiedwithMRS toensure
proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An
internal pull-up resistor forces TRST HIGH if left unconnected.
WADEN
(P4)
WCLK
(T7)
WEN
(T6)
Write Address
Enable
Write Clock
Write Enable
LVTTL
INPUT
The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to
be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided
that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue cycle(s). WADEN should
not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note, that
a write queue selection cannot be made, (WADEN must NOT go active) until programming of the part has
been completed and SENO has gone LOW.
HSTL-LVTTL
INPUT
When enabled by WEN, the rising edge of WCLK writes data into the selected queue via the input bus,
Din. The queue to be written to is selected via the WRADD address bus and a rising edge of WCLK while
WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also select the flag
quadrant to be placed on the PAFn bus during direct flag operation. During polled flag operation the PAFn
bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The PAFn, PAF and
FF outputs are all synchronized to WCLK. During device expansion the FXO and FXI signals are based
on WCLK. The WCLK must be continuous and free-running.
HSTL-LVTTL The WEN input enables write operations to a selected queue based on a rising edge of WCLK. A queue
INPUT to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless of the state
of WEN. Data present on Din can be written to a newly selected queue on the second WCLK cycle after
queueselectionprovidedthatWEN isLOW.AwriteenableisnotrequiredtocyclethePAFnbus(inpolled
mode) or to select the device, (in direct mode).
WRADD
[5:0]
(WRADD5-T1
WRADD4-R1
WRADD3-R2
WRADD2-P3
WRADD1-N1
WRADD0-N2)
Write Address
Bus
HSTL-LVTTL
INPUT
For the 8Q device the WRADD bus is 6 bits. The WRADD bus is a dual purpose address bus. The first
function of WRADD is to select a queue to be written to. The least significant 3 bits of the bus, WRADD[2:0]
are used to address 1 of 8 possible queues within a multi-queue device. The most significant 3 bits,
WRADD[5:3] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSb’s will address a device with the matching ID code. The address present on the
WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that
data present on the Din bus can be written into the previously selected queue on this WCLK edge and
on the next rising WCLK also, providing that WEN is LOW). Two WCLK rising edges after write queue
10


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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
WRADD
(Continued)
Name
Write Address
I/O TYPE
Description
HSTL-LVTTL select, data can be written into the newly selected queue.
INPUT The second function of the WRADD bus is to select the device of queues to be loaded on to the PAFnbus
during strobed flag mode. The most significant 3 bits, WRADD[5:3] are again used to select 1 of 8 possible
multi-queue devices that may be connected in expansion mode. Address bits WRADD[2:0] are don’t care
during quadrant selection. The quadrant address present on the WRADD bus will be selected on the rising
edge of WCLK provided that FSTR is HIGH, (note, that data can be written into the previously selected
queue on this WCLK edge). Please refer to Table 1 for details on the WRADD bus.
VCC +2.5V Supply
(See below)
Power These are VCC power supply pins and must all be connected to a +2.5V supply rail.
VDDQ
O/P Rail Voltage
(See Pin No.
table below)
Power
These pins must be tied to the desired output rail voltage. For LVTTL I/O these pins must be connected
to +2.5V, for HSTL these pins must be connected to +1.5V and for eHSTL these pins must be connected
to +1.8V.
GND Ground Pin
(See below)
Ground These are Ground pins and must all be connected to the GND supply rail.
Vref Reference HSTL This is a Voltage Reference input and must be connected to a voltage level determined from the table
(K3) Voltage
INPUT "Recommended DC Operating Conditions". The input provides the reference level for HSTL/eHSTL
inputs. For LVTTL I/O mode this input should be tied to GND.
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 50-54 and Figures 30-32.
PIN NUMBER TABLE
Symbol
Name
I/O TYPE
Pin Number
D[17:0]
Din
Q[17:0]
VCC
VDDQ
GND
DNC
Data Input Bus HSTL-LVTTL D17-C1, D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5, D6-B5, D5-C5,
INPUT D4-A6, D3-B6, D2-C6, D1-A7, D0-B7
DataOutputBus HSTL-LVTTL Q17-C15, Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14, Q11-B14, Q10-C14, Q9-A13, Q8-B13,
Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11, Q(1,0)-C(11,10)
+2.5V Supply
Power D(7-10),E(6,7,10,11),F(5,12),G(4,5,12,13),H(4,13),J(4,13),K(4,5,12,13),L(5,12),M(6,7,10,11),N(7-10)
O/P Rail Voltage Power D(4-6,11-13), E(4,5,12,13), F(4,13), L(4,13), M(4,5,12,13), N(4-6,11-13)
Ground Pin
Ground C(2,3), D(1-3), E(1-3,8,9), F(1-3,6-11), G(1-3,6-11), H(1-3,5-12), J(1,3,5-12,14), K(2,6-11,14),
L(6-11,14), M(8,9), N(15,16), P(1,2)
Do Not Connect None B16, C16, D(15,16), E(14-16), F(14-16), G(14-16), H(14-16), J(15-16), R9
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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
Rating
Terminal Voltage
with respect to GND
Commercial
–0.5 to +3.6(2)
TSTG
StorageTemperature
–55 to +125
Unit
V
°C
IOUT
DC Output Current
–50 to +50
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
CAPACITANCE (TA= +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
CIN(2,3)
COUT(1,2)
Input
Capacitance
Output
Capacitance
VIN = 0V
VOUT = 0V
10(3)
15
NOTES:
1. With output deselected, (OE VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
Unit
pF
pF
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Min. Typ.
VCC Supply Voltage
GND Supply Voltage
2.375 2.5
00
VIH Input High Voltage LVTTL
eHSTL
HSTL
1.7
VREF+0.2
VREF+0.2
VIL Input Low Voltage
LVTTL
eHSTL
HSTL
-0.3 —
——
——
VREF VoltageReferenceInput eHSTL
(HSTL only)
HSTL
0.8 0.9
0.68 0.75
TA OperatingTemperatureCommercial
0—
TA OperatingTemperatureIndustrial
-40 —
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
Max.
2.625
0
3.45
0.7
VREF-0.2
VREF-0.2
1.0
0.9
70
85
Unit
V
V
V
V
V
V
V
V
V
V
°C
°C
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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
Parameter
Min. Max.
ILI InputLeakageCurrent
–10 10
ILO
VOH(3)
VOL
Output Leakage Current
Output Logic “1” Voltage,
Output Logic “0” Voltage,
IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
–10
VDDQ -0.4
VDDQ -0.4
VDDQ -0.4
10
0.4V
0.4V
0.4V
ICC1(1,2)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
— 80
— 150
— 150
ICC2(1)
ICC3(1)
Standby VCC Current (VCC = 2.5V)
Standby VCC Current in Power Down mode(VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
— 25
— 100
— 100
——
— 50
— 50
IDDQ(1,2)
Active VDDQ Current (VDDQ = 2.5V LVTTL)
(VDDQ = 1.5V HSTL)
(VDDQ = 1.8V eHSTL)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
— 10
— 10
— 10
NOTES:
1. Both WCLK and RCLK toggling at 20MHz.
2. Data inputs toggling at 10MHz.
3. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)].
4. Outputs are not 3.3V tolerant.
5. The following inputs should be pulled to GND: WRADD, RDADD, WADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.
The following inputs should be pulled to VCC: WEN, REN, SENI, PRS, MRS, TDI, TMS and TRST.
All other inputs are don't care and should be at a known state.
Unit
µA
µA
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
13


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
HSTL
1.5V AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
0.25 to 1.25V
0.4ns
0.75
VDDQ/2
AC TEST LOADS
VDDQ/2
50
I/O Z0 = 50
NOTE:
1. VDDQ = 1.5V±.
EXTENDED HSTL
1.8V AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
0.4 to 1.4V
0.4ns
0.9
VDDQ/2
NOTE:
1. VDDQ = 1.8V±.
2.5V LVTTL
2.5V AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
GND to 2.5V
1ns
VCC/2
VDDQ/2
6113 drw04
Figure 2a. AC Test Load
6
5
4
3
2
1
20 30 50 80 100
Capacitance (pF)
200
6113 drw04a
Figure 2b. Lumped Capacitive Load, Typical Derating
NOTE:
1. For LVTTL VCC = VDDQ.
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
OE
VIH
VIL
Output
Normally
LOW
VCC/2
tOE & tOLZ
100mV
tOHZ
100mV
VCC/2
VOL
Output
Normally VCC/2
HIGH
NOTE:
1. REN is HIGH.
100mV
100mV
14
VOH
VCC/2
6113 drw04b


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72T51333L5
IDT72T51343L5
IDT72T51333L6
IDT72T51343L6
IDT72T51353L5
IDT72T51353L6
Symbol
Parameter
Min. Max.
Min. Max. Unit
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tPRSS
tPRSH
tOLZ (OE-Qn)(2)
tOHZ(2)
tOE
fC
tSCLK
tSCKH
tSCKL
tSDS
tSDH
tSENS
tSENH
tSDO
tSENO
tSDOP
tSENOP
tPCWQ
tPCRQ
tAS
tAH
tWFF
tROV
tSTS
tSTH
tQS
tQH
tWAF
tRAE
tPAF
Clock Cycle Frequency (WCLK & RCLK)
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
Reset Setup Time
Reset Recovery Time
Partial Reset Setup
Partial Reset Hold
Output Enable to Output in Low-Impedance
Output Enable to Output in High-Impedance
Output Enable to Data Output Valid
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data In Setup
Serial Data In Hold
Serial Enable Setup
Serial Enable Hold
SCLK to Serial Data Out
SCLK to Serial Enable Out
Serial Data Out Propagation Delay
Serial Enable Propagation Delay
Programming Complete to Write Queue Selection
Programming Complete to Read Queue Selection
Address Setup
Address Hold
Write Clock to Full Flag
Read Clock to Output Valid
PAE/PAF Strobe Setup
PAE/PAF Strobe Hold
Queue Setup
Queue Hold
WCLK to PAF flag
RCLK to PAE flag
Write Clock to Synchronous Almost-Full Flag Bus
— 200
0.6 3.6
5—
2.3 —
2.3 —
1.5 —
0.5 —
1.5 —
0.5 —
30 —
15 —
10 —
1.5 —
0.5 —
0.6 3.6
0.6 3.6
0.6 3.6
— 10
100 —
45 —
45 —
20 —
1.2 —
20 —
1.2 —
— 20
— 20
1.5 3.7
1.5 3.7
20 —
20 —
1.5 —
1.0 —
— 3.6
— 3.6
1.5 —
0.5 —
1.5 —
1.0 —
0.6 3.6
0.6 3.6
0.6 3.6
— 166 MHz
0.6 3.7 ns
6 — ns
2.7 — ns
2.7 — ns
2.0 — ns
0.5 — ns
2.0 — ns
0.5 — ns
30 — ns
15 — ns
10 — ns
2.0 — ns
0.5 — ns
0.6 3.7 ns
0.6 3.7 ns
0.6 3.7 ns
— 10 MHz
100 — ns
45 — ns
45 — ns
20 — ns
1.2 — ns
20 — ns
1.2 — ns
— 20 ns
— 20 ns
1.5 3.7 ns
1.5 3.7 ns
20 — ns
20 ns
2.5 — ns
1.5 — ns
— 3.7 ns
— 3.7 ns
2.0 — ns
0.5 — ns
2.0 — ns
0.5 — ns
0.6 3.7 ns
0.6 3.7 ns
0.6 3.7 ns
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
15


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Symbol
tPAE
tERCLK
tCLKEN
tPAELZ(2)
tPAEHZ(2)
tPAFLZ(2)
tPAFHZ(2)
tFFHZ(2)
tFFLZ(2)
tOVLZ(2)
tOVHZ(2)
tFSYNC
tFXO
tESYNC
tEXO
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tXIS
tXIH
Parameter
Read Clock to Synchronous Almost-Empty Flag Bus
RCLK to Echo RCLK Output
RCLK to Echo REN Output
RCLK to PAE Flag Bus to Low-Impedance
RCLK to PAE Flag Bus to High-Impedance
WCLK to PAF Flag Bus to Low-Impedance
WCLK to PAF Flag Bus to High-Impedance
WCLK to Full Flag to High-Impedance
WCLK to Full Flag to Low-Impedance
RCLK to Output Valid Flag to Low-Impedance
RCLK to Output Valid Flag to High-Impedance
WCLK to PAF Bus Sync to Output
WCLK to PAF Bus Expansion to Output
RCLK to PAE Bus Sync to Output
RCLK to PAE Bus Expansion to Output
SKEW time between RCLK and WCLK for FF and OV
SKEW time between RCLK and WCLK for PAF and PAE
SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7]
SKEW time between RCLK and WCLK for OV
Expansion Input Setup
Expansion Input Hold
Commercial
IDT72T51333L5
IDT72T51343L5
IDT72T51353L5
Min. Max.
0.6 3.6
— 4.0
— 3.6
0.6 3.6
0.6 3.6
0.6 3.6
0.6 3.6
0.6 3.6
0.6 3.6
0.6 3.6
0.6 3.6
0.6 3.6
0.6 3.6
0.6 3.6
0.6 3.6
4—
5—
5—
5—
1.0 —
0.5 —
Com'l & Ind'l(1)
IDT72T51333L6
IDT72T51343L6
IDT72T51353L6
Min. Max.
0.6 3.7
— 4.2
— 3.7
0.6 3.7
0.6 3.7
0.6 3.7
0.6 3.7
0.6 3.7
0.6 3.7
0.6 3.7
0.6 3.7
0.6 3.7
0.6 3.7
0.6 3.7
0.6 3.7
4.5 —
6—
6—
6—
1.0 —
0.5 —
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
16


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
MASTER RESET
A Master Reset is performed by toggling the MRS input from HIGH to LOW
to HIGH. During a master reset all internal multi-queue device setup and control
registers are initialized and require programming either serially by the user via
the serial port, or using the default settings. During a master reset the state of
the following inputs determine the functionality of the part, these pins should be
held HIGH or LOW.
FM – Flag bus Mode
IW, OW – Bus Matching options
MAST – Master Device
ID0, 1, 2 – Device ID
DFM – Programming mode, serial or default
DF – Offset value for PAE and PAF
Once a master reset has taken place, the device must be programmed either
serially or via the default method before any read/write operations can begin.
See Figure 5, Master Reset for relevant timing.
PARTIAL RESET
A Partial Reset is a means by which the user can reset both the read and write
pointers of a single queue that has been setup within a multi-queue device.
Before a partial reset can take place on a queue, the respective queue must be
selected on both the read port and write port a minimum of 2 RCLK and 2 WCLK
cycles before the PRS goes LOW. The partial reset is then performed by toggling
the PRS input from HIGH to LOW to HIGH, maintaining the LOW state for at least
one WCLK and one RCLK cycle. Once a partial reset has taken place a minimum
of 3 WCLK and 3 RCLK cycles must occur before enabled writes or reads can
occur.
A Partial Reset only resets the read and write pointers of a given queue, a
partial reset will not effect the overall configuration and setup of the multi-queue
device and its queues.
See Figure 6, Partial Reset for relevant timing.
SERIAL PROGRAMMING
The multi-queue flow-control device is a fully programmable device, provid-
ing the user with flexibility in how queues are configured in terms of the number
of queues, depth of each queue and position of the PAF/PAE flags within
respective queues. All user programming is done via the serial port after a master
reset has taken place. Internally the multi-queue device has setup registers
which must be serially loaded, these registers contain values for every queue
within the device, such as the depth and PAE/PAF offset values. The
IDT72T51333/72T51343/72T51353 devices are capable of up to 8 queues
and therefore contain 4 sets of registers for the setup of each queue.
DuringaMasterResetiftheDFM(DefaultMode)inputisLOW,thenthedevice
will require serial programming by the user. It is recommended that the user
utilize a ‘C’ program provided by IDT, this program will prompt the user for all
information regarding the multi-queue setup. The program will then generate a
serial bit stream which should be serially loaded into the device via the serial port.
For the IDT72T51333/72T51343/72T51353 devices the serial programming
requires a total number of serially loaded bits per device, (SCLK cycles with
SENI enabled), calculated by: 19+(Qx72) where Q is the number of queues the
user wishes to setup within the device.
Once the master reset is complete and MRS is HIGH, the device can be
serially loaded. Data present on the SI (serial in), input is loaded into the serial
port on a rising edge of SCLK (serial clock), provided that SENI (serial in
enable), is LOW. Once serial programming of the device has been successfully
completed the device will indicate this via the SENO (serial output enable) going
active, LOW. Upon detection of completion of programming, the user should
cease all programming and take SENI inactive, HIGH. Note, SENO follows SENI
once programming of a device is complete. Therefore, SENO will go LOW after
programming provided SENIis LOW, once SENI is taken HIGH again, SENO
will also go HIGH. The operation of the SO output is similar, when programming
of a given device is complete, the SO output will follow the SI input.
If devices are being used in expansion mode the serial ports of devices should
be cascaded. The user can load all devices via the serial input port control pins,
SI & SENI, of the first device in the chain. Again, the user may utilize the ‘C’
program to generate the serial bit stream, the program prompting the user for
the number of devices to be programmed. The SENO and SO (serial out) of
the first device should be connected to the SENI and SI inputs of the second
device respectively and so on, with the SENO & SO outputs connecting to the
SENI & SI inputs of all devices through the chain. All devices in the chain should
beconnectedtoacommonSCLK.Theserialoutputportofthefinaldeviceshould
be monitored by the user. When SENO of the final device goes LOW, this
indicates that serial programming of all devices has been successfully com-
pleted. Upon detection of completion of programming, the user should cease all
programming and take SENI of the first device in the chain inactive, HIGH.
As mentioned, the first device in the chain has its serial input port controlled
by the user, this is the first device to have its internal registers serially loaded
by the serial bit stream. When programming of this device is complete it will take
its SENO output LOW and bypass the serial data loaded on the SI input to its
SO output. The serial input of the second device in the chain is now loaded with
the data from the SO of the first device, while the second device has its SENI
input LOW. This process continues through the chain until all devices are
programmed and the SENO of the final device goes LOW.
Once all serial programming has been successfully completed, normal
operations, (queue selections on the read and write ports) may begin. When
connected in expansion mode, the IDT72T51333/72T51343/72T51353 de-
vices require a total number of serially loaded bits per device to complete serial
programming, (SCLK cycles with SENI enabled), calculated by: n[19+(Qx72)]
where Q is the number of queues the user wishes to setup within the device,
where n is the number of devices in the chain.
See Figure 7, Serial Port Connection and Figure 8, Serial Programmingfor
connection and timing information.
DEFAULT PROGRAMMING
During a Master Reset if the DFM (Default Mode) input is HIGH the multi-
queue device will be configured for default programming, (serial programming
is not permitted). Default programming provides the user with a simpler,
however limited means by which to setup the multi-queue flow-control device,
rather than using the serial programming method. The default mode will
configure a multi-queue device such that the maximum number of queues
possible are setup, with all of the parts available memory blocks being allocated
equallybetweenthequeues.Thevaluesofthe PAE/PAFoffsetsisdetermined
by the state of the DF (default) pin during a master reset.
For the IDT72T51333/72T51343/72T51353 devices the default mode will
setup 8 queues, each queue configured as follows: For the IDT72T51333 with
x9 input and x9 output ports, 8,192 x 9. If one or both ports is x18, 4,096 x 18.
For the IDT72T51343 with x9 input and x9 output ports, 16,384 x 9. If one or
both ports is x18, 8,192 x 18. For the IDT72T51353 with x9 input and x9 output
ports, 32,768 x 9. If one or both ports is x18, 16,384 x 18. For both devices
the value of the PAE/PAFoffsets is determined at master reset by the state of
theDFinput.IfDFisLOWthenboththePAE& PAFoffsetwillbe8,ifHIGHthen
the value is 128.
When configuring the IDT72T51333/72T51343/72T51353 devices in de-
fault mode the user simply has to apply WCLK cycles after a master reset, until
17


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SENOgoesLOW,thissignalsthatdefaultprogrammingiscomplete.Theseclock
cycles are required for the device to load its internal setup registers. When a
single multi-queue is used, the completion of device programming is signaled
by the SENO output of a device going from HIGH to LOW. Note, that SENI must
be held LOW when a device is setup for default programming mode.
When multi-queue devices are connected in expansion mode, theSENI of
the first device in a chain can be held LOW. The SENO of a device should connect
tothe SENIofthenextdeviceinthechain.TheSENO ofthefinaldeviceisused
to indicate that default programming of all devices is complete. When the final
SENO goes LOW normal operations may begin. Again, all devices will be
programmed with their maximum number of queues and the memory divided
equally between them. Please refer to Figure 9, Default Programming.
WRITE QUEUE SELECTION & WRITE OPERATION
The IDT72T51333/72T51343/72T51353 multi-queue flow-control devices
have up to 8 queues that data can be written into via a common write port using
the data inputs, Din, write clock, WCLK and write enable, WEN. The queue
address present on the write address bus, WRADD during a rising edge on
WCLK while write address enable, WADEN is HIGH, is the queue selected for
write operations. The state of WEN is don’t care during the write queue selection
cycle. The queue selection only has to be made on a single WCLK cycle, this
will remain the selected queue until another queue is selected, the selected
queue is always the last queue selected.
The write port is designed such that 100% bus utilization can be obtained.
This means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed. When a new queue
is selected for write operations the address for that queue must be present on
the WRADD bus during a rising edge of WCLK provided that WADEN is HIGH.
A queue to be written to need only be selected on a single rising edge of WCLK.
All subsequent writes will be written to that queue until a new queue is selected.
A minimum of 2 WCLK cycles must occur between queue selections on the write
port. On the next WCLK rising edge the write port discrete full flag will update
to show the full status of the newly selected queue. On the second rising edge
of WCLK, data present on the data input bus, Din can be written into the newly
selected queue provided that WENis LOW and the new queue is not full. The
cycle of the queue selection and the next cycle will continue to write data present
on the data input bus, Din into the previous queue provided thatWENis active
LOW.
IfWEN isHIGH,inactiveforthese2clockcycles,thendatawillnotbewritten
in to the previous queue.
If the newly selected queue is full at the point of its selection, then writes to that
queue will be prevented, a full queue cannot be written into.
In the 8 queue multi-queue device the WRADD address bus is 5 bits wide.
The least significant 2 bits are used to address one of the 4 available queues
within a single multi-queue device. The most significant 3 bits are used when
a device is connected in expansion mode, up to 8 devices can be connected
in expansion, each device having its own 3 bit address. The selected device
is the one for which the address matches a 3 bit ID code, which is statically setup
on the ID pins, ID0, ID1, and ID2 of each individual device.
Note, the WRADD bus is also used in conjunction with FSTR (almost full flag
bus strobe), to address the almost full flag bus of a respective device during direct
mode of operation.
Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure
10, Write Queue Select, Write Operation and Full flag Operation and Figure
12, Full Flag Timing Expansion Mode for timing diagrams.
TABLE 1 — WRITE ADDRESS BUS, WRADD[5:0]
Operation WCLK WADEN FSTR
WRADD[5:0]
Write Queue
Select
PAFn Flag
Bus Device
Select
1 0 543 2 1 0
Device Select Write Queue Address
(Compared to (3 bits = 8 Queues)
ID0,1,2)
543 2 1 0
01
Device Select
XX X
(Compared to
ID0,1,2)
6113 drw05
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(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
READ QUEUE SELECTION & READ OPERATION
The multi-queue flow-control device has up to 8 queues that data is read from
via a common read port using the data outputs, Qout, read clock, RCLK and
read enable, REN. An output enable, OE control pin is also provided to allow
High-Impedance selection of the Qout data outputs. The multi-queue device
read port operates in a mode similar to “First Word Fall Through” on a traditional
IDT FIFO, but with the added feature of data output pipelining. This data
pipelining on the output port allows the user to achieve 100% bus utilization,
which is the ability to read out a data word on every rising edge of RCLK
regardless of whether a new queue is being selected for read operations.
The queue address present on the read address bus, RDADD during a rising
edge on RCLK while read address enable, RADEN is HIGH, is the queue
selected for read operations. A queue to be read from need only be selected
on a single rising edge of RCLK. All subsequent reads will be read from that
queue until a new queue is selected. A minimum of 3 RCLK cycles must occur
between queue selections on the read port. Data from the newly selected queue
will be present on the Qout outputs after 3 RCLK cycles plus an access time,
provided that OE is active, LOW. On the same RCLK rising edge that the new
queue is selected, data can still be read from the previously selected queue,
provided that REN is LOW, active and the previous queue is not empty on the
following rising edge of RCLK a word will be read from the previously selected
queue regardless of REN due to the fall through operation, (provided the queue
isnotempty). RememberthatOEallowstheusertoplacetheQout,dataoutput
bus into High-Impedance and the data can be read onto the output register
regardless of OE.
When a queue is selected on the read port, the next word available in that
queue (provided that the queue is not empty), will fall through to the output
register after 3 RCLK cycles. As mentioned, in the previous 3 RCLK cycles to
the new data being available, data can still be read from the previous queue,
providedthatthequeueisnotempty.Atthepointofqueueselection,the internal
data pipeline is loaded with the last word from the previous queue and the next
word from the new queue, both these words will fall through to the output register
consecutively upon selection of the new queue. This pipelining effect provides
the user with 100% bus utilization, and brings about the possibility that a “NULL”
queue may be required within a multi-queue device. Null queue operation is
discussed in the next section on.
If an empty queue is selected for read operations on the rising edge of RCLK,
on the same RCLK edge and the following RCLK edge, 2 final reads will be made
fromthepreviousqueue,providedthat RENisactive,LOW.OnthenextRCLK
rising edge a read from the new queue will not occur, because the queue is
empty. The last word in the data output register (from the previous queue), will
remain there, but the output valid flag, OV will go HIGH, to indicate that the data
present is no longer valid.
The RDADD bus is also used in conjunction with ESTR (almost empty flag
bus strobe), to address the almost empty flag bus quadrant during direct mode
of operation. In the 8 queue multi-queue device the RDADD address bus is 6
bits wide. The least significant 3 bits are used to address one of the 8 available
queues within a single multi-queue device. The most significant 3 bits are used
when a device is connected in expansion mode, up to 8 devices can be
connected in expansion, each device having its own 3 bit address. The selected
device is the one for which the address matches a 3 bit ID code, which is statically
setup on the ID pins, ID0, ID1, and ID2 of each individual device.
Refer to Table 2, for Read Address bus arrangement. Also, refer to Figures
13,15 & 16 for read queue selection and read port operation timing diagrams.
TABLE 2 — READ ADDRESS BUS, RDADD[5:0]
Operation RCLK RADEN ESTR
Read Queue
Select
10
PAEn Flag
Bus Device
Select
Null Queue
Select
01
10
Null-Q
RDADD[5:0]
0 543 2 10
Device Select Read Queue Address
(Compared to (3 bits = 8 Queues)
ID0,1,2)
543 2 1 0
0 Device Select
XXX
(Compared to
ID0,1,2)
543 2 1 0
1 X XX X X X
6113 drw06
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(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NULL QUEUE OPERATION (OF THE READ PORT)
Pipelining of data to the output port enables the device to provide 100% bus
utilization in standard mode. Data can be read out of the multi-queue flow-control
device on every RCLK cycle regardless of queue switches or other operations.
The device architecture is such that the pipeline is constantly filled with the next
words in a selected queue to be read out, again providing 100% bus utilization.
This type of architecture does assume that the user is constantly switching
queues such that during a queue switch, the last data word required from the
previous queue will fall through the pipeline to the output.
Note, that if reads cease at the empty boundary of a queue, then the last word
will automatically flow through the pipeline to the output.
The Null Q operation is achieved by setting the Null Q signal HIGH during
a queue select. Note that the read address bus RDADD[5:0] is a don't care. The
Null Queue is a separate queue within the device and thus the maximum number
of queues and memory is always available regardless of whether or not the Null
queue is used. Also note that in expansion mode a user may want to use a
dedicated null queue for each device. A null queue can be selected when no
further reads are required from a previously selected queue. Changing to a null
queue will continue to propagate data in the pipeline to the previous queue's
output. The Null Q can remain selected until a data becomes available in another
queue for reading. The Null-Q can be utilized in either standard or packet mode.
Note: If the user switches the read port to the null queue, this queue is seen
as and treated as an empty queue, therefore after switching to the null queue
the last word from the previous queue will remain in the output register and the
OV flag will go HIGH, indicating data is not valid.
The Null queue operation only has significance to the read port of the multi-
queue, it is a means to force data through the pipeline to the output. Null Q
selection and operation has no meaning on the write port of the device. Also,
refer to Figure 17, Read Operation and Null Queue Select for diagram.
BUS MATCHING OPERATION
Bus Matching operation between the input port and output port is available.
During a master reset of the multi-queue the state of the two setup pins, IW (Input
Width) and OW (Output Width) determine the input and output port buswidths
as per the selections shown in Table 3, “Bus Matching Set-up”. 9 bit bytes or
18 bit words can be written into and read form the queues. When writing to or
reading from the multi-queue in a bus matching mode, the device orders data in
a“LittleEndian”format.SeeFigure3,BusMatchingByteArrangementfordetails.
The Full flag and Almost Full flag operation is always based on writes and
reads of data widths determined by the write port width. For example, if the input
port is x18 and the output port is x9, then two data reads from a full queue will
be required to cause the full flag to go HIGH (queue not full). Conversely, the
Output Valid flag and Almost Empty flag operations are always based on writes
andreadsofdatawidthsdeterminedbythereadport.Forexample,iftheinputport
is x9 and the output port is x18, two write operations will be required to cause the
output valid flag of an empty queue to go LOW, output valid (queue is not empty).
Note, that the input port serves all queues within a device, as does the output
port, therefore the input bus width to all queues is equal (determined by the input
port size) and the output bus width from all queues is equal (determined by the
output port size).
TABLE 3 BUS-MATCHING SET-UP
IW
OW
Write Port
Read Port
0 0 x18 x18
0 1 x18 x9
1 0 x9 x18
1 1 x9 x9
FULL FLAG OPERATION
The multi-queue flow-control device provides a single Full Flag output, FF.
The FF flag output provides a full status of the queue currently selected on the
write port for write operations. Internally the multi-queue flow-control device
monitorsandmaintainsastatusofthefullconditionofallqueueswithinit,however
only the queue that is selected for write operations has its full status output to the
FF flag. This dedicated flag is often referred to as the “active queue full flag”.
When queue switches are being made on the write port, the FF flag output
will switch to the new queue and provide the user with the new queue status,
on the cycle after a new queue selection is made. The user then has a full status
for the new queue one cycle ahead of the WCLK rising edge that data can be
written into the new queue. That is, a new queue can be selected on the write
port via the WRADD bus, WADEN enable and a rising edge of WCLK. On the
second rising edge of WCLK, the FF flag output will show the full status of the
newly selected queue. On the third rising edge of WCLK following the queue
selection, data can be written into the newly selected queue provided that data
and enable setup & hold times are met.
Note, the FF flag will provide status of a newly selected queue two WCLK cycle
after queue selection, which is one cycle before data can be written to that queue.
This prevents the user from writing data to a queue that is full, (assuming that
a queue switch has been made to a queue that is actually full).
The FF flag is synchronous to the WCLK and all transitions of the FF flag occur
based on a rising edge of WCLK. Internally the multi-queue device monitors and
keeps a record of the full status for all queues. It is possible that the status of a
FF flag maybe changing internally even though that flag is not the active queue
flag (selected on the write port). A queue selected on the read port may
experience a change of its internal full flag status based on read operations.
See Figure 10, Write Queue Select, Write Operation and Full Flag
Operation and Figure 12, Full Flag Timing in Expansion Mode for timing
information.
EXPANSION MODE - FULL FLAG OPERATION
When multi-queue devices are connected in Expansion mode theFF flags
of all devices should be connected together, such that a system controller
monitoring and managing the multi-queue devices write port only looks at a
single FF flag (as opposed to a discrete FF flag for each device). This FF flag
is only pertinent to the queue being selected for write operations at that time.
Remember, that when in expansion mode only one multi-queue device can be
written to at any moment in time, thus the FF flag provides status of the active
queue on the write port.
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheFF flag
output have a High-Impedance capability, such that when a queue selection is
made only a single device drives the FF flag bus and all other FF flag outputs
connected to the FF flag bus are placed into High-Impedance. The user does
not have to select this High-Impedance state, a given multi-queue flow-control
device will automatically place its FF flag output into High-Impedance when none
of its queues are selected for write operations.
When queues within a single device are selected for write operations, the FF
flag output of that device will maintain control of the FF flag bus. ItsFF flag will
simply update between queue switches to show the respective queue full status.
The multi-queue device places its FF flag output into High-Impedance based
on the 3 bit ID code found in the 3 most significant bits of the write queue address
bus,WRADD.Ifthe3mostsignificantbitsofWRADDmatchthe3bitIDcodesetup
on the static inputs, ID0, ID1 and ID2 then the FF flag output of the respective
device will be in a Low-Impedance state. If they do not match, then the FF flag
output of the respective device will be in a High-Impedance state. See Figure
12, Full Flag Timing in Expansion Mode for details of flag operation, including
when more than one device is connected in expansion.
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT VALID FLAG OPERATION
The multi-queue flow-control device provides a single Output Valid flag
output, OV. The OV provides an empty status or data output valid status for the
data word currently available on the output register of the read port. The rising
edge of an RCLK cycle that places new data onto the output register of the read
port, also updates the OV flag to show whether or not that new data word is
actually valid. Internally the multi-queue flow-control device monitors and
maintains a status of the empty condition of all queues within it, however only
the queue that is selected for read operations has its output valid (empty) status
output to the OV flag, giving a valid status for the word being read at that time.
The nature of the first word fall through operation means that when the last
data word is read from a selected queue, the OV flag will go HIGH on the next
enabled read, that is, on the next rising edge of RCLK while REN is LOW.
When queue switches are being made on the read port, the OV flag will switch
to show status of the new queue in line with the data output from the new queue.
When a queue selection is made the first data from that queue will appear on
the Qout data outputs 3 RCLK cycles later, the OV will change state to indicate
validity of the data from the newly selected queue on this 3rdRCLK cycle also.
The previous cycles will continue to output data from the previous queue and
the OV flag will indicate the status of those outputs. Again, the OV flag always
indicates status for the data currently present on the output register.
The OV flag is synchronous to the RCLK and all transitions of the OV flag occur
based on a rising edge of RCLK. Internally the multi-queue device monitors and
keeps a record of the output valid (empty) status for all queues. It is possible that
the status of an OV flag may be changing internally even though that respective
flag is not the active queue flag (selected on the read port). A queue selected
on the write port may experience a change of its internal OV flag status based
on write operations, that is, data may be written into that queue causing it to
become “not empty”.
See Figure 13,Read Queue Select, Read Operationand Figure 14, Output
Valid Flag Timing for details of the timing.
EXPANSION MODE – OUTPUT VALID FLAG OPERATION
Whenmulti-queuedevicesareconnectedinExpansionmode,the OVflags
of all devices should be connected together, such that a system controller
monitoring and managing the multi-queue devices read port only looks at a
single OV flag (as opposed to a discreteOV flag for each device). This OV flag
is only pertinent to the queue being selected for read operations at that time.
Remember, that when in expansion mode only one multi-queue device can be
read from at any moment in time, thus theOV flag provides status of the active
queue on the read port.
This connection of flag outputs to create a single flag requires that the OV flag
output have a High-Impedance capability, such that when a queue selection is
made only a single device drives the OV flag bus and all other OV flag outputs
connected to theOV flag bus are placed into High-Impedance. The user does
not have to select this High-Impedance state, a given multi-queue flow-control
devicewillautomaticallyplaceitsOVflagoutputintoHigh-Impedancewhennone
of its queues are selected for read operations.
When queues within a single device are selected for read operations, the OV
flag output of that device will maintain control of theOV flag bus. ItsOV flagwill
simply update between queue switches to show the respective queue output
valid status.
The multi-queue device places its OV flag output into High-Impedance based
on the 3 bit ID code found in the 3 most significant bits of the read queue address
bus,RDADD.Ifthe3mostsignificantbitsofRDADDmatchthe3bitIDcodesetup
on the static inputs, ID0, ID1 and ID2 then the OV flag output of the respective
device will be in a Low-Impedance state. If they do not match, then the OV flag
output of the respective device will be in a High-Impedance state. See Figure
14, Output Valid Flag Timingfor details of flag operation, including when more
than one device is connected in expansion.
ALMOST FULL FLAG
As previously mentioned the multi-queue flow-control device provides a
single Programmable Almost Full flag output, PAF. The PAF flag output provides
a status of the almost full condition for the active queue currently selected on the
write port for write operations. Internally the multi-queue flow-control device
monitors and maintains a status of the almost full condition of all queues within
it, however only the queue that is selected for write operations has its full status
output to the PAF flag. This dedicated flag is often referred to as the “active queue
almost full flag”. The position of the PAF flag boundary within a queue can be
at any point within that queues depth. This location can be user programmed
via the serial port or one of the default values (8 or 128) can be selected if the
user has performed default programming.
As mentioned, every queue within a multi-queue device has its own almost
full status, when a queue is selected on the write port, this status is output via the
PAF flag. The PAF flag value for each queue is programmed during multi-queue
device programming (along with the number of queues, queue depths and
almost empty values). ThePAF offset value, m, for a respective queue can be
programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory
depth for that queue. The PAF value of different queues within the same device
can be different values.
Whenqueueswitchesarebeingmadeonthewriteport,the PAFflagoutput
will switch to the new queue and provide the user with the new queue status,
on the third cycle after a new queue selection is made, on the same WCLK cycle
that data can actually be written to the new queue. That is, a new queue can
be selected on the write port via the WRADD bus, WADEN enableandarising
edge of WCLK. On the third rising edge of WCLK following a queue selection,
the PAF flag output will show the full status of the newly selected queue. The PAF
is flag output is triple register buffered, so when a write operation occurs at the
almost full boundary causing the selected queue status to go almost full the PAF
will go LOW 3 WCLK cycles after the write. The same is true when a read occurs,
there will be a 3 WCLK cycle delay after the read operation.
So the PAF flag delays are:
from a write operation to PAF flag LOW is 2 WCLK + tWAF
The delay from a read operation to PAFflag HIGH is tSKEW2 + WCLK + tWAF
Note, if tSKEW is violated there will be one added WCLK cycle delay.
The PAF flagissynchronoustotheWCLKandalltransitionsofthePAFflag
occur based on a rising edge of WCLK. Internally the multi-queue device
monitors and keeps a record of the almost full status for all queues. It is possible
thatthestatusofa PAFflagmaybechanginginternallyeventhoughthatflagis
not the active queue flag (selected on the write port). A queue selected on the
read port may experience a change of its internal almost full flag status based
on read operations. The multi-queue flow-control device also provides a
duplicate of the PAF flag on the PAF[7:0] flag bus, this will be discussed in detail
in a later section of the data sheet.
See Figures 19 and 20 for Almost Full flag timing and queue switching.
ALMOST EMPTY FLAG
As previously mentioned the multi-queue flow-control device provides a
single Programmable Almost Empty flag output, PAE. The PAE flag output
provides a status of the almost empty condition for the active queue currently
selected on the read port for read operations. Internally the multi-queue flow-
control device monitors and maintains a status of the almost empty condition of
all queues within it, however only the queue that is selected for read operations
has its empty status output to the PAE flag. This dedicated flag is often referred
to as the “active queue almost empty flag”. The position of the PAE flag boundary
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
within a queue can be at any point within that queues depth. This location can
be user programmed via the serial port or one of the default values (8 or 128)
can be selected if the user has performed default programming.
As mentioned, every queue within a multi-queue device has its own almost
empty status, when a queue is selected on the read port, this status is output via
the PAEflag. The PAEflag value for each queue is programmed during multi-
queue device programming (along with the number of queues, queue depths
and almost full values). The PAEoffset value, n, for a respective queue can be
programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total memory
depth for that queue. The PAE value of different queues within the same device
can be different values.
Whenqueueswitchesarebeingmadeonthereadport,thePAE flagoutput
will switch to the new queue and provide the user with the new queue status,
on the third cycle after a new queue selection is made, on the same RCLK cycle
that data actually falls through to the output register from the new queue. That
is, a new queue can be selected on the read port via the RDADD bus, RADEN
enable and a rising edge of RCLK. On the third rising edge of RCLK following
a queue selection, the data word from the new queue will be available at the
output register and the PAE flag output will show the empty status of the newly
selected queue. The PAE is flag output is triple register buffered, so when a read
operation occurs at the almost empty boundary causing the selected queue
status to go almost empty the PAE will go LOW 3 RCLK cycles after the read.
The same is true when a write occurs, there will be a 3 RCLK cycle delay after
the write operation.
So the PAE flag delays are:
from a read operation to PAE flag LOW is 2 RCLK + tRAE
The delay from a write operation toPAE flag HIGH is tSKEW2+ RCLK + tRAE
Note, if tSKEW is violated there will be one added RCLK cycle delay.
ThePAE flag is synchronous to the RCLK and all transitions of the PAEflag
occur based on a rising edge of RCLK. Internally the multi-queue device
monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible
thatthestatusofa PAEflagmaybechanginginternallyeventhoughthatflagis
not the active queue flag (selected on the read port). A queue selected on the
write port may experience a change of its internal almost empty flag status based
on write operations. The multi-queue flow-control device also provides a
duplicate of the PAE flag on the PAE[7:0] flag bus, this will be discussed in detail
in a later section of the data sheet.
See Figures 21 and 22 for Almost Empty flag timing and queue switching.
POWER DOWN (PD)
This device has a power down feature intended for reducing power
consumption for HSTL/eHSTL configured inputs when the device is idle for a
long period of time. By entering the power down state certain inputs can be
disabled, thereby significantly reducing the power consumption of the part. All
WEN and REN signals must be disabled for a minimum of four WCLK and RCLK
cycles before activating the power down signal. The power down signal is
asynchronous and needs to be held LOW throughout the desired power down
time. During power down, the following conditions for the inputs/outputs signals
are:
All data in Queue(s) memory are retained.
All data inputs become inactive.
All write and read pointers maintain their last value before power down.
All enables, chip selects, and clock input pins become inactive.
All data outputs become inactive and enter high-impedance state.
All flag outputs will maintain their current states before power down.
Allprogrammableflagoffsetsmaintaintheirvalues.
All echo clocks and enables will become inactive and enter high-
impedance state.
The serial programming and JTAG port will become inactive and enter
high-impedance state.
All setup and configuration CMOS static inputs are not affected, as these
pins are tied to a known value and do not toggle during operation.
All internal counters, registers, and flags will remain unchanged and maintain
their current state prior to power down. Clock inputs can be continuous and free-
running during power down, but will have no affect on the part. However, it is
recommended that the clock inputs be low when the power down is active. To
exit power down state and resume normal operations, disable the power down
signal by bringing it HIGH. There must be a minimum of 1µs waiting period before
read and write operations can resume. The device will continue from where it
had stopped and no form of reset is required after exiting power down state. The
power down feature does not provide any power savings when the inputs are
configured for LVTTL operation. However, it will reduce the current for I/Os that
are not tied directly to VCC or GND. See Figure 28, Power Down Operation,
for the associated timing diagram.
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING
Output Valid, OV Flag Boundary
I/O Set-Up
OV Boundary Condition
In18 to out18 or In9 to out9
(Both ports selected for same queue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(see note below for timing)
In18 to out9)
(Both ports selected for same queue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(see note below for timing)
In9 to out18
(Both ports selected for same queue
when the 1st Word is written in)
OV Goes LOW after 2nd Write
(see note below for timing)
NOTE:
1. OV Timing
Assertion:
Write to OV LOW: tSKEW1 + RCLK + tROV
If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tROV
De-assertion:
Read Operation to OV HIGH: tROV
I/O Set-Up
Full Flag, FF Boundary
FF Boundary Condition
In18 to out18 or In9 to out9
(Both ports selected for same queue
when the 1st Word is written in)
FF Goes LOW after D+1 Writes
(see note below for timing)
In18 to out18 or In9 to out9
(Write port only selected for queue
when the 1st Word is written in)
FF Goes LOW after D Writes
(see note below for timing)
In18 to out9
(Both ports selected for same queue
when the 1st Word is written in)
FF Goes LOW after D Writes
(see note below for timing)
In18 to out9
(Write port only selected for queue
when the 1st Word is written in)
FF Goes LOW after D Writes
(see note below for timing)
In9 to out18
(Both ports selected for same queue
when the 1st Word is written in)
FF Goes LOW after ([D+1] x 2) Writes
(see note below for timing)
In9 to out18
(Write port only selected for queue
when the 1st Word is written in)
FF Goes LOW after (D x 2) Writes
(see note below for timing)
NOTE:
D = Queue Depth
FF Timing
Assertion:
Write Operation to FF LOW: tWFF
De-assertion:
Read to FF HIGH: tSKEW1 + tWFF
If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
I/O Set-Up
PAF & PAFn Boundary
In18 to out18 or In9 to out9
PAF/PAFn Goes LOW after
(Both ports selected for same queue when the 1st D+1-m Writes
Word is written in until the boundary is reached) (see note below for timing)
In18 to out18 or In9 to out9
PAF/PAFn Goes LOW after
(Write port only selected for same queue when the D-m Writes
1st Word is written in until the boundary is reached) (see note below for timing)
In18 to out9
PAF/PAFn Goes LOW after
D-m Writes (see below for timing)
In9 to out18
PAF/PAFn Goes LOW after
([D+1-m] x 2) Writes
(see note below for timing)
NOTE:
D = Queue Depth
m = Almost Full Offset value.
Default values: if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
PAF Timing
Assertion: Write Operation to PAF LOW: 2 WCLK + tWAF
De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF
PAFn Timing
Assertion: Write Operation to PAFn LOW: 2 WCLK* + tPAF
De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Programmable Almost Empty Flag, PAE Boundary
I/O Set-Up
PAE Assertion
In18 to out18 or In9 to out9
PAE Goes HIGH after n+2
(Both ports selected for same queue when the 1st Writes
Word is written in until the boundary is reached) (see note below for timing)
In18 to out9
PAE Goes HIGH after n+1
(Both ports selected for same queue when the 1st Writes
Word is written in until the boundary is reached) (see note below for timing)
In9 to out18
PAE Goes HIGH after
(Both ports selected for same queue when the 1st ([n+2] x 2) Writes
Word is written in until the boundary is reached) (see note below for timing)
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAE Timing
Assertion: Read Operation to PAE LOW: 2 RCLK + tRAE
De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
Programmable Almost Empty Flag Bus, PAEn Boundary
I/O Set-Up
PAEn Boundary Condition
In18 to out18 or In9 to out9
PAEn Goes HIGH after
(Both ports selected for same queue when the 1st n+2 Writes
Word is written in until the boundary is reached) (see note below for timing)
In18 to out18 or In9 to out9
PAEn Goes HIGH after
(Write port only selected for same queue when the n+1 Writes
1st Word is written in until the boundary is reached) (see note below for timing)
In18 to out9
PAEn Goes HIGH after n+1
Writes (see below for timing)
In9 to out18
PAEn Goes HIGH after
(Both ports selected for same queue when the 1st ([n+2] x 2) Writes
Word is written in until the boundary is reached) (see note below for timing)
In9 to out18
PAEn Goes HIGH after
(Write port only selected for same queue when the ([n+1] x 2) Writes
1st Word is written in until the boundary is reached) (see note below for timing)
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAEn Timing
Assertion: Read Operation to PAEn LOW: 2 RCLK* + tPAE
De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
24


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PAFn FLAG BUS OPERATION
The IDT72T51333/72T51343/72T51353 multi-queue flow-control devices
can be configured for up to 8 queues, each queue having its own almost full
status. An active queue has its flag status output to the discrete flags, FF and PAF,
on the write port. Queues that are not selected for a write operation can have
their PAF status monitored via the PAFn bus. ThePAFn flag bus is 8 bits wide,
so that all 8 queues can have their status output to the bus. When a single multi-
queue device is used anywhere from 1 to 8 queues may be set-up within the
part, each queue having its own dedicated PAF flag output on the PAFn bus.
Queues 1 through 8 have their PAF status to PAF[0] through PAF[7]
respectively. If less than 8 queues are used then only the associated PAFn
outputs will be required, unused PAFn outputs will be don’t care outputs. When
devices are connected in expansion mode the PAFn flag bus can also be
expanded beyond 8 bits to produce a wider PAFn bus that encompasses all
queues.
Alternatively, the 8 bit PAFn flag bus of each device can be connected together
toformasingle8bitbus,i.e.PAF[0]ofdevice1willconnectto PAF[0]ofdevice
2 etc. When connecting devices in this manner the PAFn can only be driven
by a single device at any time, (the PAFn outputs of all other devices must be
in high impedance state). There are two methods by which the user can select
which device has control of the bus, these are “Direct” (Addressed) mode or
“Polled” (Looped) mode, determined by the state of the FM (flag Mode) input
during a Master Reset.
PAFn BUS EXPANSION - DIRECT MODE
If FM is LOW at Master Reset then the PAFn bus operates in Direct
(addressed) mode. In direct mode the user can address the device they require
to control the PAFn bus. The address present on the 3 most significant bits of
the WRADD[5:0] address bus with FSTR (PAF flag strobe), HIGH will be
selected as the device on a rising edge of WCLK. So to address the first device
in a bank of devices the WRADD[5:0] address should be “000xxx” the second
device “001xxx” and so on. The 3 most significant bits of the WRADD[5:0]
address bus correspond to the device ID inputs ID[2:0]. The PAFn bus will
change status to show the new device selected 1 WCLK cycle after device
selection. Note, that if a read or write operation is occurring to a specific queue,
say queue ‘x’ on the same cycle as a PAFn bus switch to the device containing
queue ‘x’, then there may be an extra WCLK cycle delay before that queues
status is correctly shown on the respective output of the PAFn bus. However,
the “active” PAF flag will show correct status at all times.
Devices can be selected on consecutive WCLK cycles, that is the device
controlling the PAFn bus can change every WCLK cycle. Also, data present
on the input bus, Din, can be written into a queue on the same WLCK rising edge
that a device is being selected on the PAFn bus, the only restriction being that
a write queue selection and PAFn bus selection cannot be made on the same cycle.
PAFn BUS EXPANSION– POLLED MODE
If FM is HIGH at Master Reset then the PAFn bus operates in Polled (Looped)
mode. In polled mode the PAFn bus automatically cycles through the devices
connected in expansion. In expansion mode one device will be set as the
Master, MAST input tied HIGH, all other devices will have MAST tied LOW. The
master device is the first device to take control of the PAFn bus and place the
PAF status of its queues onto the bus on the first rising edge of WCLK after the
MRS input goes HIGH once a Master Reset is complete. The FSYNC (PAF sync
pulse) output of the first device (master device), will be HIGH for one cycle of
WCLK indicating that it is has control of the PAFn bus for that cycle.
The device also passes a “token” onto the next device in the chain, the next
device assuming control of the PAFn bus on the next WCLK cycle. This token
passing is done via the FXO outputs and FXI inputs of the devices (“PAFn
Expansion Out” and “PAFn Expansion In”). The FXO output of the first device
connecting to the FXI input of the second device in the chain, the FXO of the
second device connects to the FXI of the third device and so on. The FXO of
the final device in a chain connects to the FXI of the first device, so that once the
PAFn bus has cycled through all devices control is again passed to the first
device. The FXO output of a device will be HIGH for the WCLK cycle it has control
of the bus.
Please refer to Figure 26, PAFn Bus – Polled Mode for timing information.
PAEn FLAG BUS OPERATION
The IDT72T51333/72T51343/72T51353 multi-queue flow-control devices
can be configured for up to 8 queues, each queue having its own almost empty
status.Anactivequeuehasitsflagstatusoutputtothediscreteflags,OVandPAE,
on the read port. Queues that are not selected for a read operation can have
theirPAE statusmonitoredviathePAEnbus.ThePAEnflagbusis8bitswide,
so that all 8 queues can have their status output to the bus. The multi-queue
device can provide “Almost Empty” status via the PAEn bus of its queues. If it
is LOW then the PAEn bus will provide “Almost Empty” status.
When a single multi-queue device is used anywhere from 1 to 8 queues may
be set-up within the part, each queue having its own dedicated PAEn flag output
onthe PAEnbus.Queues1through8havetheirPAE statustoPAE[0]through
PAE[7] respectively. If less than 8 queues are used then only the associated
PAEnoutputswillberequired,unused PAEnoutputswillbedon’tcareoutputs.
When devices are connected in expansion mode the PAEn flag bus can also
be expanded beyond 8 bits to produce a wider PAEn bus that encompasses
all queues.
Alternatively, the 8 bit PAEn flag bus of each device can be connected
togethertoformasingle8bitbus,i.e. PAE[0]ofdevice1willconnecttoPAE[0]
of device 2 etc. When connecting devices in this manner the PAEn bus can only
be driven by a single device at any time, (the PAEn outputs of all other devices
must be in high impedance state). There are two methods by which the user
can select which device has control of the bus, these are “Direct” (Addressed)
mode or “Polled” (Looped) mode, determined by the state of the FM (flag Mode)
input during a Master Reset.
PAEn BUS EXPANSION- DIRECT MODE
If FM is LOW at Master Reset then the PAEn bus operates in Direct
(addressed) mode. In direct mode the user can address the device they require
to control the PAEn bus. The address present on the 3 most significant bits of
the RDADD[5:0] address bus with ESTR (PAE flag strobe), HIGH will be
selected as the device on a rising edge of RCLK. So to address the first device
in a bank of devices the RDADD[5:0] address should be “000xxx” the second
device “001xxx” and so on. The 3 most significant bits of the RDADD[5:0]
address bus correspond to the device ID inputs ID[2:0]. The PAEn bus will
change status to show the new device selected 1 RCLK cycle after device
selection. Note, that if a read or write operation is occurring to a specific queue,
say queue ‘x’ on the same cycle as aPAEnbusswitchtothedevicecontaining
queue ‘x’, then there may be an extra RCLK cycle delay before that queues
status is correctly shown on the respective output of the PAEn bus. However,
the “active” PAE flag will show correct status at all times.
Devices can be selected on consecutive RCLK cycles, that is the device
controlling the PAEn bus can change every RCLK cycle. Also, data can be read
out of a queue on the same RCLK rising edge that a device is being selected
on the PAEn bus, the only restriction being that a read queue selection and PAEn
bus selection cannot be made on the same cycle.
25


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PAEn BUS EXPANSION- POLLED MODE
If FM is HIGH at Master Reset then the PAEn bus operates in Polled
(Looped) mode. In polled mode the PAEn bus automatically cycles through the
devices connected in expansion. In expansion mode one device will be set
as the Master, MAST input tied HIGH, all other devices will have MAST tied
LOW. The master device is the first device to take control of the PAEn bus and
placethePAEstatusofitsqueues onto the bus on the first rising edge of RCLK
after the MRS input goes HIGHonceaMasterResetiscomplete.TheESYNC
(PAE sync pulse) output of the first device (master device), will be HIGH for
one cycle of RCLK indicating that it is has control of the PAEn bus for that
cycle.
The device also passes a “token” onto the next device in the chain, the next
device assuming control of the PAEn bus on the next RCLK cycle. This token
passing is done via the EXO outputs and EXI inputs of the devices (“PAEn
Expansion Out” and “PAEn Expansion In”). The EXO output of the first device
connecting to the EXI input of the second device in the chain, the EXO of the
second device connects to the EXI of the third device and so on. The EXO of
the final device in a chain connects to the EXI of the first device, so that once the
PAEn bus has cycled through all devices control is again passed to the first
device. The EXO output of a device will be HIGH for the RCLK cycle it has control
of the bus.
Please refer to Figure 27, PAEn Bus – Polled Mode for timing information.
26


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ECHO READ CLOCK (ERCLK)
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
selectable via IOSEL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of REN and RADEN.
The ERCLK output follows the RCLK input with an associated delay. This
delay provides the user with a more effective read clock source when reading
data from the Qn outputs. This is especially helpful at high speeds when variables
withinthedevicemaycausechangesinthedataaccesstimes. Thesevariations
in access time maybe caused by ambient temperature, supply voltage, device
characteristics. The ERCLK output also compensates for any trace length
delays between the Qn data outputs and receiving devices inputs.
Any variations effecting the data access time will also have a corresponding
effect on the ERCLK output produced by the queue device, therefore the ERCLK
output level transitions should always be at the same position in time relative to
the data outputs. Note, that ERCLK is guaranteed by design to be slower than
the slowest Qn, data output. Refer to Figure 3, Echo Read Clock and Data
Output Relationship and Figure 23, Echo RCLK & Echo REN Operation for
timinginformation.
ECHO READ ENABLE (EREN)
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
selectable via IOSEL.
The EREN output is provided to be used in conjunction with the ERCLK
output and provides the reading device with a more effective scheme for reading
data from the Qn output port at high speeds. TheERENoutput is controlled by
internal logic that behaves as follows: TheEREN output is active LOW for the
RCLK cycle that a new word is read out of the queue. That is, a rising edge of
RCLK will cause EREN to go active (LOW) if REN is active and the queue is
NOT empty.
RCLK
ERCLK
tERCLK
tERCLK
QSLOWEST(3)
tA tD
6113 drw07
NOTES:
1. REN is LOW. OE is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
Figure 3. Echo Read Clock and Data Output Relationship
27


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BYTE ORDER ON INPUT PORT:
D17-D9
A
D8-D0
B Write to Queue
BYTE ORDER ON OUTPUT PORT:
BE IW OW
LLL
Q17-Q9 Q8-Q0
A B Read from Queue
(a) x18 INPUT to x18 OUTPUT - BIG ENDIAN
BE IW OW
HLL
Q17-Q9
B
Q8-Q0
A Read from Queue
(b) x18 INPUT to x18 OUTPUT - LITTLE ENDIAN
BE IW OW
LLH
BE IW OW
HLH
BYTE ORDER ON INPUT PORT:
Q17-Q9
Q8-Q0
A 1st: Read from Queue
Q17-Q9 Q8-Q0
B 2nd: Read from Queue
(c) x18 INPUT to x9 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
B 1st: Read from Queue
Q17-Q9
Q8-Q0
A 2nd: Read from Queue
(d) x18 INPUT to x9 OUTPUT - LITTLE ENDIAN
D17-D9
D8-D0
A 1st: Write to Queue
D17-Q9
D8-Q0
B 2nd: Write to Queue
BYTE ORDER ON OUTPUT PORT:
BE IW OW
LHL
BE IW OW
HHL
Q17-Q9
A
Q8-Q0
B Read from Queue
(a) x9 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
B
Q8-Q0
A Read from Queue
(a) x9 INPUT to x18 OUTPUT - LITTLE ENDIAN
6113 drw08
Figure 4. Bus-Matching Byte Arrangement
28


IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MRS
WEN
REN
SENI
FSTR,
ESTR
WADEN,
RADEN
ID0, ID1,
ID2
OW, IW
FM
MAST
DFM
DF
FF
OV
PAF
PAE
tRSS
tRSS
tRSS
tRSS
tRSS
tRSS
tRSS
tRSS
tRSS
tRSS
PAFn
PAEn
Qn
NOTES:
1. OE can toggle during this period.
2. PRS should be HIGH during a MRS.
tRS
tRSR
HIGH = Looped
LOW = Strobed (Direct)
HIGH = Master Device
LOW = Slave Device
HIGH = Default Programming
LOW = Serial Programming
tRSF
tRSF
tRSF
tRSF
tRSF
tRSF
tRSF
HIGH = Offset Value is 128
LOW = Offset value is 8
LOGIC "1" if Master Device
HIGH-Z if Slave Device
HIGH-Z if Slave Device
LOGIC “0" if Master Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
HIGH-Z if Slave Device
LOGIC "0" if Master Device
HIGH-Z if Slave Device
LOGIC "0" if Master Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
LOGIC "1" if OE is LOW and device is Master
HIGH-Z if OE is HIGH or Device is Slave
6113 drw09
Figure 5. Master Reset
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IDT72T51353 (IDT)
(IDT72T513x3) MULTI-QUEUE FLOW-CONTROL DEVICES

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
WADEN
WEN
WRADD
FF
PAF
Active Bus
PAF-Qx(5)
PRS
RCLK
REN
RADEN
RDADD
OV
PAE
Active Bus
PAE-Qx(6)
w-3 w-2
w-1 w
w+1
w+2
w+3
tQS tQH
tENS
tENS
tAS
Qx
tAH
tPRSS
tPRSH
tWFF
tWAF
tPAF
tQS tQH
tAS
Qx
tAH
tENS
tPRSS
tPRSH
tENS
tROV
tRAE
tPAE
r-2 r-1 r r+1 r+2 r+3 r+4
NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 3 clock cycles before the Partial Reset takes place, on both the write and read ports.
6113 drw10
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
Figure 6. Partial Reset
Master Reset
Default Mode
DFM = 0
Serial Enable
Serial Input
DFM
MRS
MQ1
SENI
SENO
SI SO
SCLK
DFM
MRS
MQ2
SENI
SENO
SI SO
SCLK
DFM
MRS
MQn
SENI
SENO
SI SO
SCLK
Serial Loading
Complete
Serial Clock
Figure 7. Serial Port Connection for Serial Programming
30
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