DD-00429 (Data Device Corporation)
ARINC 429 Microprocessor Interface

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DD-00429
ARINC 429 MICROPROCESSOR
INTERFACE
DESCRIPTION
DDC's DD-00429 provides a complete and flexible interface between
a microprocessor and an ARINC 429 data bus. The DD-00429 inter-
faces to a processor through a 128 x 32 bit static ram as well as four
32 x 32 receive FIFOs and two 32 x 32 transmit FIFOs. The DD-
00429 can be easily interfaced to 8- or 16-bit processors via a
buffered shared RAM configuration.
The DD-00429, when configured with two Transceivers, supports four
ARINC 429 Receive channels (Rx0, Rx1, Rx2 and Rx3) each receiv-
ing data independently. The receive data rates (high or low speed) for
channel Rx0 and Rx1 can be programmed independently from Rx2
and Rx3. The DD-00429 can decode and sort data based on the
ARINC 429 Label and SDI bits via the Data Match Processor, and
store it in RAM and/or FIFOs via the Data Store Processor.
The DD-00429, when configured with two Line Drivers, supports two
ARINC 429 Transmit channels (Tx0 and Tx1) and can transmit data
independently. The transmit data rate can also be programmed inde-
pendently. There are two 32 x 32 bit FIFOs for each of the transmit-
ters that send out data.
The DD-00429 has the capability of programming three general pur-
pose interrupts as well as generating an interrupt based on an error
condition. The general purpose interrupts can be programmed to trig-
ger other external hardware. They can either be LEVEL or PULSE
driven.
The features built into the DD-00429 enable the user to off-load the
host processor and use that processing time to implement operations
other than polling the ARINC 429 Bus. The decoding and sorting of
data allows the user to gather data much quicker than past designs.
If the user requires a microprocessor in the avionics box, this device
will facilitate a clean and quick design.
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Make sure the next
Card you purchase
has...
®
FEATURES
• Four ARINC 429 Receive Channels,
(configured with Transceivers)
• Two ARINC 429 Transmit Channels
(configured with Drivers)
• 128 x 32 Shared RAM Interface
• Label and Destination Decoding and
Sorting
• Two 32 x 32 Transmit FIFO's
• Four 32 x 32 Receive FIFO’s
• Interfaces Easily to 8- or 16-Bit
Microprocessor
• Built-in Fault Detection Circuitry
• Free “C” Library Software
• Application Note AN/A-6 “FAQ’s”
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7234
All trademarks are the property of their respective owners.
© 1998, 1999 Data Device Corporation


DD-00429 (Data Device Corporation)
ARINC 429 Microprocessor Interface

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A1OUT
B1OUT
DD-03182
LINE
DRIVER
A2OUT
B2OUT
DD-03182
LINE
DRIVER
ARINC 429
RECEIVE 0
ARINC 429
RECEIVE 1
ARINC 429
RECEIVE 2
ARINC 429
RECEIVE 3
ARINC 429
TRANSMIT 0
ARINC 429
TRANSMIT 1
2
2
ARINC 429
WRAPAROUND Rx0 LOGIC
WRAPAROUND
ARINC 429
Rx1 LOGIC
WRAPAROUND
ARINC 429
Rx2 LOGIC
WRAPAROUND
ARINC 429
Rx3 LOGIC
ARINC 429
Tx0 LOGIC
ARINC 429
Tx1 LOGIC
DD-03182 LINE DRIVER (x2)
DD-03282 TRANSCEIVER (x2)
Rx DATA
Tx FIFO
32 WORDS
Tx FIFO
32 WORDS
128 X 16
STATIC RAM
DMT RAM
CTRL DATA ADDR
128 X 32
STATIC RAM
Rx RAM
CTRL DATA ADDR
DATA
MATCH
PROCESSOR
DATA ADDR
DMP
DATA
ADDR
ADDR
DATA
DATA
DATA
STORE
PROCESSOR
DATA ADDR
Rx0 FIFO
32 WORDS
Rx1 FIFO
32 WORDS
Rx2 FIFO
32 WORDS
Rx3 FIFO
32 WORDS
DATA
INTERRUPT
CONTROLLER
3
CPU INTERFACE
16 12
IRQ DATA ADDR CONTROL
MICROPROCESSOR
OR CPU
DD-00429 FP/VP ASIC
FIGURE 1. CHIP SET BLOCK DIAGRAM


DD-00429 (Data Device Corporation)
ARINC 429 Microprocessor Interface

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TABLE 1. DD-00429 ABSOLUTE MAXIMUM RATINGS (TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER
DC Supply Voltage
Signal Input Voltage (logic inputs)
Storage Temperature
Operating Temperature
Lead Temperature (soldering)
Body Temperature (soldering)
MIN
MAX
UNITS
-0.3 7.0 Vdc
-0.3 Vdd+0.3 Vdc
-85 125
°C
-40 85
°C
280 (for 3 sec)
°C
210 (for 30 sec)
°C
TABLE 2. DD-00429 SPECIFICATIONS (TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
MIN
MAX
UNITS
COMMENTS
LOGIC INPUTS/OUTPUTS
DC Supply Voltage
DC Supply Current
Schmitt 0Threshold
Schmitt 1Threshold
Vdd 4.5 5.5 Vdc
Idd 42.2 mA Device operation @ 16 MHz,
Typical Idd = 38.4 mA @ 5.0V. (@85°C)
Vt-
0.2*Vdd
Vdc
RESET RC*, 16 MHZ CLOCK
Vt+ 0.8*Vdd
Vdc RESET RC*, 16 MHZ CLOCK
Schmitt Hysteresis
Input Logic Voltage Low
Input Logic Voltage High
Input Logic Current Low
Input Logic Current Low
Input Logic Current High
Output Voltage Logic Low
Output Voltage Logic High
Output Leakage Current, Hi-Z
Vh 1
Vdc RESET RC*, 16 MHZ CLOCK
Vil 0.8 Vdc All other Inputs. (See Note 1).
Vih 2.0
Vdc All other Inputs. (See Note 1).
Iil
-25.3
-137
µA Input pins with internal pull-up logic: INT/MOT*,
8/16*, ZERO WAIT MODE and MASTER
RESET* @ Vdd = 5.5V
Iil
-1.0 1.0
µA All other Inputs. (See Note 1).
Iih -1.0 1.0 µA All other Inputs. (See Note 1).
Vol 0.4 Vdc Io1=3.84 mA minimum @Vdd= 4.5V.
(See note 2)
Voh 2.4
Vdc Ioh=3.84 mA minimum @Vdd= 4.5V.
(See note 2)
Ioz -10 10 µA For TXDB0-TXDB15, D0-D15, READY,
DTACK*, ERROR*, IRQ3*, IRQ2* and IRQ1 @
vdd = 5.5V
NOTES:
1. TTL compatible input logic voltage levels at CMOS input logic current levels.
2. CMOS output logic voltage at current levels.
ARINC 429 RECEIVERS
The DD-00429 supports four ARINC 429 inputs, designated
Receive channels 0 through 3 (Rx0, Rx1, Rx2 and Rx3). The
architecture of each of the four receiver circuits is identical and
each receives data independently. ARINC 429 data is directly
received into the ARINC 429 transceiver. Input protection, in
accordance with the ARINC 429 specification, is provided along
with voltage level translation from +5 V bipolar, nonreturn-to-zero
data to conventional, +5 V logic levels.
Receive Data Rates: Data rates can be programmed for chan-
nels 0 and 1 independently of channels 2 and 3 via bits 2 and 3
of Arinc Control Register 2. The receiver circuitry will success-
fully decode an incoming ARINC 429 data stream as long as the
data rate is within ±5% of the nominal rate as determined by the
Hi Speed/Low Speed Bit and the associated ARINC Clock input
(ARINC CLK 0 or ARINC CLK 1). The two 1 MHz ARINC clock
inputs may be tied to the 1 MHz clock output or may be con-
nected to another clock source.
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ARINC 429 Microprocessor Interface

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The ARINC CLK input should nominally be 10 times (for High-
Speed Mode) or 80 times (for Low-Speed mode) the desired
ARINC Data Rate. ARINC CLK 0 is used to synchronize chan-
nels Rx0 and Rx1 while ARINC CLK 1 is used to synchronize
channels Rx2 and Rx3.
Filtering and Sorting Rx Data: The receiver circuitry converts
the serial data stream into a 32-bit-wide parallel data word. The
32-bit word is processed internally by a Data Match Processor
(DMP). It compares the incoming data to a table of data initial-
ized by the processor. This determines what incoming data is to
be saved, where it is going to be saved, and if any interrupts are
to be generated. The table of data is stored in a 128 word x 16
bit Data Match Table (DMT) RAM. When a match between the
received ARINC 429 data and the criteria stored in a DMT entry
is found, the received data, the storage address and modes, and
interrupt parameters are passed to the Data Store Processor
(DSP). The storage address in the Receive RAM is the address
of the first matching DMT entry minus 200 hex.
There are three requirements that must be met in order to match
incoming ARINC 429 data to each DMT entry:
1) System Address Label: Bits 0-7 of the DMT are compared
to the System Address Label (SAL) of the incoming ARINC
429 data word. If the DMT SAL entry is zero then the SAL of
the incoming data word is ignored (or considered a match).
2) Source/Destination Bits: Bits 8 and 9 of each DMT entry
are compared to the Source/Destination (S/D) bits of the
incoming ARINC 429 data word. If these bits match, or if Bit
10 of the DMT entry is set to a 1, then the S/D bit comparison
is considered a match. It is also possible, through DMP
Control Register 1, to enable All Call Modeas defined in the
ARINC 429 specification. When enabled for a particular
receive channel, the S/D bits will be considered a match when
the incoming ARINC 429 data contains a 00 in its S/D bit pair.
3) Receive Channel Number: Bits 12 and 13 of each DMT
entry are compared to the number of the channel which
received the ARINC 429 data.
ARINC 429 TRANSMITTER(S)
The DD-00429 supports two ARINC 429 transmitters. Each of
these channels transmits data independently and are designat-
ed Tx0 and Tx1. The transmit output of the DD-00429 is a TTL
encoded digital data stream which can be connected directly to
the ARINC 429 line driver.
Transmit Data Rates: Data rates can be programmed for
Channels 0 and 1 independently. The transmit data rate is deter-
mined by the High-Speed/Low-Speed Bit for each of the Tx chan-
nels in Arinc Control Register 1 and the associated ARINC Clock
input (ARINC CLK 0 or ARINC CLK 1). The two, 1 MHz ARINC
clock inputs may be tied to the 1 MHz clock output or they may
be connected to another clock source to achieve transmit data
rates other than 100 kHz or 12.5 kHz. The transmit clock input
should be 10 times (for High-Speed Mode) or 80 times (for Low-
Speed mode) the desired ARINC transmit data rate.
Transmit FIFOs: Each transmitter channel is provided with an
output FIFO which is 32 words deep by 32 bits wide. When writ-
ing data to the Tx FIFO, the associated Disable Tx(n) bit in
ARINC Control Register 2 can be set to a logic zero until the
FIFO is loaded with the desired data. Upon setting the Disable
Tx(n) low the transmit channel will send the 32-bit message
words with appropriate interword gaps on the ARINC 429 output.
A status bit indicating that the FIFO is empty is supplied for each
transmitter in the ARINC Status Register.
Wraparound testing can be performed from Tx0 to Rx0 and Rx1,
and from Tx1 to Rx2 and Rx3. The data received on Rx1 and
Rx3 in wraparound test mode is inverted. Wraparound testing is
enabled by setting the appropriate bits in Arinc Control Register
1. The parity of the transmitted word can be altered to no parity
(instead of the usual odd parity) by setting the associated Tx(n)
Parity bit in the Arinc Control Register 1. This is useful to verify
proper operation of the parity check circuitry for each of the
receive circuits during wraparound test mode.
A Data Match has occurred when all of the previous conditions
are satisfied; the data will then be stored in a RAM location
whose address equals the matching DMT entry minus 200 hex.
Bit 11 of each DMT entry, when set, will cause the incoming
ARINC 429 data to be stored in the corresponding receive chan-
nel FIFO (as well as the Rx RAM) when the data match condi-
tions are met.
Bits 14 and 15 of each DMT entry provide the ability to cause
one of three general purpose interrupts upon a data match con-
dition. If set to 00then no interrupt will occur upon a data match
condition (more information on interrupts is described later).
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ARINC 429 Microprocessor Interface

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PROCESSOR INTERFACE
The processor interface allows for the use of either an 8- or 16-
bit data bus. Intel or Motorola control signal formats can also be
used.
INTERRUPT OPERATIONAL MODES
The DD-00429 provides four interrupt outputs. Three of these
interrupt outputs (IRQ1, IRQ2, and IRQ3) are general purpose
programmable interrupts. The fourth interrupt is an Error interrupt
output which is specifically used to provide indications of various
error conditions and is nonmaskable.
ERROR INTERRUPT OPERATION
When an error condition occurs, the ERROR output pin goes low
to indicate the presence of an error. The error pin will go high
again when the Error Status Register is clear. Each of these bits
is cleared by either reading the Error Status Register or remov-
ing the error condition.
GENERAL PURPOSE INTERRUPTS
The three general purpose interrupt outputs can be used for mul-
tilevel interrupts or to trigger other external hardware for various
conditions. Each condition can be mapped to any one of the
three general purpose interrupts or disabled (by mapping to
IRQ0 which does not exist). Each interrupt output can be pro-
grammed to be either a LEVEL interrupt or PULSE interrupt via
the associated IRQ Control Register 2. When programmed for
pulse interrupt mode, the associated interrupt pin will go low for
1 µS and return high again. When programmed for LEVEL inter-
rupt mode, the interrupt will remain until the associated IRQ
Status Register is read, thus clearing the associated bits in each
interrupt register.
Each of the individual interrupt registers can be masked by set-
ting their corresponding bit in IRQ Control Register 1. It should
be noted that the masking function only prevents the associated
IRQ pin from becoming active. When the mask bit is cleared, an
interrupt can occur in LEVEL IRQ mode if one or more interrupt
conditions occurred during the time when the mask was set. If
the user needs to ensure the interrupt will not occur upon clear-
ing the mask bit, the CPU should be programmed to read the
associated interrupt status register immediately prior to clearing
the IRQ mask bit.
ZERO WAIT MODE OPERATION
When Zero Wait Mode is enabled by not grounding the ZERO
WAIT pin, the host microprocessor may read data from the DD-
00429 shared memory resources (DMT and Rx RAM) without
using the READY or DTACK signals to insert wait states into the
microprocessor cycle. This is accomplished by an additional
dummy readof the desired address. This dummy read causes
the DD-00429 to fetch the data from the source and place it in a
latch. The data can then be read from the latch (word-by-word or
byte-by-byte) by reading the same addresses. Thus for a 32-bit
read in 8-bit mode, the microprocessor would perform a total of
five read operations. The first read would be the dummy read;
subsequent reads would transfer the data.
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DD-00429 (Data Device Corporation)
ARINC 429 Microprocessor Interface

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PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DESCRIPTION
+5V
TX DB11
TX DB12
TX DB13
TX DB14
TX DB15
EN RX1
EN RX0
SELECT
RX RDY1
RX RDY0
GND
GND
GND
INT/ MOTO
8/16
+5V
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CS0
CS1
CS2
BIST R3 (N/C)
GND
+5V
GND
TABLE 3. DD-00429VP (144-PIN TQFP) ASIC PINOUTS
PIN NO.
DESCRIPTION
PIN NO.
DESCRIPTION
37 +5V
73 +5V
38 XTAL1 (N/C)
74 OSC CLK OUT (N/C)
39 GND
75 BIST DMT (N/C)
40 TSB2 (N/C)
76 BIST RAM 7 (N/C)
41 TSB3 (N/C)
77 BIST RAM 24 (N/C)
42 TSA0 (N/C)
78 D0
43 TSA1 (N/C)
79 D1
44 TSA2 (N/C)
80 D2
45 TSA3 (N/C)
81 D3
46 TMA0 (N/C)
82 D4
47 TMA1 (N/C)
83 D5
48 TMA2 (N/C)
84 D6
49 TMA3 (N/C)
85 D7
50 TMA4 (N/C)
86 GND
51 TMA5 (N/C)
87 +5V
52 TMA6 (N/C)
88 GND
53 TMA7 (N/C)
89 +5V
54 TSB0 (N/C)
90 D8
55 TSB1 (N/C)
91 D9
56 +5V
92 D10
57 GND
93 D11
58 TMB4 (N/C)
94 D12
59 TMB5 (N/C)
95 D13
60 TMB6 (N/C)
96 D14
61 TMB7 (N/C)
97 D15
62 ZERO WAIT MODE
98 GND
63 READY
99 GND
64 RD or DS
100 IRQ3
65 WR or RD/WR
101 IRQ2
66 DTACK
102 IRQ1
67 ERROR
103 RESET RC
68 MASTER RESET
104 ARINC CLK OUT
69 +5V
105 ARINC CLK 1
70 BIST TOA (N/C)
106 ARINC CLK 0
71 BIST TOB (N/C)
107 BIST R2 (N/C)
72 GND
108 GND
.866 ±0.004
(22.00 ±0.1)
.787 ±0.004
(22.00 ±0.1)
PIN NO.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DESCRIPTION
+5V
RESET 1
CW STRB1
EN TX1 OUT
TX1 EMPTY
LD TX1 HI
LD TX1 LOW
+5V
GND
+5V
16 MHZ CLOCK
EN RX3
EN RX2
RX RDY3
RX RDY2
+5V
GND
RESET 0
CW STRB 0
EN TX0 OUT
TX0 EMPTY
LD TX0 HI
LD TX0 LOW
GND
TX DB0
TX DB1
TX DB2
TX DB3
TX DB4
TX DB5
TX DB6
TX DB7
TX DB8
TX DB9
TX DB10
GND
.866 ±0.004
(22.00 ±0.1)
.787 ±0.004
(20.00 ±0.1)
DD-00429VP
PIN 1
.008
+0.02
0.01
(0.22 ±0.05)
.0197
(0.50)
Data Device Corporation
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.055 ±0.002
(1.40 ±0.05)
.004 ±0.002
(0.1 ±0.05)
.024 ±0.006
(0.60 ±0.15)
.059 ±0.004
(1.50 ±0.1)
DIMENSIONS IN INCHES (MILLIMETERS).
FIGURE 2. DD-00429VP MECHANICAL OUTLINE (144-PIN TQFP)
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ARINC 429 Microprocessor Interface

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PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DESCRIPTION
+5V
TX DB11
TX DB12
TX DB13
TX DB14
TX DB15
EN RX1
EN RX0
SELECT
RX RDY1
RX RDY0
GND
GND
GND
INT/ MOTO
8/16
+5V
TX0 A
TX0 B
TX1 A
TX1 B
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CS0
CS1
CS2
BIST R3 (N/C)
GND
+5V
GND
TABLE 4. DD-00429FP (160-PIN PQFP) ASIC PINOUTS
PIN NO.
DESCRIPTION
PIN NO.
DESCRIPTION
41 +5V
81 +5V
42 XTAL1 (N/C)
82 OSC CLK OUT (N/C)
43 GND
83 BIST T1A (N/C)
44 TSB2 (N/C)
84 BIST T1B (N/C)
45 TSB3 (N/C)
85 BIST DMT (N/C)
46 TSA0 (N/C)
86 BIST RAM7 (N/C)
47 TSA1 (N/C)
87 BIST RAM24 (N/C)
48 TSA2 (N/C)
88 D0
49 TSA3 (N/C)
89 D1
50 TMA0 (N/C)
90 D2
51 TMA1 (N/C)
91 D3
52 TMA2 (N/C)
92 D4
53 TMA3 (N/C)
93 D5
54 TMA4 (N/C)
94 D6
55 TMA5 (N/C)
95 D7
56 TMA6 (N/C)
96 GND
57 TMA7 (N/C)
97 +5V
58 TSB0 (N/C)
98 GND
59 TSB1 (N/C)
99 +5V
60 +5V
100 D8
61 GND
101 D9
62 TMB0 (N/C)
D10
63 TMB1 (N/C)
103 D11
64 TMB2 (N/C)
104 D12
65 TMB3 (N/C)
105 D13
66 TMB4 (N/C)
106 D14
67 TMB5 (N/C)
107 D15
68 TMB6 (N/C)
108 GND
69 TMB7 (N/C)
109 GND
70 ZERO WAIT MODE
110 IRQ3
71 READY
111 IRQ2
72 RD or DS
112 IRQ1
73 WR or RD/ WR
113 RESET RC
74 DTACK
114 ARINC CLK OUT
75 ERROR
115 ARINC CLK 1
76 MASTER RESET
116 ARINC CLK 0
77 +5V
117 BIST R0 (N/C)
78 BIST TOA (N/C)
118 BIST R1 (N/C)
79 BIST TOB (N/C)
119 BIST R2 (N/C)
80 GND
120 GND
PIN NO. 1
INDEX
1.102 ±0.004
(27.99 ±0.1 )
39 EQ. SP. @
0.0256 = 0.998
(0.65 = 25.36)
(TOL. NONCUM)
1 PIN NUMBERS
FOR REF. ONLY
160
1
121
120
39 EQ. SP. @
0.0256 = 0.998
(0.65 = 25.36)
(TOL. NONCUM)
DD-00429FP
1.102 ±0.004
(27.99 ±0.1 )
1
0.0256
(.65)
(TYP)
0.012 ±0.003
(0.3 ±0.08 )
(TYP)
40 81
41 80
PIN NO.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
DESCRIPTION
+5V
RESET 1
CW STRB1
EN TX1 OUT
TX1 B IN
TX1 A IN
TX1 EMPTY
LD TX1 HI
LD TX1 LOW
+5V
GND
+5V
16 MHZ CLOCK
EN RX3
EN RX2
RX RDY 3
RX RDY 2
+5V
GND
RESET 0
CW STRB0
EN TX0 OUT
TX0B IN
TX0A IN
TX0 EMPTY
LOAD TX0 HI
LD TX0 LOW
GND
TX DB0
TX DB1
TX DB2
TX DB3
TX DB4
TX DB5
TX DB6
TX DB7
TX DB8
TX DB9
TX DB10
GND
0.133 (3.38)
(REF)
0.013 +0.000
(0.33) -0.003
SEE DETAIL "A"
0.077(1.96)
(TYP)
1.256 ±0.01
(31.9) (TYP)
0.146 +0.008
(3.71) -0.000
DETAIL "A"
NTS
0.031(.79)
(TYP)
0.016 (0.41)
(MIN) (TYP)
0.007 ±0.002
(0.18) (TYP)
Notes:
1 LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN ±0.010 (±0.25).
2. DIMENSIONS IN INCHES (MILLIMETERS).
FIGURE 3. DD-00429FP ASIC MECHANICAL OUTLINE (160-PIN PQFP)
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ARINC 429 Microprocessor Interface

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ORDERING INFORMATION
Chip Set:
DD-00429XP - X00
Temperature Range:
2 = -40 - +85°C
ASIC Package Type:
P = Plastic
Lead Type:
F = 160-Pin Quad Flat Pack
V = 144-Pin TQFP
Note: The Line Drivers AND Transceivers are required to complete the ARINC
429 Interface (see additional ordering information). The DD-00429 is only the
Microprocessor Interface/RAM/FIFO and Interrupt Controller.
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
G1 web-09/02-0
105 Wilbur Place, Bohemia, New York 11716-2482
For Technical Support - 1-800-DDC-5757 ext. 7677 or 7381
Headquarters - Tel: (631) 567-5600 ext. 7420, Fax: (631) 567-7358
Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610
West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
Ireland - Tel: +353-21-341065, Fax: +353-21-341568
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
8
U
®
STERED
DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NO. A5976
PRINTED IN THE U.S.A.




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