74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT190
Presettable synchronous BCD
decade up/down counter
Product specification
File under Integrated Circuits, IC06
December 1990


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT190
FEATURES
Synchronous reversible counting
Asynchronous parallel load
Count enable control for synchronous expansion
Single up/down control input
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT190 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT190 are asynchronously presettable
up/down BCD decade counters. They contain four
master/slave flip-flops with internal gating and steering
logic to provide asynchronous preset and synchronous
count-up and count-down operation.
Asynchronous parallel load capability permits the counter
to be preset to any desired number. Information present on
the parallel data inputs (D0 to D3) is loaded into the counter
and appears on the outputs when the parallel load (PL)
input is LOW. As indicated in the function table, this
operation overrides the counting function.
Counting is inhibited by a HIGH level on the count enable
(CE) input. When CE is LOW internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input. The up/down (U/D) input signal determines
the direction of counting as indicated in the function table.
The CE input may go LOW when the clock is in either
state, however, the LOW-to-HIGH CE transition must
occur only when the clock is HIGH. Also, the U/D input
should be changed only when either CE or CP is HIGH.
Overflow/underflow indications are provided by two types
of outputs, the terminal count (TC) and ripple clock (RC).
The TC output is normally LOW and goes HIGH when a
circuit reaches zero in the count-down mode or reaches “9”
in the count-up-mode. The TC output will remain HIGH
until a state change occurs, either by counting or
presetting, or until U/D is changed. Do not use the TC
output as a clock signal because it is subject to decoding
spikes. The TC signal is used internally to enable the RC
output. When TC is HIGH and CE is LOW, the RC output
follows the clock pulse (CP). This feature simplifies the
design of multistage counters as shown in Figs 5 and 6.
In Fig.5, each RC output is used as the clock input to the
next higher stage. It is only necessary to inhibit the first
stage to prevent counting in all stages, since a HIGH on
CE inhibits the RC output pulse as indicated in the function
table. The timing skew between state changes in the first
and last stages is represented by the cumulative delay of
the clock as it ripples through the preceding stages. This
can be a disadvantage of this configuration in some
applications.
Fig.6 shows a method of causing state changes to occur
simultaneously in all stages. The RC outputs propagate
the carry/borrow signals in ripple fashion and all clock
inputs are driven in parallel. In this configuration the
duration of the clock LOW state must be long enough to
allow the negative-going edge of the carry/borrow signal to
ripple through to the last stage before the clock goes
HIGH. Since the RC output of any package goes HIGH
shortly after its CP input goes HIGH there is no such
restriction on the HIGH-state duration of the clock.
In Fig.7, the configuration shown avoids ripple delays and
their associated restrictions. Combining the TC signals
from all the preceding stages forms the CE input for a
given stage. An enable must be included in each carry
gate in order to inhibit counting. The TC output of a given
stage it not affected by its own CE signal therefore the
simple inhibit scheme of Figs 5 and 6 does not apply.
December 1990
2


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT190
QUICK REFERENCE DATA
GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay CP to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
TYPICAL
HC
22
28
3.5
36
HCT
24
30
3.5
38
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
3


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
PIN DESCRIPTION
PIN NO.
3, 2, 6, 7
4
5
8
11
12
13
14
15, 1, 10, 9
16
SYMBOL
Q0 to Q3
CE
U/D
GND
PL
TC
RC
CP
D0 to D3
VCC
NAME AND FUNCTION
flip-flop outputs
count enable input (active LOW)
up/down input
ground (0 V)
parallel load input (active LOW)
terminal count output
ripple clock output (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data inputs
positive supply voltage
Product specification
74HC/HCT190
Fig.1 Pin configuration.
Fig.2 Logic symbol.
December 1990
Fig.3 IEC logic symbol.
4


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT190
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
parallel load
count up
count down
hold (do nothing)
INPUTS
PL U/D CE CP
LX X X
LX X X
HL I
HH I
HX H X
OUTPUTS
Dn Qn
LL
HH
X count up
X count down
X no change
TC AND RC FUNCTION TABLE
INPUTS
U/D CE
HH
LH
LL
LH
HH
HL
CP
X
X
X
X
TERMINAL COUNT STATE
Q0 Q1
HX
HX
HX
Q2
X
X
X
Q3
H
H
H
LL
LL
LL
L
L
L
L
L
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
= LOW-to-HIGH CP transition
= one LOW level pulse
= TC goes LOW on a LOW-to-HIGH CP transition
OUTPUTS
TC RC
LH
HH
LH
HH
December 1990
5


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT190
Fig.5 N-stage ripple counter using ripple clock.
Fig.6 Synchronous n-stage counter using ripple carry/borrow.
December 1990
Fig.7 Synchronous n-stage counter with parallel gated carry/borrow.
6


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT190
Sequence
Load (present) to BCD seven;
count up to eight, nine, zero,
one and two;
inhibit;
count down to one, zero, nine,
eight and seven.
Fig.8 Typical load, count and inhibit sequence.
December 1990
Fig.9 Logic diagram.
7


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT190
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HC
+25
40 TO +85
UNIT
40 TO +125
VCC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
tPHL/ tPLH propagation delay
CP to TC
72 220
26 44
21 37
83 255
30 51
24 43
275
55
47
320
64
54
330 ns
66
56
385 ns
77
65
2.0 Fig.10
4.5
6.0
2.0 Fig.10
4.5
6.0
tPHL/ tPLH propagation delay
CP to RC
44 150
16 30
13 26
190
38
33
225 ns
45
38
2.0 Fig.11
4.5
6.0
tPHL/ tPLH propagation delay
CE to RC
tPHL/ tPLH propagation delay
Dn to Qn
33 130
12 26
10 22
63 220
23 44
18 37
165
33
28
275
55
47
195 ns
39
33
330 ns
66
56
2.0 Fig.11
4.5
6.0
2.0 Fig.12
4.5
6.0
tPHL/ tPLH propagation delay
PL to Qn
63 220
23 44
18 37
275
55
47
330 ns
66
56
2.0 Fig.13
4.5
6.0
tPHL/ tPLH propagation delay
U/D to TC
tPHL/ tPLH propagation delay
U/D to RC
44 190
16 38
13 32
50 210
18 42
14 36
240
48
41
265
53
45
285 ns
57
48
315 ns
63
54
2.0 Fig.14
4.5
6.0
2.0 Fig.14
4.5
6.0
tTHL/ tTLH output transition time
19 75
7 15
6 13
95
19
16
110 ns
22
19
2.0 Fig.15
4.5
6.0
tW clock pulse width 155 28
HIGH or LOW
31 10
26 8
tW parallel load pulse width 100 25
LOW
20 9
17 7
195 235 ns 2.0 Fig.10
39 47
4.5
33 40
6.0
125 150 ns 2.0 Fig.15
25 30
4.5
21 26
6.0
December 1990
8


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT190
SYMBOL PARAMETER
trem removal time
PL to CP
tsu set-up time
U/D to CP
tsu set-up time
Dn to PL
tsu set-up time
CE to CP
th hold time
U/D to CP
th hold time
Dn to PL
th hold time
CE to CP
fmax maximum clock pulse
frequency
Tamb (°C)
TEST CONDITIONS
74HC
+25
40 TO +85
UNIT
40 TO +125
VCC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
35 8
73
62
45 55 ns 2.0 Fig.15
9 11
4.5
89
6.0
205 61
41 22
35 18
255 310 ns 2.0 Fig.17
51 62
4.5
43 53
6.0
100 19
20 7
17 6
125 150 ns 2.0 Fig.16
25 30
4.5
21 26
6.0
140 39
28 14
24 11
175 210 ns 2.0 Fig.17
35 42
4.5
30 36
6.0
0 44
0
0
ns 2.0 Fig.17
0 16
0
0
4.5
0 13
0
0
6.0
0 14
0
0
ns 2.0 Fig.16
0 5
0
0
4.5
0 4
0
0
6.0
0 19
0
0
ns 2.0 Fig.17
0 7
0
0
4.5
0 6
0
0
6.0
3.0 8.3
2.4
2.0
MHz 2.0 Fig.10
15 25 12 10
4.5
18 30 14 12
6.0
December 1990
9


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT190
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
Dn
CP
U/D
CE, PL
UNIT LOAD COEFFICIENT
0.5
0.65
1.15
1.5
December 1990
10


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT190
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HCT
+25
40 to +85
40 to +125
UNIT
VCC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tTHL/ tTLH
propagation delay
CP to Qn
propagation delay
CP to TC
propagation delay
CP to RC
propagation delay
CE to RC
propagation delay
Dn to Qn
propagation delay
PL to Qn
propagation delay
U/D to TC
propagation delay
U/D to RC
output transition time
28 48
34 58
20 35
18 33
24 44
29 49
24 45
26 45
7 15
60
73
44
41
55
61
56
56
19
72 ns 4.5 Fig.10
87 ns 4.5 Fig.10
53 ns 4.5 Fig.11
50 ns 4.5 Fig.11
66 ns 4.5 Fig.12
74 ns 4.5 Fig.13
68 ns 4.5 Fig.14
68 ns 4.5 Fig.14
22 ns 4.5 Fig.15
tW clock pulse width 25 10
31
38
ns 4.5 Fig.10
HIGH or LOW
tW parallel load pulse width 22 12
28
33
ns 4.5 Fig.15
LOW
trem removal time 7 1 9 11 ns 4.5 Fig.15
PL to CP
tsu set-up time
U/D to CP
42 25
53
63
ns 4.5 Fig.17
tsu set-up time
Dn to PL
tsu set-up time
CE to CP
20 10
25
30
ns 4.5 Fig.16
31 18
39
47
ns 4.5 Fig.17
th hold time
U/D to CP
0 18
0
0
ns 4.5 Fig.17
th hold time
Dn to PL
th hold time
CE to CP
0 6
0
0
ns 4.5 Fig.16
0 10
0
0
ns 4.5 Fig.17
fmax maximum clock pulse 16 27 13 11
frequency
MHz 4.5 Fig.10
December 1990
11


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
AC WAVEFORMS
Product specification
74HC/HCT190
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the clock (CP) to
output (Qn) propagation delays, the clock
pulse width and the maximum clock pulse
frequency.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the clock and count
enable inputs (CP, CE) to ripple clock
output (RC) propagation delays.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing the input (Dn) to output
(Qn) propagation delays.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.13 Waveforms showing the input (PL) to output
(Qn) propagation delays.
(1) HC :
VM = 50%;
VI = GND to
VCC.
HCT :
VM = 1.3 V;
VI = GND to
3 V.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing the up/down count
input (U/D) to terminal count and ripple
clock output (TC, RC) propagation delays.
Fig.15 Waveforms showing the parallel load input
(PL) pulse width, removal time to clock (CP)
and the output (Qn) transition times.
December 1990
12


74HC190 (Philips)
Presettable synchronous BCD decade up/down counter

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Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT190
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.16 Waveforms showing the set-up and hold times from the parallel load input (PL) to the data input (Dn).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the
clock (CP).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
13




74HC190.pdf
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