74HC03 (Philips)
Quad 2-input NAND gate

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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT03
Quad 2-input NAND gate
Product specification
File under Integrated Circuits, IC06
December 1990


74HC03 (Philips)
Quad 2-input NAND gate

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Philips Semiconductors
Quad 2-input NAND gate
Product specification
74HC/HCT03
FEATURES
Level shift capability
Output capability: standard (open drain)
ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT03 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT03 provide the 2-input NAND function.
The 74HC/HCT03 have open-drain N-transistor outputs,
which are not clamped by a diode connected to VCC. In
the OFF-state, i.e. when one input is LOW, the output
may be pulled to any voltage between GND and VOmax.
This allows the device to be used as a LOW-to-HIGH or
HIGH-to-LOW level shifter. For digital operation and
OR-tied output applications, these devices must have a
pull-up resistor to establish a logic HIGH level.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
tPZL/ tPLZ
CI
CPD
PARAMETER
propagation delay
input capacitance
power dissipation capacitance per gate
CONDITIONS
TYPICAL
HC HCT
CL = 15 pF; RL = 1 k; VCC = 5 V 8
3.5
10
3.5
notes 1, 2 and 3
4.0 4.0
UNIT
ns
pF
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2× fi + (CL × VCC2 × fo) + (VO2/RL) × duty factor LOW, where:
fi = input frequency in MHz
fo = output frequency in MHz
VO = output voltage in V
CL = output load capacitance in pF
VCC = supply voltage in V
RL = pull-up resistor in M
(CL × VCC2 × fo) = sum of outputs
(VO2/RL) = sum of outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
3. The given value of CPD is obtained with:
CL = 0 pF and RL =
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2


74HC03 (Philips)
Quad 2-input NAND gate

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Philips Semiconductors
Quad 2-input NAND gate
PIN DESCRIPTION
PIN NO.
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
NAME AND FUNCTION
data inputs
data inputs
data outputs
ground (0 V)
positive supply voltage
Product specification
74HC/HCT03
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUTS
OUTPUT
nA nB
LL
LH
HL
HH
nY
Z
Z
Z
L
Note
1. H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
Fig.4 Functional diagram.
December 1990
Fig.5 Logic diagram (one gate).
3


74HC03 (Philips)
Quad 2-input NAND gate

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Philips Semiconductors
Quad 2-input NAND gate
Product specification
74HC/HCT03
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
VCC
VO
IIK
IOK
IO
PARAMETER
DC supply voltage
DC output voltage
DC input diode current
DC output diode current
DC output sink current
MIN.
0.5
0.5
MAX.
+7
+7
20
20
25
UNIT
V
V
mA
mA
mA
CONDITIONS
for VI < −0.5 V or VI > VCC + 0.5 V
for VO < −0.5 V
for 0.5 V < VO
±ICC;
±IGND
Tstg
Ptot
DC VCC or GND current
50 mA
storage temperature range 65
power dissipation per package
plastic DIL
plastic mini-pack (SO)
+150 °C
750 mW
500 mW
for temperature range; 40 to +125 °C
74HC/HCT
above +70 °C: derate linearly with 12 mW/K
above +70 °C: derate linearly with 8 mW/K
December 1990
4


74HC03 (Philips)
Quad 2-input NAND gate

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Philips Semiconductors
Quad 2-input NAND gate
Product specification
74HC/HCT03
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that the VOH values are
not valid for open drain. They are replaced by IOZ as given below.
Output capability: standard (open drain), excepting VOH
ICC category: SSI
Voltages are referenced to GND (ground = 0 V)
SYMBOL
IOZ
PARAMETER
HIGH level output
leakage current
min.
+25
typ.
Tamb (°C)
74HC
40 to +85 40 to +125
max. min. max. min. max.
0.5 5.0 10.0
TEST CONDITIONS
UNIT VCC VI OTHER
(V)
2.0 VO = VO(max)(1)
µA to VIL or GND
6.0
Note
1. The maximum operating output voltage (VO(max)) is 6.0 V.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
SYMBOL PARAMETER
74HC
+25 40 to +85
min. typ. max. min. max.
tPZL/
tPLZ
tTHL
propagation delay
nA, nB to nY
output transition time
28 95
10 19
8 16
19 75
7 15
6 13
120
24
20
95
19
16
TEST CONDITIONS
40 to +125
UNIT VCC WAVEFORMS
(V)
min. max.
145
29 ns
25
2.0 Fig.6
4.5
6.0
110 ns
22
19
2.0
4.5 Fig.6
6.0
December 1990
5


74HC03 (Philips)
Quad 2-input NAND gate

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Philips Semiconductors
Quad 2-input NAND gate
Product specification
74HC/HCT03
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that the VOH values are
not valid for open drain. They are replaced by IOZ as given below.
Output capability: standard (open drain), excepting VOH
ICC category: SSI
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER
Tamb (°C)
74HCT
+25 40 to +85
min. typ. max. min. max.
IOZ
HIGH level output
leakage current
0.5 5.0
TEST CONDITIONS
40 to +125
UNIT
VCC
(V)
VI
min. max.
OTHER
10.0 µA
4.5
to
5.5
VIL
VO = VO(max)(1)
or GND
Note
1. The maximum operating output voltage (VO(max)) is 6.0 V.
Note to HCT types
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
nA, nB
UNIT LOAD COEFFICIENT
1.0
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
SYMBOL PARAMETER
74HCT
+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
tPZL/ tPLZ propagation delay
nA, nB, to nY
12 24
30
36
tTHL output transition time
7 15
19
22
UNIT
ns
ns
TEST CONDITIONS
VCC WAVEFORMS
(V)
4.5 Fig.6
4.5 Fig.6
December 1990
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74HC03 (Philips)
Quad 2-input NAND gate

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Philips Semiconductors
Quad 2-input NAND gate
AC WAVEFORMS
Product specification
74HC/HCT03
HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.
TEST CIRCUIT AND WAVEFORMS
Fig.7 Test circuit (open drain)
Fig.8 Input pulse definitions.
Definitions for Figs. 7, 8:
CL = load capacitance including jig and probe
capacitance
(see AC CHARACTERISTICS for values).
RT = termination resistance should be equal to the
output impedance ZO of the pulse generator.
tr = tf = 6 ns; when measuring fmax, there is no
constraint on tr, tf with 50% duty factor.
FAMILY AMPLITUDE
74HC VCC
74HCT 3.0 V
VM
50%
1.3 V
tr; tf
fmax;
PULSE
WIDTH
OTHER
< 2 ns
6 ns
< 2 ns
6 ns
December 1990
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74HC03 (Philips)
Quad 2-input NAND gate

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Philips Semiconductors
Quad 2-input NAND gate
APPLICATION INFORMATION
Product specification
74HC/HCT03
(1) RON(max) = 0.26 V / 4 mA = 65 (at 25 °C)
(a)
Fig.9 Pull-up configuration.
(b)
(1) VCC (R) = 2.0 V; VIL = 0.5 V.
(2) VCC (R) = 5.0 V; VIL = 0.8 V.
(3) VCC (R) = 4.5 V; VIL = 1.35 V.
(4) VCC (R) = 6.0 V; VIL = 1.8 V.
Fig.10 Minimum resistive load as a function of the pull-up voltage.
Notes to Figs 9 and 10
If VP VCC (R) > 0.5 V a positive current will flow into the receiver (as described in the “USER GUIDE”; input/output
protection), this will not affect the receiver provided the current does not exceed 20 mA. At VCC < 4.5 V, RON (max) is not
guaranteed; RON(max) can be estimated using Figs 33 and 34 in the “USER GUIDE”.
Note to Application information
All values given are typical unless otherwise specified.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
8




74HC03.pdf
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