80L186EB (Intel Corporation)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

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80C186EB 80C188EB AND 80L186EB 80L188EB
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
X Full Static Operation
X True CMOS Inputs and Outputs
Y Integrated Feature Set
Low-Power Static CPU Core
Two Independent UARTs each with
an Integral Baud Rate Generator
Two 8-Bit Multiplexed I O Ports
Programmable Interrupt Controller
Three Programmable 16-Bit
Timer Counters
Clock Generator
Ten Programmable Chip Selects with
Integral Wait-State Generator
Memory Refresh Control Unit
System Level Testing Support (ONCE
Mode)
Y Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I O
Y Speed Versions Available (5V)
25 MHz (80C186EB25 80C188EB25)
20 MHz (80C186EB20 80C188EB20)
13 MHz (80C186EB13 80C188EB13)
Y Available in Extended Temperature
Range (b40 C to a85 C)
Y Speed Versions Available (3V)
16 MHz (80L186EB16 80L188EB16)
13 MHz (80L186EB13 80L188EB13)
Y Low-Power Operating Modes
Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
Powerdown Mode Freezes All
Internal Clocks
Y Supports 80C187 Numeric Coprocessor
Interface (80C186EB PLCC Only)
Y Available In
80-Pin Quad Flat Pack (QFP)
84-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin Shrink Quad Flat Pack (SQFP)
The 80C186EB is a second generation CHMOS High-Integration microprocessor It has features that are new
to the 80C186 family and include a STATIC CPU core an enhanced Chip Select decode unit two independent
Serial Channels I O ports and the capability of Idle or Powerdown low power modes
272433 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
June, 2002
Order Number: 272433-005
COPYRIGHT © INTEL CORPORATION, 2002


80L186EB (Intel Corporation)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

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80C186EB 80C188EB and 80L186EB 80L188EB
16-Bit High-Integration Embedded Processors
CONTENTS
INTRODUCTION
CORE ARCHITECTURE
Bus Interface Unit
Clock Generator
80C186EC PERIPHERAL
ARCHITECTURE
Interrupt Control Unit
Timer Counter Unit
Serial Communications Unit
Chip-Select Unit
I O Port Unit
Refresh Control Unit
Power Management Unit
80C187 Interface (80C186EB Only)
ONCE Test Mode
PACKAGE INFORMATION
Prefix Identification
Pin Descriptions
80C186EB PINOUT
PACKAGE THERMAL
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PAGE
4
4
4
4
5
5
5
7
7
7
7
7
7
7
8
8
8
14
22
23
23
CONTENTS
Recommended Connections
PAGE
23
DC SPECIFICATIONS
ICC versus Frequency and Voltage
PDTMR Pin Delay Calculation
24
27
27
AC SPECIFICATIONS
AC Characteristics 80C186EB25
AC Characteristics 80C186EB20 13
AC Characteristics 80L186EB16
Relative Timings
Serial Port Mode 0 Timings
28
28
30
32
36
37
AC TEST CONDITIONS
38
AC TIMING WAVEFORMS
38
DERATING CURVES
41
RESET
42
BUS CYCLE WAVEFORMS
45
EXECUTION TIMINGS
52
INSTRUCTION SET SUMMARY
53
ERRATA
59
REVISION HISTORY
59
2


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16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

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80C186EB 80C188EB 80L186EB 80L188EB
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
Figure 1 80C186EB 80C188EB Block Diagram
272433 – 2
3


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80C186EB 80C188EB 80L186EB 80L188EB
INTRODUCTION
Unless specifically noted all references to the
80C186EB apply to the 80C188EB 80L186EB and
80L188EB References to pins that differ between
the 80C186EB 80L186EB and the 80C188EB
80L188EB are given in parentheses The ‘‘L’’ in the
part number denotes low voltage operation Physi-
cally and functionally the ‘‘C’’ and ‘‘L’’ devices are
identical
The 80C186EB is the first product in a new genera-
tion of low-power high-integration microprocessors
It enhances the existing 186 family by offering new
features and new operating modes The 80C186EB
is object code compatible with the 80C186XL
80C188XL microprocessors
The 80L186EB is the 3V version of the 80C186EB
The 80L186EB is functionally identical to the
80C186EB embedded processor Current
80C186EB users can easily upgrade their designs to
use the 80L186EB and benefit from the reduced
power consumption inherent in 3V operation
The feature set of the 80C186EB meets the needs
of low power space critical applications Low-Power
applications benefit from the static design of the
CPU core and the integrated peripherals as well as
low voltage operation Minimum current consump-
tion is achieved by providing a Powerdown mode
that halts operation of the device and freezes the
clock circuits Peripheral design enhancements en-
sure that non-initialized peripherals consume little
current
Space critical applications benefit from the inte-
gration of commonly used system peripherals Two
serial channels are provided for services such as
diagnostics inter-processor communication modem
interface terminal display interface and many oth-
ers A flexible chip select unit simplifies memory and
peripheral interfacing The interrupt unit provides
sources for up to 129 external interrupts and will pri-
oritize these interrupts with those generated from
the on-chip peripherals Three general purpose tim-
er counters and sixteen multiplexed I O port pins
round out the feature set of the 80C186EB
Figure 1 shows a block diagram of the 80C186EB
80C188EB The Execution Unit (EU) is an enhanced
8086 CPU core that includes dedicated hardware to
speed up effective address calculations enhance
execution speed for multiple-bit shift and rotate in-
structions and for multiply and divide instructions
string move instructions that operate at full bus
bandwidth ten new instruction and fully static oper-
ation The Bus Interface Unit (BIU) is the same as
that found on the original 186 family products ex-
cept the queue status mode has been deleted and
buffer interface control has been changed to ease
system design timings An independent internal bus
is used to allow communication between the BIU
and internal peripherals
CORE ARCHITECTURE
Bus Interface Unit
The 80C186EB core incorporates a bus controller
that generates local bus control signals In addition
it employs a HOLD HLDA protocol to share the local
bus with other bus masters
The bus controller is responsible for generating 20
bits of address read and write strobes bus cycle
status information and data (for write operations) in-
formation It is also responsible for reading data off
the local bus during a read operation A READY in-
put pin is provided to extend a bus cycle beyond the
minimum four states (clocks)
The local bus controller also generates two control
signals (DEN and DT R) when interfacing to exter-
nal transceiver chips (Both DEN and DT R are
available on the PLCC devices only DEN is avail-
able on the QFP and SQFP devices ) This capability
allows the addition of transceivers for simple buffer-
ing of the multiplexed address data bus
Clock Generator
The processor provides an on-chip clock generator
for both internal and external clock generation The
clock generator features a crystal oscillator a divide-
by-two counter and two low-power operating
modes
The oscillator circuit is designed to be used with ei-
ther a parallel resonant fundamental or third-over-
tone mode crystal network Alternatively the oscilla-
tor circuit may be driven from an external clock
source Figure 2 shows the various operating modes
of the oscillator circuit
The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide-by-two counter This counter is
used to drive all internal phase clocks and the exter-
nal CLKOUT signal CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys-
tem components All AC timings are referenced to
CLKOUT
4


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80C186EB 80C188EB 80L186EB 80L188EB
272433 – 4
272433 – 3
(A) Crystal Connection
(B) Clock Connection
NOTE
The L1C1 network is only required when using a third-
overtone crystal
Figure 2 Clock Configurations
The following parameters are recommended when
choosing a crystal
Temperature Range
Application Specific
ESR (Equivalent Series Resistance)
40X max
C0 (Shunt Capacitance of Crystal)
7 0 pF max
CL (Load Capacitance)
Drive Level
20 pF g 2 pF
1 mW max
80C186EB PERIPHERAL
ARCHITECTURE
The 80C186EB has integrated several common sys-
tem peripherals with a CPU core to create a com-
pact yet powerful system The integrated peripher-
als are designed to be flexible and provide logical
interconnections between supporting units (e g the
interrupt control unit supports interrupt requests
from the timer counters or serial channels)
The list of integrated peripherals includes
 7-Input Interrupt Control Unit
 3-Channel Timer Counter Unit
 2-Channel Serial Communications Unit
 10-Output Chip-Select Unit
 I O Port Unit
 Refresh Control Unit
 Power Management Unit
The registers associated with each integrated peri-
heral are contained within a 128 x 16 register file
called the Peripheral Control Block (PCB) The PCB
can be located in either memory or I O space on
any 256 Byte address boundary
Figure 3 provides a list of the registers associated
with the PCB The Register Bit Summary at the end
of this specification individually lists all of the regis-
ters and identifies each of their programming attri-
butes
Interrupt Control Unit
The 80C186EB can receive interrupts from a num-
ber of sources both internal and external The inter-
rupt control unit serves to merge these requests on
a priority basis for individual service by the CPU
Each interrupt source can be independently masked
by the Interrupt Control Unit (ICU) or all interrupts
can be globally masked by the CPU
Internal interrupt sources include the Timers and Se-
rial channel 0 External interrupt sources come from
the five input pins INT4 0 The NMI interrupt pin is
not controlled by the ICU and is passed directly to
the CPU Although the Timer and Serial channel
each have only one request input to the ICU sepa-
rate vector types are generated to service individual
interrupts within the Timer and Serial channel units
Timer Counter Unit
The 80C186EB Timer Counter Unit (TCU) provides
three 16-bit programmable timers Two of these are
highly flexible and are connected to external pins for
control or clocking A third timer is not connected to
any external pins and can only be clocked internally
However it can be used to clock the other two timer
channels The TCU can be used to count external
events time external events generate non-repeti-
tive waveforms generate timed interrupts etc
5


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80C186EB 80C188EB 80L186EB 80L188EB
PCB
Offset
Function
00H Reserved
02H End Of Interrupt
04H Poll
06H Poll Status
08H Interrupt Mask
0AH Priority Mask
0CH
In-Service
0EH Interrupt Request
10H Interrupt Status
12H Timer Control
14H Serial Control
16H INT4 Control
18H INT0 Control
1AH INT1 Control
1CH INT2 Control
1EH INT3 Control
20H Reserved
22H Reserved
24H Reserved
26H Reserved
28H Reserved
2AH
Reserved
2CH
Reserved
2EH
Reserved
30H Timer0 Count
32H Timer0 Compare A
34H Timer0 Compare B
36H Timer0 Control
38H Timer1 Count
3AH Timer1 Compare A
3CH Timer1 Compare B
3EH Timer1 Control
PCB
Offset
Function
PCB
Offset
Function
40H Timer2 Count
80H GCS0 Start
42H Timer2 Compare 82H GCS0 Stop
44H Reserved
84H GCS1 Start
46H Timer2 Control
86H GCS1 Stop
48H Reserved
88H GCS2 Start
4AH
Reserved
8AH
GCS2 Stop
4CH
Reserved
8CH GCS3 Start
4EH
Reserved
8EH
GCS3 Stop
50H Port 1 Direction
90H GCS4 Start
52H Port 1 Pin
92H GCS4 Stop
54H Port 1 Control
94H GCS5 Start
56H Port 1 Latch
96H GCS5 Stop
58H Port 2 Direction
98H GCS6 Start
5AH
Port 2 Pin
9AH
GCS6 Stop
5CH Port 2 Control
9CH GCS7 Start
5EH Port 2 Latch
9EH
GCS7 Stop
60H Serial0 Baud
A0H
LCS Start
62H Serial0 Count
A2H
LCS Stop
64H Serial0 Control
A4H
UCS Start
66H Serial0 Status
A6H
UCS Stop
68H Serial0 RBUF
A8H
Relocation
6AH Serial0 TBUF
AAH
Reserved
6CH
Reserved
ACH
Reserved
6EH
Reserved
AEH
Reserved
70H Serial1 Baud
B0H Refresh Base
72H Serial1 Count
B2H Refresh Time
74H Serial1 Control
B4H Refresh Control
76H Serial1 Status
B6H
Reserved
78H Serial1 RBUF
B8H Power Control
7AH Serial1 TBUF
BAH
Reserved
7CH
Reserved
BCH
Step ID
7EH
Reserved
BEH
Reserved
Figure 3 Peripheral Control Block Registers
PCB
Offset
C0H
C2H
C4H
C6H
C8H
CAH
CCH
CEH
D0H
D2H
D4H
D6H
D8H
DAH
DCH
DEH
E0H
E2H
E4H
E6H
E8H
EAH
ECH
EEH
F0H
F2H
F4H
F6H
F8H
FAH
FCH
FEH
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6


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80C186EB 80C188EB 80L186EB 80L188EB
Serial Communications Unit
The Serial Control Unit (SCU) of the 80C186EB con-
tains two independent channels Each channel is
identical in operation except that only channel 0 is
supported by the integrated interrupt controller
(channel 1 has an external interrupt pin) Each
channel has its own baud rate generator that is in-
dependent of the Timer Counter Unit and can be
internally or externally clocked at up to one half the
80C186EB operating frequency
Independent baud rate generators are provided for
each of the serial channels For the asynchronous
modes the generator supplies an 8x baud clock to
both the receive and transmit register logic A 1x
baud clock is provided in the synchronous mode
Chip-Select Unit
The 80C186EB Chip-Select Unit (CSU) integrates
logic which provides up to ten programmable chip-
selects to access both memories and peripherals In
addition each chip-select can be programmed to
automatically insert additional clocks (wait-states)
into the current bus cycle and automatically termi-
nate a bus cycle independent of the condition of the
READY input pin
I O Port Unit
The I O Port Unit (IPU) on the 80C186EB supports
two 8-bit channels of input output or input output
operation Port 1 is multiplexed with the chip select
pins and is output only Most of Port 2 is multiplexed
with the serial channel pins Port 2 pins are limited to
either an output or input function depending on the
operation of the serial pin it is multiplexed with
Refresh Control Unit
The Refresh Control Unit (RCU) automatically gen-
erates a periodic memory read bus cycle to keep
dynamic or pseudo-static memory refreshed A 9-bit
counter controls the number of clocks between re-
fresh requests
A 12-bit address generator is maintained by the RCU
and is presented on the A12 1 address lines during
the refresh bus cycle Address bits A19 13 are pro-
grammable to allow the refresh address block to be
located on any 8 Kbyte boundary
Power Management Unit
The 80C186EB Power Management Unit (PMU) is
provided to control the power consumption of the
device The PMU provides three power modes Ac-
tive Idle and Powerdown
Active Mode indicates that all units on the
80C186EB are functional and the device consumes
maximum power (depending on the level of periph-
eral operation) Idle Mode freezes the clocks of the
Execution and Bus units at a logic zero state (all
peripherals continue to operate normally)
The Powerdown mode freezes all internal clocks at
a logic zero level and disables the crystal oscillator
All internal registers hold their values provided VCC
is maintained Current consumption is reduced to
just transistor junction leakage
80C187 Interface (80C186EB Only)
The 80C186EB (PLCC package only) supports the
direct connection of the 80C187 Numerics Coproc-
essor
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system the 80C186EB has a test
mode available which forces all output and input
output pins to be placed in the high-impedance
state ONCE stands for ‘‘ON Circuit Emulation’’ The
ONCE mode is selected by forcing the A19 ONCE
pin LOW (0) during a processor reset (this pin is
weakly held to a HIGH (1) level) while RESIN is ac-
tive
7


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80C186EB 80C188EB 80L186EB 80L188EB
PACKAGE INFORMATION
This section describes the pins pinouts and thermal
characteristics for the 80C186EB in the Plastic
Leaded Chip Carrier (PLCC) package Shrink Quad
Flat Pack (SQFP) and Quad Flat Pack (QFP) pack-
age For complete package specifications and infor-
mation see the Intel Packaging Outlines and Dimen-
sions Guide (Order Number 231369)
Prefix Identification
With the extended temperature range operational
characteristics are guaranteed over the temperature
range corresponding to b40 C to a85 C ambient
Package types are identified by a two-letter prefix to
the part number The prefixes are listed in Table 1
Table 1 Prefix Identification
Prefix Note
Package
Type
Temperature
Type
TN
PLCC
Extended
TS QFP (EIAJ) Extended
SB 1 SQFP
Extended Commercial
N 1 PLCC
Commercial
S 1 QFP (EIAJ) Commercial
NOTE
1 The 5V 25 MHz and 3V 16 MHz versions are only avail-
able in commercial temperature range corresponding to
0 C to a70 C ambient
Pin Descriptions
Each pin or logical set of pins is described in Table
3 There are three columns for each entry in the Pin
Description Table
The Pin Name column contains a mnemonic that
describes the pin function Negation of the signal
name (for example RESIN) denotes a signal that is
active low
The Pin Type column contains two kinds of informa-
tion The first symbol indicates whether a pin is pow-
er (P) ground (G) input only (I) output only (O) or
input output (I O) Some pins have multiplexed
functions (for example A19 S6) Additional symbols
indicate additional characteristics for each pin Table
2 lists all the possible symbols for this column
The Input Type column indicates the type of input
(Asynchronous or Synchronous)
Asynchronous pins require that setup and hold times
be met only in order to guarantee recognition at a
particular clock edge Synchronous pins require that
setup and hold times be met to guarantee proper
operation For example missing the setup or hold
time for the SRDY pin (a synchronous input) will re-
sult in a system failure or lockup Input pins may also
be edge- or level-sensitive The possible character-
istics for input pins are S(E) S(L) A(E) and A(L)
The Output States column indicates the output
state as a function of the device operating mode
Output states are dependent upon the current activi-
ty of the processor There are four operational
states that are different from regular operation bus
hold reset Idle Mode and Powerdown Mode Ap-
propriate characteristics for these states are also in-
dicated in this column with the legend for all possi-
ble characteristics in Table 2
The Pin Description column contains a text de-
scription of each pin
As an example consider AD15 0 I O signifies the
pins are bidirectional S(L) signifies that the input
function is synchronous and level-sensitive H(Z)
signifies that as outputs the pins are high-imped-
ance upon acknowledgement of bus hold R(Z) sig-
nifies that the pins float during reset P(X) signifies
that the pins retain their states during Powerdown
Mode
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Symbol
P
G
I
O
IO
S(E)
S(L)
A(E)
A(L)
H(1)
H(0)
H(Z)
H(Q)
H(X)
R(WH)
R(1)
R(0)
R(Z)
R(Q)
R(X)
I(1)
I(0)
I(Z)
I(Q)
I(X)
P(1)
P(0)
P(Z)
P(Q)
P(X)
80C186EB 80C188EB 80L186EB 80L188EB
Table 2 Pin Description Nomenclature
Description
Power Pin (Apply aVCC Voltage)
Ground (Connect to VSS)
Input Only Pin
Output Only Pin
Input Output Pin
Synchronous Edge Sensitive
Synchronous Level Sensitive
Asynchronous Edge Sensitive
Asynchronous Level Sensitive
Output Driven to VCC during Bus Hold
Output Driven to VSS during Bus Hold
Output Floats during Bus Hold
Output Remains Active during Bus Hold
Output Retains Current State during Bus Hold
Output Weakly Held at VCC during Reset
Output Driven to VCC during Reset
Output Driven to VSS during Reset
Output Floats during Reset
Output Remains Active during Reset
Output Retains Current State during Reset
Output Driven to VCC during Idle Mode
Output Driven to VSS during Idle Mode
Output Floats during Idle Mode
Output Remains Active during Idle Mode
Output Retains Current State during Idle Mode
Output Driven to VCC during Powerdown Mode
Output Driven to VSS during Powerdown Mode
Output Floats during Powerdown Mode
Output Remains Active during Powerdown Mode
Output Retains Current State during Powerdown Mode
9


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80C186EB 80C188EB 80L186EB 80L188EB
Pin
Name
VCC
VSS
CLKIN
OSCOUT
CLKOUT
RESIN
RESOUT
PDTMR
NMI
TEST BUSY
(TEST)
AD15 0
(AD7 0)
Pin
Type
P
G
I
O
O
I
O
IO
I
I
IO
Input
Type
A(E)
A(L)
A(L)
A(E)
A(E)
S(L)
Table 3 Pin Descriptions
Output
States
Description
POWER connections consist of four pins which must be
shorted externally to a VCC board plane
GROUND connections consist of six pins which must be
shorted externally to a VSS board plane
CLocK INput is an input for an external clock An external
oscillator operating at two times the required processor
operating frequency can be connected to CLKIN For crystal
operation CLKIN (along with OSCOUT) are the crystal
connections to an internal Pierce oscillator
H(Q)
R(Q)
P(Q)
OSCillator OUTput is only used when using a crystal to
generate the external clock OSCOUT (along with CLKIN)
are the crystal connections to an internal Pierce oscillator
This pin is not to be used as 2X clock output for non-crystal
applications (i e this pin is N C for non-crystal applications)
OSCOUT does not float in ONCE mode
H(Q)
R(Q)
P(Q)
CLocK OUTput provides a timing reference for inputs and
outputs of the processor and is one-half the input clock
(CLKIN) frequency CLKOUT has a 50% duty cycle and
transistions every falling edge of CLKIN
RESet IN causes the processor to immediately terminate
any bus cycle in progress and assume an initialized state All
pins will be driven to a known state and RESOUT will also
be driven active The rising edge (low-to-high) transition
synchronizes CLKOUT with CLKIN before the processor
begins fetching opcodes at memory location 0FFFF0H
H(0) RESet OUTput that indicates the processor is currently in
R(1) the reset state RESOUT will remain active as long as RESIN
P(0) remains active
H(WH)
R(Z)
P(1)
Power-Down TiMeR pin (normally connected to an external
capacitor) that determines the amount of time the processor
waits after an exit from power down before resuming normal
operation The duration of time required will depend on the
startup characteristics of the crystal oscillator
Non-Maskable Interrupt input causes a TYPE-2 interrupt to
be serviced by the CPU NMI is latched internally
TEST is used during the execution of the WAIT instruction to
suspend CPU operation until the pin is sampled active
(LOW) TEST is alternately known as BUSY when interfacing
with an 80C187 numerics coprocessor (80C186EB only)
H(Z)
R(Z)
P(X)
These pins provide a multiplexed Address and Data bus
During the address phase of the bus cycle address bits 0
through 15 (0 through 7 on the 80C188EB) are presented on
the bus and can be latched using ALE 8- or 16-bit data
information is transferred during the data phase of the bus
cycle
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
10


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80C186EB 80C188EB 80L186EB 80L188EB
Table 3 Pin Descriptions (Continued)
Pin
Name
Pin Input Output
Type Type States
Description
A18 16
A19 ONCE
(A15 A8)
(A18 16)
(A19 ONCE)
IO
A(L) H(Z) These pins provide multiplexed Address during the address
R(WH) phase of the bus cycle Address bits 16 through 19 are presented
P(X) on these pins and can be latched using ALE These pins are
driven to a logic 0 during the data phase of the bus cycle On the
80C188EB A15 – A8 provide valid address information for the
entire bus cycle During a processor reset (RESIN active) A19
ONCE is used to enable ONCE mode A18 16 must not be driven
low during reset or improper operation may result
S2 0
O
H(Z)
R(Z)
P(1)
Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
S2 S1 S0
Bus Cycle Initiated
0 0 0 Interrupt Acknowledge
0 0 1 Read I O
0 1 0 Write I O
0 1 1 Processor HALT
1 0 0 Queue Instruction Fetch
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive (no bus activity)
ALE O
H(0) Address Latch Enable output is used to strobe address
R(0) information into a transparent type latch during the address phase
P(0) of the bus cycle
BHE
(RFSH)
O
H(Z)
R(Z)
P(X)
Byte High Enable output to indicate that the bus cycle in progress
is transferring data over the upper half of the data bus BHE and
A0 have the following logical encoding
A0 BHE Encoding (for the 80C186EB 80L186EB only)
0 0 Word Transfer
0 1 Even Byte Transfer
1 0 Odd Byte Transfer
1 1 Refresh Operation
On the 80C188EB 80L188EB RFSH is asserted low to indicate a
refresh bus cycle
RD O H(Z) ReaD output signals that the accessed memory or I O device
R(Z) must drive data information onto the data bus
P(1)
WR O H(Z) WRite output signals that data available on the data bus are to be
R(Z) written into the accessed memory or I O device
P(1)
READY
I A(L)
S(L)
READY input to signal the completion of a bus cycle READY
must be active to terminate any bus cycle unless it is ignored by
correctly programming the Chip-Select Unit
DEN
O
H(Z)
R(Z)
P(1)
Data ENable output to control the enable of bi-directional
transceivers in a buffered system DEN is active only when data is
to be transferred on the bus
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
11


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80C186EB 80C188EB 80L186EB 80L188EB
Pin
Name
DT R
LOCK
HOLD
HLDA
NCS
(N C )
ERROR
(N C )
PEREQ
(N C )
UCS
LCS
P1 0 GCS0
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
Pin
Type
O
O
I
O
O
I
I
O
O
O
Input
Type
A(L)
A(L)
A(L)
Table 3 Pin Descriptions (Continued)
Output
States
Description
H(Z)
R(Z)
P(X)
Data Transmit Receive output controls the direction of a
bi-directional buffer in a buffered system DT R is only
available for the PLCC package
H(Z)
R(WH)
P(1)
LOCK output indicates that the bus cycle in progress is not
to be interrupted The processor will not service other bus
requests (such as HOLD) while LOCK is active This pin is
configured as a weakly held high input while RESIN is
active and must not be driven low
HOLD request input to signal that an external bus master
wishes to gain control of the local bus The processor will
relinquish control of the local bus between instruction
boundaries not conditioned by a LOCK prefix
H(1) HoLD Acknowledge output to indicate that the processor
R(0) has relinquished control of the local bus When HLDA is
P(0) asserted the processor will (or has) floated its data bus
and control signals allowing another bus master to drive the
signals directly
H(1) Numerics Coprocessor Select output is generated when
R(1) accessing a numerics coprocessor NCS is not provided on
P(1) the QFP or SQFP packages This signal does not exist on
the 80C188EB 80L188EB
ERROR input that indicates the last numerics coprocessor
operation resulted in an exception condition An interrupt
TYPE 16 is generated if ERROR is sampled active at the
beginning of a numerics operation ERROR is not provided
on the QFP or SQFP packages This signal does not exist
on the 80C188EB 80L188EB
CoProcessor REQuest signals that a data transfer
between an External Numerics Coprocessor and Memory is
pending PEREQ is not provided on the QFP or SQFP
packages This signal does not exist on the 80C188EB
80L188EB
H(1) Upper Chip Select will go active whenever the address of
R(1) a memory or I O bus cycle is within the address limitations
P(1) programmed by the user After reset UCS is configured to
be active for memory accesses between 0FFC00H and
0FFFFFH
H(1) Lower Chip Select will go active whenever the address of
R(1) a memory bus cycle is within the address limitations
P(1) programmed by the user LCS is inactive after a reset
H(X) H(1)
R(1)
P(X) P(1)
These pins provide a multiplexed function If enabled each
pin can provide a Generic Chip Select output which will go
active whenever the address of a memory or I O bus cycle
is within the address limitations programmed by the user
When not programmed as a Chip-Select each pin may be
used as a general purpose output Port As an output port
pin the value of the pin can be read internally
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
12


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80C186EB 80C188EB 80L186EB 80L188EB
Pin
Name
T0OUT
T1OUT
T0IN
T1IN
INT0
INT1
INT4
INT2 INTA0
INT3 INTA1
P2 7
P2 6
CTSO
P2 4 CTS1
TXD0
P2 1 TXD1
RXD0
P2 0 RXD1
P2 5 BCLK0
P2 2 BCLK1
P2 3 SINT1
Pin
Type
O
I
I
IO
IO
I
O
IO
I
O
Table 3 Pin Descriptions (Continued)
Input
Type
Output
States
Description
H(Q)
R(1)
P(Q)
Timer OUTput pins can be programmed to provide a
single clock or continuous waveform generation
depending on the timer mode selected
A(L) Timer INput is used either as clock or control signals
A(E) depending on the timer mode selected
A(E L)
Maskable INTerrupt input will cause a vector to a
specific Type interrupt routine To allow interrupt
expansion INT0 and or INT1 can be used with
INTA0 and INTA1 to interface with an external slave
controller
A(E L)
H(1) These pins provide a multiplexed function As inputs
R(Z) they provide a maskable INTerrupt that will cause
P(1) the CPU to vector to a specific Type interrupt routine
As outputs each is programmatically controlled to
provide an INTERRUPT ACKNOWLEDGE
handshake signal to allow interrupt expansion
A(L)
H(X)
BI-DIRECTIONAL open-drain Port pins
R(Z)
P(X)
A(L) Clear-To-Send input is used to prevent the
transmission of serial data on their respective TXD
signal pin CTS1 is multiplexed with an input only port
function
H(X) H(Q)
R(1)
P(X) P(Q)
Transmit Data output provides serial data
information TXD1 is multiplexed with an output only
Port function During synchronous serial
communications TXD will function as a clock output
A(L) R(Z) Receive Data input accepts serial data information
H(Q)
RXD1 is multiplexed with an input only Port function
P(X) During synchronous serial communications RXD is
bi-directional and will become an output for
transmission or data (TXD becomes the clock)
A(L) A(E)
Baud CLocK input can be used as an alternate clock
source for each of the integrated serial channels
BCLKx is multiplexed with an input only Port function
and cannot exceed a clock rate greater than one-half
the operating frequency of the processor
H(X) H(Q)
R(0)
P(X) P(X)
Serial INTerrupt output will go active to indicate
serial channel 1 requires service SINT1 is
multiplexed with an output only Port function
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
13


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80C186EB 80C188EB 80L186EB 80L188EB
80C186EB PINOUT
Tables 4 and 5 list the 80C186EB 80C188EB pin
names with package location for the 84-pin Plastic
Leaded Chip Carrier (PLCC) component Figure 5
depicts the complete 80C186EB 80C188EB pinout
(PLCC package) as viewed from the top side of the
component (i e contacts facing down)
Tables 6 and 7 list the 80C186EB 80C188EB pin
names with package location for the 80-pin Quad
Flat Pack (QFP) component Figure 6 depicts the
complete 80C186EB 80C188EB (QFP package) as
viewed from the top side of the component (i e con-
tacts facing down)
Tables 8 and 9 list the 80186EB 80188EB pin
names with package location for the 80-pin Shrink
Quad Flat Pack (SQFP) component Figure 7 depicts
the complete 80C186EB 80C188EB (SQFP pack-
age) as viewed from the top side of the component
(i e contacts facing down)
Address Data Bus
Name Location
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8 (A8)
AD9 (A9)
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13 (A13)
AD14 (A14)
AD15 (A15)
A16
A17
A18
A19 ONCE
61
66
68
70
72
74
76
78
62
67
69
71
73
75
77
79
80
81
82
83
Table 4 PLCC Pin Names with Package Location
Bus Control
Processor Control
Name
Location
Name
Location
ALE
BHE (RFSH)
S0
S1
S2
RD
WR
READY
DEN
DT R
LOCK
HOLD
HLDA
6
7
10
9
8
4
5
18
11
16
15
13
12
Power
Name
Location
RESIN
RESOUT
CLKIN
OSCOUT
CLKOUT
TEST BUSY
NCS (N C )
PEREQ (N C )
ERROR (N C )
PDTMR
NMI
INT0
INT1
INT2 INTA0
INT3 INTA1
INT4
37
38
41
40
44
14
60
39
3
36
17
31
32
33
34
35
VSS 2 22 43
63 65 84
VCC 1 23
42 64
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
IO
Name
Location
UCS
LCS
P1 0 GCS0
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
T0OUT
T0IN
T1OUT
T1IN
RXD0
TXD0
P2 5 BCLK0
CTS0
P2 0 RXD1
P2 1 TXD1
P2 2 BCLK1
P2 3 SINT1
P2 4 CTS1
P2 6
P2 7
30
29
28
27
26
25
24
21
20
19
45
46
47
48
53
52
54
51
57
58
59
55
56
50
49
14


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80C186EB 80C188EB 80L186EB 80L188EB
Location
Name
1 VCC
2 VSS
3 ERROR (N C )
4 RD
5 WR
6 ALE
7 BHE (RFSH)
8 S2
9 S1
10 S0
11 DEN
12 HLDA
13 HOLD
14 TEST BUSY
15 LOCK
16 DT R
17 NMI
18 READY
19 P1 7 GCS7
20 P1 6 GCS6
21 P1 5 GCS5
Table 5 PLCC Package Locations with Pin Name
Location
Name
Location
Name
22 VSS
23 VCC
24 P1 4 GCS4
25 P1 3 GCS3
26 P1 2 GCS2
27 P1 1 GCS1
28 P1 0 GCS0
29 LCS
30 UCS
31 INT0
32 INT1
33 INT2 INTA0
34 INT3 INTA1
35 INT4
36 PDTMR
37 RESIN
38 RESOUT
39 PEREQ (N C )
40 OSCOUT
41 CLKIN
42 VCC
43 VSS
44 CLKOUT
45 T0OUT
46 T0IN
47 T1OUT
48 T1IN
49 P2 7
50 P2 6
51 CTS0
52 TXD0
53 RXD0
54 P2 5 BCLK0
55 P2 3 SINT1
56 P2 4 CTS1
57 P2 0 RXD1
58 P2 1 TXD1
59 P2 2 BCLK1
60 NCS (N C )
61 AD0
62 AD8 (A8)
63 VSS
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
Location
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Name
VCC
VSS
AD1
AD9 (A9)
AD2
AD10 (A10)
AD3
AD11 (A11)
AD4
AD12 (A12)
AD5
AD13 (A13)
AD6
AD14 (A14)
AD7
AD15 (A15)
A16
A17
A18
A19 ONCE
VSS
15


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80C186EB 80C188EB 80L186EB 80L188EB
NOTE
This is the FPO number location (indicated by X’s)
Pin names in parentheses apply to the 80C188EB 80L188EB
Figure 4 84-Pin Plastic Leaded Chip Carrier Pinout Diagram
272433 – 5
16


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80C186EB 80C188EB 80L186EB 80L188EB
Address Data Bus
Name Location
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8 (A8)
AD9 (A9)
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13 (A13)
AD14 (A14)
AD15 (A15)
A16
A17
A18
A19 ONCE
10
15
17
19
21
23
25
27
11
16
18
20
22
24
26
28
29
30
31
32
Table 6 QFP Pin Name with Package Location
Bus Control
Processor Control
Name
Location
Name Location
ALE
BHE (RFSH)
S0
S1
S2
RD
WR
READY
DEN
LOCK
HOLD
HLDA
38
39
42
41
40
36
37
49
43
47
45
44
RESIN
RESOUT
CLKIN
OSCOUT
CLKOUT
TEST
PDTMR
NMI
INT0
INT1
INT2 INTA0
INT3 INTA1
INT4
68
69
71
70
74
46
67
48
62
63
64
65
66
Power
Name
Location
VSS 12 14 33
35 53 73
VCC 13 34
54 72
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
IO
Name
Location
UCS
LCS
P1 0 GCS0
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
T0OUT
T0IN
T1OUT
T1IN
RXD0
TXD0
P2 5 BCLK0
CTS0
P2 0 RXD1
P2 1 TXD1
P2 2 BCLK1
P2 3 SINT1
P2 4 CTS1
P2 6
P2 7
61
60
59
58
57
56
55
52
51
50
75
76
77
78
3
2
4
1
7
8
9
5
6
80
79
17


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80C186EB 80C188EB 80L186EB 80L188EB
Location
Name
1 CTS0
2 TXD0
3 RXD0
4 P2 5 BCLK0
5 P2 3 SINT1
6 P2 4 CTS1
7 P2 0 RXD1
8 P2 1 TXD1
9 P2 2 BCLK1
10 AD0
11 AD8 (A8)
12 VSS
13 VCC
14 VSS
15 AD1
16 AD9 (A9)
17 AD2
18 AD10 (A10)
19 AD3
20 AD11 (A11)
Table 7 QFP Package Location with Pin Names
Location
Name
Location
Name
21 AD4
22 AD12 (A12)
23 AD5
24 AD13 (A13)
25 AD6
26 AD14 (A14)
27 AD7
28 AD15 (A15)
29 A16
30 A17
31 A18
32 A19 ONCE
33 VSS
34 VCC
35 VSS
36 RD
37 WR
38 ALE
39 BHE (RFSH)
40 S2
41 S1
42 S0
43 DEN
44 HLDA
45 HOLD
46 TEST
47 LOCK
48 NMI
49 READY
50 P1 7 GCS7
51 P1 6 GCS6
52 P1 5 GCS5
53 VSS
54 VCC
55 P1 4 GCS4
56 P1 3 GCS3
57 P1 2 GCS2
58 P1 1 GCS1
59 P1 0 GCS0
60 LCS
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
Location
Name
61 UCS
62 INT0
63 INT1
64 INT2 INTA0
65 INT3 INTA1
66 INT4
67 PDTMR
68 RESIN
69 RESOUT
70 OSCOUT
71 CLKIN
72 VCC
73 VSS
74 CLKOUT
75 T0OUT
76 T0IN
77 T1OUT
78 T1IN
79 P2 7
80 P2 6
18


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80C186EB 80C188EB 80L186EB 80L188EB
NOTE
This is the FPO number location (indicated by X’s)
Pin names in parentheses apply to the 80C188EB 80L188EB
Figure 5 Quad Flat Pack Pinout Diagram
272433 – 6
19


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80C186EB 80C188EB 80L186EB 80L188EB
Table 8 SQFP Pin Functions with Location
AD Bus
Bus Control
Processor Control
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8 (A8)
AD9 (A9)
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13 (A13)
AD14 (A14)
AD15 (A15)
A16
A17
A18
A19 ONCE
47 ALE
75 RESIN
25
52 BHE (RFSH ) 76 RESOUT
26
54 S0
79 CLKIN
28
56 S1
78 OSCOUT
27
58 S2
77 CLKOUT
31
60 RD
73 TEST BUSY
3
62 WR
74 NMI
5
64 READY
6 INT0
19
48 DEN
80 INT1
20
53 LOCK
4 INT2 INTA0
21
55 HOLD
2 INT3 INTA1
22
57 HLDA
1 INT4
23
59
PDTMR
24
61
63
65 Power and Ground
66 VCC 11
67 VCC 29
68 VCC 50
69 VCC 71
VSS 10
VSS 30
VSS 49
VSS 51
VSS 70
VSS 72
1 HLDA
2 HOLD
3 TEST
4 LOCK
5 NMI
6 READY
7 P1 7 GCS7
8 P1 6 GCS6
9 P1 5 GCS5
10 VSS
11 VCC
12 P1 4 GCS4
13 P1 3 GCS3
14 P1 2 GCS2
15 P1 1 GCS1
16 P1 0 GCS0
17 LCS
18 UCS
19 INT0
20 INT1
Table 9 SQFP Pin Locations with Pin Names
21 INT1 INTA0
22 INT3 INTA1
23 INT4
24 PDTMR
25 RESIN
26 RESOUT
27 OSCOUT
28 CLKIN
29 VCC
30 VSS
31 CLKOUT
32 T0OUT
33 T0IN
34 T1OUT
35 T1IN
36 P2 7
37 P2 6
38 CTS0
39 TXD0
40 RXD0
41 P2 5 BCLK0
42 P2 3 SINT1
43 P2 4 CTS1
44 P2 0 RXD1
45 P2 1 TXD1
46 P2 2 BCLK1
47 AD0
48 AD8 (A8)
49 VSS
50 VCC
51 VSS
52 AD1
53 AD9 (A9)
54 AD2
55 AD10 (A10)
56 AD3
57 AD11 (A11)
58 AD4
59 AD12 (A12)
60 AD5
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
20
UCS
LCS
IO
P1 0 GCS0
P1 1 GCS1
P1 2 GCS2
P1 3 GCS3
P1 4 GCS4
P1 5 GCS5
P1 6 GCS6
P1 7 GCS7
P2 0 RXD1
P2 1 TXD1
P2 2 BCLK1
P2 3 SINT1
P2 4 CTS1
P2 5 BCLK0
P2 6
P2 7
CTS0
TXD0
RXD0
T0IN
T1IN
T0OUT
T1OUT
18
17
16
15
14
13
12
9
8
7
44
45
46
42
43
41
37
36
38
39
40
33
35
32
34
61 AD13 (A13)
62 AD6
63 AD14 (A14)
64 AD7
65 AD15 (A15)
66 A16
67 A17
68 A18
69 A19 ONCE
70 VSS
71 VCC
72 VSS
73 RD
74 WR
75 ALE
76 BHE (RFSH )
77 S2
78 S1
79 S0
80 DEN


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80C186EB 80C188EB 80L186EB 80L188EB
NOTE
XXXXXXXXC indicates Intel FPO number
Pin names in parentheses apply to the 80C188EB 80L188EB
Figure 6 SQFP Package
272433 – 7
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80C186EB 80C188EB 80L186EB 80L188EB
PACKAGE THERMAL
SPECIFICATIONS
The 80C186EB 80L186EB is specified for operation
when TC (the case temperature) is within the range
of b40 C to a100 C (PLCC package) or b40 C to
a114 C (QFP package) TC may be measured in
any environment to determine whether the proces-
sor is within the specified operating range The case
temperature must be measured at the center of the
top surface
TA (the ambient temperature) can be calculated
from iCA (thermal resistance from the case to ambi-
ent) with the following equation
TA e TC b P iCA
Typical values for iCA at various airflows are given
in Table 10 P (the maximum power consumption
specified in watts) is calculated by using the maxi-
mum ICC as tabulated in the DC specifications and
VCC of 5 5V
Table 10 Thermal Resistance (iCA) at Various Airflows (in C Watt)
Airflow Linear ft min (m sec)
0 200 400 600 800 1000
(0) (1 01) (2 03) (3 04) (4 06) (5 07)
iCA (PLCC)
iCA (QFP)
iCA (SQFP)
30 24
58 47
70 TBD
21
43
TBD
19
40
TBD
17
38
TBD
16 5
36
TBD
22


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80C186EB 80C188EB 80L186EB 80L188EB
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Storage Temperature
Case Temp under Bias
Supply Voltage
with Respect to VSS
Voltage on other Pins
with Respect to VSS
b65 C to a150 C
b65 C to a120 C
b0 5V to a 6 5V
b0 5V to VCC a 0 5V
Recommended Connections
Power and ground connections must be made to
multiple VCC and VSS pins Every 80C186EB-based
circuit board should include separate power (VCC)
and ground (VSS) planes Every VCC pin must be
connected to the power plane and every VSS pin
must be connected to the ground plane Pins identi-
fied as ‘‘NC’’ must not be connected in the system
Liberal decoupling capacitance should be placed
near the processor The processor can cause tran-
sient power surges when its output buffers tran-
sition particularly when connected to large capaci-
tive loads
NOTICE This data sheet contains preliminary infor-
mation on new products in production It is valid for
the devices indicated in the revision history The
specifications are subject to change without notice
WARNING Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
Low inductance capacitors and interconnects are
recommended for best high frequency electrical per-
formance Inductance is reduced by placing the de-
coupling capacitors as close as possible to the proc-
essor VCC and VSS package pins
Always connect any unused input to an appropriate
signal level In particular unused interrupt inputs
(INT0 4) should be connected to VCC through a pull-
up resistor (in the range of 50 KX) Leave any un-
used output pin or any NC pin unconnected
23


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80C186EB 80C188EB 80L186EB 80L188EB
DC SPECIFICATIONS (80C186EB 80C188EB)
Symbol
Parameter
Min Max Units
Notes
VCC
VIL
VIH
VOL
VOH
VHYR
ILI1
Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Hysterisis on RESIN
Input Leakage Current for Pins
AD15 0 (AD7 0) READY HOLD
RESIN CLKIN TEST NMI INT4 0
T0IN T1IN RXD0 BCLK0 CTS0
RXD1 BCLK1 CTS1 P2 6 P2 7
45 55 V
b0 5
0 3 VCC
V
0 7 VCC VCC a 0 5 V
0 45
V IOL e 3 mA (Min)
VCC b 0 5
V IOH e b2 mA (MIn)
0 50
V
g15
mA 0V s VIN s VCC
ILI2 Input Leakage Current for Pins
ERROR PEREQ
g0 275 g7 mA 0V s VIN k VCC
ILI3 Input Leakage Current for Pins
A19 ONCE A18 16 LOCK
b0 275
b5 0
mA VIN e 0 7 VCC (Note 1)
ILO Output Leakage Current
g15
mA 0 45 s VOUT s VCC
(Note 2)
ICC Supply Current Cold (RESET)
80C186EB25
115 mA (Notes 3 7)
80C186EB20
108 mA (Note 3)
80C186EB13
73 mA (Note 3)
IID Supply Current Idle
80C186EB25
91 mA (Notes 4 7)
80C186EB20
76 mA (Note 4)
80C186EB13
48 mA (Note 4)
IPD Supply Current Powerdown
80C186EB25
100 mA (Notes 5 7)
80C186EB20
100 mA (Note 5)
80C186EB13
100 mA (Note 5)
CIN
COUT
Input Pin Capacitance
Output Pin Capacitance
0 15 pF TF e 1 MHz
0 15 pF TF e 1 MHz (Note 6)
NOTES
1 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more
current than specified (on any of these pins) may invoke a factory test mode
2 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD
3 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as
specified in AC Test Conditions and all floating outputs driven to VCC or GND
4 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL
outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
5 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with
ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
6 Output Capacitance is the capacitive load of a floating output pin
7 Operating temperature for 25 MHz is 0 C to 70 C VCC e 5 0 g10%
24


80L186EB (Intel Corporation)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

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80C186EB 80C188EB 80L186EB 80L188EB
DC SPECIFICATIONS (80L186EB16) (operating temperature 0 C to 70 C)
Symbol
Parameter
Min Max Units
Notes
VCC
VIL
VIH
VOL
VOH
VHYR
ILI1
Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Hysterisis on RESIN
Input Leakage Current for pins
AD15 0 (AD7 0) READY HOLD
RESIN CLKIN TEST NMI
INT4 0 T0IN T1IN RXD0
BCLK0 CTS0 RXD1 BCLK1
CTS1 SINT1 P2 6 P2 7
30 55 V
b0 5
0 3 VCC
V
0 7 VCC VCC a 0 5 V
0 45 V IOL e 1 6 mA (Min) (Note 1)
VCC b 0 5
V IOH e b1 mA (Min) (Note 1)
0 50
V
g15
mA 0V s VIN s VCC
ILI2 Input Leakage Current for Pins b0 275 b2 mA VIN e 0 7 VCC (Note 2)
A19 ONCE A18 16 LOCK
ILO
ICC3
Output Leakage Current
Supply Current (RESET 3 3V)
80L186EB16
g15
54
mA 0 45 s VOUT s VCC (Note 3)
mA (Note 4)
IID3 Supply Current Idle (3 3V)
80L186EB16
38 mA (Note 5)
IPD3 Supply Current Powerdown (3 3V)
80L186EB16
40 mA (Note 6)
CIN
COUT
Input Pin Capacitance
Output Pin Capacitance
0 15 pF TF e 1 MHz
0 15 pF TF e 1 MHz (Note 7)
NOTES
1 IOL and IOH measured at VCC e 3 0V
2 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more
current than specified (on any of these pins) may invoke a factory test mode
3 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD
4 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as
specified in AC Test Conditions and all floating outputs driven to VCC or GND
5 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL
outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
6 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with
ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
7 Output Capacitance is the capacitive load of a floating output pin
25


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80C186EB 80C188EB 80L186EB 80L188EB
DC SPECIFICATIONS (80L186EB13 80L188EB13
Symbol
Parameter
Min Max Units
Notes
VCC
VIL
VIH
VOL
VOH
VHYR
ILI1
Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Hysterisis on RESIN
Input Leakage Current for pins
AD15 0 (AD7 0) READY HOLD
RESIN CLKIN TEST NMI
INT4 0 T0IN T1IN RXD0
BCLK0 CTS0 RXD1 BCLK1
CTS1 SINT1 P2 6 P2 7
27 55 V
b0 5
0 3 VCC
V
0 7 VCC VCC a 0 5 V
0 45 V IOL e 1 6 mA (Min) (Note 1)
VCC b 0 5
V IOH e b1 mA (Min) (Note 1)
0 50
V
g15
mA 0V s VIN s VCC
ILI2 Input Leakage Current for Pins b0 275 b2 mA VIN e 0 7 VCC (Note 2)
A19 ONCE A18 16 LOCK
ILO
ICC5
Output Leakage Current
Supply Current (RESET 5 5V)
80L186EB13
80L186EB8
g15
73
45
mA 0 45 s VOUT s VCC (Note 3)
mA (Note 4)
mA (Note 4)
ICC3
Supply Current (RESET 2 7V)
80L186EB13
80L186EB8
36 mA (Note 4)
22 mA (Note 4)
IID5 Supply Current Idle (5 5V)
80L186EB13
80L186EB8
48 mA (Note 5)
31 mA (Note 5)
IID3 Supply Current Idle (2 7V)
80L186EB13
80L186EB8
24 mA (Note 5)
15 mA (Note 5)
IPD5 Supply Current Powerdown (5 5V)
80L186EB13
80L186EB8
100 mA (Note 6)
100 mA (Note 6)
IPD3 Supply Current Powerdown (2 7V)
80L186EB13
80L186EB8
30 mA (Note 6)
30 mA (Note 6)
CIN
COUT
Input Pin Capacitance
Output Pin Capacitance
0 15 pF TF e 1 MHz
0 15 pF TF e 1 MHz (Note 7)
NOTES
1 IOL and IOH measured at VCC e 2 7V
2 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more
current than specified (on any of these pins) may invoke a factory test mode
3 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD
4 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as
specified in AC Test Conditions and all floating outputs driven to VCC or GND
5 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL
outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
6 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with
ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND
7 Output Capacitance is the capacitive load of a floating output pin
26


80L186EB (Intel Corporation)
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

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80C186EB 80C188EB 80L186EB 80L188EB
ICC VERSUS FREQUENCY AND VOLTAGE
The current (ICC) consumption of the processor is
essentially composed of two components IPD and
ICCS
IPD is the quiescent current that represents internal
device leakage and is measured with all inputs or
floating outputs at GND or VCC (no clock applied to
the device) IPD is equal to the Powerdown current
and is typically less than 50 mA
ICCS is the switching current used to charge and
discharge parasitic device capacitance when chang-
ing logic levels Since ICCS is typically much greater
than IPD IPD can often be ignored when calculating
ICC
ICCS is related to the voltage and frequency at which
the device is operating It is given by the formula
Where
Power e V c I e V2 c CDEV c f
I e ICC e ICCS e V c CDEV c f
V e Device operating voltage (VCC)
CDEV e Device capacitance
f e Device operating frequency
ICCS e ICC e Device current
Measuring CDEV on a device like the 80C186EB
would be difficult Instead CDEV is calculated using
the above formula by measuring ICC at a known VCC
and frequency (see Table 11) Using this CDEV val-
ue ICC can be calculated at any voltage and fre-
quency within the specified operating range
EXAMPLE Calculate the typical ICC when operating
at 10 MHz 4 8V
PDTMR PIN DELAY CALCULATION
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown A delay is required
only when using the on-chip oscillator to allow the
crystal or resonator circuit time to stabilize
NOTE
The PDTMR pin function does not apply when
RESIN is asserted (i e a device reset during Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabi-
lized)
To calculate the value of capacitor required to pro-
vide a desired delay use the equation
440 c t e CPD (5V 25 C)
Where t e desired delay in seconds
CPD e capacitive load on PDTMR in mi-
crofarads
EXAMPLE To get a delay of 300 ms a capacitor
value of CPD e 440 c (300 c 10b6) e 0 132 mF is
required Round up to standard (available) capaci-
tive values
NOTE
The above equation applies to delay times greater
than 10 ms and will compute the TYPICAL capaci-
tance needed to achieve the desired delay A delay
variance of a50% or b25% can occur due to
temperature voltage and device process ex-
tremes In general higher VCC and or lower tem-
perature will decrease delay time while lower VCC
and or higher temperature will increase delay time
ICC e ICCS e 4 8 c 0 583 c 10 28 mA
Table 11 Device Capacitance (CDEV) Values
Parameter
Typ Max
Units
Notes
CDEV (Device in Reset)
0 583
1 02
mA V MHz
12
CDEV (Device in Idle)
0 408 0 682 mA V MHz
12
1 Max CDEV is calculated at b40 C all floating outputs driven to VCC or GND and all
outputs loaded to 50 pF (including CLKOUT and OSCOUT)
2 Typical CDEV is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and
OSCOUT which are not loaded
27


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80C186EB 80C188EB 80L186EB 80L188EB
AC SPECIFICATIONS
AC Characteristics 80C186EB25
Symbol
Parameter
INPUT CLOCK
TF CLKIN Frequency
TC CLKIN Period
TCH CLKIN High Time
TCL CLKIN Low Time
TCR CLKIN Rise Time
TCF CLKIN Fall Time
OUTPUT CLOCK
TCD CLKIN to CLKOUT Delay
T CLKOUT Period
TPH CLKOUT High Time
TPL CLKOUT Low Time
TPR CLKOUT Rise Time
TPF CLKOUT Fall Time
OUTPUT DELAYS
TCHOV1
TCHOV2
TCLOV1
ALE S2 0 DEN DT R BHE (RFSH) LOCK A19 16
GCS0 7 LCS UCS NCS RD WR
BHE (RFSH) DEN LOCK RESOUT HLDA T0OUT
T1OUT A19 16
TCLOV2 RD WR GCS7 0 LCS UCS AD15 0 (AD7 0 A15 8)
NCS INTA1 0 S2 0
TCHOF
TCLOF
RD WR BHE (RFSH) DT R LOCK S2 0 A19 16
DEN AD15 0 (AD7 0 A15 8)
25 MHz
Min Max
Units Notes
0 50 MHz 1
20 % ns 1
8 % ns 1 2
8 % ns 1 2
1 7 ns 1 3
1 7 ns 1 3
0
(T 2) b 5
(T 2) b 5
1
1
16
2 TC
(T 2) a 5
(T 2) a 5
6
6
ns
ns
ns
ns
ns
ns
14
1
1
1
15
15
3 17 ns 1 4 6 7
3 20 ns 1 4 6 8
3 17 ns 1 4 6
3 20 ns 1 4 6
0 20 ns 1
0 20 ns 1
28


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16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

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80C186EB 80C188EB 80L186EB 80L188EB
AC SPECIFICATIONS
AC Characteristics 80C186EB25 (Continued)
Symbol
Parameter
SYNCHRONOUS INPUTS
TCHIS TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7
TCHIH TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0
TCLIS
TCLIH
TCLIS
TCLIH
AD15 0 (AD7 0) READY
READY AD15 0 (AD7 0)
HOLD PEREQ ERROR
HOLD PEREQ ERROR
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measure at VIH for high time VIL for low time
3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL
4 Specified for a 50 pF load see Figure 13 for capacitive derating information
5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF
6 See Figure 14 for rise and fall times
7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
8 TCHOV2 applies to RD and WR only after a HOLD release
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
25 MHz
Units Notes
Min Max
10 ns 1 9
3 ns 1 9
10 ns 1 10
3 ns 1 10
10 ns 1 9
3 ns 1 9
29


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80C186EB 80C188EB 80L186EB 80L188EB
AC SPECIFICATIONS
AC Characteristics 80C186EB20 80C186EB13
Symbol
Parameter
20 MHz
Min Max
13 MHz
Min Max
Units Notes
INPUT CLOCK
TF CLKIN Frequency
TC CLKIN Period
TCH CLKIN High Time
TCL CLKIN Low Time
TCR CLKIN Rise Time
TCF CLKIN Fall Time
OUTPUT CLOCK
0 40 0 26 MHz 1
25 % 38 5 % ns 1
10 % 12 % ns 1 2
10 % 12 % ns 1 2
1 8 1 8 ns 1 3
1 8 1 8 ns 1 3
TCD CLKIN to CLKOUT Delay
T CLKOUT Period
TPH CLKOUT High Time
TPL CLKOUT Low Time
TPR CLKOUT Rise Time
TPF CLKOUT Fall Time
OUTPUT DELAYS
0
(T 2) b 5
(T 2) b 5
1
1
17
2 TC
(T 2) a 5
(T 2) a 5
6
6
0
(T 2) b 5
(T 2) b 5
1
1
23
2 TC
(T 2) a 5
(T 2) a 5
6
6
ns
ns
ns
ns
ns
ns
14
1
1
1
15
15
TCHOV1 ALE S2 0 DEN DT R
BHE (RFSH) LOCK
A19 16
3 22 3 25 ns 1 4 6 7
TCHOV2 GCS0 7 LCS UCS NCS
3
27
3
30 ns 1 4 6 8
RD WR
TCLOV1 BHE (RFSH) DEN LOCK
3
22
3
25 ns 1 4 6
RESOUT HLDA T0OUT
T1OUT A19 16
TCLOV2 RD WR GCS7 0 LCS
UCS AD15 0 (AD7 0
3 27 3 30 ns 1 4 6
A15 8) NCS INTA1 0 S2 0
TCHOF RD WR BHE (RFSH)
0 25 0 25 ns 1
DT R LOCK S2 0 A19 16
TCLOF DEN AD15 0 (AD7 0
A15 8)
0 25 0 25 ns 1
30




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