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80186 80188
HIGH-INTEGRATION 16-BIT MICROPROCESSORS
Y Integrated Feature Set
Enhanced 8086-2 CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-bit Timers
Programmable Memory and
Peripheral Chip-Select Logic
Programmable Wait State Generator
Local Bus Controller
Y Available in 10 MHz and 8 MHz
Versions
Y High-Performance Processor
4 Mbyte Sec Bus Bandwidth
Interface 8 MHz (80186)
5 Mbyte Sec Bus Bandwidth
Interface 10 MHz (80186)
Y Direct Addressing Capability to 1 Mbyte
of Memory and 64 Kbyte I O
Y Completely Object Code Compatible
with All Existing 8086 8088 Software
10 New Instruction Types
Y Numerics Coprocessing Capability
Through 8087 Interface
Y Available in 68 Pin
Plastic Leaded Chip Carrier (PLCC)
Ceramic Pin Grid Array (PGA)
Ceramic Leadless Chip Carrier (LCC)
Y Available in EXPRESS
Standard Temperature with Burn-In
Extended Temperature Range
(b40 C to a85 C)
Figure 1 Block Diagram
272430 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1994
Order Number 272430-002
COPYRIGHT INTEL CORPORATION 1995
1
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80186 80188 High-Integration 16-Bit Microprocessors
CONTENTS
FUNCTIONAL DESCRIPTION
Introduction
CLOCK GENERATOR
Oscillator
Clock Generator
READY Synchronization
RESET Logic
LOCAL BUS CONTROLLER
Memory Peripheral Control
Local Bus Arbitration
Local Bus Controller and Reset
PERIPHERAL ARCHITECTURE
Chip-Select Ready Generation Logic
DMA Channels
Timers
Interrupt Controller
PAGE
9
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10
10
10
10
10
11
11
12
CONTENTS
ABSOLUTE MAXIMUM RATINGS
D C CHARACTERISTICS
A C CHARACTERISTICS
EXPLANATION OF THE AC
SYMBOLS
WAVEFORMS
EXPRESS
EXECUTION TIMINGS
INSTRUCTION SET SUMMARY
FOOTNOTES
REVISION HISTORY
PAGE
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32
33
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Contacts Facing Up
80186 80188
Contacts Facing Down
Figure 2 Ceramic Leadless Chip Carrier (JEDEC Type A)
Pins Facing Up
Pins Facing Down
272430 – 2
Figure 3 Ceramic Pin Grid Array
NOTE
Pin names in parentheses apply to the 80188
272430 – 3
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80186 80188
Leads Facing Up
Leads Facing Down
Figure 4 Plastic Leaded Chip Carrier
NOTE
Pin names in parentheses apply to the 80188
272430 – 4
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80186 80188
Table 1 Pin Descriptions
Symbol
Pin
No Type
Name and Function
VCC 9 I SYSTEM POWER a5 volt power supply
43
VSS 26 I System Ground
60
RESET
57 O Reset Output indicates that the CPU is being reset and can be used as a system
reset It is active HIGH synchronized with the processor clock and lasts an
integer number of clock periods corresponding to the length of the RES signal
X1 59 I Crystal Inputs X1 and X2 provide external connections for a fundamental mode
X2 58 O parallel resonant crystal for the internal oscillator Instead of using a crystal an
external clock may be applied to X1 while minimizing stray capacitance on X2
The input or oscillator frequency is internally divided by two to generate the
clock signal (CLKOUT)
CLKOUT
56 O Clock Output provides the system with a 50% duty cycle waveform All device
pin timings are specified relative to CLKOUT
RES
24 I An active RES causes the processor to immediately terminate its present
activity clear the internal logic and enter a dormant state This signal may be
asynchronous to the processor clock The processor begins fetching
instructions approximately 6 clock cycles after RES is returned HIGH For
proper initialization VCC must be within specifications and the clock signal must
be stable for more than 4 clocks with RES held LOW RES is internally
synchronized This input is provided with a Schmitt-trigger to facilitate power-on
RES generation via an RC network
TEST
47 I O TEST is examined by the WAIT instruction If the TEST input is HIGH when
‘‘WAIT’’ execution begins instruction execution will suspend TEST will be
resampled until it goes LOW at which time execution will resume If interrupts
are enabled while the processor is waiting for TEST interrupts will be serviced
During power-up active RES is required to configure TEST as an input This pin
is synchronized internally
TMR IN 0
TMR IN 1
20 I Timer Inputs are used either as clock or control signals depending upon the
21 I programmed timer mode These inputs are active HIGH (or LOW-to-HIGH
transitions are counted) and internally synchronized
TMR OUT 0
TMR OUT 1
22 O Timer outputs are used to provide single pulse or continous waveform
23 O generation depending upon the timer mode selected
DRQ0
DRQ1
18 I DMA Request is asserted HIGH by an external device when it is ready for DMA
19 I Channel 0 or 1 to perform a transfer These signals are level-triggered and
internally synchronized
NMI 46 I The Non-Maskable Interrupt input causes a Type 2 interrupt An NMI transition
from LOW to HIGH is latched and synchronized internally and initiates the
interrupt at the next instruction boundary NMI must be asserted for at least one
clock The Non-Maskable Interrupt cannot be avoided by programming
INT0
INT1 SELECT
INT2 INTA0
INT3 INTA1 IRQ
45
44
42
41
I Maskable Interrupt Requests can be requested by activating one of these pins
I When configured as inputs these pins are active HIGH Interrupt Requests are
I O synchronized internally INT2 and INT3 may be configured to provide active-
I O LOW interrupt-acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To ensure recognition all
interrupt requests must remain active until the interrupt is acknowledged When
Slave Mode is selected the function of these pins changes (see Interrupt
Controller section of this data sheet)
NOTE
Pin names in parentheses apply to the 80188
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80186 80188
Table 1 Pin Descriptions (Continued)
Symbol
Pin
No
Type
Name and Function
A19 S6
A18 S5
A17 S4
A16 S3
65 O Address Bus Outputs (16–19) and Bus Cycle Status (3–6) indicate the four most
66 O significant address bits during T1 These signals are active HIGH During T2 T3 TW
67 O and T4 the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a
68 O DMA-initiated bus cycle During the same T-states S3 S4 and S5 are always LOW
The status pins float during bus HOLD or RESET
AD15 (A15)
AD14 (A14)
AD13 (A13)
AD12 (A12)
AD11 (A11)
AD10 (A10)
AD9 (A9)
AD8 (A8)
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1
3
5
7
10
12
14
16
2
4
6
8
11
13
15
17
I O Address Data Bus signals constitute the time multiplexed memory or I O address (T1)
I O and data (T2 T3 TW and T4) bus The bus is active HIGH A0 is analogous to BHE for
I O the lower byte of the data bus pins D7 through D0 It is LOW during T1 when a byte is
I O to be transferred onto the lower portion of the bus in memory or I O operations BHE
I O does not exist on the 80188 as the data bus is only 8 bits wide
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BHE S7
(S7)
64 O During T1 the Bus High Enable signal should be used to determine if data is to be
enabled onto the most significant half of the data bus pins D15–D8 BHE is LOW
during T1 for read write and interrupt acknowledge cycles when a byte is to be
transferred on the higher half of the bus The S7 status information is available during
T2 T3 and T4 S7 is logically equivalent to BHE BHE S7 floats during HOLD On the
80188 S7 is high during normal operation
BHE and A0 Encodings (80186 Only)
BHE A0
Value Value
Function
0 0 Word Transfer
0 1 Byte Transfer on upper half of data bus (D15–D8)
1 0 Byte Transfer on lower half of data bus (D7–D0)
1 1 Reserved
ALE QS0 61 O Address Latch Enable Queue Status 0 is provided by the processor to latch the
address ALE is active HIGH Addresses are guaranteed to be valid on the trailing
edge of ALE The ALE rising edge is generated off the rising edge of the CLKOUT
immediately preceding T1 of the associated bus cycle effectively one-half clock cycle
earlier than in the 8086 The trailing edge is generated off the CLKOUT rising edge in
T1 as in the 8086 Note that ALE is never floated
WR QS1
63 O Write Strobe Queue Status 1 indicates that the data on the bus is to be written into a
memory or an I O device WR is active for T2 T3 and TW of any write cycle It is active
LOW and floats during HOLD When the processor is in queue status mode the ALE
QS0 and WR QS1 pins provide information about processor instruction queue
interaction
QS1 QS0
Queue Operation
0 0 No queue operation
0 1 First opcode byte fetched from the queue
1 1 Subsequent byte fetched from the queue
1 0 Empty the queue
NOTE
Pin names in parentheses apply to the 80188
6
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80186 80188
Table 1 Pin Descriptions (Continued)
Symbol
Pin
No
Type
Name and Function
RD QSMD 62
I O Read Strobe is an active LOW signal which indicates that the processor is
performing a memory or I O read cycle It is guaranteed not to go LOW
before the A D bus is floated An internal pull-up ensures that RD is HIGH
during RESET Following RESET the pin is sampled to determine whether
the processor is to provide ALE RD and WR or queue status information
To enable Queue Status Mode RD must be connected to GND RD will
float during bus HOLD
ARDY
55 I Asynchronous Ready informs the processor that the addressed memory
space or I O device will complete a data transfer The ARDY pin accepts a
rising edge that is asynchronous to CLKOUT and is active HIGH The
falling edge of ARDY must be synchronized to the processor clock
Connecting ARDY HIGH will always assert the ready condition to the CPU
If this line is unused it should be tied LOW to yield control to the SRDY pin
SRDY
49 I Synchronous Ready informs the processor that the addressed memory
space or I O device will complete a data transfer The SRDY pin accepts an
active-HIGH input synchronized to CLKOUT The use of SRDY allows a
relaxed system timing over ARDY This is accomplished by elimination of
the one-half clock cycle required to internally synchronize the ARDY input
signal Connecting SRDY high will always assert the ready condition to the
CPU If this line is unused it should be tied LOW to yield control to the
ARDY pin
LOCK
48 O LOCK output indicates that other system bus masters are not to gain
control of the system bus while LOCK is active LOW The LOCK signal is
requested by the LOCK prefix instruction and is activated at the beginning
of the first data cycle associated with the instruction following the LOCK
prefix It remains active until the completion of that instruction No
instruction prefetching will occur while LOCK is asserted When executing
more than one LOCK instruction always make sure there are 6 bytes of
code between the end of the first LOCK instruction and the start of the
second LOCK instruction LOCK is driven HIGH for one clock during RESET
and then floated
S0 52 O Bus cycle status S0 –S2 are encoded to provide bus-transaction
S1 53 O information
S2 54 O
Bus Cycle Status Information
S2 S1 S0
Bus Cycle Initiated
0 0 0 Interrupt Acknowledge
0 0 1 Read I O
0 1 0 Write I O
0 1 1 Halt
1 0 0 Instruction Fetch
1 0 1 Read Data from Memory
1 1 0 Write Data to Memory
1 1 1 Passive (no bus cycle)
The status pins float during HOLD
S2 may be used as a logical M IO indicator and S1 as a DT R indicator
NOTE
Pin names in parentheses apply to the 80188
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80186 80188
Table 1 Pin Descriptions (Continued)
Symbol
Pin
No
Type
Name and Function
HOLD
HLDA
50 I HOLD indicates that another bus master is requesting the local bus The
51 O HOLD input is active HIGH HOLD may be asynchronous with respect to the
processor clock The processor will issue a HLDA (HIGH) in response to a
HOLD request at the end of T4 or Ti Simultaneous with the issuance of
HLDA the processor will float the local bus and control lines After HOLD is
detected as being LOW the processor will lower HLDA When the processor
needs to run another bus cycle it will again drive the local bus and control
lines
UCS
34 O Upper Memory Chip Select is an active LOW output whenever a memory
reference is made to the defined upper portion (1K – 256K block) of memory
This line is not floated during bus HOLD The address range activating UCS is
software programmable
LCS 33 O Lower Memory Chip Select is active LOW whenever a memory reference is
made to the defined lower portion (1K – 256K) of memory This line is not
floated during bus HOLD The address range activating LCS is software
programmable
MCS0
MCS1
MCS2
MCS3
38 O Mid-Range Memory Chip Select signals are active LOW when a memory
37 O reference is made to the defined mid-range portion of memory (8K – 512K)
36 O These lines are not floated during bus HOLD The address ranges activating
35 O MCS0 –3 are software programmable
PCS0
PCS1
PCS2
PCS3
PCS4
25 O Peripheral Chip Select signals 0 – 4 are active LOW when a reference is made
27 O to the defined peripheral area (64 Kbyte I O space) These lines are not
28 O floated during bus HOLD The address ranges activating PCS0 – 4 are
29 O software programmable
30 O
PCS5 A1 31
O Peripheral Chip Select 5 or Latched A1 may be programmed to provide a
sixth peripheral chip select or to provide an internally latched A1 signal The
address range activating PCS5 is software-programmable PCS5 A1 does
not float during bus HOLD When programmed to provide latched A1 this pin
will retain the previously latched value during HOLD
PCS6 A2 32
O Peripheral Chip Select 6 or Latched A2 may be programmed to provide a
seventh peripheral chip select or to provide an internally latched A2 signal
The address range activating PCS6 is software programmable PCS6 A2
does not float during bus HOLD When programmed to provide latched A2
this pin will retain the previously latched value during HOLD
DT R
40 O Data Transmit Receive controls the direction of data flow through an
external data bus transceiver When LOW data is transferred to the
processsor When HIGH the processor places write data on the data bus
DEN
39 O Data Enable is provided as a data bus transceiver output enable DEN is
active LOW during each memory and I O access DEN is HIGH whenever
DT R changes state During RESET DEN is driven HIGH for one clock then
floated DEN also floats during HOLD
NOTE
Pin names in parentheses apply to the 80188
8
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80186 80188
FUNCTIONAL DESCRIPTION
Introduction
The following Functional Description describes the
base architecture of the 80186 The 80186 is a very
high integration 16-bit microprocessor It combines
15–20 of the most common microprocessor system
components onto one chip while providing twice the
performance of the standard 8086 The 80186 is ob-
ject code compatible with the 8086 8088 microproc-
essors and adds 10 new instruction types to the
8086 8088 instruction set
For more detailed information on the architecture
please refer to the 80C186XL 80C188XL User’s
Manual The 80186 and the 80186XL devices are
functionally and register compatible
CLOCK GENERATOR
The processor provides an on-chip clock generator
for both internal and external clock generation The
clock generator features a crystal oscillator a divide-
by-two counter synchronous and asynchronous
ready inputs and reset circuitry
Oscillator
The oscillator circuit is designed to be used with a
parallel resonant fundamental mode crystal This is
used as the time base for the processor The crystal
frequency selected will be double the CPU clock fre-
quency Use of an LC or RC circuit is not recom-
mended with this oscillator If an external oscillator is
used it can be connected directly to the input pin X1
in lieu of a crystal The output of the oscillator is not
directly available outside the processor The recom-
mended crystal configuration is shown in Figure 5
272430 – 5
x
80186-10 (10 MHz) 20
80186
(8 MHz) 16
Figure 5 Recommended
Crystal Configuration
Intel recommends the following values for crystal se-
lection parameters
Temperature Range
ESR (Equivalent Series Resistance)
C0 (Shunt Capacitance of Crystal)
C1 (Load Capacitance)
Drive Level
0 to 70 C
30X max
7 0 pf max
20 pf g 2 pf
1 mW max
Clock Generator
The clock generator provides the 50% duty cycle
processor clock for the processor It does this by
dividing the oscillator output by 2 forming the sym-
metrical clock If an external oscillator is used the
state of the clock generator will change on the fall-
ing edge of the oscillator signal The CLKOUT pin
provides the processor clock signal for use outside
the device This may be used to drive other system
components All timings are referenced to the output
clock
READY Synchronization
The processor provides both synchronous and asyn-
chronous ready inputs In addition the processor as
part of the integrated chip-select logic has the capa-
bility to program WAIT states for memory and
peripheral blocks
RESET Logic
The processor provides both a RES input pin and a
synchronized RESET output pin for use with other
system components The RES input pin is provided
with hysteresis in order to facilitate power-on Reset
generation via an RC network RESET output is
guaranteed to remain active for at least five clocks
given a RES input of at least six clocks
LOCAL BUS CONTROLLER
The processor provides a local bus controller to
generate the local bus control signals In addition it
employs a HOLD HLDA protocol for relinquishing
the local bus to other bus masters It also provides
outputs that can be used to enable external buffers
and to direct the flow of data on and off the local
bus
9
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80186 80188
Memory Peripheral Control
The processor provides ALE RD and WR bus con-
trol signals The RD and WR signals are used to
strobe data from memory or I O to the processor or
to strobe data from the processor to memory or I O
The ALE line provides a strobe to latch the address
when it is valid The local bus controller does not
provide a memory I O signal If this is required use
the S2 signal (which will require external latching)
make the memory and I O spaces nonoverlapping
or use only the integrated chip-select circuitry
Local Bus Arbitration
The processor uses a HOLD HLDA system of local
bus exchange This provides an asynchronous bus
exchange mechanism This means multiple masters
utilizing the same bus can operate at separate clock
frequencies The processor provides a single
HOLD HLDA pair through which all other bus mas-
ters may gain control of the local bus External cir-
cuitry must arbitrate which external device will gain
control of the bus when there is more than one alter-
nate local bus master When the processor relin-
quishes control of the local bus it floats DEN RD
WR S0–S2 LOCK AD0–AD15 (AD0–AD7)
A16–A19 (A8–A19) BHE (S7) and DT R to allow
another master to drive these lines directly
Local Bus Controller and Reset
During RESET the local bus controller will perform
the following action
 Drive DEN RD and WR HIGH for one clock cy-
cle then float
NOTE
RD is also provided with an internal pull-up de-
vice to prevent the processor from inadvertently
entering Queue Status Mode during RESET
 Drive S0–S2 to the inactive state (all HIGH) and
then float
 Drive LOCK HIGH and then float
 Float AD0–15 (AD0–AD7) A16–19 (A8–A19)
BHE (S7) DT R
 Drive ALE LOW (ALE is never floated)
 Drive HLDA LOW
either memory or I O space Internal logic will recog-
nize control block addresses and respond to bus cy-
cles During bus cycles to internal registers the bus
controller will signal the operation externally (i e the
RD WR status address data etc lines will be driv-
en as in a normal bus cycle) but D15–0 (D7–0)
SRDY and ARDY will be ignored The base address
of the control block must be on an even 256-byte
boundary (i e the lower 8 bits of the base address
are all zeros)
The control block base address is programmed by a
16-bit relocation register contained within the control
block at offset FEH from the base address of the
control block It provides the upper 12 bits of the
base address of the control block
In addition to providing relocation information for the
control block the relocation register contains bits
which place the interrupt controller into Slave Mode
and cause the CPU to interrupt upon encountering
ESC instructions
Chip-Select Ready Generation Logic
The processor contains logic which provides
programmable chip-select generation for both mem-
ories and peripherals In addition it can be pro-
grammed to provide READY (or WAIT state) genera-
tion It can also provide latched address bits A1 and
A2 The chip-select lines are active for all memory
and I O cycles in their programmed areas whether
they be generated by the CPU or by the integrated
DMA unit
MEMORY CHIP SELECTS
The processor provides 6 memory chip select out-
puts for 3 address areas upper memory lower
memory and midrange memory One each is provid-
ed for upper memory and lower memory while four
are provided for midrange memory
UPPER MEMORY CS
The processor provides a chip select called UCS
for the top of memory The top of memory is usually
used as the system memory because after reset the
processor begins executing at memory location
FFFF0H
PERIPHERAL ARCHITECTURE
All of the integrated peripherals are controlled by
16-bit registers contained within an internal 256-byte
control block The control block may be mapped into
LOWER MEMORY CS
The processor provides a chip select for low memo-
ry called LCS The bottom of memory contains the
interrupt vector table starting at location 00000H
10
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80186 80188
The lower limit of memory defined by this chip select
is always 0H while the upper limit is programmable
By programming the upper limit the size of the
memory block is defined
MID-RANGE MEMORY CS
The processor provides four MCS lines which are
active within a user-locatable memory block This
block can be located within the 1-Mbyte memory ad-
dress space exclusive of the areas defined by UCS
and LCS Both the base address and size of this
memory block are programmable
PERIPHERAL CHIP SELECTS
The processor can generate chip selects for up to
seven peripheral devices These chip selects are ac-
tive for seven contiguous blocks of 128 bytes above
a programmable base address The base address
may be located in either memory or I O space Sev-
en CS lines called PCS0 –6 are generated by the
processor PCS5 and PCS6 can also be pro-
grammed to provide latched address bits A1 and A2
If so programmed they cannot be used as peripher-
al selects These outputs can be connected directly
to the A0 and A1 pins used for selecting internal
registers of 8-bit peripheral chips
READY GENERATION LOGIC
The processor can generate a READY signal inter-
nally for each of the memory or peripheral CS lines
The number of WAIT states to be inserted for each
peripheral or memory is programmable to provide
0–3 wait states for all accesses to the area for
which the chip select is active In addition the proc-
essor may be programmed to either ignore external
READY for each chip-select range individually or to
factor external READY with the integrated ready
generator
CHIP SELECT READY LOGIC AND RESET
Upon RESET the Chip-Select Ready Logic will per-
form the following actions
 All chip-select outputs will be driven HIGH
 Upon leaving RESET the UCS line will be pro-
grammed to provide chip selects to a 1K block
with the accompanying READY control bits set at
011 to insert 3 wait states in conjunction with ex-
ternal READY (i e UMCS resets to FFFBH)
 No other chip select or READY control registers
have any predefined values after RESET They
will not become active until the CPU accesses
their control registers Both the PACS and MPCS
registers must be accessed before the PCS lines
will become active
DMA Channels
The DMA controller provides two independent DMA
channels Data transfers can occur between memo-
ry and I O spaces (e g Memory to I O) or within the
same space (e g Memory to Memory or I O to I O)
Data can be transferred either in bytes or in words
(80186 only) to or from even or odd addresses
Each DMA channel maintains both a 20-bit source
and destination pointer which can be optionally in-
cremented or decremented after each data transfer
(by one or two depending on byte or word transfers)
Each data transfer consumes 2 bus cycles (a mini-
mum of 8 clocks) one cycle to fetch data and the
other to store data This provides a maximum data
transfer rate of 1 25 Mword sec or 2 5 Mbytes sec
at 10 MHz (half of this rate for the 80188)
DMA CHANNELS AND RESET
Upon RESET the DMA channels will perform the
following actions
 The Start Stop bit for each channel will be reset
to STOP
 Any transfer in progress is aborted
Timers
The processor provides three internal 16-bit pro-
grammable timers Two of these are highly flexible
and are connected to four external pins (2 per timer)
They can be used to count external events time ex-
ternal events generate nonrepetitive waveforms
etc The third timer is not connected to any external
pins and is useful for real-time coding and time de-
lay applications In addition the third timer can be
used as a prescaler to the other two or as a DMA
request source
11
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TIMERS AND RESET
Upon RESET the Timers will perform the following
actions
 All EN (Enable) bits are reset preventing timer
counting
 For Timers 0 and 1 the RIU bits are reset to zero
and the ALT bits are set to one This results in the
Timer Out pins going high
Interrupt Controller
The processor can receive interrupts from a number
of sources both internal and external The internal
interrupt controller serves to merge these requests
on a priority basis for individual service by the CPU
Internal interrupt sources (Timers and DMA chan-
nels) can be disabled by their own control registers
or by mask bits within the interrupt controller The
interrupt controller has its own control register that
sets the mode of operation for the controller
INTERRUPT CONTROLLER AND RESET
Upon RESET the interrupt controller will perform
the following actions
 All SFNM bits reset to 0 implying Fully Nested
Mode
 All PR bits in the various control registers set to 1
This places all sources at lowest priority (level
111)
 All LTM bits reset to 0 resulting in edge-sense
mode
 All Interrupt Service bits reset to 0
 All Interrupt Request bits reset to 0
 All MSK (Interrupt Mask) bits set to 1 (mask)
 All C (Cascade) bits reset to 0 (non-Cascade)
 All PRM (Priority Mask) bits set to 1 implying no
levels masked
 Initialized to Master Mode
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80186 80188
NOTE
Pin names in parenthesis apply to 80188
(1) BHE does not exist on the 80188 this is only required for a 16-bit data bus
Figure 6 Typical 80186 80188 Computer
272430 – 6
13
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80186 80188
NOTE
Pin names in parentheses apply to 80188
(1) BHE does not exist on the 80188 this is only required for a 16-bit data bus
Figure 7 Typical 80186 80188 Multi-Master Bus Interface
14
272430 – 7
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80186 80188
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias
0 C to 70 C
Storage Temperature
b65 C to a150 C
Voltage on any Pin with
Respect to Ground
b1 0V to a7V
Power Dissipation
3W
NOTICE This is a production data sheet The specifi-
cations are subject to change without notice
WARNING Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
D C CHARACTERISTICS (TA e 0 C to a70 C VCC e 5V g10%)
Applicable to 8 MHz and 10 MHz devices
Symbol
Parameter
Min
Max
Units
Test Conditions
VIL Input Low Voltage
b0 5
a0 8
V
VIH Input High Voltage
2 0 VCC a 0 5
V
(All except X1 and (RES)
VIH1
Input High Voltage (RES) 3 0 VCC a 0 5
V
VOL Output Low Voltage
0 45
V Ia e 2 5 mA for S0 – S2
Ia e 2 0 mA for all other Outputs
VOH Output High Voltage
24
V Ioa e b400 mA
ICC Power Supply Current
600 mA TA e b40 C
550 mA TA e 0 C
415 mA TA e a70 C
ILI Input Leakage Current
g10
mA 0V k VIN k VCC
ILO Output Leakage Current
g10
mA 0 45V k VOUT k VCC
VCLO
Clock Output Low
0 6 V Ia e 4 0 mA
VCHO
Clock Output High
40
V Ioa e b200 mA
VCLI Clock Input Low Voltage b0 5 0 6
V
VCHI
Clock Input High Voltage 3 9 VCC a 1 0
V
CIN Input Capacitance
10 pF
CIO I O Capacitance
For extended temperature parts only
20 pF
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80186 80188
A C CHARACTERISTICS (TA e 0 C to a70 C VCC e 5V g10%)
Timing Requirements All Timings Measured At 1 5V Unless Otherwise Noted
Symbol
Parameter
8 MHz
Min Max
10 MHz
Units
Min Max
Test
Conditions
TDVCL
TCLDX
TARYHCH
Data in Setup (A D)
Data in Hold (A D)
Asynchronous Ready
(ARDY) Active Setup
Time(1)
20
10
20
15 ns
8 ns
15 ns
TARYLCL
TCLARX
TARYCHL
ARDY Inactive Setup Time
ARDY Hold Time
Asynchronous Ready
Inactive Hold Time
35
15
15
25 ns
15 ns
15 ns
TSRYCL
Synchronous Ready (SRDY)
Transition Setup Time(2)
20
20 ns
TCLSRY
SRDY Transition Hold
Time(2)
15
15 ns
THVCL
TINVCH
HOLD Setup(1)
INTR NMI TEST TIM IN
Setup(1)
25
25
20 ns
25 ns
TINVCL
DRQ0 DRQ1 Setup(1)
Master Interface Timing Responses
25
20 ns
TCLAV
TCLAX
TCLAZ
Address Valid Delay
Address Hold
Address Float Delay
5 55 5 44 ns CL e 20 pF–200 pF
all Outputs
10 10 ns (Except TCLTMV)
TCLAX 35 TCLAX 30 ns 8 MHz and 10 MHz
TCHCZ
Command Lines Float Delay
45
40 ns
TCHCV
Command Lines Valid Delay
55
45 ns
(after Float)
TLHLL
TCHLH
TCHLL
TLLAX
ALE Width
ALE Active Delay
ALE Inactive Delay
Address Hold from ALE
Inactive
TCLCLb35
TCLCLb30
35 30
35 30
TCHCLb25
TCHCLb20
ns
ns
ns
ns
TCLDV
Data Valid Delay
TCLDOX Data Hold Time
TWHDX Data Hold after WR
TCVCTV Control Active Delay 1
TCHCTV Control Active Delay 2
TCVCTX Control Inactive Delay
TCVDEX
DEN Inactive Delay
(Non-Write Cycle)
1 To guarantee recognition at next clock
2 To guarantee proper operation
10 44 10 40
10 10
TCLCLb40
TCLCLb34
5 50 5 40
10 55 10 44
5 55 5 44
10 70 10 56
ns
ns
ns
ns
ns
ns
ns
16
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80186 80188
A C CHARACTERISTICS (TA e 0 C to a70 C VCC e 5V g10%) (Continued)
Master Interface Timing Responses (Continued)
Symbol
Parameter
8 MHz
Min Max
10 MHz
Units
Min Max
Test
Conditions
TAZRL
TCLRL
TCLRH
TRHAV
Address Float to RD Active
RD Active Delay
RD Inactive Delay
RD Inactive to Address
Active
0 0 ns
10 70 10 56 ns
10 55 10 44 ns
TCLCLb40
TCLCLb40
ns
TCLHAV
TRLRH
TWLWH
TAVLL
TCHSV
TCLSH
TCLTMV
HLDA Valid Delay
RD Width
WR Width
Address Valid to ALE Low
Status Active Delay
Status Inactive Delay
Timer Output Delay
5 50 5 40
2TCLCLb50
2TCLCLb46
2TCLCLb40
2TCLCLb34
TCLCHb25
TCLCHb19
10 55 10 45
10 65 10 50
60 48
ns
ns
ns
ns
ns
ns
ns 100 pF max
8 10 MHz
TCLRO Reset Delay
TCHQSV Queue Status Delay
TCHDX Status Hold Time
TAVCH Address Valid to Clock High
TCLLV
LOCK Valid Invalid Delay
Chip-Select Timing Responses
60 48 ns
35 28 ns
10 10 ns
10 10 ns
5 65 5 60 ns
TCLCSV
TCXCSX
Chip-Select Active Delay
Chip-Select Hold from
Command Inactive
66 45 ns
35 35 ns
TCHCSX Chip-Select Inactive Delay
CLKIN Requirements
5 35 5 32 ns
TCKIN
CLKIN Period
TCKHL CLKIN Fall Time
TCKLH CLKIN Rise Time
TCLCK CLKIN Low Time
TCHCK CLKIN High Time
CLKOUT Timing (200 pF load)
62 5 250 50 250 ns
10 10 ns 3 5 to 1 0V
10 10 ns 1 0 to 3 5V
25 20 ns 1 5V
25 20 ns 1 5V
TCICO
TCLCL
TCLCH
TCHCL
TCH1CH2
TCL2CL1
CLKIN to CLKOUT Skew
CLKOUT Period
CLKOUT Low Time
CLKOUT High Time
CLKOUT Rise Time
CLKOUT Fall Time
125
TCLCLb7 5
TCLCLb7 5
50
500
15
15
25 ns
100 500 ns
TCLCLb6 0
TCLCLb6 0
12
ns 1 5V
ns 1 5V
ns 1 0 to 3 5V
12 ns 3 5 to 1 0V
17
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80186 80188
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has from 5 to 7 characters The
first character is always a ‘‘T’’ (stands for time) The
other characters depending on their positions
stand for the name of a signal or the logical status of
that signal The following is a list of all the charac-
ters and what they stand for
A Address
ARY Asynchronous Ready Input
C Clock Output
CK Clock Input
CS Chip Select
CT Control (DT R DEN )
D Data Input
DE DEN
H Logic Level High
IN Input (DRQ0 TIM0 )
L Logic Level Low or ALE
O Output
QS Queue Status (QS1 QS2)
R RD signal RESET signal
S Status (S0 S1 S2)
SRY Synchronous Ready Input
V Valid
W WR Signal
X No Longer a Valid Logic Level
Z Float
Examples
TCLAV
TCHLH
TCLCSV
Time from Clock low to Address valid
Time from Clock high to ALE high
Time from Clock low to Chip Select valid
18
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WAVEFORMS
MAJOR CYCLE TIMING
80186 80188
NOTE
Pin names in parentheses apply to the 80188
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80186 80188
WAVEFORMS (Continued)
MAJOR CYCLE TIMING (Continued)
NOTES
1 INTA occurs one clock later in slave mode
2 Status inactive just prior to T4
3 If latched A1 and A2 are selected instead of PCS5 and PCS6 only TCLCSV is applicable
4 Pin names in parentheses apply to the 80188
272430 – 9
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WAVEFORMS (Continued)
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80186 80188
272430 – 10
272430 – 11
272430 – 12
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80186 80188
WAVEFORMS (Continued)
272430 – 13
272430 – 14
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WAVEFORMS (Continued)
READY TIMING
80186 80188
272430 – 15
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80186 80188
NOTE
Pin names in parentheses apply to the 80188
24
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WAVEFORMS (Continued)
80186 80188
272430 – 17
EXPRESS
The Intel EXPRESS system offers enhancements to
the operational specifications of the microprocessor
EXPRESS products are designed to meet the needs
of those applications whose operating requirements
exceed commercial standards
The EXPRESS program includes the commercial
standard temperature range with burn-in and an ex-
tended temperature range without burn-in
With the commercial standard temperature range
operational characteristics are guaranteed over the
temperature range of 0 C to a70 C With the ex-
tended temperature range option operational char-
acteristics are guaranteed over the range of b40 C
to a85 C
The optional burn-in is dynamic for a minimum time
of 160 hours at a125 C with VCC e 5 5V g0 25V
following guidelines in MIL-STD-883 Method 1015
Package types and EXPRESS versions are identified
by a one- or two-letter prefix to the part number The
prefixes are listed in Table 2 All A C and D C speci-
fications not mentioned in this section are the same
for both commercial and EXPRESS parts
Prefix
A
N
R
TA
QA
QR
Table 2 Prefix Identification
Package
Type
Temperature
Range
Burn-In
PGA
Commercial
No
PLCC
Commercial
No
LCC
Commercial
No
PGA
Extended
No
PGA
Commercial
Yes
LCC
Commercial
Yes
NOTE
Not all package temperature range speed combinations
are available
25
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80186 80188
EXECUTION TIMINGS
A determination of program execution timing must
consider the bus cycles necessary to prefetch in-
structions as well as the number of execution unit
cycles necessary to execute instructions The fol-
lowing instruction timings represent the minimum ex-
ecution time in clock cycles for each instruction The
timings given are based on the following assump-
tions
 The opcode along with any data or displacement
required for execution of a particular instruction
has been prefetched and resides in the queue at
the time it is needed
 No wait states or bus HOLDS occur
 All word-data is located on even-address bound-
aries
All instructions which involve memory accesses can
also require one or two additional clocks above the
minimum timings shown due to the asynchronous
handshake between the bus interface unit (BIU) and
execution unit
All jumps and calls include the time required to fetch
the opcode of the next instruction at the destination
address
The 80186 has sufficient bus performance to ensure
that an adequate number of prefetched bytes will
reside in the queue (6 bytes) most of the time
Therefore actual program execution time will not be
substantially greater than that derived from adding
the instruction timings shown
The 80188 is noticeably limited in its performance
relative to the execution unit A sufficient number of
prefetched bytes may not reside in the prefetch
queue (4 bytes) much of the time Therefore actual
program execution time may be substantially greater
than that derived from adding the instruction timings
shown
26
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80186 80188
INSTRUCTION SET SUMMARY
Function
Format
DATA TRANSFER
MOV e Move
Register to Register Memory
Register memory to register
Immediate to register memory
Immediate to register
Memory to accumulator
Accumulator to memory
Register memory to segment register
Segment register to register memory
PUSH e Push
Memory
Register
Segment register
Immediate
1000100w
1000101w
1100011w
1 0 1 1 w reg
1010000w
1010001w
10001110
10001100
mod reg r m
mod reg r m
mod 000 r m
data
addr-low
addr-low
mod 0 reg r m
mod 0 reg r m
11111111
0 1 0 1 0 reg
0 0 0 reg 1 1 0
011010s0
mod 1 1 0 r m
data
data
data if we1
addr-high
addr-high
data if se0
data if we1
80186
Clock
Cycles
80188
Clock
Cycles
Comments
2 12
29
12 13
34
8
9
29
2 11
2 12
29
12 13
34
8
9
2 13
2 15
8 16-bit
8 16-bit
16 20
10 14
9 13
10 14
PUSHA e Push All
POP e Pop
Memory
Register
Segment register
01100000
10001111
0 1 0 1 1 reg
0 0 0 reg 1 1 1
mod 0 0 0 r m
(reg i 01)
36 68
20 24
10 14
8 12
POPA e Pop All
01100001
51 83
XCHG e Exchange
Register memory with register
1 0 0 0 0 1 1 w mod reg r m
4 17
4 17
Register with accumulator
1 0 0 1 0 reg
33
IN e Input from
Fixed port
1110010w
port
10 10
Variable port
OUT e Output to
Fixed port
1110110w
1110011w
port
88
99
Variable port
1110111w
77
XLAT e Translate byte to AL
11010111
11 15
LEA e Load EA to register
1 0 0 0 1 1 0 1 mod reg r m
66
LDS e Load pointer to DS
1 1 0 0 0 1 0 1 mod reg r m
(mod i 11)
18 26
LES e Load pointer to ES
1 1 0 0 0 1 0 0 mod reg r m
(mod i 11)
18 26
LAHF e Load AH with flags
10011111
22
SAHF e Store AH into flags
10011110
33
PUSHF e Push flags
10011100
9 13
POPF e Pop flags
10011101
Shaded areas indicate instructions not available in 8086 8088 microsystems
8 12
NOTE
Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer
27
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80186 80188
INSTRUCTION SET SUMMARY (Continued)
Function
Format
DATA TRANSFER (Continued)
SEGMENT e Segment Override
CS
SS
DS
ES
ARITHMETIC
ADD e Add
Reg memory with register to either
Immediate to register memory
Immediate to accumulator
ADC e Add with carry
Reg memory with register to either
Immediate to register memory
Immediate to accumulator
INC e Increment
Register memory
Register
SUB e Subtract
Reg memory and register to either
Immediate from register memory
Immediate from accumulator
SBB e Subtract with borrow
Reg memory and register to either
Immediate from register memory
Immediate from accumulator
DEC e Decrement
Register memory
Register
CMP e Compare
Register memory with register
Register with register memory
Immediate with register memory
Immediate with accumulator
NEG e Change sign register memory
AAA e ASCII adjust for add
DAA e Decimal adjust for add
AAS e ASCII adjust for subtract
DAS e Decimal adjust for subtract
00101110
00110110
00111110
00100110
000000dw
100000sw
0000010w
mod reg r m
mod 0 0 0 r m
data
000100dw
100000sw
0001010w
mod reg r m
mod 0 1 0 r m
data
1111111w
0 1 0 0 0 reg
mod 0 0 0 r m
001010dw
100000sw
0010110w
mod reg r m
mod 1 0 1 r m
data
000110dw
100000sw
0001110w
mod reg r m
mod 0 1 1 r m
data
1111111w
0 1 0 0 1 reg
mod 0 0 1 r m
0011101w
0011100w
100000sw
0011110w
1111011w
00110111
00100111
00111111
00101111
mod reg r m
mod reg r m
mod 1 1 1 r m
data
mod 0 1 1 r m
data
data if we1
data
data if we1
data
data if we1
data
data if we1
data
data if we1
data if s we01
data if s we01
data if s we01
data if s we01
data if s we01
80186
Clock
Cycles
80188
Clock
Cycles
Comments
22
22
22
22
3 10
4 16
34
3 10
4 16
34
3 15
3
3 10
4 16
34
3 10
4 16
34
3 15
3
3 10
3 10
3 10
34
3 10
8
4
7
4
3 10
4 16
34
3 10
4 16
34
3 15
3
3 10
4 16
34
3 10
4 16
34
3 15
3
3 10
3 10
3 10
34
3 10
8
4
7
4
8 16-bit
8 16-bit
8 16-bit
8 16-bit
8 16-bit
MUL e Multiply (unsigned)
1 1 1 1 0 1 1 w mod 100 r m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
Shaded areas indicate instructions not available in 8086 8088 microsystems
26 – 28
35 – 37
32 – 34
41 – 43
26 – 28
35 – 37
32 – 34
41 – 43
NOTE
Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer
28
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80186 80188
INSTRUCTION SET SUMMARY (Continued)
Function
ARITHMETIC (Continued)
IMUL e Integer multiply (signed)
Register-Byte
Register-Word
Memory-Byte
Memory-Word
IMUL e Integer Immediate multiply
(signed)
Format
1 1 1 1 0 1 1 w mod 1 0 1 r m
0 1 1 0 1 0 s 1 mod reg r m
data
80186
Clock
Cycles
80188
Clock
Cycles
Comments
data if se0
25 – 28
34 – 37
31 – 34
40 – 43
22 – 25
29 – 32
25 – 28
34 – 37
31 – 34
40 – 43
22 – 25
29 – 32
DIV e Divide (unsigned)
Register-Byte
Register-Word
Memory-Byte
Memory-Word
IDIV e Integer divide (signed)
Register-Byte
Register-Word
Memory-Byte
Memory-Word
AAM e ASCII adjust for multiply
1 1 1 1 0 1 1 w mod 1 1 0 r m
1 1 1 1 0 1 1 w mod 1 1 1 r m
11010100 00001010
29 29
38 38
35 35
44 44
44 – 52
53 – 61
50 – 58
59 – 67
19
44 – 52
53 – 61
50 – 58
59 – 67
19
AAD e ASCII adjust for divide
11010101 00001010
15 15
CBW e Convert byte to word
10011000
22
CWD e Convert word to double word
10011001
44
LOGIC
Shift Rotate Instructions
Register Memory by 1
1 1 0 1 0 0 0 w mod TTT r m
2 15
2 15
Register Memory by CL
1 1 0 1 0 0 1 w mod TTT r m
5an 17an 5an 17an
Register Memory by Count
1 1 0 0 0 0 0 w mod TTT r m
count
5an 17an 5an 17an
AND e And
Reg memory and register to either
TTT Instruction
0 0 0 ROL
0 0 1 ROR
0 1 0 RCL
0 1 1 RCR
1 0 0 SHL SAL
1 0 1 SHR
1 1 1 SAR
0 0 1 0 0 0 d w mod reg r m
3 10
3 10
Immediate to register memory
1 0 0 0 0 0 0 w mod 1 0 0 r m
data
data if we1
4 16
4 16
Immediate to accumulator
0010010w
data
data if we1
3 4 3 4 8 16-bit
TESTeAnd function to flags no result
Register memory and register
1000010w
mod reg r m
3 10
3 10
Immediate data and register memory
1 1 1 1 0 1 1 w mod 0 0 0 r m
data
data if we1
4 10
4 10
Immediate data and accumulator
1010100w
data
data if we1
3 4 3 4 8 16-bit
OReOr
Reg memory and register to either
0 0 0 0 1 0 d w mod reg r m
3 10
3 10
Immediate to register memory
1 0 0 0 0 0 0 w mod 0 0 1 r m
data
data if we1
4 16
4 16
Immediate to accumulator
0000110w
data
data if we1
Shaded areas indicate instructions not available in 8086 8088 microsystems
3 4 3 4 8 16-bit
NOTE
Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer
29
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80186 80188
INSTRUCTION SET SUMMARY (Continued)
Function
Format
LOGIC (Continued)
XOR e Exclusive or
Reg memory and register to either
0 0 1 1 0 0 d w mod reg r m
Immediate to register memory
1 0 0 0 0 0 0 w mod 1 1 0 r m
Immediate to accumulator
0011010w
data
NOT e Invert register memory
STRING MANIPULATION
MOVS e Move byte word
1 1 1 1 0 1 1 w mod 0 1 0 r m
1010010w
CMPS e Compare byte word
1010011w
SCAS e Scan byte word
1010111w
LODS e Load byte wd to AL AX
1010110w
STOS e Store byte wd from AL AX
1010101w
INS e Input byte wd from DX port
0110110w
OUTS e Output byte wd to DX port
0110111w
Repeated by count in CX (REP REPE REPZ REPNE REPNZ)
MOVS e Move string
11110010 1010010w
CMPS e Compare string
1111001z 1010011w
SCAS e Scan string
1111001z 1010111w
LODS e Load string
11110010 1010110w
STOS e Store string
11110010 1010101w
INS e Input string
11110010 0110110w
data
data if we1
data if we1
80186
Clock
Cycles
80188
Clock
Cycles
Comments
3 10
4 16
34
3 10
14
22
15
12
10
14
14
3 10
4 16
34
3 10
14
22
15
12
10
14
14
8 16-bit
8a8n
5a22n
5a15n
6a11n
6a9n
8a8n
8a8n
5a22n
5a15n
6a11n
6a9n
8a8n
OUTS e Output string
CONTROL TRANSFER
CALL e Call
Direct within segment
Register memory
indirect within segment
11110010 0110111w
11101000
11111111
disp-low
mod 0 1 0 r m
disp-high
8a8n
8a8n
15
13 19
19
17 27
Direct intersegment
10011010
segment offset
segment selector
23 31
Indirect intersegment
JMP e Unconditional jump
Short long
Direct within segment
Register memory
indirect within segment
1 1 1 1 1 1 1 1 mod 0 1 1 r m
(mod i 11)
11101011
11101001
11111111
disp-low
disp-low
mod 1 0 0 r m
disp-high
38 54
14
14
11 17
14
14
11 21
Direct intersegment
11101010
segment offset
segment selector
14 14
Indirect intersegment
1 1 1 1 1 1 1 1 mod 1 0 1 r m
(mod i 11)
26 34
Shaded areas indicate instructions not available in 8086 8088 microsystems
NOTE
Clock cycles shown for byte transfers for word operations add 4 clock cycles for each memory transfer
30
30
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