MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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19-1822; Rev 1; 2/02
Single-Supply, Low-Power, Serial 8-Bit ADCs
General Description
The MAX1115/MAX1116 low-power, 8-bit, analog-to-
digital converters (ADCs) feature an internal track/hold
(T/H), voltage reference, VDD monitor, clock, and serial
interface. The MAX1115 is specified from +2.7V to
+5.5V, and the MAX1116 is specified from +4.5V to
+5.5V. Both parts consume only 175µA at 100ksps.
The full-scale analog input range is determined by the
internal reference of +2.048V (MAX1115) or +4.096V
(MAX1116). The MAX1115/MAX1116 also feature
AutoShutdown™ power-down mode which reduces
power consumption to <1µA when the device is not in
use. The 3-wire serial interface directly connects to
SPI™, QSPI™, and MICROWIRE™ devices without
external logic. Conversions up to 100ksps are per-
formed using an internal clock.
The MAX1115/MAX1116 are available in an 8-pin
SOT23 package with a footprint that is just 30% of an
8-pin SO.
Features
o Single Supply
+2.7V to +3.6V (MAX1115)
+4.5V to +5.5V (MAX1116)
o Input Voltage Range: 0 to VREF
o Internal Track/Hold; 100kHz Sampling Rate
o Internal Reference
+2.048V (MAX1115)
+4.096V (MAX1116)
o SPI/QSPI/MICROWIRE-Compatible Serial Interface
o Small 8-Pin SOT23 Package
o Automatic Power-Down
o Low Power
175µA at 100ksps
18µA at +3V and 10ksps
1µA in Power-Down Mode
________________________Applications
Low-Power, Hand-Held Portable Devices
System Diagnostics
Battery-Powered Test Equipment
Receive-Signal-Strength Indicators
4mA to 20mA Powered Remote Data-Acquisition
Systems
AutoShutdown is a trademark of Maxim Integrated Products.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
PART
MAX1115EKA
MAX1116EKA
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
8 SOT23
8 SOT23
TOP
MARK
AADU
AADV
Pin Configuration
TOP VIEW
VDD 1
CH0 2
I.C. 3
GND 4
MAX1115
MAX1116
SOT23
8 SCLK
7 DOUT
6 CONVST
5 I.C.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +6.0V
CH0 to GND ...............................................-0.3V to (VDD + 0.3V)
Digital Output to GND ................................-0.3V to (VDD + 0.3V)
Digital Input to GND ..............................................-0.3V to +6.0V
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin SOT23 (derate 8.9mW/°C above +70°C)............714mW
Operating Temperature Range
MAX111_EKA ..................................................-40°C to + 85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX1115), VDD = +4.5V to +5.5V (MAX1116), TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
DC ACCURACY
Resolution
8
Relative Accuracy
Differential Nonlinearity
INL
DNL
(Note 1)
±1
±1
Offset Error
Gain Error
0.5
±5
Gain Temperature Coefficient
90
VDD/2 Sampling Error
±2 ±7
DYNAMIC PERFORMANCE (25kHz sine-wave input, VIN = VREF (P-P), fSCLK = 5MHz, fSAMPLE = 100ksps, RIN = 100)
Signal-to-Noise Plus Distortion
SINAD
48
Total Harmonic Distortion
(up to the 5th Harmonic)
THD
-69
Spurious-Free Dynamic Range
SFDR
66
Small-Signal Bandwidth
ANALOG INPUT
f-3dB
4
Input Voltage Range
Input Leakage Current
Input Capacitance
INTERNAL REFERENCE
VCH = 0 or VDD
CIN
0 VREF
±0.7 ±10
18
Voltage
VREF
MAX1115
MAX1116
2.048
4.096
POWER REQUIREMENTS
Supply Voltage
MAX1115
VDD MAX1116
2.7 5.5
4.5 5.5
Supply Current (Note 2)
MAX1115
fSAMPLE = 10ksps
fSAMPLE = 100ksps
IDD fSAMPLE = 10ksps
MAX1116
fSAMPLE = 100ksps
Shutdown
14 21
135 190
19 25
182 230
0.8 10
UNITS
Bits
LSB
LSB
LSB
%FSR
ppm/°C
%
dB
dB
dB
MHz
V
µA
pF
V
V
µA
2 _______________________________________________________________________________________


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX1115), VDD = +4.5V to +5.5V (MAX1116), TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Supply Rejection Ratio
PSRR Full-scale or zero input
DIGITAL INPUTS (CNVST AND SCLK)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hystersis
Input Current High
VHYST
IIH
Input Current Low
Input Capacitance
IIL
CIN
DIGITAL OUTPUT (DOUT)
Output High Voltage
VOH
ISOURCE = 2mA
Output Low Voltage
ISINK = 2mA
VOL ISINK = 4mA
Three-State Leakage Current
IL
Three-State Output Capacitance COUT
TIMING CHARACTERISTICS (Figures 6a6d)
CNVST High Time
tcsh
CNVST Low Time
Conversion Time
tcsl
tconv
Serial Clock High Time
Serial Clock Low Time
tch
tcl
Serial Clock Period
tcp
Falling of CNVST to DOUT
Active
tcsd CLOAD = 100pF, Figure 1
MIN TYP MAX
±0.5 ±1
2
0.8
0.2
±10
±10
2
VDD - 0.5
±0.01
4
0.4
0.8
±10
100
100
7.5
75
75
200
100
Serial Clock Falling Edge to
DOUT
tcd CLOAD = 100pF
10 100
Serial Clock Rising Edge
To DOUT High-Z
tchz CLOAD = 100pF, Figure 2
100 500
Last Serial Clock to Next CNVST
(successive conversions on CH0)
tccs
50
UNITS
LSB/V
V
V
V
µA
µA
pF
V
V
µA
pF
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and off-
set have been calibrated.
Note 2: Input = 0, with logic input levels of 0 and VDD.
_______________________________________________________________________________________ 3


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
Typical Operating Characteristics
(VDD = +3V (MAX1115), VDD = +5V (MAX1116), fscu = 5MHz, fsample = 100ksps, CLOAD = 100pF, TA = +25°C, unless otherwise
noted.)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
50 100 150 200 250 300
OUTPUT CODE
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
50 100 150 200 250 300
OUTPUT CODE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
3.5 4.5
SUPPLY VOLTAGE (V)
5.5
100.0
SUPPLY CURRENT vs.
CONVERSION RATE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
200
SUPPLY CURRENT
vs. TEMPERATURE
200
MAX1116
10.0 VDD = +5V
MAX1115
VDD = +3V
1.0
0
0.01
5.5
0.1 1
10
CONVERSION (ksps)
CONVERSION TIME
vs. SUPPLY VOLTAGE
100
5.4
5.3
5.2
5.1
5.0
2.5
3.5 4.5
SUPPLY VOLTAGE (V)
5.5
150
100 MAX1115
MAX1116
50 DOUT = 00000000
VDD = VDIGITAL INPUTS
0
2.5
5.5
3.5 4.5
SUPPLY VOLTAGE (V)
CONVERSION TIME
vs. TEMPERATURE
5.5
5.4 VDD = +3V
5.3
5.2
5.1
VDD = +5V
5.0
-40
-15 10 35 60
TEMPERATURE (°C)
85
150
100
MAX1115
VDD = +3V
MAX1116
VDD = +5V
50
DOUT = 00000000
VDD = VREF = VDIGITAL INPUTS
0
-40
-15 10
35 60
TEMPERATURE (°C)
85
GAIN ERROR vs.
SUPPLY VOLTAGE
1.4
1.2
1.0
MAX1115
0.8 VDD = +3V
0.6
MAX1116
VDD = +5V
0.4
0.2
0
2.5 3.5 4.5 5.5
SUPPLY VOLTAGE (V)
4 _______________________________________________________________________________________


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
Typical Operating Characteristics (continued)
(VDD = +3V (MAX1115), VDD = +5V (MAX1116), fscu = 5MHz, fsample = 100ksps, CLOAD = 100pF, TA = +25°C, unless otherwise
noted.)
GAIN ERROR
vs. TEMPERATURE
FFT PLOT
2.0 0 fSAMPLE = 100kHz
1.5
fIN = 25.1kHz
-20 AIN = 0.9xVREF p-p
1.0
-40
0.5
0 MAX1116
-0.5 VDD = +5V
-1.0
-1.5
MAX1115
VDD = +3V
-60
-80
-100
-2.0
-40
-15 10 35 60
TEMPERATURE (°C)
85
-120
0
10k 20k 30k 40k
ANALOG INPUT FREQUENCY (Hz)
50k
OFFSET ERROR vs.
SUPPLY VOLTAGE
0.5
0.4
0.3
0.2
MAX1116
VDD = +3V
0.1
0
-0.1
-0.2 MAX1115
-0.3 VDD = +3V
-0.4
-0.5
2.5
3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
5.5
21.0%
MAX1115
REFERENCE VOLTAGE
vs. NUMBER OF PIECES
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-40
OFFSET ERROR vs.
TEMPERATURE
MAX1116
VDD = +3V
MAX1115
VDD = +5V
-15 10 35 60
TEMPERATURE (°C)
85
21.0%
MAX1116
REFERENCE VOLTAGE
vs. NUMBER OF PIECES
17.5%
17.5%
14.0%
14.0%
10.5%
10.5%
7.0% 7.0%
3.5% 3.5%
0
1.982
2.008 2.034 2.060 2.086
REFERENCE VOLTAGE (V)
2.112
0
3.980
4.020 4.060 4.100 4.140
REFERENCE VOLTAGE (V)
4.180
_______________________________________________________________________________________ 5


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
Pin Description
PIN NAME
FUNCTION
1 VDD Positive Supply Voltage
2
CH0
Analog Voltage Input
3, 5 I.C. Internally Connected. Connect to ground.
4
GND
Ground
6 CNVST Convert/Start Input. CNVST initiates a power-up and starts a conversion on its falling edge.
Serial Data Output. Data is clocked out on the falling edge of SCLK. DOUT goes low at the start of a
7
DOUT
conversion and presents the MSB at the completion of a conversion. DOUT goes high impedance
once data has been fully clocked out.
8
SCLK
Serial Clock. Used for clocking out data on DOUT.
VDD VDD
DOUT
DOUT
3k
DOUT
DOUT
3k
3k
GND
a) VOL TO VOH
CLOAD
CLOAD
GND
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for Enable Time
3k
GND
CLOAD
CLOAD
GND
a) VOH TO HIGH-Z
b) VOL TO HIGH-Z
Figure 2. Load Circuits for Disable Time
Detailed Description
The MAX1115/MAX1116 ADCs use a successive-
approximation conversion technique and input
track/hold (T/H) circuitry to convert an analog signal to
an 8-bit digital output. The SPI/QSPI/MICROWIRE-
compatible interface directly connects to microproces-
sors (µPs) without additional circuitry (Figure 3).
Track/Hold
The input architecture of the ADC is illustrated in the
equivalent-input circuit shown in Figure 4 and is com-
posed of the T/H, input multiplexer, input comparator,
switched capacitor DAC, and auto-zero rail.
The acquisition interval begins with the falling edge of
CNVST. During the acquisition interval, the analog input
(CH0) is connected to the hold capacitor (CHOLD).
Once the acquisition is complete, the T/H switch opens
and CHOLD is connected to GND, which retains the
charge on CHOLD as a sample of the signal at the ana-
log input.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of <1.5kis
recommended for accurate sample settling. A 100pF
capacitor at the ADC inputs also improves the accuracy
of an input sample.
Conversion Process
The MAX1115/MAX1116 conversion process is internal-
ly timed. The total acquisition and conversion process
takes <7.5µs. Once an input sample has been
acquired, the comparators negative input is then con-
nected to an auto-zero supply. Since the device
requires only a single supply, the negative input of the
comparator is set to equal VDD/2. The capacitive DAC
restores the positive input to VDD/2 within the limits of 8-
bit resolution. This action is equivalent to transferring a
charge QIN = 16pF VIN from CHOLD to the binary-
weighted capacitive DAC, which forms a digital repre-
sentation of the analog-input signal.
6 _______________________________________________________________________________________


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
ANALOG
INPUTS
CH0 VDD
0.1µF
GND
MAX1115
MAX1116
CONVST
SCLK
DOUT
VDD
VDD
1µF
CPU
I/O
SCK (SK)
MISO (SI)
GND
Figure 3. Typical Operating Circuit
GND
CH0
VDD
2
CAPACITIVE DAC
CHOLD
16pF
HOLD
RIN
6.5k
TRACK
Figure 4. Equivalent Input Circuit
COMPARATOR
AUTO-ZERO
RAIL
Input Voltage Range
Internal protection diodes that clamp the analog input
to VDD and GND allow the input pin (CH0) to swing
from (GND - 0.3V) to (VDD + 0.3V) without damage.
However, for accurate conversions, the inputs must not
exceed (VDD + 50mV) or be less than (GND - 50mV).
Input Bandwidth
The ADCs input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADCs sampling rate by
using undersampling techniques. Anti-alias filtering is
recommended to avoid high-frequency signals being
aliased into the frequency band of interest.
Serial Interface
The MAX1115/MAX1116 have a 3-wire serial interface.
The CNVST and SCLK inputs are used to control the
device, while the three-state DOUT pin is used to
access the conversion results.
The serial interface provides connection to microcon-
trollers (µCs) with SPI, QSPI, and MICROWIRE serial
interfaces at clock rates up to 5MHz. The interface sup-
ports either an idle high or low SCLK format. For SPI
and QSPI, set CPOL = CPHA = 0 or CPOL = CPHA = 1
in the SPI control registers of the µC. Figure 5 shows
the MAX1115/MAX1116 common serial-interface con-
nections. See Figures 6a6d for details on the serial-
interface timing and protocol.
I/O
SCK
MISO
a) SPI
SS
CS
SCK
MISO
b) QSPI
SS
I/O
SK
SI
+3V
+3V
CONVST
SCLK
DOUT
MAX1115
MAX1116
CONVST
SCLK
DOUT
MAX1115
MAX1116
CONVST
SCLK
DOUT
MAX1115
MAX1116
c) MICROWIRE
Figure 5. Common Serial-Interface Connections
_______________________________________________________________________________________ 7


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
ACTIVE
tCSH
CNVST
CH0
tCONV
POWER-DOWN MODE
tch tcp
CH0
tccs
SCLK IDLE LOW
tcsd
DOUT
tcd tcl
IDLE LOW
tchz
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
Figure 6a. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle Low
ACTIVE
tCSH
POWER-DOWN MODE
CNVST
CH0
tCONV tch tcp
SCLK IDLE HIGH
CH0
tccs
IDLE HIGH
DOUT
tcsd
tcd tcl
tchz
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
Figure 6b. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle High
Digital Inputs and Outputs
The MAX1115/MAX1116 perform conversions by using
an internal clock. This frees the µP from the burden of
running the SAR conversion clock, and allows the con-
version results to be read back at the µPs convenience
at any clock rate up to 5MHz.
The acquisition interval begins with the falling edge of
CNVST. CNVST can idle between conversions in either
a high or low state. If idled in a low state, CNVST must
be brought high for at least 50ns, then brought low to
initiate a conversion. To select VDD/2 for conversion,
the CNVST pin must be brought high and low for a
second time (Figures 6c and 6d).
8 _______________________________________________________________________________________


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
ACTIVE
tCSH
CH0
CNVST
VDD
2
tCONV
POWER-DOWN MODE
tch tcp
tCSL
CH0
VDD
2
tccs
SCLK
IDLE LOW
tcsd
DOUT
tcd tcl
IDLE LOW
tchz
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
Figure 6c. Conversion and Interface Timing, Conversion on VDD / 2 with SCLK Idle Low
ACTIVE
tCSH
CH0
CNVST
VDD
2
tCONV
SCLK
IDLE HIGH
POWER-DOWN MODE
tch tcp
tcsl
VDD
CH0 2
tccs
IDLE HIGH
tcsd
DOUT
tcd tcl
tchz
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
Figure 6d. Conversion and Interface Timing, Conversion on VDD / 2 with SCLK Idle High
After CNVST is brought low, allow 7.5µs for the conver-
sion to be completed. While the internal conversion is in
progress, DOUT is low. The MSB is present at the
DOUT pin immediately after conversion is completed.
The conversion result is clocked out at the DOUT pin
and is coded in straight binary (Figure 7). Data is
clocked out at SCLKs falling edge in MSB-first format
at rates up to 5MHz. Once all data bits are clocked out,
DOUT goes high impedance (100ns to 500ns after the
rising edge) of the eighth SCLK pulse.
SCLK is ignored during the conversion process. Only
after a conversion is complete will SCLK cause serial
data to be output. Falling edges on CNVST during an
_______________________________________________________________________________________ 9


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
OUTPUT CODE
11111111
11111110
11111101
FULL-SCALE
TRANSITION
SYSTEM POWER SUPPLIES
GND +3V/+5V
FS = VREFIN + VIN-
1LSB = VREFIN
256
00000011
00000010
00000001
00000000
012 3
INPUT VOLTAGE (LSB)
FS
FS - 1/2 LSB
Figure 7. Input/Output Transfer Function
active conversion process interrupt the current conver-
sion and cause the input multiplexer to switch to VDD/2.
To reinitiate a conversion on CH0, it is necessary to allow
for a conversion to be complete and all of the data to be
read out. Once a conversion has been completed, the
MAX1115/MAX1116 goes into Autoshutdown mode
(typically <1µA) until the next conversion is initiated.
Applications Information
Power-On Reset
When power is first applied, the MAX1115/MAX1116
are in AutoShutdown (typically <1µA). A conversion
can be started by toggling CNVST high to low.
Powering up the MAX1115/MAX1116 with CNVST low
does not start a conversion.
AutoShutdown and Supply Current
Requirements
The MAX1115/MAX1116 are designed to automatically
shutdown once a conversion is complete, without any
external control. An input sample and conversion
process typically takes 5µs to complete, during which
time the supply current to the analog sections of the
device are fully on. All analog circuitry is shutdown after
a conversion completes, which results in a supply cur-
rent of <1µA (see Shutdown Current vs. Supply Voltage
plot in the Typical Operating Characteristics section).
The digital conversion result is maintained in a static
register and is available for access through the serial
interface at any time.
1µF 10
0.1µF
GND IN-
MAX1115
MAX1116
VDD DGND VDD
DIGITAL
CIRCUITRY
Figure 8. Power-Supply Connections
The power consumption consequence of this architec-
ture is dramatic when relatively slow conversion rates
are needed. For example, at a conversion rate of
10ksps, the average supply current for the MAX1115 is
15µA, while at 1ksps it drops to 15µA. At 0.1ksps it is
just 0.3µA, or a miniscule 1µW of power consumption
(see Average Supply Current vs. Conversion Rate plot
in the Typical Operating Characteristics sections).
Transfer Function
Figure 7 depicts the input/output transfer function.
Output coding is binary with a +2.048V reference,
1LSB = 8mV(VREF/256).
Layout, Grounding, and Bypassing
For best performance, board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another or run digital lines under-
neath the ADC package.
Figure 8 shows the recommended system-ground con-
nections. A single-point analog ground (star-ground
point) should be established at the ADC ground.
Connect all analog grounds to the star-ground. The
ground-return to the power supply for the star ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the VDD power supply can
affect the comparator in the ADC. Bypass the supply to
the star ground with a 0.1µF capacitor close to the VDD
pin of the MAX1115/MAX1116. Minimize capacitor lead
10 ______________________________________________________________________________________


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
Functional Diagram
SCLK
CNVST
CONTROL
LOGIC AND
INTERNAL
OCSILLATOR
CH0
INPUT
MULTIPLEXER
INPUT
TRACK
AND HOLD
8-BIT
SAR
ADC
OUTPUT
SHIFT
REGISTER
DOUT
SPLIT
VDD/2
INTERNAL
REFERENCE
2.096V
OR 4.096V
MAX1115
MAX1116
lengths for best supply-noise rejection. If the power
supply is noisy, a 0.1µF capacitor in conjunction with a
10series resistor can be connected to form a low-
pass filter.
Chip Information
TRANSISTOR COUNT: 2000
PROCESS: BiCMOS
______________________________________________________________________________________ 11


MAX1115 (Maxim)
Single-Supply / Low-Power / Serial 8-Bit ADCs

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Single-Supply, Low-Power, Serial 8-Bit ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2002 Maxim Integrated Products
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is a registered trademark of Maxim Integrated Products.




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